1 /****************************************************************************** 2 * emulate.c 3 * 4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. 5 * 6 * Copyright (c) 2005 Keir Fraser 7 * 8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode 9 * privileged instructions: 10 * 11 * Copyright (C) 2006 Qumranet 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 13 * 14 * Avi Kivity <avi@qumranet.com> 15 * Yaniv Kamay <yaniv@qumranet.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 21 */ 22 23 #include <linux/kvm_host.h> 24 #include "kvm_cache_regs.h" 25 #include <linux/module.h> 26 #include <asm/kvm_emulate.h> 27 #include <linux/stringify.h> 28 #include <asm/debugreg.h> 29 30 #include "x86.h" 31 #include "tss.h" 32 33 /* 34 * Operand types 35 */ 36 #define OpNone 0ull 37 #define OpImplicit 1ull /* No generic decode */ 38 #define OpReg 2ull /* Register */ 39 #define OpMem 3ull /* Memory */ 40 #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */ 41 #define OpDI 5ull /* ES:DI/EDI/RDI */ 42 #define OpMem64 6ull /* Memory, 64-bit */ 43 #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */ 44 #define OpDX 8ull /* DX register */ 45 #define OpCL 9ull /* CL register (for shifts) */ 46 #define OpImmByte 10ull /* 8-bit sign extended immediate */ 47 #define OpOne 11ull /* Implied 1 */ 48 #define OpImm 12ull /* Sign extended up to 32-bit immediate */ 49 #define OpMem16 13ull /* Memory operand (16-bit). */ 50 #define OpMem32 14ull /* Memory operand (32-bit). */ 51 #define OpImmU 15ull /* Immediate operand, zero extended */ 52 #define OpSI 16ull /* SI/ESI/RSI */ 53 #define OpImmFAddr 17ull /* Immediate far address */ 54 #define OpMemFAddr 18ull /* Far address in memory */ 55 #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */ 56 #define OpES 20ull /* ES */ 57 #define OpCS 21ull /* CS */ 58 #define OpSS 22ull /* SS */ 59 #define OpDS 23ull /* DS */ 60 #define OpFS 24ull /* FS */ 61 #define OpGS 25ull /* GS */ 62 #define OpMem8 26ull /* 8-bit zero extended memory operand */ 63 #define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */ 64 #define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */ 65 #define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */ 66 #define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */ 67 68 #define OpBits 5 /* Width of operand field */ 69 #define OpMask ((1ull << OpBits) - 1) 70 71 /* 72 * Opcode effective-address decode tables. 73 * Note that we only emulate instructions that have at least one memory 74 * operand (excluding implicit stack references). We assume that stack 75 * references and instruction fetches will never occur in special memory 76 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need 77 * not be handled. 78 */ 79 80 /* Operand sizes: 8-bit operands or specified/overridden size. */ 81 #define ByteOp (1<<0) /* 8-bit operands. */ 82 /* Destination operand type. */ 83 #define DstShift 1 84 #define ImplicitOps (OpImplicit << DstShift) 85 #define DstReg (OpReg << DstShift) 86 #define DstMem (OpMem << DstShift) 87 #define DstAcc (OpAcc << DstShift) 88 #define DstDI (OpDI << DstShift) 89 #define DstMem64 (OpMem64 << DstShift) 90 #define DstMem16 (OpMem16 << DstShift) 91 #define DstImmUByte (OpImmUByte << DstShift) 92 #define DstDX (OpDX << DstShift) 93 #define DstAccLo (OpAccLo << DstShift) 94 #define DstMask (OpMask << DstShift) 95 /* Source operand type. */ 96 #define SrcShift 6 97 #define SrcNone (OpNone << SrcShift) 98 #define SrcReg (OpReg << SrcShift) 99 #define SrcMem (OpMem << SrcShift) 100 #define SrcMem16 (OpMem16 << SrcShift) 101 #define SrcMem32 (OpMem32 << SrcShift) 102 #define SrcImm (OpImm << SrcShift) 103 #define SrcImmByte (OpImmByte << SrcShift) 104 #define SrcOne (OpOne << SrcShift) 105 #define SrcImmUByte (OpImmUByte << SrcShift) 106 #define SrcImmU (OpImmU << SrcShift) 107 #define SrcSI (OpSI << SrcShift) 108 #define SrcXLat (OpXLat << SrcShift) 109 #define SrcImmFAddr (OpImmFAddr << SrcShift) 110 #define SrcMemFAddr (OpMemFAddr << SrcShift) 111 #define SrcAcc (OpAcc << SrcShift) 112 #define SrcImmU16 (OpImmU16 << SrcShift) 113 #define SrcImm64 (OpImm64 << SrcShift) 114 #define SrcDX (OpDX << SrcShift) 115 #define SrcMem8 (OpMem8 << SrcShift) 116 #define SrcAccHi (OpAccHi << SrcShift) 117 #define SrcMask (OpMask << SrcShift) 118 #define BitOp (1<<11) 119 #define MemAbs (1<<12) /* Memory operand is absolute displacement */ 120 #define String (1<<13) /* String instruction (rep capable) */ 121 #define Stack (1<<14) /* Stack instruction (push/pop) */ 122 #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */ 123 #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */ 124 #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */ 125 #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */ 126 #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */ 127 #define Escape (5<<15) /* Escape to coprocessor instruction */ 128 #define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */ 129 #define ModeDual (7<<15) /* Different instruction for 32/64 bit */ 130 #define Sse (1<<18) /* SSE Vector instruction */ 131 /* Generic ModRM decode. */ 132 #define ModRM (1<<19) 133 /* Destination is only written; never read. */ 134 #define Mov (1<<20) 135 /* Misc flags */ 136 #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */ 137 #define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */ 138 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ 139 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ 140 #define Undefined (1<<25) /* No Such Instruction */ 141 #define Lock (1<<26) /* lock prefix is allowed for the instruction */ 142 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ 143 #define No64 (1<<28) 144 #define PageTable (1 << 29) /* instruction used to write page table */ 145 #define NotImpl (1 << 30) /* instruction is not implemented */ 146 /* Source 2 operand type */ 147 #define Src2Shift (31) 148 #define Src2None (OpNone << Src2Shift) 149 #define Src2Mem (OpMem << Src2Shift) 150 #define Src2CL (OpCL << Src2Shift) 151 #define Src2ImmByte (OpImmByte << Src2Shift) 152 #define Src2One (OpOne << Src2Shift) 153 #define Src2Imm (OpImm << Src2Shift) 154 #define Src2ES (OpES << Src2Shift) 155 #define Src2CS (OpCS << Src2Shift) 156 #define Src2SS (OpSS << Src2Shift) 157 #define Src2DS (OpDS << Src2Shift) 158 #define Src2FS (OpFS << Src2Shift) 159 #define Src2GS (OpGS << Src2Shift) 160 #define Src2Mask (OpMask << Src2Shift) 161 #define Mmx ((u64)1 << 40) /* MMX Vector instruction */ 162 #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */ 163 #define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */ 164 #define Avx ((u64)1 << 43) /* Advanced Vector Extensions */ 165 #define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */ 166 #define NoWrite ((u64)1 << 45) /* No writeback */ 167 #define SrcWrite ((u64)1 << 46) /* Write back src operand */ 168 #define NoMod ((u64)1 << 47) /* Mod field is ignored */ 169 #define Intercept ((u64)1 << 48) /* Has valid intercept field */ 170 #define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */ 171 #define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */ 172 #define NearBranch ((u64)1 << 52) /* Near branches */ 173 #define No16 ((u64)1 << 53) /* No 16 bit operand */ 174 #define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */ 175 176 #define DstXacc (DstAccLo | SrcAccHi | SrcWrite) 177 178 #define X2(x...) x, x 179 #define X3(x...) X2(x), x 180 #define X4(x...) X2(x), X2(x) 181 #define X5(x...) X4(x), x 182 #define X6(x...) X4(x), X2(x) 183 #define X7(x...) X4(x), X3(x) 184 #define X8(x...) X4(x), X4(x) 185 #define X16(x...) X8(x), X8(x) 186 187 #define NR_FASTOP (ilog2(sizeof(ulong)) + 1) 188 #define FASTOP_SIZE 8 189 190 /* 191 * fastop functions have a special calling convention: 192 * 193 * dst: rax (in/out) 194 * src: rdx (in/out) 195 * src2: rcx (in) 196 * flags: rflags (in/out) 197 * ex: rsi (in:fastop pointer, out:zero if exception) 198 * 199 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for 200 * different operand sizes can be reached by calculation, rather than a jump 201 * table (which would be bigger than the code). 202 * 203 * fastop functions are declared as taking a never-defined fastop parameter, 204 * so they can't be called from C directly. 205 */ 206 207 struct fastop; 208 209 struct opcode { 210 u64 flags : 56; 211 u64 intercept : 8; 212 union { 213 int (*execute)(struct x86_emulate_ctxt *ctxt); 214 const struct opcode *group; 215 const struct group_dual *gdual; 216 const struct gprefix *gprefix; 217 const struct escape *esc; 218 const struct instr_dual *idual; 219 const struct mode_dual *mdual; 220 void (*fastop)(struct fastop *fake); 221 } u; 222 int (*check_perm)(struct x86_emulate_ctxt *ctxt); 223 }; 224 225 struct group_dual { 226 struct opcode mod012[8]; 227 struct opcode mod3[8]; 228 }; 229 230 struct gprefix { 231 struct opcode pfx_no; 232 struct opcode pfx_66; 233 struct opcode pfx_f2; 234 struct opcode pfx_f3; 235 }; 236 237 struct escape { 238 struct opcode op[8]; 239 struct opcode high[64]; 240 }; 241 242 struct instr_dual { 243 struct opcode mod012; 244 struct opcode mod3; 245 }; 246 247 struct mode_dual { 248 struct opcode mode32; 249 struct opcode mode64; 250 }; 251 252 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a 253 254 enum x86_transfer_type { 255 X86_TRANSFER_NONE, 256 X86_TRANSFER_CALL_JMP, 257 X86_TRANSFER_RET, 258 X86_TRANSFER_TASK_SWITCH, 259 }; 260 261 static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr) 262 { 263 if (!(ctxt->regs_valid & (1 << nr))) { 264 ctxt->regs_valid |= 1 << nr; 265 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr); 266 } 267 return ctxt->_regs[nr]; 268 } 269 270 static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr) 271 { 272 ctxt->regs_valid |= 1 << nr; 273 ctxt->regs_dirty |= 1 << nr; 274 return &ctxt->_regs[nr]; 275 } 276 277 static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr) 278 { 279 reg_read(ctxt, nr); 280 return reg_write(ctxt, nr); 281 } 282 283 static void writeback_registers(struct x86_emulate_ctxt *ctxt) 284 { 285 unsigned reg; 286 287 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16) 288 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]); 289 } 290 291 static void invalidate_registers(struct x86_emulate_ctxt *ctxt) 292 { 293 ctxt->regs_dirty = 0; 294 ctxt->regs_valid = 0; 295 } 296 297 /* 298 * These EFLAGS bits are restored from saved value during emulation, and 299 * any changes are written back to the saved value after emulation. 300 */ 301 #define EFLAGS_MASK (X86_EFLAGS_OF|X86_EFLAGS_SF|X86_EFLAGS_ZF|X86_EFLAGS_AF|\ 302 X86_EFLAGS_PF|X86_EFLAGS_CF) 303 304 #ifdef CONFIG_X86_64 305 #define ON64(x) x 306 #else 307 #define ON64(x) 308 #endif 309 310 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *)); 311 312 #define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t" 313 #define FOP_RET "ret \n\t" 314 315 #define FOP_START(op) \ 316 extern void em_##op(struct fastop *fake); \ 317 asm(".pushsection .text, \"ax\" \n\t" \ 318 ".global em_" #op " \n\t" \ 319 FOP_ALIGN \ 320 "em_" #op ": \n\t" 321 322 #define FOP_END \ 323 ".popsection") 324 325 #define FOPNOP() FOP_ALIGN FOP_RET 326 327 #define FOP1E(op, dst) \ 328 FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET 329 330 #define FOP1EEX(op, dst) \ 331 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception) 332 333 #define FASTOP1(op) \ 334 FOP_START(op) \ 335 FOP1E(op##b, al) \ 336 FOP1E(op##w, ax) \ 337 FOP1E(op##l, eax) \ 338 ON64(FOP1E(op##q, rax)) \ 339 FOP_END 340 341 /* 1-operand, using src2 (for MUL/DIV r/m) */ 342 #define FASTOP1SRC2(op, name) \ 343 FOP_START(name) \ 344 FOP1E(op, cl) \ 345 FOP1E(op, cx) \ 346 FOP1E(op, ecx) \ 347 ON64(FOP1E(op, rcx)) \ 348 FOP_END 349 350 /* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */ 351 #define FASTOP1SRC2EX(op, name) \ 352 FOP_START(name) \ 353 FOP1EEX(op, cl) \ 354 FOP1EEX(op, cx) \ 355 FOP1EEX(op, ecx) \ 356 ON64(FOP1EEX(op, rcx)) \ 357 FOP_END 358 359 #define FOP2E(op, dst, src) \ 360 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET 361 362 #define FASTOP2(op) \ 363 FOP_START(op) \ 364 FOP2E(op##b, al, dl) \ 365 FOP2E(op##w, ax, dx) \ 366 FOP2E(op##l, eax, edx) \ 367 ON64(FOP2E(op##q, rax, rdx)) \ 368 FOP_END 369 370 /* 2 operand, word only */ 371 #define FASTOP2W(op) \ 372 FOP_START(op) \ 373 FOPNOP() \ 374 FOP2E(op##w, ax, dx) \ 375 FOP2E(op##l, eax, edx) \ 376 ON64(FOP2E(op##q, rax, rdx)) \ 377 FOP_END 378 379 /* 2 operand, src is CL */ 380 #define FASTOP2CL(op) \ 381 FOP_START(op) \ 382 FOP2E(op##b, al, cl) \ 383 FOP2E(op##w, ax, cl) \ 384 FOP2E(op##l, eax, cl) \ 385 ON64(FOP2E(op##q, rax, cl)) \ 386 FOP_END 387 388 /* 2 operand, src and dest are reversed */ 389 #define FASTOP2R(op, name) \ 390 FOP_START(name) \ 391 FOP2E(op##b, dl, al) \ 392 FOP2E(op##w, dx, ax) \ 393 FOP2E(op##l, edx, eax) \ 394 ON64(FOP2E(op##q, rdx, rax)) \ 395 FOP_END 396 397 #define FOP3E(op, dst, src, src2) \ 398 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET 399 400 /* 3-operand, word-only, src2=cl */ 401 #define FASTOP3WCL(op) \ 402 FOP_START(op) \ 403 FOPNOP() \ 404 FOP3E(op##w, ax, dx, cl) \ 405 FOP3E(op##l, eax, edx, cl) \ 406 ON64(FOP3E(op##q, rax, rdx, cl)) \ 407 FOP_END 408 409 /* Special case for SETcc - 1 instruction per cc */ 410 #define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t" 411 412 asm(".global kvm_fastop_exception \n" 413 "kvm_fastop_exception: xor %esi, %esi; ret"); 414 415 FOP_START(setcc) 416 FOP_SETCC(seto) 417 FOP_SETCC(setno) 418 FOP_SETCC(setc) 419 FOP_SETCC(setnc) 420 FOP_SETCC(setz) 421 FOP_SETCC(setnz) 422 FOP_SETCC(setbe) 423 FOP_SETCC(setnbe) 424 FOP_SETCC(sets) 425 FOP_SETCC(setns) 426 FOP_SETCC(setp) 427 FOP_SETCC(setnp) 428 FOP_SETCC(setl) 429 FOP_SETCC(setnl) 430 FOP_SETCC(setle) 431 FOP_SETCC(setnle) 432 FOP_END; 433 434 FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET 435 FOP_END; 436 437 static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt, 438 enum x86_intercept intercept, 439 enum x86_intercept_stage stage) 440 { 441 struct x86_instruction_info info = { 442 .intercept = intercept, 443 .rep_prefix = ctxt->rep_prefix, 444 .modrm_mod = ctxt->modrm_mod, 445 .modrm_reg = ctxt->modrm_reg, 446 .modrm_rm = ctxt->modrm_rm, 447 .src_val = ctxt->src.val64, 448 .dst_val = ctxt->dst.val64, 449 .src_bytes = ctxt->src.bytes, 450 .dst_bytes = ctxt->dst.bytes, 451 .ad_bytes = ctxt->ad_bytes, 452 .next_rip = ctxt->eip, 453 }; 454 455 return ctxt->ops->intercept(ctxt, &info, stage); 456 } 457 458 static void assign_masked(ulong *dest, ulong src, ulong mask) 459 { 460 *dest = (*dest & ~mask) | (src & mask); 461 } 462 463 static void assign_register(unsigned long *reg, u64 val, int bytes) 464 { 465 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ 466 switch (bytes) { 467 case 1: 468 *(u8 *)reg = (u8)val; 469 break; 470 case 2: 471 *(u16 *)reg = (u16)val; 472 break; 473 case 4: 474 *reg = (u32)val; 475 break; /* 64b: zero-extend */ 476 case 8: 477 *reg = val; 478 break; 479 } 480 } 481 482 static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt) 483 { 484 return (1UL << (ctxt->ad_bytes << 3)) - 1; 485 } 486 487 static ulong stack_mask(struct x86_emulate_ctxt *ctxt) 488 { 489 u16 sel; 490 struct desc_struct ss; 491 492 if (ctxt->mode == X86EMUL_MODE_PROT64) 493 return ~0UL; 494 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS); 495 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */ 496 } 497 498 static int stack_size(struct x86_emulate_ctxt *ctxt) 499 { 500 return (__fls(stack_mask(ctxt)) + 1) >> 3; 501 } 502 503 /* Access/update address held in a register, based on addressing mode. */ 504 static inline unsigned long 505 address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg) 506 { 507 if (ctxt->ad_bytes == sizeof(unsigned long)) 508 return reg; 509 else 510 return reg & ad_mask(ctxt); 511 } 512 513 static inline unsigned long 514 register_address(struct x86_emulate_ctxt *ctxt, int reg) 515 { 516 return address_mask(ctxt, reg_read(ctxt, reg)); 517 } 518 519 static void masked_increment(ulong *reg, ulong mask, int inc) 520 { 521 assign_masked(reg, *reg + inc, mask); 522 } 523 524 static inline void 525 register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc) 526 { 527 ulong *preg = reg_rmw(ctxt, reg); 528 529 assign_register(preg, *preg + inc, ctxt->ad_bytes); 530 } 531 532 static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc) 533 { 534 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc); 535 } 536 537 static u32 desc_limit_scaled(struct desc_struct *desc) 538 { 539 u32 limit = get_desc_limit(desc); 540 541 return desc->g ? (limit << 12) | 0xfff : limit; 542 } 543 544 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) 545 { 546 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) 547 return 0; 548 549 return ctxt->ops->get_cached_segment_base(ctxt, seg); 550 } 551 552 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, 553 u32 error, bool valid) 554 { 555 WARN_ON(vec > 0x1f); 556 ctxt->exception.vector = vec; 557 ctxt->exception.error_code = error; 558 ctxt->exception.error_code_valid = valid; 559 return X86EMUL_PROPAGATE_FAULT; 560 } 561 562 static int emulate_db(struct x86_emulate_ctxt *ctxt) 563 { 564 return emulate_exception(ctxt, DB_VECTOR, 0, false); 565 } 566 567 static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err) 568 { 569 return emulate_exception(ctxt, GP_VECTOR, err, true); 570 } 571 572 static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err) 573 { 574 return emulate_exception(ctxt, SS_VECTOR, err, true); 575 } 576 577 static int emulate_ud(struct x86_emulate_ctxt *ctxt) 578 { 579 return emulate_exception(ctxt, UD_VECTOR, 0, false); 580 } 581 582 static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err) 583 { 584 return emulate_exception(ctxt, TS_VECTOR, err, true); 585 } 586 587 static int emulate_de(struct x86_emulate_ctxt *ctxt) 588 { 589 return emulate_exception(ctxt, DE_VECTOR, 0, false); 590 } 591 592 static int emulate_nm(struct x86_emulate_ctxt *ctxt) 593 { 594 return emulate_exception(ctxt, NM_VECTOR, 0, false); 595 } 596 597 static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg) 598 { 599 u16 selector; 600 struct desc_struct desc; 601 602 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg); 603 return selector; 604 } 605 606 static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector, 607 unsigned seg) 608 { 609 u16 dummy; 610 u32 base3; 611 struct desc_struct desc; 612 613 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg); 614 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg); 615 } 616 617 /* 618 * x86 defines three classes of vector instructions: explicitly 619 * aligned, explicitly unaligned, and the rest, which change behaviour 620 * depending on whether they're AVX encoded or not. 621 * 622 * Also included is CMPXCHG16B which is not a vector instruction, yet it is 623 * subject to the same check. 624 */ 625 static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size) 626 { 627 if (likely(size < 16)) 628 return false; 629 630 if (ctxt->d & Aligned) 631 return true; 632 else if (ctxt->d & Unaligned) 633 return false; 634 else if (ctxt->d & Avx) 635 return false; 636 else 637 return true; 638 } 639 640 static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt, 641 struct segmented_address addr, 642 unsigned *max_size, unsigned size, 643 bool write, bool fetch, 644 enum x86emul_mode mode, ulong *linear) 645 { 646 struct desc_struct desc; 647 bool usable; 648 ulong la; 649 u32 lim; 650 u16 sel; 651 652 la = seg_base(ctxt, addr.seg) + addr.ea; 653 *linear = la; 654 *max_size = 0; 655 switch (mode) { 656 case X86EMUL_MODE_PROT64: 657 if (is_noncanonical_address(la)) 658 goto bad; 659 660 *max_size = min_t(u64, ~0u, (1ull << 48) - la); 661 if (size > *max_size) 662 goto bad; 663 break; 664 default: 665 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL, 666 addr.seg); 667 if (!usable) 668 goto bad; 669 /* code segment in protected mode or read-only data segment */ 670 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8)) 671 || !(desc.type & 2)) && write) 672 goto bad; 673 /* unreadable code segment */ 674 if (!fetch && (desc.type & 8) && !(desc.type & 2)) 675 goto bad; 676 lim = desc_limit_scaled(&desc); 677 if (!(desc.type & 8) && (desc.type & 4)) { 678 /* expand-down segment */ 679 if (addr.ea <= lim) 680 goto bad; 681 lim = desc.d ? 0xffffffff : 0xffff; 682 } 683 if (addr.ea > lim) 684 goto bad; 685 if (lim == 0xffffffff) 686 *max_size = ~0u; 687 else { 688 *max_size = (u64)lim + 1 - addr.ea; 689 if (size > *max_size) 690 goto bad; 691 } 692 la &= (u32)-1; 693 break; 694 } 695 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0)) 696 return emulate_gp(ctxt, 0); 697 return X86EMUL_CONTINUE; 698 bad: 699 if (addr.seg == VCPU_SREG_SS) 700 return emulate_ss(ctxt, 0); 701 else 702 return emulate_gp(ctxt, 0); 703 } 704 705 static int linearize(struct x86_emulate_ctxt *ctxt, 706 struct segmented_address addr, 707 unsigned size, bool write, 708 ulong *linear) 709 { 710 unsigned max_size; 711 return __linearize(ctxt, addr, &max_size, size, write, false, 712 ctxt->mode, linear); 713 } 714 715 static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst, 716 enum x86emul_mode mode) 717 { 718 ulong linear; 719 int rc; 720 unsigned max_size; 721 struct segmented_address addr = { .seg = VCPU_SREG_CS, 722 .ea = dst }; 723 724 if (ctxt->op_bytes != sizeof(unsigned long)) 725 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1); 726 rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear); 727 if (rc == X86EMUL_CONTINUE) 728 ctxt->_eip = addr.ea; 729 return rc; 730 } 731 732 static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst) 733 { 734 return assign_eip(ctxt, dst, ctxt->mode); 735 } 736 737 static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst, 738 const struct desc_struct *cs_desc) 739 { 740 enum x86emul_mode mode = ctxt->mode; 741 int rc; 742 743 #ifdef CONFIG_X86_64 744 if (ctxt->mode >= X86EMUL_MODE_PROT16) { 745 if (cs_desc->l) { 746 u64 efer = 0; 747 748 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 749 if (efer & EFER_LMA) 750 mode = X86EMUL_MODE_PROT64; 751 } else 752 mode = X86EMUL_MODE_PROT32; /* temporary value */ 753 } 754 #endif 755 if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32) 756 mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; 757 rc = assign_eip(ctxt, dst, mode); 758 if (rc == X86EMUL_CONTINUE) 759 ctxt->mode = mode; 760 return rc; 761 } 762 763 static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel) 764 { 765 return assign_eip_near(ctxt, ctxt->_eip + rel); 766 } 767 768 static int segmented_read_std(struct x86_emulate_ctxt *ctxt, 769 struct segmented_address addr, 770 void *data, 771 unsigned size) 772 { 773 int rc; 774 ulong linear; 775 776 rc = linearize(ctxt, addr, size, false, &linear); 777 if (rc != X86EMUL_CONTINUE) 778 return rc; 779 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception); 780 } 781 782 /* 783 * Prefetch the remaining bytes of the instruction without crossing page 784 * boundary if they are not in fetch_cache yet. 785 */ 786 static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size) 787 { 788 int rc; 789 unsigned size, max_size; 790 unsigned long linear; 791 int cur_size = ctxt->fetch.end - ctxt->fetch.data; 792 struct segmented_address addr = { .seg = VCPU_SREG_CS, 793 .ea = ctxt->eip + cur_size }; 794 795 /* 796 * We do not know exactly how many bytes will be needed, and 797 * __linearize is expensive, so fetch as much as possible. We 798 * just have to avoid going beyond the 15 byte limit, the end 799 * of the segment, or the end of the page. 800 * 801 * __linearize is called with size 0 so that it does not do any 802 * boundary check itself. Instead, we use max_size to check 803 * against op_size. 804 */ 805 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode, 806 &linear); 807 if (unlikely(rc != X86EMUL_CONTINUE)) 808 return rc; 809 810 size = min_t(unsigned, 15UL ^ cur_size, max_size); 811 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear)); 812 813 /* 814 * One instruction can only straddle two pages, 815 * and one has been loaded at the beginning of 816 * x86_decode_insn. So, if not enough bytes 817 * still, we must have hit the 15-byte boundary. 818 */ 819 if (unlikely(size < op_size)) 820 return emulate_gp(ctxt, 0); 821 822 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end, 823 size, &ctxt->exception); 824 if (unlikely(rc != X86EMUL_CONTINUE)) 825 return rc; 826 ctxt->fetch.end += size; 827 return X86EMUL_CONTINUE; 828 } 829 830 static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, 831 unsigned size) 832 { 833 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr; 834 835 if (unlikely(done_size < size)) 836 return __do_insn_fetch_bytes(ctxt, size - done_size); 837 else 838 return X86EMUL_CONTINUE; 839 } 840 841 /* Fetch next part of the instruction being emulated. */ 842 #define insn_fetch(_type, _ctxt) \ 843 ({ _type _x; \ 844 \ 845 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \ 846 if (rc != X86EMUL_CONTINUE) \ 847 goto done; \ 848 ctxt->_eip += sizeof(_type); \ 849 _x = *(_type __aligned(1) *) ctxt->fetch.ptr; \ 850 ctxt->fetch.ptr += sizeof(_type); \ 851 _x; \ 852 }) 853 854 #define insn_fetch_arr(_arr, _size, _ctxt) \ 855 ({ \ 856 rc = do_insn_fetch_bytes(_ctxt, _size); \ 857 if (rc != X86EMUL_CONTINUE) \ 858 goto done; \ 859 ctxt->_eip += (_size); \ 860 memcpy(_arr, ctxt->fetch.ptr, _size); \ 861 ctxt->fetch.ptr += (_size); \ 862 }) 863 864 /* 865 * Given the 'reg' portion of a ModRM byte, and a register block, return a 866 * pointer into the block that addresses the relevant register. 867 * @highbyte_regs specifies whether to decode AH,CH,DH,BH. 868 */ 869 static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg, 870 int byteop) 871 { 872 void *p; 873 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop; 874 875 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) 876 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1; 877 else 878 p = reg_rmw(ctxt, modrm_reg); 879 return p; 880 } 881 882 static int read_descriptor(struct x86_emulate_ctxt *ctxt, 883 struct segmented_address addr, 884 u16 *size, unsigned long *address, int op_bytes) 885 { 886 int rc; 887 888 if (op_bytes == 2) 889 op_bytes = 3; 890 *address = 0; 891 rc = segmented_read_std(ctxt, addr, size, 2); 892 if (rc != X86EMUL_CONTINUE) 893 return rc; 894 addr.ea += 2; 895 rc = segmented_read_std(ctxt, addr, address, op_bytes); 896 return rc; 897 } 898 899 FASTOP2(add); 900 FASTOP2(or); 901 FASTOP2(adc); 902 FASTOP2(sbb); 903 FASTOP2(and); 904 FASTOP2(sub); 905 FASTOP2(xor); 906 FASTOP2(cmp); 907 FASTOP2(test); 908 909 FASTOP1SRC2(mul, mul_ex); 910 FASTOP1SRC2(imul, imul_ex); 911 FASTOP1SRC2EX(div, div_ex); 912 FASTOP1SRC2EX(idiv, idiv_ex); 913 914 FASTOP3WCL(shld); 915 FASTOP3WCL(shrd); 916 917 FASTOP2W(imul); 918 919 FASTOP1(not); 920 FASTOP1(neg); 921 FASTOP1(inc); 922 FASTOP1(dec); 923 924 FASTOP2CL(rol); 925 FASTOP2CL(ror); 926 FASTOP2CL(rcl); 927 FASTOP2CL(rcr); 928 FASTOP2CL(shl); 929 FASTOP2CL(shr); 930 FASTOP2CL(sar); 931 932 FASTOP2W(bsf); 933 FASTOP2W(bsr); 934 FASTOP2W(bt); 935 FASTOP2W(bts); 936 FASTOP2W(btr); 937 FASTOP2W(btc); 938 939 FASTOP2(xadd); 940 941 FASTOP2R(cmp, cmp_r); 942 943 static int em_bsf_c(struct x86_emulate_ctxt *ctxt) 944 { 945 /* If src is zero, do not writeback, but update flags */ 946 if (ctxt->src.val == 0) 947 ctxt->dst.type = OP_NONE; 948 return fastop(ctxt, em_bsf); 949 } 950 951 static int em_bsr_c(struct x86_emulate_ctxt *ctxt) 952 { 953 /* If src is zero, do not writeback, but update flags */ 954 if (ctxt->src.val == 0) 955 ctxt->dst.type = OP_NONE; 956 return fastop(ctxt, em_bsr); 957 } 958 959 static u8 test_cc(unsigned int condition, unsigned long flags) 960 { 961 u8 rc; 962 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf); 963 964 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF; 965 asm("push %[flags]; popf; call *%[fastop]" 966 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags)); 967 return rc; 968 } 969 970 static void fetch_register_operand(struct operand *op) 971 { 972 switch (op->bytes) { 973 case 1: 974 op->val = *(u8 *)op->addr.reg; 975 break; 976 case 2: 977 op->val = *(u16 *)op->addr.reg; 978 break; 979 case 4: 980 op->val = *(u32 *)op->addr.reg; 981 break; 982 case 8: 983 op->val = *(u64 *)op->addr.reg; 984 break; 985 } 986 } 987 988 static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg) 989 { 990 ctxt->ops->get_fpu(ctxt); 991 switch (reg) { 992 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break; 993 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break; 994 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break; 995 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break; 996 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break; 997 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break; 998 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break; 999 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break; 1000 #ifdef CONFIG_X86_64 1001 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break; 1002 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break; 1003 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break; 1004 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break; 1005 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break; 1006 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break; 1007 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break; 1008 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break; 1009 #endif 1010 default: BUG(); 1011 } 1012 ctxt->ops->put_fpu(ctxt); 1013 } 1014 1015 static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, 1016 int reg) 1017 { 1018 ctxt->ops->get_fpu(ctxt); 1019 switch (reg) { 1020 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break; 1021 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break; 1022 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break; 1023 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break; 1024 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break; 1025 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break; 1026 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break; 1027 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break; 1028 #ifdef CONFIG_X86_64 1029 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break; 1030 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break; 1031 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break; 1032 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break; 1033 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break; 1034 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break; 1035 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break; 1036 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break; 1037 #endif 1038 default: BUG(); 1039 } 1040 ctxt->ops->put_fpu(ctxt); 1041 } 1042 1043 static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) 1044 { 1045 ctxt->ops->get_fpu(ctxt); 1046 switch (reg) { 1047 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break; 1048 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break; 1049 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break; 1050 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break; 1051 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break; 1052 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break; 1053 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break; 1054 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break; 1055 default: BUG(); 1056 } 1057 ctxt->ops->put_fpu(ctxt); 1058 } 1059 1060 static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) 1061 { 1062 ctxt->ops->get_fpu(ctxt); 1063 switch (reg) { 1064 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break; 1065 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break; 1066 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break; 1067 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break; 1068 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break; 1069 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break; 1070 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break; 1071 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break; 1072 default: BUG(); 1073 } 1074 ctxt->ops->put_fpu(ctxt); 1075 } 1076 1077 static int em_fninit(struct x86_emulate_ctxt *ctxt) 1078 { 1079 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1080 return emulate_nm(ctxt); 1081 1082 ctxt->ops->get_fpu(ctxt); 1083 asm volatile("fninit"); 1084 ctxt->ops->put_fpu(ctxt); 1085 return X86EMUL_CONTINUE; 1086 } 1087 1088 static int em_fnstcw(struct x86_emulate_ctxt *ctxt) 1089 { 1090 u16 fcw; 1091 1092 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1093 return emulate_nm(ctxt); 1094 1095 ctxt->ops->get_fpu(ctxt); 1096 asm volatile("fnstcw %0": "+m"(fcw)); 1097 ctxt->ops->put_fpu(ctxt); 1098 1099 ctxt->dst.val = fcw; 1100 1101 return X86EMUL_CONTINUE; 1102 } 1103 1104 static int em_fnstsw(struct x86_emulate_ctxt *ctxt) 1105 { 1106 u16 fsw; 1107 1108 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1109 return emulate_nm(ctxt); 1110 1111 ctxt->ops->get_fpu(ctxt); 1112 asm volatile("fnstsw %0": "+m"(fsw)); 1113 ctxt->ops->put_fpu(ctxt); 1114 1115 ctxt->dst.val = fsw; 1116 1117 return X86EMUL_CONTINUE; 1118 } 1119 1120 static void decode_register_operand(struct x86_emulate_ctxt *ctxt, 1121 struct operand *op) 1122 { 1123 unsigned reg = ctxt->modrm_reg; 1124 1125 if (!(ctxt->d & ModRM)) 1126 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3); 1127 1128 if (ctxt->d & Sse) { 1129 op->type = OP_XMM; 1130 op->bytes = 16; 1131 op->addr.xmm = reg; 1132 read_sse_reg(ctxt, &op->vec_val, reg); 1133 return; 1134 } 1135 if (ctxt->d & Mmx) { 1136 reg &= 7; 1137 op->type = OP_MM; 1138 op->bytes = 8; 1139 op->addr.mm = reg; 1140 return; 1141 } 1142 1143 op->type = OP_REG; 1144 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 1145 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp); 1146 1147 fetch_register_operand(op); 1148 op->orig_val = op->val; 1149 } 1150 1151 static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg) 1152 { 1153 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP) 1154 ctxt->modrm_seg = VCPU_SREG_SS; 1155 } 1156 1157 static int decode_modrm(struct x86_emulate_ctxt *ctxt, 1158 struct operand *op) 1159 { 1160 u8 sib; 1161 int index_reg, base_reg, scale; 1162 int rc = X86EMUL_CONTINUE; 1163 ulong modrm_ea = 0; 1164 1165 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */ 1166 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */ 1167 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */ 1168 1169 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6; 1170 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3; 1171 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07); 1172 ctxt->modrm_seg = VCPU_SREG_DS; 1173 1174 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) { 1175 op->type = OP_REG; 1176 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 1177 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, 1178 ctxt->d & ByteOp); 1179 if (ctxt->d & Sse) { 1180 op->type = OP_XMM; 1181 op->bytes = 16; 1182 op->addr.xmm = ctxt->modrm_rm; 1183 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm); 1184 return rc; 1185 } 1186 if (ctxt->d & Mmx) { 1187 op->type = OP_MM; 1188 op->bytes = 8; 1189 op->addr.mm = ctxt->modrm_rm & 7; 1190 return rc; 1191 } 1192 fetch_register_operand(op); 1193 return rc; 1194 } 1195 1196 op->type = OP_MEM; 1197 1198 if (ctxt->ad_bytes == 2) { 1199 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX); 1200 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP); 1201 unsigned si = reg_read(ctxt, VCPU_REGS_RSI); 1202 unsigned di = reg_read(ctxt, VCPU_REGS_RDI); 1203 1204 /* 16-bit ModR/M decode. */ 1205 switch (ctxt->modrm_mod) { 1206 case 0: 1207 if (ctxt->modrm_rm == 6) 1208 modrm_ea += insn_fetch(u16, ctxt); 1209 break; 1210 case 1: 1211 modrm_ea += insn_fetch(s8, ctxt); 1212 break; 1213 case 2: 1214 modrm_ea += insn_fetch(u16, ctxt); 1215 break; 1216 } 1217 switch (ctxt->modrm_rm) { 1218 case 0: 1219 modrm_ea += bx + si; 1220 break; 1221 case 1: 1222 modrm_ea += bx + di; 1223 break; 1224 case 2: 1225 modrm_ea += bp + si; 1226 break; 1227 case 3: 1228 modrm_ea += bp + di; 1229 break; 1230 case 4: 1231 modrm_ea += si; 1232 break; 1233 case 5: 1234 modrm_ea += di; 1235 break; 1236 case 6: 1237 if (ctxt->modrm_mod != 0) 1238 modrm_ea += bp; 1239 break; 1240 case 7: 1241 modrm_ea += bx; 1242 break; 1243 } 1244 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 || 1245 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0)) 1246 ctxt->modrm_seg = VCPU_SREG_SS; 1247 modrm_ea = (u16)modrm_ea; 1248 } else { 1249 /* 32/64-bit ModR/M decode. */ 1250 if ((ctxt->modrm_rm & 7) == 4) { 1251 sib = insn_fetch(u8, ctxt); 1252 index_reg |= (sib >> 3) & 7; 1253 base_reg |= sib & 7; 1254 scale = sib >> 6; 1255 1256 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0) 1257 modrm_ea += insn_fetch(s32, ctxt); 1258 else { 1259 modrm_ea += reg_read(ctxt, base_reg); 1260 adjust_modrm_seg(ctxt, base_reg); 1261 /* Increment ESP on POP [ESP] */ 1262 if ((ctxt->d & IncSP) && 1263 base_reg == VCPU_REGS_RSP) 1264 modrm_ea += ctxt->op_bytes; 1265 } 1266 if (index_reg != 4) 1267 modrm_ea += reg_read(ctxt, index_reg) << scale; 1268 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) { 1269 modrm_ea += insn_fetch(s32, ctxt); 1270 if (ctxt->mode == X86EMUL_MODE_PROT64) 1271 ctxt->rip_relative = 1; 1272 } else { 1273 base_reg = ctxt->modrm_rm; 1274 modrm_ea += reg_read(ctxt, base_reg); 1275 adjust_modrm_seg(ctxt, base_reg); 1276 } 1277 switch (ctxt->modrm_mod) { 1278 case 1: 1279 modrm_ea += insn_fetch(s8, ctxt); 1280 break; 1281 case 2: 1282 modrm_ea += insn_fetch(s32, ctxt); 1283 break; 1284 } 1285 } 1286 op->addr.mem.ea = modrm_ea; 1287 if (ctxt->ad_bytes != 8) 1288 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea; 1289 1290 done: 1291 return rc; 1292 } 1293 1294 static int decode_abs(struct x86_emulate_ctxt *ctxt, 1295 struct operand *op) 1296 { 1297 int rc = X86EMUL_CONTINUE; 1298 1299 op->type = OP_MEM; 1300 switch (ctxt->ad_bytes) { 1301 case 2: 1302 op->addr.mem.ea = insn_fetch(u16, ctxt); 1303 break; 1304 case 4: 1305 op->addr.mem.ea = insn_fetch(u32, ctxt); 1306 break; 1307 case 8: 1308 op->addr.mem.ea = insn_fetch(u64, ctxt); 1309 break; 1310 } 1311 done: 1312 return rc; 1313 } 1314 1315 static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt) 1316 { 1317 long sv = 0, mask; 1318 1319 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) { 1320 mask = ~((long)ctxt->dst.bytes * 8 - 1); 1321 1322 if (ctxt->src.bytes == 2) 1323 sv = (s16)ctxt->src.val & (s16)mask; 1324 else if (ctxt->src.bytes == 4) 1325 sv = (s32)ctxt->src.val & (s32)mask; 1326 else 1327 sv = (s64)ctxt->src.val & (s64)mask; 1328 1329 ctxt->dst.addr.mem.ea = address_mask(ctxt, 1330 ctxt->dst.addr.mem.ea + (sv >> 3)); 1331 } 1332 1333 /* only subword offset */ 1334 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; 1335 } 1336 1337 static int read_emulated(struct x86_emulate_ctxt *ctxt, 1338 unsigned long addr, void *dest, unsigned size) 1339 { 1340 int rc; 1341 struct read_cache *mc = &ctxt->mem_read; 1342 1343 if (mc->pos < mc->end) 1344 goto read_cached; 1345 1346 WARN_ON((mc->end + size) >= sizeof(mc->data)); 1347 1348 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size, 1349 &ctxt->exception); 1350 if (rc != X86EMUL_CONTINUE) 1351 return rc; 1352 1353 mc->end += size; 1354 1355 read_cached: 1356 memcpy(dest, mc->data + mc->pos, size); 1357 mc->pos += size; 1358 return X86EMUL_CONTINUE; 1359 } 1360 1361 static int segmented_read(struct x86_emulate_ctxt *ctxt, 1362 struct segmented_address addr, 1363 void *data, 1364 unsigned size) 1365 { 1366 int rc; 1367 ulong linear; 1368 1369 rc = linearize(ctxt, addr, size, false, &linear); 1370 if (rc != X86EMUL_CONTINUE) 1371 return rc; 1372 return read_emulated(ctxt, linear, data, size); 1373 } 1374 1375 static int segmented_write(struct x86_emulate_ctxt *ctxt, 1376 struct segmented_address addr, 1377 const void *data, 1378 unsigned size) 1379 { 1380 int rc; 1381 ulong linear; 1382 1383 rc = linearize(ctxt, addr, size, true, &linear); 1384 if (rc != X86EMUL_CONTINUE) 1385 return rc; 1386 return ctxt->ops->write_emulated(ctxt, linear, data, size, 1387 &ctxt->exception); 1388 } 1389 1390 static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt, 1391 struct segmented_address addr, 1392 const void *orig_data, const void *data, 1393 unsigned size) 1394 { 1395 int rc; 1396 ulong linear; 1397 1398 rc = linearize(ctxt, addr, size, true, &linear); 1399 if (rc != X86EMUL_CONTINUE) 1400 return rc; 1401 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data, 1402 size, &ctxt->exception); 1403 } 1404 1405 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, 1406 unsigned int size, unsigned short port, 1407 void *dest) 1408 { 1409 struct read_cache *rc = &ctxt->io_read; 1410 1411 if (rc->pos == rc->end) { /* refill pio read ahead */ 1412 unsigned int in_page, n; 1413 unsigned int count = ctxt->rep_prefix ? 1414 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1; 1415 in_page = (ctxt->eflags & X86_EFLAGS_DF) ? 1416 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) : 1417 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)); 1418 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count); 1419 if (n == 0) 1420 n = 1; 1421 rc->pos = rc->end = 0; 1422 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n)) 1423 return 0; 1424 rc->end = n * size; 1425 } 1426 1427 if (ctxt->rep_prefix && (ctxt->d & String) && 1428 !(ctxt->eflags & X86_EFLAGS_DF)) { 1429 ctxt->dst.data = rc->data + rc->pos; 1430 ctxt->dst.type = OP_MEM_STR; 1431 ctxt->dst.count = (rc->end - rc->pos) / size; 1432 rc->pos = rc->end; 1433 } else { 1434 memcpy(dest, rc->data + rc->pos, size); 1435 rc->pos += size; 1436 } 1437 return 1; 1438 } 1439 1440 static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt, 1441 u16 index, struct desc_struct *desc) 1442 { 1443 struct desc_ptr dt; 1444 ulong addr; 1445 1446 ctxt->ops->get_idt(ctxt, &dt); 1447 1448 if (dt.size < index * 8 + 7) 1449 return emulate_gp(ctxt, index << 3 | 0x2); 1450 1451 addr = dt.address + index * 8; 1452 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc, 1453 &ctxt->exception); 1454 } 1455 1456 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, 1457 u16 selector, struct desc_ptr *dt) 1458 { 1459 const struct x86_emulate_ops *ops = ctxt->ops; 1460 u32 base3 = 0; 1461 1462 if (selector & 1 << 2) { 1463 struct desc_struct desc; 1464 u16 sel; 1465 1466 memset (dt, 0, sizeof *dt); 1467 if (!ops->get_segment(ctxt, &sel, &desc, &base3, 1468 VCPU_SREG_LDTR)) 1469 return; 1470 1471 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ 1472 dt->address = get_desc_base(&desc) | ((u64)base3 << 32); 1473 } else 1474 ops->get_gdt(ctxt, dt); 1475 } 1476 1477 static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt, 1478 u16 selector, ulong *desc_addr_p) 1479 { 1480 struct desc_ptr dt; 1481 u16 index = selector >> 3; 1482 ulong addr; 1483 1484 get_descriptor_table_ptr(ctxt, selector, &dt); 1485 1486 if (dt.size < index * 8 + 7) 1487 return emulate_gp(ctxt, selector & 0xfffc); 1488 1489 addr = dt.address + index * 8; 1490 1491 #ifdef CONFIG_X86_64 1492 if (addr >> 32 != 0) { 1493 u64 efer = 0; 1494 1495 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 1496 if (!(efer & EFER_LMA)) 1497 addr &= (u32)-1; 1498 } 1499 #endif 1500 1501 *desc_addr_p = addr; 1502 return X86EMUL_CONTINUE; 1503 } 1504 1505 /* allowed just for 8 bytes segments */ 1506 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1507 u16 selector, struct desc_struct *desc, 1508 ulong *desc_addr_p) 1509 { 1510 int rc; 1511 1512 rc = get_descriptor_ptr(ctxt, selector, desc_addr_p); 1513 if (rc != X86EMUL_CONTINUE) 1514 return rc; 1515 1516 return ctxt->ops->read_std(ctxt, *desc_addr_p, desc, sizeof(*desc), 1517 &ctxt->exception); 1518 } 1519 1520 /* allowed just for 8 bytes segments */ 1521 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1522 u16 selector, struct desc_struct *desc) 1523 { 1524 int rc; 1525 ulong addr; 1526 1527 rc = get_descriptor_ptr(ctxt, selector, &addr); 1528 if (rc != X86EMUL_CONTINUE) 1529 return rc; 1530 1531 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc, 1532 &ctxt->exception); 1533 } 1534 1535 /* Does not support long mode */ 1536 static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1537 u16 selector, int seg, u8 cpl, 1538 enum x86_transfer_type transfer, 1539 struct desc_struct *desc) 1540 { 1541 struct desc_struct seg_desc, old_desc; 1542 u8 dpl, rpl; 1543 unsigned err_vec = GP_VECTOR; 1544 u32 err_code = 0; 1545 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ 1546 ulong desc_addr; 1547 int ret; 1548 u16 dummy; 1549 u32 base3 = 0; 1550 1551 memset(&seg_desc, 0, sizeof seg_desc); 1552 1553 if (ctxt->mode == X86EMUL_MODE_REAL) { 1554 /* set real mode segment descriptor (keep limit etc. for 1555 * unreal mode) */ 1556 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg); 1557 set_desc_base(&seg_desc, selector << 4); 1558 goto load; 1559 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) { 1560 /* VM86 needs a clean new segment descriptor */ 1561 set_desc_base(&seg_desc, selector << 4); 1562 set_desc_limit(&seg_desc, 0xffff); 1563 seg_desc.type = 3; 1564 seg_desc.p = 1; 1565 seg_desc.s = 1; 1566 seg_desc.dpl = 3; 1567 goto load; 1568 } 1569 1570 rpl = selector & 3; 1571 1572 /* NULL selector is not valid for TR, CS and SS (except for long mode) */ 1573 if ((seg == VCPU_SREG_CS 1574 || (seg == VCPU_SREG_SS 1575 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl)) 1576 || seg == VCPU_SREG_TR) 1577 && null_selector) 1578 goto exception; 1579 1580 /* TR should be in GDT only */ 1581 if (seg == VCPU_SREG_TR && (selector & (1 << 2))) 1582 goto exception; 1583 1584 if (null_selector) /* for NULL selector skip all following checks */ 1585 goto load; 1586 1587 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr); 1588 if (ret != X86EMUL_CONTINUE) 1589 return ret; 1590 1591 err_code = selector & 0xfffc; 1592 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR : 1593 GP_VECTOR; 1594 1595 /* can't load system descriptor into segment selector */ 1596 if (seg <= VCPU_SREG_GS && !seg_desc.s) { 1597 if (transfer == X86_TRANSFER_CALL_JMP) 1598 return X86EMUL_UNHANDLEABLE; 1599 goto exception; 1600 } 1601 1602 if (!seg_desc.p) { 1603 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; 1604 goto exception; 1605 } 1606 1607 dpl = seg_desc.dpl; 1608 1609 switch (seg) { 1610 case VCPU_SREG_SS: 1611 /* 1612 * segment is not a writable data segment or segment 1613 * selector's RPL != CPL or segment selector's RPL != CPL 1614 */ 1615 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) 1616 goto exception; 1617 break; 1618 case VCPU_SREG_CS: 1619 if (!(seg_desc.type & 8)) 1620 goto exception; 1621 1622 if (seg_desc.type & 4) { 1623 /* conforming */ 1624 if (dpl > cpl) 1625 goto exception; 1626 } else { 1627 /* nonconforming */ 1628 if (rpl > cpl || dpl != cpl) 1629 goto exception; 1630 } 1631 /* in long-mode d/b must be clear if l is set */ 1632 if (seg_desc.d && seg_desc.l) { 1633 u64 efer = 0; 1634 1635 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 1636 if (efer & EFER_LMA) 1637 goto exception; 1638 } 1639 1640 /* CS(RPL) <- CPL */ 1641 selector = (selector & 0xfffc) | cpl; 1642 break; 1643 case VCPU_SREG_TR: 1644 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) 1645 goto exception; 1646 old_desc = seg_desc; 1647 seg_desc.type |= 2; /* busy */ 1648 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc, 1649 sizeof(seg_desc), &ctxt->exception); 1650 if (ret != X86EMUL_CONTINUE) 1651 return ret; 1652 break; 1653 case VCPU_SREG_LDTR: 1654 if (seg_desc.s || seg_desc.type != 2) 1655 goto exception; 1656 break; 1657 default: /* DS, ES, FS, or GS */ 1658 /* 1659 * segment is not a data or readable code segment or 1660 * ((segment is a data or nonconforming code segment) 1661 * and (both RPL and CPL > DPL)) 1662 */ 1663 if ((seg_desc.type & 0xa) == 0x8 || 1664 (((seg_desc.type & 0xc) != 0xc) && 1665 (rpl > dpl && cpl > dpl))) 1666 goto exception; 1667 break; 1668 } 1669 1670 if (seg_desc.s) { 1671 /* mark segment as accessed */ 1672 if (!(seg_desc.type & 1)) { 1673 seg_desc.type |= 1; 1674 ret = write_segment_descriptor(ctxt, selector, 1675 &seg_desc); 1676 if (ret != X86EMUL_CONTINUE) 1677 return ret; 1678 } 1679 } else if (ctxt->mode == X86EMUL_MODE_PROT64) { 1680 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3, 1681 sizeof(base3), &ctxt->exception); 1682 if (ret != X86EMUL_CONTINUE) 1683 return ret; 1684 if (is_noncanonical_address(get_desc_base(&seg_desc) | 1685 ((u64)base3 << 32))) 1686 return emulate_gp(ctxt, 0); 1687 } 1688 load: 1689 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg); 1690 if (desc) 1691 *desc = seg_desc; 1692 return X86EMUL_CONTINUE; 1693 exception: 1694 return emulate_exception(ctxt, err_vec, err_code, true); 1695 } 1696 1697 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1698 u16 selector, int seg) 1699 { 1700 u8 cpl = ctxt->ops->cpl(ctxt); 1701 return __load_segment_descriptor(ctxt, selector, seg, cpl, 1702 X86_TRANSFER_NONE, NULL); 1703 } 1704 1705 static void write_register_operand(struct operand *op) 1706 { 1707 return assign_register(op->addr.reg, op->val, op->bytes); 1708 } 1709 1710 static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op) 1711 { 1712 switch (op->type) { 1713 case OP_REG: 1714 write_register_operand(op); 1715 break; 1716 case OP_MEM: 1717 if (ctxt->lock_prefix) 1718 return segmented_cmpxchg(ctxt, 1719 op->addr.mem, 1720 &op->orig_val, 1721 &op->val, 1722 op->bytes); 1723 else 1724 return segmented_write(ctxt, 1725 op->addr.mem, 1726 &op->val, 1727 op->bytes); 1728 break; 1729 case OP_MEM_STR: 1730 return segmented_write(ctxt, 1731 op->addr.mem, 1732 op->data, 1733 op->bytes * op->count); 1734 break; 1735 case OP_XMM: 1736 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm); 1737 break; 1738 case OP_MM: 1739 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm); 1740 break; 1741 case OP_NONE: 1742 /* no writeback */ 1743 break; 1744 default: 1745 break; 1746 } 1747 return X86EMUL_CONTINUE; 1748 } 1749 1750 static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes) 1751 { 1752 struct segmented_address addr; 1753 1754 rsp_increment(ctxt, -bytes); 1755 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); 1756 addr.seg = VCPU_SREG_SS; 1757 1758 return segmented_write(ctxt, addr, data, bytes); 1759 } 1760 1761 static int em_push(struct x86_emulate_ctxt *ctxt) 1762 { 1763 /* Disable writeback. */ 1764 ctxt->dst.type = OP_NONE; 1765 return push(ctxt, &ctxt->src.val, ctxt->op_bytes); 1766 } 1767 1768 static int emulate_pop(struct x86_emulate_ctxt *ctxt, 1769 void *dest, int len) 1770 { 1771 int rc; 1772 struct segmented_address addr; 1773 1774 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); 1775 addr.seg = VCPU_SREG_SS; 1776 rc = segmented_read(ctxt, addr, dest, len); 1777 if (rc != X86EMUL_CONTINUE) 1778 return rc; 1779 1780 rsp_increment(ctxt, len); 1781 return rc; 1782 } 1783 1784 static int em_pop(struct x86_emulate_ctxt *ctxt) 1785 { 1786 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1787 } 1788 1789 static int emulate_popf(struct x86_emulate_ctxt *ctxt, 1790 void *dest, int len) 1791 { 1792 int rc; 1793 unsigned long val, change_mask; 1794 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT; 1795 int cpl = ctxt->ops->cpl(ctxt); 1796 1797 rc = emulate_pop(ctxt, &val, len); 1798 if (rc != X86EMUL_CONTINUE) 1799 return rc; 1800 1801 change_mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | 1802 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF | 1803 X86_EFLAGS_TF | X86_EFLAGS_DF | X86_EFLAGS_NT | 1804 X86_EFLAGS_AC | X86_EFLAGS_ID; 1805 1806 switch(ctxt->mode) { 1807 case X86EMUL_MODE_PROT64: 1808 case X86EMUL_MODE_PROT32: 1809 case X86EMUL_MODE_PROT16: 1810 if (cpl == 0) 1811 change_mask |= X86_EFLAGS_IOPL; 1812 if (cpl <= iopl) 1813 change_mask |= X86_EFLAGS_IF; 1814 break; 1815 case X86EMUL_MODE_VM86: 1816 if (iopl < 3) 1817 return emulate_gp(ctxt, 0); 1818 change_mask |= X86_EFLAGS_IF; 1819 break; 1820 default: /* real mode */ 1821 change_mask |= (X86_EFLAGS_IOPL | X86_EFLAGS_IF); 1822 break; 1823 } 1824 1825 *(unsigned long *)dest = 1826 (ctxt->eflags & ~change_mask) | (val & change_mask); 1827 1828 return rc; 1829 } 1830 1831 static int em_popf(struct x86_emulate_ctxt *ctxt) 1832 { 1833 ctxt->dst.type = OP_REG; 1834 ctxt->dst.addr.reg = &ctxt->eflags; 1835 ctxt->dst.bytes = ctxt->op_bytes; 1836 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1837 } 1838 1839 static int em_enter(struct x86_emulate_ctxt *ctxt) 1840 { 1841 int rc; 1842 unsigned frame_size = ctxt->src.val; 1843 unsigned nesting_level = ctxt->src2.val & 31; 1844 ulong rbp; 1845 1846 if (nesting_level) 1847 return X86EMUL_UNHANDLEABLE; 1848 1849 rbp = reg_read(ctxt, VCPU_REGS_RBP); 1850 rc = push(ctxt, &rbp, stack_size(ctxt)); 1851 if (rc != X86EMUL_CONTINUE) 1852 return rc; 1853 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP), 1854 stack_mask(ctxt)); 1855 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), 1856 reg_read(ctxt, VCPU_REGS_RSP) - frame_size, 1857 stack_mask(ctxt)); 1858 return X86EMUL_CONTINUE; 1859 } 1860 1861 static int em_leave(struct x86_emulate_ctxt *ctxt) 1862 { 1863 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP), 1864 stack_mask(ctxt)); 1865 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes); 1866 } 1867 1868 static int em_push_sreg(struct x86_emulate_ctxt *ctxt) 1869 { 1870 int seg = ctxt->src2.val; 1871 1872 ctxt->src.val = get_segment_selector(ctxt, seg); 1873 if (ctxt->op_bytes == 4) { 1874 rsp_increment(ctxt, -2); 1875 ctxt->op_bytes = 2; 1876 } 1877 1878 return em_push(ctxt); 1879 } 1880 1881 static int em_pop_sreg(struct x86_emulate_ctxt *ctxt) 1882 { 1883 int seg = ctxt->src2.val; 1884 unsigned long selector; 1885 int rc; 1886 1887 rc = emulate_pop(ctxt, &selector, 2); 1888 if (rc != X86EMUL_CONTINUE) 1889 return rc; 1890 1891 if (ctxt->modrm_reg == VCPU_SREG_SS) 1892 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; 1893 if (ctxt->op_bytes > 2) 1894 rsp_increment(ctxt, ctxt->op_bytes - 2); 1895 1896 rc = load_segment_descriptor(ctxt, (u16)selector, seg); 1897 return rc; 1898 } 1899 1900 static int em_pusha(struct x86_emulate_ctxt *ctxt) 1901 { 1902 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP); 1903 int rc = X86EMUL_CONTINUE; 1904 int reg = VCPU_REGS_RAX; 1905 1906 while (reg <= VCPU_REGS_RDI) { 1907 (reg == VCPU_REGS_RSP) ? 1908 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg)); 1909 1910 rc = em_push(ctxt); 1911 if (rc != X86EMUL_CONTINUE) 1912 return rc; 1913 1914 ++reg; 1915 } 1916 1917 return rc; 1918 } 1919 1920 static int em_pushf(struct x86_emulate_ctxt *ctxt) 1921 { 1922 ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM; 1923 return em_push(ctxt); 1924 } 1925 1926 static int em_popa(struct x86_emulate_ctxt *ctxt) 1927 { 1928 int rc = X86EMUL_CONTINUE; 1929 int reg = VCPU_REGS_RDI; 1930 u32 val; 1931 1932 while (reg >= VCPU_REGS_RAX) { 1933 if (reg == VCPU_REGS_RSP) { 1934 rsp_increment(ctxt, ctxt->op_bytes); 1935 --reg; 1936 } 1937 1938 rc = emulate_pop(ctxt, &val, ctxt->op_bytes); 1939 if (rc != X86EMUL_CONTINUE) 1940 break; 1941 assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes); 1942 --reg; 1943 } 1944 return rc; 1945 } 1946 1947 static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) 1948 { 1949 const struct x86_emulate_ops *ops = ctxt->ops; 1950 int rc; 1951 struct desc_ptr dt; 1952 gva_t cs_addr; 1953 gva_t eip_addr; 1954 u16 cs, eip; 1955 1956 /* TODO: Add limit checks */ 1957 ctxt->src.val = ctxt->eflags; 1958 rc = em_push(ctxt); 1959 if (rc != X86EMUL_CONTINUE) 1960 return rc; 1961 1962 ctxt->eflags &= ~(X86_EFLAGS_IF | X86_EFLAGS_TF | X86_EFLAGS_AC); 1963 1964 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS); 1965 rc = em_push(ctxt); 1966 if (rc != X86EMUL_CONTINUE) 1967 return rc; 1968 1969 ctxt->src.val = ctxt->_eip; 1970 rc = em_push(ctxt); 1971 if (rc != X86EMUL_CONTINUE) 1972 return rc; 1973 1974 ops->get_idt(ctxt, &dt); 1975 1976 eip_addr = dt.address + (irq << 2); 1977 cs_addr = dt.address + (irq << 2) + 2; 1978 1979 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception); 1980 if (rc != X86EMUL_CONTINUE) 1981 return rc; 1982 1983 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception); 1984 if (rc != X86EMUL_CONTINUE) 1985 return rc; 1986 1987 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS); 1988 if (rc != X86EMUL_CONTINUE) 1989 return rc; 1990 1991 ctxt->_eip = eip; 1992 1993 return rc; 1994 } 1995 1996 int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) 1997 { 1998 int rc; 1999 2000 invalidate_registers(ctxt); 2001 rc = __emulate_int_real(ctxt, irq); 2002 if (rc == X86EMUL_CONTINUE) 2003 writeback_registers(ctxt); 2004 return rc; 2005 } 2006 2007 static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq) 2008 { 2009 switch(ctxt->mode) { 2010 case X86EMUL_MODE_REAL: 2011 return __emulate_int_real(ctxt, irq); 2012 case X86EMUL_MODE_VM86: 2013 case X86EMUL_MODE_PROT16: 2014 case X86EMUL_MODE_PROT32: 2015 case X86EMUL_MODE_PROT64: 2016 default: 2017 /* Protected mode interrupts unimplemented yet */ 2018 return X86EMUL_UNHANDLEABLE; 2019 } 2020 } 2021 2022 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt) 2023 { 2024 int rc = X86EMUL_CONTINUE; 2025 unsigned long temp_eip = 0; 2026 unsigned long temp_eflags = 0; 2027 unsigned long cs = 0; 2028 unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | 2029 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_TF | 2030 X86_EFLAGS_IF | X86_EFLAGS_DF | X86_EFLAGS_OF | 2031 X86_EFLAGS_IOPL | X86_EFLAGS_NT | X86_EFLAGS_RF | 2032 X86_EFLAGS_AC | X86_EFLAGS_ID | 2033 X86_EFLAGS_FIXED; 2034 unsigned long vm86_mask = X86_EFLAGS_VM | X86_EFLAGS_VIF | 2035 X86_EFLAGS_VIP; 2036 2037 /* TODO: Add stack limit check */ 2038 2039 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes); 2040 2041 if (rc != X86EMUL_CONTINUE) 2042 return rc; 2043 2044 if (temp_eip & ~0xffff) 2045 return emulate_gp(ctxt, 0); 2046 2047 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 2048 2049 if (rc != X86EMUL_CONTINUE) 2050 return rc; 2051 2052 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes); 2053 2054 if (rc != X86EMUL_CONTINUE) 2055 return rc; 2056 2057 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); 2058 2059 if (rc != X86EMUL_CONTINUE) 2060 return rc; 2061 2062 ctxt->_eip = temp_eip; 2063 2064 if (ctxt->op_bytes == 4) 2065 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); 2066 else if (ctxt->op_bytes == 2) { 2067 ctxt->eflags &= ~0xffff; 2068 ctxt->eflags |= temp_eflags; 2069 } 2070 2071 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ 2072 ctxt->eflags |= X86_EFLAGS_FIXED; 2073 ctxt->ops->set_nmi_mask(ctxt, false); 2074 2075 return rc; 2076 } 2077 2078 static int em_iret(struct x86_emulate_ctxt *ctxt) 2079 { 2080 switch(ctxt->mode) { 2081 case X86EMUL_MODE_REAL: 2082 return emulate_iret_real(ctxt); 2083 case X86EMUL_MODE_VM86: 2084 case X86EMUL_MODE_PROT16: 2085 case X86EMUL_MODE_PROT32: 2086 case X86EMUL_MODE_PROT64: 2087 default: 2088 /* iret from protected mode unimplemented yet */ 2089 return X86EMUL_UNHANDLEABLE; 2090 } 2091 } 2092 2093 static int em_jmp_far(struct x86_emulate_ctxt *ctxt) 2094 { 2095 int rc; 2096 unsigned short sel, old_sel; 2097 struct desc_struct old_desc, new_desc; 2098 const struct x86_emulate_ops *ops = ctxt->ops; 2099 u8 cpl = ctxt->ops->cpl(ctxt); 2100 2101 /* Assignment of RIP may only fail in 64-bit mode */ 2102 if (ctxt->mode == X86EMUL_MODE_PROT64) 2103 ops->get_segment(ctxt, &old_sel, &old_desc, NULL, 2104 VCPU_SREG_CS); 2105 2106 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2107 2108 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, 2109 X86_TRANSFER_CALL_JMP, 2110 &new_desc); 2111 if (rc != X86EMUL_CONTINUE) 2112 return rc; 2113 2114 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc); 2115 if (rc != X86EMUL_CONTINUE) { 2116 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64); 2117 /* assigning eip failed; restore the old cs */ 2118 ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS); 2119 return rc; 2120 } 2121 return rc; 2122 } 2123 2124 static int em_jmp_abs(struct x86_emulate_ctxt *ctxt) 2125 { 2126 return assign_eip_near(ctxt, ctxt->src.val); 2127 } 2128 2129 static int em_call_near_abs(struct x86_emulate_ctxt *ctxt) 2130 { 2131 int rc; 2132 long int old_eip; 2133 2134 old_eip = ctxt->_eip; 2135 rc = assign_eip_near(ctxt, ctxt->src.val); 2136 if (rc != X86EMUL_CONTINUE) 2137 return rc; 2138 ctxt->src.val = old_eip; 2139 rc = em_push(ctxt); 2140 return rc; 2141 } 2142 2143 static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt) 2144 { 2145 u64 old = ctxt->dst.orig_val64; 2146 2147 if (ctxt->dst.bytes == 16) 2148 return X86EMUL_UNHANDLEABLE; 2149 2150 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) || 2151 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) { 2152 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0); 2153 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32); 2154 ctxt->eflags &= ~X86_EFLAGS_ZF; 2155 } else { 2156 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) | 2157 (u32) reg_read(ctxt, VCPU_REGS_RBX); 2158 2159 ctxt->eflags |= X86_EFLAGS_ZF; 2160 } 2161 return X86EMUL_CONTINUE; 2162 } 2163 2164 static int em_ret(struct x86_emulate_ctxt *ctxt) 2165 { 2166 int rc; 2167 unsigned long eip; 2168 2169 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 2170 if (rc != X86EMUL_CONTINUE) 2171 return rc; 2172 2173 return assign_eip_near(ctxt, eip); 2174 } 2175 2176 static int em_ret_far(struct x86_emulate_ctxt *ctxt) 2177 { 2178 int rc; 2179 unsigned long eip, cs; 2180 u16 old_cs; 2181 int cpl = ctxt->ops->cpl(ctxt); 2182 struct desc_struct old_desc, new_desc; 2183 const struct x86_emulate_ops *ops = ctxt->ops; 2184 2185 if (ctxt->mode == X86EMUL_MODE_PROT64) 2186 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, 2187 VCPU_SREG_CS); 2188 2189 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 2190 if (rc != X86EMUL_CONTINUE) 2191 return rc; 2192 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 2193 if (rc != X86EMUL_CONTINUE) 2194 return rc; 2195 /* Outer-privilege level return is not implemented */ 2196 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl) 2197 return X86EMUL_UNHANDLEABLE; 2198 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl, 2199 X86_TRANSFER_RET, 2200 &new_desc); 2201 if (rc != X86EMUL_CONTINUE) 2202 return rc; 2203 rc = assign_eip_far(ctxt, eip, &new_desc); 2204 if (rc != X86EMUL_CONTINUE) { 2205 WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64); 2206 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS); 2207 } 2208 return rc; 2209 } 2210 2211 static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt) 2212 { 2213 int rc; 2214 2215 rc = em_ret_far(ctxt); 2216 if (rc != X86EMUL_CONTINUE) 2217 return rc; 2218 rsp_increment(ctxt, ctxt->src.val); 2219 return X86EMUL_CONTINUE; 2220 } 2221 2222 static int em_cmpxchg(struct x86_emulate_ctxt *ctxt) 2223 { 2224 /* Save real source value, then compare EAX against destination. */ 2225 ctxt->dst.orig_val = ctxt->dst.val; 2226 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX); 2227 ctxt->src.orig_val = ctxt->src.val; 2228 ctxt->src.val = ctxt->dst.orig_val; 2229 fastop(ctxt, em_cmp); 2230 2231 if (ctxt->eflags & X86_EFLAGS_ZF) { 2232 /* Success: write back to memory; no update of EAX */ 2233 ctxt->src.type = OP_NONE; 2234 ctxt->dst.val = ctxt->src.orig_val; 2235 } else { 2236 /* Failure: write the value we saw to EAX. */ 2237 ctxt->src.type = OP_REG; 2238 ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 2239 ctxt->src.val = ctxt->dst.orig_val; 2240 /* Create write-cycle to dest by writing the same value */ 2241 ctxt->dst.val = ctxt->dst.orig_val; 2242 } 2243 return X86EMUL_CONTINUE; 2244 } 2245 2246 static int em_lseg(struct x86_emulate_ctxt *ctxt) 2247 { 2248 int seg = ctxt->src2.val; 2249 unsigned short sel; 2250 int rc; 2251 2252 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2253 2254 rc = load_segment_descriptor(ctxt, sel, seg); 2255 if (rc != X86EMUL_CONTINUE) 2256 return rc; 2257 2258 ctxt->dst.val = ctxt->src.val; 2259 return rc; 2260 } 2261 2262 static int emulator_has_longmode(struct x86_emulate_ctxt *ctxt) 2263 { 2264 u32 eax, ebx, ecx, edx; 2265 2266 eax = 0x80000001; 2267 ecx = 0; 2268 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); 2269 return edx & bit(X86_FEATURE_LM); 2270 } 2271 2272 #define GET_SMSTATE(type, smbase, offset) \ 2273 ({ \ 2274 type __val; \ 2275 int r = ctxt->ops->read_std(ctxt, smbase + offset, &__val, \ 2276 sizeof(__val), NULL); \ 2277 if (r != X86EMUL_CONTINUE) \ 2278 return X86EMUL_UNHANDLEABLE; \ 2279 __val; \ 2280 }) 2281 2282 static void rsm_set_desc_flags(struct desc_struct *desc, u32 flags) 2283 { 2284 desc->g = (flags >> 23) & 1; 2285 desc->d = (flags >> 22) & 1; 2286 desc->l = (flags >> 21) & 1; 2287 desc->avl = (flags >> 20) & 1; 2288 desc->p = (flags >> 15) & 1; 2289 desc->dpl = (flags >> 13) & 3; 2290 desc->s = (flags >> 12) & 1; 2291 desc->type = (flags >> 8) & 15; 2292 } 2293 2294 static int rsm_load_seg_32(struct x86_emulate_ctxt *ctxt, u64 smbase, int n) 2295 { 2296 struct desc_struct desc; 2297 int offset; 2298 u16 selector; 2299 2300 selector = GET_SMSTATE(u32, smbase, 0x7fa8 + n * 4); 2301 2302 if (n < 3) 2303 offset = 0x7f84 + n * 12; 2304 else 2305 offset = 0x7f2c + (n - 3) * 12; 2306 2307 set_desc_base(&desc, GET_SMSTATE(u32, smbase, offset + 8)); 2308 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, offset + 4)); 2309 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, offset)); 2310 ctxt->ops->set_segment(ctxt, selector, &desc, 0, n); 2311 return X86EMUL_CONTINUE; 2312 } 2313 2314 static int rsm_load_seg_64(struct x86_emulate_ctxt *ctxt, u64 smbase, int n) 2315 { 2316 struct desc_struct desc; 2317 int offset; 2318 u16 selector; 2319 u32 base3; 2320 2321 offset = 0x7e00 + n * 16; 2322 2323 selector = GET_SMSTATE(u16, smbase, offset); 2324 rsm_set_desc_flags(&desc, GET_SMSTATE(u16, smbase, offset + 2) << 8); 2325 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, offset + 4)); 2326 set_desc_base(&desc, GET_SMSTATE(u32, smbase, offset + 8)); 2327 base3 = GET_SMSTATE(u32, smbase, offset + 12); 2328 2329 ctxt->ops->set_segment(ctxt, selector, &desc, base3, n); 2330 return X86EMUL_CONTINUE; 2331 } 2332 2333 static int rsm_enter_protected_mode(struct x86_emulate_ctxt *ctxt, 2334 u64 cr0, u64 cr4) 2335 { 2336 int bad; 2337 2338 /* 2339 * First enable PAE, long mode needs it before CR0.PG = 1 is set. 2340 * Then enable protected mode. However, PCID cannot be enabled 2341 * if EFER.LMA=0, so set it separately. 2342 */ 2343 bad = ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE); 2344 if (bad) 2345 return X86EMUL_UNHANDLEABLE; 2346 2347 bad = ctxt->ops->set_cr(ctxt, 0, cr0); 2348 if (bad) 2349 return X86EMUL_UNHANDLEABLE; 2350 2351 if (cr4 & X86_CR4_PCIDE) { 2352 bad = ctxt->ops->set_cr(ctxt, 4, cr4); 2353 if (bad) 2354 return X86EMUL_UNHANDLEABLE; 2355 } 2356 2357 return X86EMUL_CONTINUE; 2358 } 2359 2360 static int rsm_load_state_32(struct x86_emulate_ctxt *ctxt, u64 smbase) 2361 { 2362 struct desc_struct desc; 2363 struct desc_ptr dt; 2364 u16 selector; 2365 u32 val, cr0, cr4; 2366 int i; 2367 2368 cr0 = GET_SMSTATE(u32, smbase, 0x7ffc); 2369 ctxt->ops->set_cr(ctxt, 3, GET_SMSTATE(u32, smbase, 0x7ff8)); 2370 ctxt->eflags = GET_SMSTATE(u32, smbase, 0x7ff4) | X86_EFLAGS_FIXED; 2371 ctxt->_eip = GET_SMSTATE(u32, smbase, 0x7ff0); 2372 2373 for (i = 0; i < 8; i++) 2374 *reg_write(ctxt, i) = GET_SMSTATE(u32, smbase, 0x7fd0 + i * 4); 2375 2376 val = GET_SMSTATE(u32, smbase, 0x7fcc); 2377 ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1); 2378 val = GET_SMSTATE(u32, smbase, 0x7fc8); 2379 ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1); 2380 2381 selector = GET_SMSTATE(u32, smbase, 0x7fc4); 2382 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7f64)); 2383 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7f60)); 2384 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7f5c)); 2385 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_TR); 2386 2387 selector = GET_SMSTATE(u32, smbase, 0x7fc0); 2388 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7f80)); 2389 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7f7c)); 2390 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7f78)); 2391 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_LDTR); 2392 2393 dt.address = GET_SMSTATE(u32, smbase, 0x7f74); 2394 dt.size = GET_SMSTATE(u32, smbase, 0x7f70); 2395 ctxt->ops->set_gdt(ctxt, &dt); 2396 2397 dt.address = GET_SMSTATE(u32, smbase, 0x7f58); 2398 dt.size = GET_SMSTATE(u32, smbase, 0x7f54); 2399 ctxt->ops->set_idt(ctxt, &dt); 2400 2401 for (i = 0; i < 6; i++) { 2402 int r = rsm_load_seg_32(ctxt, smbase, i); 2403 if (r != X86EMUL_CONTINUE) 2404 return r; 2405 } 2406 2407 cr4 = GET_SMSTATE(u32, smbase, 0x7f14); 2408 2409 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smbase, 0x7ef8)); 2410 2411 return rsm_enter_protected_mode(ctxt, cr0, cr4); 2412 } 2413 2414 static int rsm_load_state_64(struct x86_emulate_ctxt *ctxt, u64 smbase) 2415 { 2416 struct desc_struct desc; 2417 struct desc_ptr dt; 2418 u64 val, cr0, cr4; 2419 u32 base3; 2420 u16 selector; 2421 int i, r; 2422 2423 for (i = 0; i < 16; i++) 2424 *reg_write(ctxt, i) = GET_SMSTATE(u64, smbase, 0x7ff8 - i * 8); 2425 2426 ctxt->_eip = GET_SMSTATE(u64, smbase, 0x7f78); 2427 ctxt->eflags = GET_SMSTATE(u32, smbase, 0x7f70) | X86_EFLAGS_FIXED; 2428 2429 val = GET_SMSTATE(u32, smbase, 0x7f68); 2430 ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1); 2431 val = GET_SMSTATE(u32, smbase, 0x7f60); 2432 ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1); 2433 2434 cr0 = GET_SMSTATE(u64, smbase, 0x7f58); 2435 ctxt->ops->set_cr(ctxt, 3, GET_SMSTATE(u64, smbase, 0x7f50)); 2436 cr4 = GET_SMSTATE(u64, smbase, 0x7f48); 2437 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smbase, 0x7f00)); 2438 val = GET_SMSTATE(u64, smbase, 0x7ed0); 2439 ctxt->ops->set_msr(ctxt, MSR_EFER, val & ~EFER_LMA); 2440 2441 selector = GET_SMSTATE(u32, smbase, 0x7e90); 2442 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7e92) << 8); 2443 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7e94)); 2444 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7e98)); 2445 base3 = GET_SMSTATE(u32, smbase, 0x7e9c); 2446 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_TR); 2447 2448 dt.size = GET_SMSTATE(u32, smbase, 0x7e84); 2449 dt.address = GET_SMSTATE(u64, smbase, 0x7e88); 2450 ctxt->ops->set_idt(ctxt, &dt); 2451 2452 selector = GET_SMSTATE(u32, smbase, 0x7e70); 2453 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7e72) << 8); 2454 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7e74)); 2455 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7e78)); 2456 base3 = GET_SMSTATE(u32, smbase, 0x7e7c); 2457 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_LDTR); 2458 2459 dt.size = GET_SMSTATE(u32, smbase, 0x7e64); 2460 dt.address = GET_SMSTATE(u64, smbase, 0x7e68); 2461 ctxt->ops->set_gdt(ctxt, &dt); 2462 2463 r = rsm_enter_protected_mode(ctxt, cr0, cr4); 2464 if (r != X86EMUL_CONTINUE) 2465 return r; 2466 2467 for (i = 0; i < 6; i++) { 2468 r = rsm_load_seg_64(ctxt, smbase, i); 2469 if (r != X86EMUL_CONTINUE) 2470 return r; 2471 } 2472 2473 return X86EMUL_CONTINUE; 2474 } 2475 2476 static int em_rsm(struct x86_emulate_ctxt *ctxt) 2477 { 2478 unsigned long cr0, cr4, efer; 2479 u64 smbase; 2480 int ret; 2481 2482 if ((ctxt->emul_flags & X86EMUL_SMM_MASK) == 0) 2483 return emulate_ud(ctxt); 2484 2485 /* 2486 * Get back to real mode, to prepare a safe state in which to load 2487 * CR0/CR3/CR4/EFER. Also this will ensure that addresses passed 2488 * to read_std/write_std are not virtual. 2489 * 2490 * CR4.PCIDE must be zero, because it is a 64-bit mode only feature. 2491 */ 2492 cr0 = ctxt->ops->get_cr(ctxt, 0); 2493 if (cr0 & X86_CR0_PE) 2494 ctxt->ops->set_cr(ctxt, 0, cr0 & ~(X86_CR0_PG | X86_CR0_PE)); 2495 cr4 = ctxt->ops->get_cr(ctxt, 4); 2496 if (cr4 & X86_CR4_PAE) 2497 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PAE); 2498 efer = 0; 2499 ctxt->ops->set_msr(ctxt, MSR_EFER, efer); 2500 2501 smbase = ctxt->ops->get_smbase(ctxt); 2502 if (emulator_has_longmode(ctxt)) 2503 ret = rsm_load_state_64(ctxt, smbase + 0x8000); 2504 else 2505 ret = rsm_load_state_32(ctxt, smbase + 0x8000); 2506 2507 if (ret != X86EMUL_CONTINUE) { 2508 /* FIXME: should triple fault */ 2509 return X86EMUL_UNHANDLEABLE; 2510 } 2511 2512 if ((ctxt->emul_flags & X86EMUL_SMM_INSIDE_NMI_MASK) == 0) 2513 ctxt->ops->set_nmi_mask(ctxt, false); 2514 2515 ctxt->emul_flags &= ~X86EMUL_SMM_INSIDE_NMI_MASK; 2516 ctxt->emul_flags &= ~X86EMUL_SMM_MASK; 2517 return X86EMUL_CONTINUE; 2518 } 2519 2520 static void 2521 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, 2522 struct desc_struct *cs, struct desc_struct *ss) 2523 { 2524 cs->l = 0; /* will be adjusted later */ 2525 set_desc_base(cs, 0); /* flat segment */ 2526 cs->g = 1; /* 4kb granularity */ 2527 set_desc_limit(cs, 0xfffff); /* 4GB limit */ 2528 cs->type = 0x0b; /* Read, Execute, Accessed */ 2529 cs->s = 1; 2530 cs->dpl = 0; /* will be adjusted later */ 2531 cs->p = 1; 2532 cs->d = 1; 2533 cs->avl = 0; 2534 2535 set_desc_base(ss, 0); /* flat segment */ 2536 set_desc_limit(ss, 0xfffff); /* 4GB limit */ 2537 ss->g = 1; /* 4kb granularity */ 2538 ss->s = 1; 2539 ss->type = 0x03; /* Read/Write, Accessed */ 2540 ss->d = 1; /* 32bit stack segment */ 2541 ss->dpl = 0; 2542 ss->p = 1; 2543 ss->l = 0; 2544 ss->avl = 0; 2545 } 2546 2547 static bool vendor_intel(struct x86_emulate_ctxt *ctxt) 2548 { 2549 u32 eax, ebx, ecx, edx; 2550 2551 eax = ecx = 0; 2552 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); 2553 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx 2554 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx 2555 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx; 2556 } 2557 2558 static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt) 2559 { 2560 const struct x86_emulate_ops *ops = ctxt->ops; 2561 u32 eax, ebx, ecx, edx; 2562 2563 /* 2564 * syscall should always be enabled in longmode - so only become 2565 * vendor specific (cpuid) if other modes are active... 2566 */ 2567 if (ctxt->mode == X86EMUL_MODE_PROT64) 2568 return true; 2569 2570 eax = 0x00000000; 2571 ecx = 0x00000000; 2572 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); 2573 /* 2574 * Intel ("GenuineIntel") 2575 * remark: Intel CPUs only support "syscall" in 64bit 2576 * longmode. Also an 64bit guest with a 2577 * 32bit compat-app running will #UD !! While this 2578 * behaviour can be fixed (by emulating) into AMD 2579 * response - CPUs of AMD can't behave like Intel. 2580 */ 2581 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx && 2582 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx && 2583 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx) 2584 return false; 2585 2586 /* AMD ("AuthenticAMD") */ 2587 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx && 2588 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx && 2589 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx) 2590 return true; 2591 2592 /* AMD ("AMDisbetter!") */ 2593 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx && 2594 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx && 2595 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx) 2596 return true; 2597 2598 /* default: (not Intel, not AMD), apply Intel's stricter rules... */ 2599 return false; 2600 } 2601 2602 static int em_syscall(struct x86_emulate_ctxt *ctxt) 2603 { 2604 const struct x86_emulate_ops *ops = ctxt->ops; 2605 struct desc_struct cs, ss; 2606 u64 msr_data; 2607 u16 cs_sel, ss_sel; 2608 u64 efer = 0; 2609 2610 /* syscall is not available in real mode */ 2611 if (ctxt->mode == X86EMUL_MODE_REAL || 2612 ctxt->mode == X86EMUL_MODE_VM86) 2613 return emulate_ud(ctxt); 2614 2615 if (!(em_syscall_is_enabled(ctxt))) 2616 return emulate_ud(ctxt); 2617 2618 ops->get_msr(ctxt, MSR_EFER, &efer); 2619 setup_syscalls_segments(ctxt, &cs, &ss); 2620 2621 if (!(efer & EFER_SCE)) 2622 return emulate_ud(ctxt); 2623 2624 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2625 msr_data >>= 32; 2626 cs_sel = (u16)(msr_data & 0xfffc); 2627 ss_sel = (u16)(msr_data + 8); 2628 2629 if (efer & EFER_LMA) { 2630 cs.d = 0; 2631 cs.l = 1; 2632 } 2633 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2634 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2635 2636 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip; 2637 if (efer & EFER_LMA) { 2638 #ifdef CONFIG_X86_64 2639 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags; 2640 2641 ops->get_msr(ctxt, 2642 ctxt->mode == X86EMUL_MODE_PROT64 ? 2643 MSR_LSTAR : MSR_CSTAR, &msr_data); 2644 ctxt->_eip = msr_data; 2645 2646 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data); 2647 ctxt->eflags &= ~msr_data; 2648 ctxt->eflags |= X86_EFLAGS_FIXED; 2649 #endif 2650 } else { 2651 /* legacy mode */ 2652 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2653 ctxt->_eip = (u32)msr_data; 2654 2655 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF); 2656 } 2657 2658 return X86EMUL_CONTINUE; 2659 } 2660 2661 static int em_sysenter(struct x86_emulate_ctxt *ctxt) 2662 { 2663 const struct x86_emulate_ops *ops = ctxt->ops; 2664 struct desc_struct cs, ss; 2665 u64 msr_data; 2666 u16 cs_sel, ss_sel; 2667 u64 efer = 0; 2668 2669 ops->get_msr(ctxt, MSR_EFER, &efer); 2670 /* inject #GP if in real mode */ 2671 if (ctxt->mode == X86EMUL_MODE_REAL) 2672 return emulate_gp(ctxt, 0); 2673 2674 /* 2675 * Not recognized on AMD in compat mode (but is recognized in legacy 2676 * mode). 2677 */ 2678 if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA) 2679 && !vendor_intel(ctxt)) 2680 return emulate_ud(ctxt); 2681 2682 /* sysenter/sysexit have not been tested in 64bit mode. */ 2683 if (ctxt->mode == X86EMUL_MODE_PROT64) 2684 return X86EMUL_UNHANDLEABLE; 2685 2686 setup_syscalls_segments(ctxt, &cs, &ss); 2687 2688 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2689 if ((msr_data & 0xfffc) == 0x0) 2690 return emulate_gp(ctxt, 0); 2691 2692 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF); 2693 cs_sel = (u16)msr_data & ~SEGMENT_RPL_MASK; 2694 ss_sel = cs_sel + 8; 2695 if (efer & EFER_LMA) { 2696 cs.d = 0; 2697 cs.l = 1; 2698 } 2699 2700 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2701 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2702 2703 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data); 2704 ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data; 2705 2706 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data); 2707 *reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data : 2708 (u32)msr_data; 2709 2710 return X86EMUL_CONTINUE; 2711 } 2712 2713 static int em_sysexit(struct x86_emulate_ctxt *ctxt) 2714 { 2715 const struct x86_emulate_ops *ops = ctxt->ops; 2716 struct desc_struct cs, ss; 2717 u64 msr_data, rcx, rdx; 2718 int usermode; 2719 u16 cs_sel = 0, ss_sel = 0; 2720 2721 /* inject #GP if in real mode or Virtual 8086 mode */ 2722 if (ctxt->mode == X86EMUL_MODE_REAL || 2723 ctxt->mode == X86EMUL_MODE_VM86) 2724 return emulate_gp(ctxt, 0); 2725 2726 setup_syscalls_segments(ctxt, &cs, &ss); 2727 2728 if ((ctxt->rex_prefix & 0x8) != 0x0) 2729 usermode = X86EMUL_MODE_PROT64; 2730 else 2731 usermode = X86EMUL_MODE_PROT32; 2732 2733 rcx = reg_read(ctxt, VCPU_REGS_RCX); 2734 rdx = reg_read(ctxt, VCPU_REGS_RDX); 2735 2736 cs.dpl = 3; 2737 ss.dpl = 3; 2738 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2739 switch (usermode) { 2740 case X86EMUL_MODE_PROT32: 2741 cs_sel = (u16)(msr_data + 16); 2742 if ((msr_data & 0xfffc) == 0x0) 2743 return emulate_gp(ctxt, 0); 2744 ss_sel = (u16)(msr_data + 24); 2745 rcx = (u32)rcx; 2746 rdx = (u32)rdx; 2747 break; 2748 case X86EMUL_MODE_PROT64: 2749 cs_sel = (u16)(msr_data + 32); 2750 if (msr_data == 0x0) 2751 return emulate_gp(ctxt, 0); 2752 ss_sel = cs_sel + 8; 2753 cs.d = 0; 2754 cs.l = 1; 2755 if (is_noncanonical_address(rcx) || 2756 is_noncanonical_address(rdx)) 2757 return emulate_gp(ctxt, 0); 2758 break; 2759 } 2760 cs_sel |= SEGMENT_RPL_MASK; 2761 ss_sel |= SEGMENT_RPL_MASK; 2762 2763 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2764 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2765 2766 ctxt->_eip = rdx; 2767 *reg_write(ctxt, VCPU_REGS_RSP) = rcx; 2768 2769 return X86EMUL_CONTINUE; 2770 } 2771 2772 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt) 2773 { 2774 int iopl; 2775 if (ctxt->mode == X86EMUL_MODE_REAL) 2776 return false; 2777 if (ctxt->mode == X86EMUL_MODE_VM86) 2778 return true; 2779 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT; 2780 return ctxt->ops->cpl(ctxt) > iopl; 2781 } 2782 2783 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, 2784 u16 port, u16 len) 2785 { 2786 const struct x86_emulate_ops *ops = ctxt->ops; 2787 struct desc_struct tr_seg; 2788 u32 base3; 2789 int r; 2790 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7; 2791 unsigned mask = (1 << len) - 1; 2792 unsigned long base; 2793 2794 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR); 2795 if (!tr_seg.p) 2796 return false; 2797 if (desc_limit_scaled(&tr_seg) < 103) 2798 return false; 2799 base = get_desc_base(&tr_seg); 2800 #ifdef CONFIG_X86_64 2801 base |= ((u64)base3) << 32; 2802 #endif 2803 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL); 2804 if (r != X86EMUL_CONTINUE) 2805 return false; 2806 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) 2807 return false; 2808 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL); 2809 if (r != X86EMUL_CONTINUE) 2810 return false; 2811 if ((perm >> bit_idx) & mask) 2812 return false; 2813 return true; 2814 } 2815 2816 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, 2817 u16 port, u16 len) 2818 { 2819 if (ctxt->perm_ok) 2820 return true; 2821 2822 if (emulator_bad_iopl(ctxt)) 2823 if (!emulator_io_port_access_allowed(ctxt, port, len)) 2824 return false; 2825 2826 ctxt->perm_ok = true; 2827 2828 return true; 2829 } 2830 2831 static void string_registers_quirk(struct x86_emulate_ctxt *ctxt) 2832 { 2833 /* 2834 * Intel CPUs mask the counter and pointers in quite strange 2835 * manner when ECX is zero due to REP-string optimizations. 2836 */ 2837 #ifdef CONFIG_X86_64 2838 if (ctxt->ad_bytes != 4 || !vendor_intel(ctxt)) 2839 return; 2840 2841 *reg_write(ctxt, VCPU_REGS_RCX) = 0; 2842 2843 switch (ctxt->b) { 2844 case 0xa4: /* movsb */ 2845 case 0xa5: /* movsd/w */ 2846 *reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1; 2847 /* fall through */ 2848 case 0xaa: /* stosb */ 2849 case 0xab: /* stosd/w */ 2850 *reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1; 2851 } 2852 #endif 2853 } 2854 2855 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, 2856 struct tss_segment_16 *tss) 2857 { 2858 tss->ip = ctxt->_eip; 2859 tss->flag = ctxt->eflags; 2860 tss->ax = reg_read(ctxt, VCPU_REGS_RAX); 2861 tss->cx = reg_read(ctxt, VCPU_REGS_RCX); 2862 tss->dx = reg_read(ctxt, VCPU_REGS_RDX); 2863 tss->bx = reg_read(ctxt, VCPU_REGS_RBX); 2864 tss->sp = reg_read(ctxt, VCPU_REGS_RSP); 2865 tss->bp = reg_read(ctxt, VCPU_REGS_RBP); 2866 tss->si = reg_read(ctxt, VCPU_REGS_RSI); 2867 tss->di = reg_read(ctxt, VCPU_REGS_RDI); 2868 2869 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 2870 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 2871 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 2872 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 2873 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR); 2874 } 2875 2876 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, 2877 struct tss_segment_16 *tss) 2878 { 2879 int ret; 2880 u8 cpl; 2881 2882 ctxt->_eip = tss->ip; 2883 ctxt->eflags = tss->flag | 2; 2884 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax; 2885 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx; 2886 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx; 2887 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx; 2888 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp; 2889 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp; 2890 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si; 2891 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di; 2892 2893 /* 2894 * SDM says that segment selectors are loaded before segment 2895 * descriptors 2896 */ 2897 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR); 2898 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 2899 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 2900 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 2901 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 2902 2903 cpl = tss->cs & 3; 2904 2905 /* 2906 * Now load segment descriptors. If fault happens at this stage 2907 * it is handled in a context of new task 2908 */ 2909 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, 2910 X86_TRANSFER_TASK_SWITCH, NULL); 2911 if (ret != X86EMUL_CONTINUE) 2912 return ret; 2913 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, 2914 X86_TRANSFER_TASK_SWITCH, NULL); 2915 if (ret != X86EMUL_CONTINUE) 2916 return ret; 2917 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, 2918 X86_TRANSFER_TASK_SWITCH, NULL); 2919 if (ret != X86EMUL_CONTINUE) 2920 return ret; 2921 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, 2922 X86_TRANSFER_TASK_SWITCH, NULL); 2923 if (ret != X86EMUL_CONTINUE) 2924 return ret; 2925 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, 2926 X86_TRANSFER_TASK_SWITCH, NULL); 2927 if (ret != X86EMUL_CONTINUE) 2928 return ret; 2929 2930 return X86EMUL_CONTINUE; 2931 } 2932 2933 static int task_switch_16(struct x86_emulate_ctxt *ctxt, 2934 u16 tss_selector, u16 old_tss_sel, 2935 ulong old_tss_base, struct desc_struct *new_desc) 2936 { 2937 const struct x86_emulate_ops *ops = ctxt->ops; 2938 struct tss_segment_16 tss_seg; 2939 int ret; 2940 u32 new_tss_base = get_desc_base(new_desc); 2941 2942 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, 2943 &ctxt->exception); 2944 if (ret != X86EMUL_CONTINUE) 2945 return ret; 2946 2947 save_state_to_tss16(ctxt, &tss_seg); 2948 2949 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, 2950 &ctxt->exception); 2951 if (ret != X86EMUL_CONTINUE) 2952 return ret; 2953 2954 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, 2955 &ctxt->exception); 2956 if (ret != X86EMUL_CONTINUE) 2957 return ret; 2958 2959 if (old_tss_sel != 0xffff) { 2960 tss_seg.prev_task_link = old_tss_sel; 2961 2962 ret = ops->write_std(ctxt, new_tss_base, 2963 &tss_seg.prev_task_link, 2964 sizeof tss_seg.prev_task_link, 2965 &ctxt->exception); 2966 if (ret != X86EMUL_CONTINUE) 2967 return ret; 2968 } 2969 2970 return load_state_from_tss16(ctxt, &tss_seg); 2971 } 2972 2973 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, 2974 struct tss_segment_32 *tss) 2975 { 2976 /* CR3 and ldt selector are not saved intentionally */ 2977 tss->eip = ctxt->_eip; 2978 tss->eflags = ctxt->eflags; 2979 tss->eax = reg_read(ctxt, VCPU_REGS_RAX); 2980 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX); 2981 tss->edx = reg_read(ctxt, VCPU_REGS_RDX); 2982 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX); 2983 tss->esp = reg_read(ctxt, VCPU_REGS_RSP); 2984 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP); 2985 tss->esi = reg_read(ctxt, VCPU_REGS_RSI); 2986 tss->edi = reg_read(ctxt, VCPU_REGS_RDI); 2987 2988 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 2989 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 2990 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 2991 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 2992 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS); 2993 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS); 2994 } 2995 2996 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, 2997 struct tss_segment_32 *tss) 2998 { 2999 int ret; 3000 u8 cpl; 3001 3002 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3)) 3003 return emulate_gp(ctxt, 0); 3004 ctxt->_eip = tss->eip; 3005 ctxt->eflags = tss->eflags | 2; 3006 3007 /* General purpose registers */ 3008 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax; 3009 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx; 3010 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx; 3011 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx; 3012 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp; 3013 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp; 3014 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi; 3015 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi; 3016 3017 /* 3018 * SDM says that segment selectors are loaded before segment 3019 * descriptors. This is important because CPL checks will 3020 * use CS.RPL. 3021 */ 3022 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); 3023 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 3024 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 3025 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 3026 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 3027 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS); 3028 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS); 3029 3030 /* 3031 * If we're switching between Protected Mode and VM86, we need to make 3032 * sure to update the mode before loading the segment descriptors so 3033 * that the selectors are interpreted correctly. 3034 */ 3035 if (ctxt->eflags & X86_EFLAGS_VM) { 3036 ctxt->mode = X86EMUL_MODE_VM86; 3037 cpl = 3; 3038 } else { 3039 ctxt->mode = X86EMUL_MODE_PROT32; 3040 cpl = tss->cs & 3; 3041 } 3042 3043 /* 3044 * Now load segment descriptors. If fault happenes at this stage 3045 * it is handled in a context of new task 3046 */ 3047 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, 3048 cpl, X86_TRANSFER_TASK_SWITCH, NULL); 3049 if (ret != X86EMUL_CONTINUE) 3050 return ret; 3051 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, 3052 X86_TRANSFER_TASK_SWITCH, NULL); 3053 if (ret != X86EMUL_CONTINUE) 3054 return ret; 3055 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, 3056 X86_TRANSFER_TASK_SWITCH, NULL); 3057 if (ret != X86EMUL_CONTINUE) 3058 return ret; 3059 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, 3060 X86_TRANSFER_TASK_SWITCH, NULL); 3061 if (ret != X86EMUL_CONTINUE) 3062 return ret; 3063 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, 3064 X86_TRANSFER_TASK_SWITCH, NULL); 3065 if (ret != X86EMUL_CONTINUE) 3066 return ret; 3067 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, 3068 X86_TRANSFER_TASK_SWITCH, NULL); 3069 if (ret != X86EMUL_CONTINUE) 3070 return ret; 3071 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, 3072 X86_TRANSFER_TASK_SWITCH, NULL); 3073 3074 return ret; 3075 } 3076 3077 static int task_switch_32(struct x86_emulate_ctxt *ctxt, 3078 u16 tss_selector, u16 old_tss_sel, 3079 ulong old_tss_base, struct desc_struct *new_desc) 3080 { 3081 const struct x86_emulate_ops *ops = ctxt->ops; 3082 struct tss_segment_32 tss_seg; 3083 int ret; 3084 u32 new_tss_base = get_desc_base(new_desc); 3085 u32 eip_offset = offsetof(struct tss_segment_32, eip); 3086 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector); 3087 3088 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, 3089 &ctxt->exception); 3090 if (ret != X86EMUL_CONTINUE) 3091 return ret; 3092 3093 save_state_to_tss32(ctxt, &tss_seg); 3094 3095 /* Only GP registers and segment selectors are saved */ 3096 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip, 3097 ldt_sel_offset - eip_offset, &ctxt->exception); 3098 if (ret != X86EMUL_CONTINUE) 3099 return ret; 3100 3101 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, 3102 &ctxt->exception); 3103 if (ret != X86EMUL_CONTINUE) 3104 return ret; 3105 3106 if (old_tss_sel != 0xffff) { 3107 tss_seg.prev_task_link = old_tss_sel; 3108 3109 ret = ops->write_std(ctxt, new_tss_base, 3110 &tss_seg.prev_task_link, 3111 sizeof tss_seg.prev_task_link, 3112 &ctxt->exception); 3113 if (ret != X86EMUL_CONTINUE) 3114 return ret; 3115 } 3116 3117 return load_state_from_tss32(ctxt, &tss_seg); 3118 } 3119 3120 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, 3121 u16 tss_selector, int idt_index, int reason, 3122 bool has_error_code, u32 error_code) 3123 { 3124 const struct x86_emulate_ops *ops = ctxt->ops; 3125 struct desc_struct curr_tss_desc, next_tss_desc; 3126 int ret; 3127 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR); 3128 ulong old_tss_base = 3129 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR); 3130 u32 desc_limit; 3131 ulong desc_addr, dr7; 3132 3133 /* FIXME: old_tss_base == ~0 ? */ 3134 3135 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr); 3136 if (ret != X86EMUL_CONTINUE) 3137 return ret; 3138 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr); 3139 if (ret != X86EMUL_CONTINUE) 3140 return ret; 3141 3142 /* FIXME: check that next_tss_desc is tss */ 3143 3144 /* 3145 * Check privileges. The three cases are task switch caused by... 3146 * 3147 * 1. jmp/call/int to task gate: Check against DPL of the task gate 3148 * 2. Exception/IRQ/iret: No check is performed 3149 * 3. jmp/call to TSS/task-gate: No check is performed since the 3150 * hardware checks it before exiting. 3151 */ 3152 if (reason == TASK_SWITCH_GATE) { 3153 if (idt_index != -1) { 3154 /* Software interrupts */ 3155 struct desc_struct task_gate_desc; 3156 int dpl; 3157 3158 ret = read_interrupt_descriptor(ctxt, idt_index, 3159 &task_gate_desc); 3160 if (ret != X86EMUL_CONTINUE) 3161 return ret; 3162 3163 dpl = task_gate_desc.dpl; 3164 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) 3165 return emulate_gp(ctxt, (idt_index << 3) | 0x2); 3166 } 3167 } 3168 3169 desc_limit = desc_limit_scaled(&next_tss_desc); 3170 if (!next_tss_desc.p || 3171 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || 3172 desc_limit < 0x2b)) { 3173 return emulate_ts(ctxt, tss_selector & 0xfffc); 3174 } 3175 3176 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { 3177 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ 3178 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); 3179 } 3180 3181 if (reason == TASK_SWITCH_IRET) 3182 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; 3183 3184 /* set back link to prev task only if NT bit is set in eflags 3185 note that old_tss_sel is not used after this point */ 3186 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) 3187 old_tss_sel = 0xffff; 3188 3189 if (next_tss_desc.type & 8) 3190 ret = task_switch_32(ctxt, tss_selector, old_tss_sel, 3191 old_tss_base, &next_tss_desc); 3192 else 3193 ret = task_switch_16(ctxt, tss_selector, old_tss_sel, 3194 old_tss_base, &next_tss_desc); 3195 if (ret != X86EMUL_CONTINUE) 3196 return ret; 3197 3198 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) 3199 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; 3200 3201 if (reason != TASK_SWITCH_IRET) { 3202 next_tss_desc.type |= (1 << 1); /* set busy flag */ 3203 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc); 3204 } 3205 3206 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS); 3207 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR); 3208 3209 if (has_error_code) { 3210 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; 3211 ctxt->lock_prefix = 0; 3212 ctxt->src.val = (unsigned long) error_code; 3213 ret = em_push(ctxt); 3214 } 3215 3216 ops->get_dr(ctxt, 7, &dr7); 3217 ops->set_dr(ctxt, 7, dr7 & ~(DR_LOCAL_ENABLE_MASK | DR_LOCAL_SLOWDOWN)); 3218 3219 return ret; 3220 } 3221 3222 int emulator_task_switch(struct x86_emulate_ctxt *ctxt, 3223 u16 tss_selector, int idt_index, int reason, 3224 bool has_error_code, u32 error_code) 3225 { 3226 int rc; 3227 3228 invalidate_registers(ctxt); 3229 ctxt->_eip = ctxt->eip; 3230 ctxt->dst.type = OP_NONE; 3231 3232 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason, 3233 has_error_code, error_code); 3234 3235 if (rc == X86EMUL_CONTINUE) { 3236 ctxt->eip = ctxt->_eip; 3237 writeback_registers(ctxt); 3238 } 3239 3240 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 3241 } 3242 3243 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg, 3244 struct operand *op) 3245 { 3246 int df = (ctxt->eflags & X86_EFLAGS_DF) ? -op->count : op->count; 3247 3248 register_address_increment(ctxt, reg, df * op->bytes); 3249 op->addr.mem.ea = register_address(ctxt, reg); 3250 } 3251 3252 static int em_das(struct x86_emulate_ctxt *ctxt) 3253 { 3254 u8 al, old_al; 3255 bool af, cf, old_cf; 3256 3257 cf = ctxt->eflags & X86_EFLAGS_CF; 3258 al = ctxt->dst.val; 3259 3260 old_al = al; 3261 old_cf = cf; 3262 cf = false; 3263 af = ctxt->eflags & X86_EFLAGS_AF; 3264 if ((al & 0x0f) > 9 || af) { 3265 al -= 6; 3266 cf = old_cf | (al >= 250); 3267 af = true; 3268 } else { 3269 af = false; 3270 } 3271 if (old_al > 0x99 || old_cf) { 3272 al -= 0x60; 3273 cf = true; 3274 } 3275 3276 ctxt->dst.val = al; 3277 /* Set PF, ZF, SF */ 3278 ctxt->src.type = OP_IMM; 3279 ctxt->src.val = 0; 3280 ctxt->src.bytes = 1; 3281 fastop(ctxt, em_or); 3282 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); 3283 if (cf) 3284 ctxt->eflags |= X86_EFLAGS_CF; 3285 if (af) 3286 ctxt->eflags |= X86_EFLAGS_AF; 3287 return X86EMUL_CONTINUE; 3288 } 3289 3290 static int em_aam(struct x86_emulate_ctxt *ctxt) 3291 { 3292 u8 al, ah; 3293 3294 if (ctxt->src.val == 0) 3295 return emulate_de(ctxt); 3296 3297 al = ctxt->dst.val & 0xff; 3298 ah = al / ctxt->src.val; 3299 al %= ctxt->src.val; 3300 3301 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8); 3302 3303 /* Set PF, ZF, SF */ 3304 ctxt->src.type = OP_IMM; 3305 ctxt->src.val = 0; 3306 ctxt->src.bytes = 1; 3307 fastop(ctxt, em_or); 3308 3309 return X86EMUL_CONTINUE; 3310 } 3311 3312 static int em_aad(struct x86_emulate_ctxt *ctxt) 3313 { 3314 u8 al = ctxt->dst.val & 0xff; 3315 u8 ah = (ctxt->dst.val >> 8) & 0xff; 3316 3317 al = (al + (ah * ctxt->src.val)) & 0xff; 3318 3319 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al; 3320 3321 /* Set PF, ZF, SF */ 3322 ctxt->src.type = OP_IMM; 3323 ctxt->src.val = 0; 3324 ctxt->src.bytes = 1; 3325 fastop(ctxt, em_or); 3326 3327 return X86EMUL_CONTINUE; 3328 } 3329 3330 static int em_call(struct x86_emulate_ctxt *ctxt) 3331 { 3332 int rc; 3333 long rel = ctxt->src.val; 3334 3335 ctxt->src.val = (unsigned long)ctxt->_eip; 3336 rc = jmp_rel(ctxt, rel); 3337 if (rc != X86EMUL_CONTINUE) 3338 return rc; 3339 return em_push(ctxt); 3340 } 3341 3342 static int em_call_far(struct x86_emulate_ctxt *ctxt) 3343 { 3344 u16 sel, old_cs; 3345 ulong old_eip; 3346 int rc; 3347 struct desc_struct old_desc, new_desc; 3348 const struct x86_emulate_ops *ops = ctxt->ops; 3349 int cpl = ctxt->ops->cpl(ctxt); 3350 enum x86emul_mode prev_mode = ctxt->mode; 3351 3352 old_eip = ctxt->_eip; 3353 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS); 3354 3355 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 3356 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, 3357 X86_TRANSFER_CALL_JMP, &new_desc); 3358 if (rc != X86EMUL_CONTINUE) 3359 return rc; 3360 3361 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc); 3362 if (rc != X86EMUL_CONTINUE) 3363 goto fail; 3364 3365 ctxt->src.val = old_cs; 3366 rc = em_push(ctxt); 3367 if (rc != X86EMUL_CONTINUE) 3368 goto fail; 3369 3370 ctxt->src.val = old_eip; 3371 rc = em_push(ctxt); 3372 /* If we failed, we tainted the memory, but the very least we should 3373 restore cs */ 3374 if (rc != X86EMUL_CONTINUE) { 3375 pr_warn_once("faulting far call emulation tainted memory\n"); 3376 goto fail; 3377 } 3378 return rc; 3379 fail: 3380 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS); 3381 ctxt->mode = prev_mode; 3382 return rc; 3383 3384 } 3385 3386 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) 3387 { 3388 int rc; 3389 unsigned long eip; 3390 3391 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 3392 if (rc != X86EMUL_CONTINUE) 3393 return rc; 3394 rc = assign_eip_near(ctxt, eip); 3395 if (rc != X86EMUL_CONTINUE) 3396 return rc; 3397 rsp_increment(ctxt, ctxt->src.val); 3398 return X86EMUL_CONTINUE; 3399 } 3400 3401 static int em_xchg(struct x86_emulate_ctxt *ctxt) 3402 { 3403 /* Write back the register source. */ 3404 ctxt->src.val = ctxt->dst.val; 3405 write_register_operand(&ctxt->src); 3406 3407 /* Write back the memory destination with implicit LOCK prefix. */ 3408 ctxt->dst.val = ctxt->src.orig_val; 3409 ctxt->lock_prefix = 1; 3410 return X86EMUL_CONTINUE; 3411 } 3412 3413 static int em_imul_3op(struct x86_emulate_ctxt *ctxt) 3414 { 3415 ctxt->dst.val = ctxt->src2.val; 3416 return fastop(ctxt, em_imul); 3417 } 3418 3419 static int em_cwd(struct x86_emulate_ctxt *ctxt) 3420 { 3421 ctxt->dst.type = OP_REG; 3422 ctxt->dst.bytes = ctxt->src.bytes; 3423 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 3424 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1); 3425 3426 return X86EMUL_CONTINUE; 3427 } 3428 3429 static int em_rdtsc(struct x86_emulate_ctxt *ctxt) 3430 { 3431 u64 tsc = 0; 3432 3433 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc); 3434 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc; 3435 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32; 3436 return X86EMUL_CONTINUE; 3437 } 3438 3439 static int em_rdpmc(struct x86_emulate_ctxt *ctxt) 3440 { 3441 u64 pmc; 3442 3443 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc)) 3444 return emulate_gp(ctxt, 0); 3445 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc; 3446 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32; 3447 return X86EMUL_CONTINUE; 3448 } 3449 3450 static int em_mov(struct x86_emulate_ctxt *ctxt) 3451 { 3452 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr)); 3453 return X86EMUL_CONTINUE; 3454 } 3455 3456 #define FFL(x) bit(X86_FEATURE_##x) 3457 3458 static int em_movbe(struct x86_emulate_ctxt *ctxt) 3459 { 3460 u32 ebx, ecx, edx, eax = 1; 3461 u16 tmp; 3462 3463 /* 3464 * Check MOVBE is set in the guest-visible CPUID leaf. 3465 */ 3466 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); 3467 if (!(ecx & FFL(MOVBE))) 3468 return emulate_ud(ctxt); 3469 3470 switch (ctxt->op_bytes) { 3471 case 2: 3472 /* 3473 * From MOVBE definition: "...When the operand size is 16 bits, 3474 * the upper word of the destination register remains unchanged 3475 * ..." 3476 * 3477 * Both casting ->valptr and ->val to u16 breaks strict aliasing 3478 * rules so we have to do the operation almost per hand. 3479 */ 3480 tmp = (u16)ctxt->src.val; 3481 ctxt->dst.val &= ~0xffffUL; 3482 ctxt->dst.val |= (unsigned long)swab16(tmp); 3483 break; 3484 case 4: 3485 ctxt->dst.val = swab32((u32)ctxt->src.val); 3486 break; 3487 case 8: 3488 ctxt->dst.val = swab64(ctxt->src.val); 3489 break; 3490 default: 3491 BUG(); 3492 } 3493 return X86EMUL_CONTINUE; 3494 } 3495 3496 static int em_cr_write(struct x86_emulate_ctxt *ctxt) 3497 { 3498 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) 3499 return emulate_gp(ctxt, 0); 3500 3501 /* Disable writeback. */ 3502 ctxt->dst.type = OP_NONE; 3503 return X86EMUL_CONTINUE; 3504 } 3505 3506 static int em_dr_write(struct x86_emulate_ctxt *ctxt) 3507 { 3508 unsigned long val; 3509 3510 if (ctxt->mode == X86EMUL_MODE_PROT64) 3511 val = ctxt->src.val & ~0ULL; 3512 else 3513 val = ctxt->src.val & ~0U; 3514 3515 /* #UD condition is already handled. */ 3516 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0) 3517 return emulate_gp(ctxt, 0); 3518 3519 /* Disable writeback. */ 3520 ctxt->dst.type = OP_NONE; 3521 return X86EMUL_CONTINUE; 3522 } 3523 3524 static int em_wrmsr(struct x86_emulate_ctxt *ctxt) 3525 { 3526 u64 msr_data; 3527 3528 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX) 3529 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32); 3530 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data)) 3531 return emulate_gp(ctxt, 0); 3532 3533 return X86EMUL_CONTINUE; 3534 } 3535 3536 static int em_rdmsr(struct x86_emulate_ctxt *ctxt) 3537 { 3538 u64 msr_data; 3539 3540 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data)) 3541 return emulate_gp(ctxt, 0); 3542 3543 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data; 3544 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32; 3545 return X86EMUL_CONTINUE; 3546 } 3547 3548 static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt) 3549 { 3550 if (ctxt->modrm_reg > VCPU_SREG_GS) 3551 return emulate_ud(ctxt); 3552 3553 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg); 3554 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM) 3555 ctxt->dst.bytes = 2; 3556 return X86EMUL_CONTINUE; 3557 } 3558 3559 static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt) 3560 { 3561 u16 sel = ctxt->src.val; 3562 3563 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS) 3564 return emulate_ud(ctxt); 3565 3566 if (ctxt->modrm_reg == VCPU_SREG_SS) 3567 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; 3568 3569 /* Disable writeback. */ 3570 ctxt->dst.type = OP_NONE; 3571 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg); 3572 } 3573 3574 static int em_lldt(struct x86_emulate_ctxt *ctxt) 3575 { 3576 u16 sel = ctxt->src.val; 3577 3578 /* Disable writeback. */ 3579 ctxt->dst.type = OP_NONE; 3580 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR); 3581 } 3582 3583 static int em_ltr(struct x86_emulate_ctxt *ctxt) 3584 { 3585 u16 sel = ctxt->src.val; 3586 3587 /* Disable writeback. */ 3588 ctxt->dst.type = OP_NONE; 3589 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR); 3590 } 3591 3592 static int em_invlpg(struct x86_emulate_ctxt *ctxt) 3593 { 3594 int rc; 3595 ulong linear; 3596 3597 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear); 3598 if (rc == X86EMUL_CONTINUE) 3599 ctxt->ops->invlpg(ctxt, linear); 3600 /* Disable writeback. */ 3601 ctxt->dst.type = OP_NONE; 3602 return X86EMUL_CONTINUE; 3603 } 3604 3605 static int em_clts(struct x86_emulate_ctxt *ctxt) 3606 { 3607 ulong cr0; 3608 3609 cr0 = ctxt->ops->get_cr(ctxt, 0); 3610 cr0 &= ~X86_CR0_TS; 3611 ctxt->ops->set_cr(ctxt, 0, cr0); 3612 return X86EMUL_CONTINUE; 3613 } 3614 3615 static int em_hypercall(struct x86_emulate_ctxt *ctxt) 3616 { 3617 int rc = ctxt->ops->fix_hypercall(ctxt); 3618 3619 if (rc != X86EMUL_CONTINUE) 3620 return rc; 3621 3622 /* Let the processor re-execute the fixed hypercall */ 3623 ctxt->_eip = ctxt->eip; 3624 /* Disable writeback. */ 3625 ctxt->dst.type = OP_NONE; 3626 return X86EMUL_CONTINUE; 3627 } 3628 3629 static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt, 3630 void (*get)(struct x86_emulate_ctxt *ctxt, 3631 struct desc_ptr *ptr)) 3632 { 3633 struct desc_ptr desc_ptr; 3634 3635 if (ctxt->mode == X86EMUL_MODE_PROT64) 3636 ctxt->op_bytes = 8; 3637 get(ctxt, &desc_ptr); 3638 if (ctxt->op_bytes == 2) { 3639 ctxt->op_bytes = 4; 3640 desc_ptr.address &= 0x00ffffff; 3641 } 3642 /* Disable writeback. */ 3643 ctxt->dst.type = OP_NONE; 3644 return segmented_write(ctxt, ctxt->dst.addr.mem, 3645 &desc_ptr, 2 + ctxt->op_bytes); 3646 } 3647 3648 static int em_sgdt(struct x86_emulate_ctxt *ctxt) 3649 { 3650 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt); 3651 } 3652 3653 static int em_sidt(struct x86_emulate_ctxt *ctxt) 3654 { 3655 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt); 3656 } 3657 3658 static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt) 3659 { 3660 struct desc_ptr desc_ptr; 3661 int rc; 3662 3663 if (ctxt->mode == X86EMUL_MODE_PROT64) 3664 ctxt->op_bytes = 8; 3665 rc = read_descriptor(ctxt, ctxt->src.addr.mem, 3666 &desc_ptr.size, &desc_ptr.address, 3667 ctxt->op_bytes); 3668 if (rc != X86EMUL_CONTINUE) 3669 return rc; 3670 if (ctxt->mode == X86EMUL_MODE_PROT64 && 3671 is_noncanonical_address(desc_ptr.address)) 3672 return emulate_gp(ctxt, 0); 3673 if (lgdt) 3674 ctxt->ops->set_gdt(ctxt, &desc_ptr); 3675 else 3676 ctxt->ops->set_idt(ctxt, &desc_ptr); 3677 /* Disable writeback. */ 3678 ctxt->dst.type = OP_NONE; 3679 return X86EMUL_CONTINUE; 3680 } 3681 3682 static int em_lgdt(struct x86_emulate_ctxt *ctxt) 3683 { 3684 return em_lgdt_lidt(ctxt, true); 3685 } 3686 3687 static int em_lidt(struct x86_emulate_ctxt *ctxt) 3688 { 3689 return em_lgdt_lidt(ctxt, false); 3690 } 3691 3692 static int em_smsw(struct x86_emulate_ctxt *ctxt) 3693 { 3694 if (ctxt->dst.type == OP_MEM) 3695 ctxt->dst.bytes = 2; 3696 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0); 3697 return X86EMUL_CONTINUE; 3698 } 3699 3700 static int em_lmsw(struct x86_emulate_ctxt *ctxt) 3701 { 3702 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul) 3703 | (ctxt->src.val & 0x0f)); 3704 ctxt->dst.type = OP_NONE; 3705 return X86EMUL_CONTINUE; 3706 } 3707 3708 static int em_loop(struct x86_emulate_ctxt *ctxt) 3709 { 3710 int rc = X86EMUL_CONTINUE; 3711 3712 register_address_increment(ctxt, VCPU_REGS_RCX, -1); 3713 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) && 3714 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags))) 3715 rc = jmp_rel(ctxt, ctxt->src.val); 3716 3717 return rc; 3718 } 3719 3720 static int em_jcxz(struct x86_emulate_ctxt *ctxt) 3721 { 3722 int rc = X86EMUL_CONTINUE; 3723 3724 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) 3725 rc = jmp_rel(ctxt, ctxt->src.val); 3726 3727 return rc; 3728 } 3729 3730 static int em_in(struct x86_emulate_ctxt *ctxt) 3731 { 3732 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val, 3733 &ctxt->dst.val)) 3734 return X86EMUL_IO_NEEDED; 3735 3736 return X86EMUL_CONTINUE; 3737 } 3738 3739 static int em_out(struct x86_emulate_ctxt *ctxt) 3740 { 3741 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val, 3742 &ctxt->src.val, 1); 3743 /* Disable writeback. */ 3744 ctxt->dst.type = OP_NONE; 3745 return X86EMUL_CONTINUE; 3746 } 3747 3748 static int em_cli(struct x86_emulate_ctxt *ctxt) 3749 { 3750 if (emulator_bad_iopl(ctxt)) 3751 return emulate_gp(ctxt, 0); 3752 3753 ctxt->eflags &= ~X86_EFLAGS_IF; 3754 return X86EMUL_CONTINUE; 3755 } 3756 3757 static int em_sti(struct x86_emulate_ctxt *ctxt) 3758 { 3759 if (emulator_bad_iopl(ctxt)) 3760 return emulate_gp(ctxt, 0); 3761 3762 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; 3763 ctxt->eflags |= X86_EFLAGS_IF; 3764 return X86EMUL_CONTINUE; 3765 } 3766 3767 static int em_cpuid(struct x86_emulate_ctxt *ctxt) 3768 { 3769 u32 eax, ebx, ecx, edx; 3770 3771 eax = reg_read(ctxt, VCPU_REGS_RAX); 3772 ecx = reg_read(ctxt, VCPU_REGS_RCX); 3773 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); 3774 *reg_write(ctxt, VCPU_REGS_RAX) = eax; 3775 *reg_write(ctxt, VCPU_REGS_RBX) = ebx; 3776 *reg_write(ctxt, VCPU_REGS_RCX) = ecx; 3777 *reg_write(ctxt, VCPU_REGS_RDX) = edx; 3778 return X86EMUL_CONTINUE; 3779 } 3780 3781 static int em_sahf(struct x86_emulate_ctxt *ctxt) 3782 { 3783 u32 flags; 3784 3785 flags = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF | 3786 X86_EFLAGS_SF; 3787 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8; 3788 3789 ctxt->eflags &= ~0xffUL; 3790 ctxt->eflags |= flags | X86_EFLAGS_FIXED; 3791 return X86EMUL_CONTINUE; 3792 } 3793 3794 static int em_lahf(struct x86_emulate_ctxt *ctxt) 3795 { 3796 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL; 3797 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8; 3798 return X86EMUL_CONTINUE; 3799 } 3800 3801 static int em_bswap(struct x86_emulate_ctxt *ctxt) 3802 { 3803 switch (ctxt->op_bytes) { 3804 #ifdef CONFIG_X86_64 3805 case 8: 3806 asm("bswap %0" : "+r"(ctxt->dst.val)); 3807 break; 3808 #endif 3809 default: 3810 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val)); 3811 break; 3812 } 3813 return X86EMUL_CONTINUE; 3814 } 3815 3816 static int em_clflush(struct x86_emulate_ctxt *ctxt) 3817 { 3818 /* emulating clflush regardless of cpuid */ 3819 return X86EMUL_CONTINUE; 3820 } 3821 3822 static int em_movsxd(struct x86_emulate_ctxt *ctxt) 3823 { 3824 ctxt->dst.val = (s32) ctxt->src.val; 3825 return X86EMUL_CONTINUE; 3826 } 3827 3828 static bool valid_cr(int nr) 3829 { 3830 switch (nr) { 3831 case 0: 3832 case 2 ... 4: 3833 case 8: 3834 return true; 3835 default: 3836 return false; 3837 } 3838 } 3839 3840 static int check_cr_read(struct x86_emulate_ctxt *ctxt) 3841 { 3842 if (!valid_cr(ctxt->modrm_reg)) 3843 return emulate_ud(ctxt); 3844 3845 return X86EMUL_CONTINUE; 3846 } 3847 3848 static int check_cr_write(struct x86_emulate_ctxt *ctxt) 3849 { 3850 u64 new_val = ctxt->src.val64; 3851 int cr = ctxt->modrm_reg; 3852 u64 efer = 0; 3853 3854 static u64 cr_reserved_bits[] = { 3855 0xffffffff00000000ULL, 3856 0, 0, 0, /* CR3 checked later */ 3857 CR4_RESERVED_BITS, 3858 0, 0, 0, 3859 CR8_RESERVED_BITS, 3860 }; 3861 3862 if (!valid_cr(cr)) 3863 return emulate_ud(ctxt); 3864 3865 if (new_val & cr_reserved_bits[cr]) 3866 return emulate_gp(ctxt, 0); 3867 3868 switch (cr) { 3869 case 0: { 3870 u64 cr4; 3871 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) || 3872 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD))) 3873 return emulate_gp(ctxt, 0); 3874 3875 cr4 = ctxt->ops->get_cr(ctxt, 4); 3876 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 3877 3878 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) && 3879 !(cr4 & X86_CR4_PAE)) 3880 return emulate_gp(ctxt, 0); 3881 3882 break; 3883 } 3884 case 3: { 3885 u64 rsvd = 0; 3886 3887 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 3888 if (efer & EFER_LMA) 3889 rsvd = CR3_L_MODE_RESERVED_BITS & ~CR3_PCID_INVD; 3890 3891 if (new_val & rsvd) 3892 return emulate_gp(ctxt, 0); 3893 3894 break; 3895 } 3896 case 4: { 3897 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 3898 3899 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE)) 3900 return emulate_gp(ctxt, 0); 3901 3902 break; 3903 } 3904 } 3905 3906 return X86EMUL_CONTINUE; 3907 } 3908 3909 static int check_dr7_gd(struct x86_emulate_ctxt *ctxt) 3910 { 3911 unsigned long dr7; 3912 3913 ctxt->ops->get_dr(ctxt, 7, &dr7); 3914 3915 /* Check if DR7.Global_Enable is set */ 3916 return dr7 & (1 << 13); 3917 } 3918 3919 static int check_dr_read(struct x86_emulate_ctxt *ctxt) 3920 { 3921 int dr = ctxt->modrm_reg; 3922 u64 cr4; 3923 3924 if (dr > 7) 3925 return emulate_ud(ctxt); 3926 3927 cr4 = ctxt->ops->get_cr(ctxt, 4); 3928 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5)) 3929 return emulate_ud(ctxt); 3930 3931 if (check_dr7_gd(ctxt)) { 3932 ulong dr6; 3933 3934 ctxt->ops->get_dr(ctxt, 6, &dr6); 3935 dr6 &= ~15; 3936 dr6 |= DR6_BD | DR6_RTM; 3937 ctxt->ops->set_dr(ctxt, 6, dr6); 3938 return emulate_db(ctxt); 3939 } 3940 3941 return X86EMUL_CONTINUE; 3942 } 3943 3944 static int check_dr_write(struct x86_emulate_ctxt *ctxt) 3945 { 3946 u64 new_val = ctxt->src.val64; 3947 int dr = ctxt->modrm_reg; 3948 3949 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL)) 3950 return emulate_gp(ctxt, 0); 3951 3952 return check_dr_read(ctxt); 3953 } 3954 3955 static int check_svme(struct x86_emulate_ctxt *ctxt) 3956 { 3957 u64 efer; 3958 3959 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 3960 3961 if (!(efer & EFER_SVME)) 3962 return emulate_ud(ctxt); 3963 3964 return X86EMUL_CONTINUE; 3965 } 3966 3967 static int check_svme_pa(struct x86_emulate_ctxt *ctxt) 3968 { 3969 u64 rax = reg_read(ctxt, VCPU_REGS_RAX); 3970 3971 /* Valid physical address? */ 3972 if (rax & 0xffff000000000000ULL) 3973 return emulate_gp(ctxt, 0); 3974 3975 return check_svme(ctxt); 3976 } 3977 3978 static int check_rdtsc(struct x86_emulate_ctxt *ctxt) 3979 { 3980 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 3981 3982 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt)) 3983 return emulate_ud(ctxt); 3984 3985 return X86EMUL_CONTINUE; 3986 } 3987 3988 static int check_rdpmc(struct x86_emulate_ctxt *ctxt) 3989 { 3990 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 3991 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX); 3992 3993 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) || 3994 ctxt->ops->check_pmc(ctxt, rcx)) 3995 return emulate_gp(ctxt, 0); 3996 3997 return X86EMUL_CONTINUE; 3998 } 3999 4000 static int check_perm_in(struct x86_emulate_ctxt *ctxt) 4001 { 4002 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u); 4003 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes)) 4004 return emulate_gp(ctxt, 0); 4005 4006 return X86EMUL_CONTINUE; 4007 } 4008 4009 static int check_perm_out(struct x86_emulate_ctxt *ctxt) 4010 { 4011 ctxt->src.bytes = min(ctxt->src.bytes, 4u); 4012 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes)) 4013 return emulate_gp(ctxt, 0); 4014 4015 return X86EMUL_CONTINUE; 4016 } 4017 4018 #define D(_y) { .flags = (_y) } 4019 #define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i } 4020 #define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \ 4021 .intercept = x86_intercept_##_i, .check_perm = (_p) } 4022 #define N D(NotImpl) 4023 #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) } 4024 #define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) } 4025 #define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) } 4026 #define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) } 4027 #define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) } 4028 #define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) } 4029 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } 4030 #define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) } 4031 #define II(_f, _e, _i) \ 4032 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i } 4033 #define IIP(_f, _e, _i, _p) \ 4034 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \ 4035 .intercept = x86_intercept_##_i, .check_perm = (_p) } 4036 #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) } 4037 4038 #define D2bv(_f) D((_f) | ByteOp), D(_f) 4039 #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p) 4040 #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) 4041 #define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e) 4042 #define I2bvIP(_f, _e, _i, _p) \ 4043 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p) 4044 4045 #define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \ 4046 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \ 4047 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e) 4048 4049 static const struct opcode group7_rm0[] = { 4050 N, 4051 I(SrcNone | Priv | EmulateOnUD, em_hypercall), 4052 N, N, N, N, N, N, 4053 }; 4054 4055 static const struct opcode group7_rm1[] = { 4056 DI(SrcNone | Priv, monitor), 4057 DI(SrcNone | Priv, mwait), 4058 N, N, N, N, N, N, 4059 }; 4060 4061 static const struct opcode group7_rm3[] = { 4062 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa), 4063 II(SrcNone | Prot | EmulateOnUD, em_hypercall, vmmcall), 4064 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa), 4065 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa), 4066 DIP(SrcNone | Prot | Priv, stgi, check_svme), 4067 DIP(SrcNone | Prot | Priv, clgi, check_svme), 4068 DIP(SrcNone | Prot | Priv, skinit, check_svme), 4069 DIP(SrcNone | Prot | Priv, invlpga, check_svme), 4070 }; 4071 4072 static const struct opcode group7_rm7[] = { 4073 N, 4074 DIP(SrcNone, rdtscp, check_rdtsc), 4075 N, N, N, N, N, N, 4076 }; 4077 4078 static const struct opcode group1[] = { 4079 F(Lock, em_add), 4080 F(Lock | PageTable, em_or), 4081 F(Lock, em_adc), 4082 F(Lock, em_sbb), 4083 F(Lock | PageTable, em_and), 4084 F(Lock, em_sub), 4085 F(Lock, em_xor), 4086 F(NoWrite, em_cmp), 4087 }; 4088 4089 static const struct opcode group1A[] = { 4090 I(DstMem | SrcNone | Mov | Stack | IncSP, em_pop), N, N, N, N, N, N, N, 4091 }; 4092 4093 static const struct opcode group2[] = { 4094 F(DstMem | ModRM, em_rol), 4095 F(DstMem | ModRM, em_ror), 4096 F(DstMem | ModRM, em_rcl), 4097 F(DstMem | ModRM, em_rcr), 4098 F(DstMem | ModRM, em_shl), 4099 F(DstMem | ModRM, em_shr), 4100 F(DstMem | ModRM, em_shl), 4101 F(DstMem | ModRM, em_sar), 4102 }; 4103 4104 static const struct opcode group3[] = { 4105 F(DstMem | SrcImm | NoWrite, em_test), 4106 F(DstMem | SrcImm | NoWrite, em_test), 4107 F(DstMem | SrcNone | Lock, em_not), 4108 F(DstMem | SrcNone | Lock, em_neg), 4109 F(DstXacc | Src2Mem, em_mul_ex), 4110 F(DstXacc | Src2Mem, em_imul_ex), 4111 F(DstXacc | Src2Mem, em_div_ex), 4112 F(DstXacc | Src2Mem, em_idiv_ex), 4113 }; 4114 4115 static const struct opcode group4[] = { 4116 F(ByteOp | DstMem | SrcNone | Lock, em_inc), 4117 F(ByteOp | DstMem | SrcNone | Lock, em_dec), 4118 N, N, N, N, N, N, 4119 }; 4120 4121 static const struct opcode group5[] = { 4122 F(DstMem | SrcNone | Lock, em_inc), 4123 F(DstMem | SrcNone | Lock, em_dec), 4124 I(SrcMem | NearBranch, em_call_near_abs), 4125 I(SrcMemFAddr | ImplicitOps, em_call_far), 4126 I(SrcMem | NearBranch, em_jmp_abs), 4127 I(SrcMemFAddr | ImplicitOps, em_jmp_far), 4128 I(SrcMem | Stack, em_push), D(Undefined), 4129 }; 4130 4131 static const struct opcode group6[] = { 4132 DI(Prot | DstMem, sldt), 4133 DI(Prot | DstMem, str), 4134 II(Prot | Priv | SrcMem16, em_lldt, lldt), 4135 II(Prot | Priv | SrcMem16, em_ltr, ltr), 4136 N, N, N, N, 4137 }; 4138 4139 static const struct group_dual group7 = { { 4140 II(Mov | DstMem, em_sgdt, sgdt), 4141 II(Mov | DstMem, em_sidt, sidt), 4142 II(SrcMem | Priv, em_lgdt, lgdt), 4143 II(SrcMem | Priv, em_lidt, lidt), 4144 II(SrcNone | DstMem | Mov, em_smsw, smsw), N, 4145 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), 4146 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg), 4147 }, { 4148 EXT(0, group7_rm0), 4149 EXT(0, group7_rm1), 4150 N, EXT(0, group7_rm3), 4151 II(SrcNone | DstMem | Mov, em_smsw, smsw), N, 4152 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), 4153 EXT(0, group7_rm7), 4154 } }; 4155 4156 static const struct opcode group8[] = { 4157 N, N, N, N, 4158 F(DstMem | SrcImmByte | NoWrite, em_bt), 4159 F(DstMem | SrcImmByte | Lock | PageTable, em_bts), 4160 F(DstMem | SrcImmByte | Lock, em_btr), 4161 F(DstMem | SrcImmByte | Lock | PageTable, em_btc), 4162 }; 4163 4164 static const struct group_dual group9 = { { 4165 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N, 4166 }, { 4167 N, N, N, N, N, N, N, N, 4168 } }; 4169 4170 static const struct opcode group11[] = { 4171 I(DstMem | SrcImm | Mov | PageTable, em_mov), 4172 X7(D(Undefined)), 4173 }; 4174 4175 static const struct gprefix pfx_0f_ae_7 = { 4176 I(SrcMem | ByteOp, em_clflush), N, N, N, 4177 }; 4178 4179 static const struct group_dual group15 = { { 4180 N, N, N, N, N, N, N, GP(0, &pfx_0f_ae_7), 4181 }, { 4182 N, N, N, N, N, N, N, N, 4183 } }; 4184 4185 static const struct gprefix pfx_0f_6f_0f_7f = { 4186 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov), 4187 }; 4188 4189 static const struct instr_dual instr_dual_0f_2b = { 4190 I(0, em_mov), N 4191 }; 4192 4193 static const struct gprefix pfx_0f_2b = { 4194 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N, 4195 }; 4196 4197 static const struct gprefix pfx_0f_28_0f_29 = { 4198 I(Aligned, em_mov), I(Aligned, em_mov), N, N, 4199 }; 4200 4201 static const struct gprefix pfx_0f_e7 = { 4202 N, I(Sse, em_mov), N, N, 4203 }; 4204 4205 static const struct escape escape_d9 = { { 4206 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw), 4207 }, { 4208 /* 0xC0 - 0xC7 */ 4209 N, N, N, N, N, N, N, N, 4210 /* 0xC8 - 0xCF */ 4211 N, N, N, N, N, N, N, N, 4212 /* 0xD0 - 0xC7 */ 4213 N, N, N, N, N, N, N, N, 4214 /* 0xD8 - 0xDF */ 4215 N, N, N, N, N, N, N, N, 4216 /* 0xE0 - 0xE7 */ 4217 N, N, N, N, N, N, N, N, 4218 /* 0xE8 - 0xEF */ 4219 N, N, N, N, N, N, N, N, 4220 /* 0xF0 - 0xF7 */ 4221 N, N, N, N, N, N, N, N, 4222 /* 0xF8 - 0xFF */ 4223 N, N, N, N, N, N, N, N, 4224 } }; 4225 4226 static const struct escape escape_db = { { 4227 N, N, N, N, N, N, N, N, 4228 }, { 4229 /* 0xC0 - 0xC7 */ 4230 N, N, N, N, N, N, N, N, 4231 /* 0xC8 - 0xCF */ 4232 N, N, N, N, N, N, N, N, 4233 /* 0xD0 - 0xC7 */ 4234 N, N, N, N, N, N, N, N, 4235 /* 0xD8 - 0xDF */ 4236 N, N, N, N, N, N, N, N, 4237 /* 0xE0 - 0xE7 */ 4238 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N, 4239 /* 0xE8 - 0xEF */ 4240 N, N, N, N, N, N, N, N, 4241 /* 0xF0 - 0xF7 */ 4242 N, N, N, N, N, N, N, N, 4243 /* 0xF8 - 0xFF */ 4244 N, N, N, N, N, N, N, N, 4245 } }; 4246 4247 static const struct escape escape_dd = { { 4248 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw), 4249 }, { 4250 /* 0xC0 - 0xC7 */ 4251 N, N, N, N, N, N, N, N, 4252 /* 0xC8 - 0xCF */ 4253 N, N, N, N, N, N, N, N, 4254 /* 0xD0 - 0xC7 */ 4255 N, N, N, N, N, N, N, N, 4256 /* 0xD8 - 0xDF */ 4257 N, N, N, N, N, N, N, N, 4258 /* 0xE0 - 0xE7 */ 4259 N, N, N, N, N, N, N, N, 4260 /* 0xE8 - 0xEF */ 4261 N, N, N, N, N, N, N, N, 4262 /* 0xF0 - 0xF7 */ 4263 N, N, N, N, N, N, N, N, 4264 /* 0xF8 - 0xFF */ 4265 N, N, N, N, N, N, N, N, 4266 } }; 4267 4268 static const struct instr_dual instr_dual_0f_c3 = { 4269 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N 4270 }; 4271 4272 static const struct mode_dual mode_dual_63 = { 4273 N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd) 4274 }; 4275 4276 static const struct opcode opcode_table[256] = { 4277 /* 0x00 - 0x07 */ 4278 F6ALU(Lock, em_add), 4279 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg), 4280 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg), 4281 /* 0x08 - 0x0F */ 4282 F6ALU(Lock | PageTable, em_or), 4283 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg), 4284 N, 4285 /* 0x10 - 0x17 */ 4286 F6ALU(Lock, em_adc), 4287 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg), 4288 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg), 4289 /* 0x18 - 0x1F */ 4290 F6ALU(Lock, em_sbb), 4291 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg), 4292 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg), 4293 /* 0x20 - 0x27 */ 4294 F6ALU(Lock | PageTable, em_and), N, N, 4295 /* 0x28 - 0x2F */ 4296 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das), 4297 /* 0x30 - 0x37 */ 4298 F6ALU(Lock, em_xor), N, N, 4299 /* 0x38 - 0x3F */ 4300 F6ALU(NoWrite, em_cmp), N, N, 4301 /* 0x40 - 0x4F */ 4302 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)), 4303 /* 0x50 - 0x57 */ 4304 X8(I(SrcReg | Stack, em_push)), 4305 /* 0x58 - 0x5F */ 4306 X8(I(DstReg | Stack, em_pop)), 4307 /* 0x60 - 0x67 */ 4308 I(ImplicitOps | Stack | No64, em_pusha), 4309 I(ImplicitOps | Stack | No64, em_popa), 4310 N, MD(ModRM, &mode_dual_63), 4311 N, N, N, N, 4312 /* 0x68 - 0x6F */ 4313 I(SrcImm | Mov | Stack, em_push), 4314 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), 4315 I(SrcImmByte | Mov | Stack, em_push), 4316 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), 4317 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */ 4318 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */ 4319 /* 0x70 - 0x7F */ 4320 X16(D(SrcImmByte | NearBranch)), 4321 /* 0x80 - 0x87 */ 4322 G(ByteOp | DstMem | SrcImm, group1), 4323 G(DstMem | SrcImm, group1), 4324 G(ByteOp | DstMem | SrcImm | No64, group1), 4325 G(DstMem | SrcImmByte, group1), 4326 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test), 4327 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg), 4328 /* 0x88 - 0x8F */ 4329 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov), 4330 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov), 4331 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg), 4332 D(ModRM | SrcMem | NoAccess | DstReg), 4333 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm), 4334 G(0, group1A), 4335 /* 0x90 - 0x97 */ 4336 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)), 4337 /* 0x98 - 0x9F */ 4338 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), 4339 I(SrcImmFAddr | No64, em_call_far), N, 4340 II(ImplicitOps | Stack, em_pushf, pushf), 4341 II(ImplicitOps | Stack, em_popf, popf), 4342 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf), 4343 /* 0xA0 - 0xA7 */ 4344 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), 4345 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov), 4346 I2bv(SrcSI | DstDI | Mov | String, em_mov), 4347 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp_r), 4348 /* 0xA8 - 0xAF */ 4349 F2bv(DstAcc | SrcImm | NoWrite, em_test), 4350 I2bv(SrcAcc | DstDI | Mov | String, em_mov), 4351 I2bv(SrcSI | DstAcc | Mov | String, em_mov), 4352 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r), 4353 /* 0xB0 - 0xB7 */ 4354 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), 4355 /* 0xB8 - 0xBF */ 4356 X8(I(DstReg | SrcImm64 | Mov, em_mov)), 4357 /* 0xC0 - 0xC7 */ 4358 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2), 4359 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm), 4360 I(ImplicitOps | NearBranch, em_ret), 4361 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg), 4362 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg), 4363 G(ByteOp, group11), G(0, group11), 4364 /* 0xC8 - 0xCF */ 4365 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave), 4366 I(ImplicitOps | SrcImmU16, em_ret_far_imm), 4367 I(ImplicitOps, em_ret_far), 4368 D(ImplicitOps), DI(SrcImmByte, intn), 4369 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret), 4370 /* 0xD0 - 0xD7 */ 4371 G(Src2One | ByteOp, group2), G(Src2One, group2), 4372 G(Src2CL | ByteOp, group2), G(Src2CL, group2), 4373 I(DstAcc | SrcImmUByte | No64, em_aam), 4374 I(DstAcc | SrcImmUByte | No64, em_aad), 4375 F(DstAcc | ByteOp | No64, em_salc), 4376 I(DstAcc | SrcXLat | ByteOp, em_mov), 4377 /* 0xD8 - 0xDF */ 4378 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N, 4379 /* 0xE0 - 0xE7 */ 4380 X3(I(SrcImmByte | NearBranch, em_loop)), 4381 I(SrcImmByte | NearBranch, em_jcxz), 4382 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in), 4383 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out), 4384 /* 0xE8 - 0xEF */ 4385 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch), 4386 I(SrcImmFAddr | No64, em_jmp_far), 4387 D(SrcImmByte | ImplicitOps | NearBranch), 4388 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in), 4389 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out), 4390 /* 0xF0 - 0xF7 */ 4391 N, DI(ImplicitOps, icebp), N, N, 4392 DI(ImplicitOps | Priv, hlt), D(ImplicitOps), 4393 G(ByteOp, group3), G(0, group3), 4394 /* 0xF8 - 0xFF */ 4395 D(ImplicitOps), D(ImplicitOps), 4396 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti), 4397 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), 4398 }; 4399 4400 static const struct opcode twobyte_table[256] = { 4401 /* 0x00 - 0x0F */ 4402 G(0, group6), GD(0, &group7), N, N, 4403 N, I(ImplicitOps | EmulateOnUD, em_syscall), 4404 II(ImplicitOps | Priv, em_clts, clts), N, 4405 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, 4406 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N, 4407 /* 0x10 - 0x1F */ 4408 N, N, N, N, N, N, N, N, 4409 D(ImplicitOps | ModRM | SrcMem | NoAccess), 4410 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess), 4411 /* 0x20 - 0x2F */ 4412 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read), 4413 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read), 4414 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write, 4415 check_cr_write), 4416 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write, 4417 check_dr_write), 4418 N, N, N, N, 4419 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29), 4420 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29), 4421 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b), 4422 N, N, N, N, 4423 /* 0x30 - 0x3F */ 4424 II(ImplicitOps | Priv, em_wrmsr, wrmsr), 4425 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc), 4426 II(ImplicitOps | Priv, em_rdmsr, rdmsr), 4427 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc), 4428 I(ImplicitOps | EmulateOnUD, em_sysenter), 4429 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit), 4430 N, N, 4431 N, N, N, N, N, N, N, N, 4432 /* 0x40 - 0x4F */ 4433 X16(D(DstReg | SrcMem | ModRM)), 4434 /* 0x50 - 0x5F */ 4435 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 4436 /* 0x60 - 0x6F */ 4437 N, N, N, N, 4438 N, N, N, N, 4439 N, N, N, N, 4440 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f), 4441 /* 0x70 - 0x7F */ 4442 N, N, N, N, 4443 N, N, N, N, 4444 N, N, N, N, 4445 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f), 4446 /* 0x80 - 0x8F */ 4447 X16(D(SrcImm | NearBranch)), 4448 /* 0x90 - 0x9F */ 4449 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), 4450 /* 0xA0 - 0xA7 */ 4451 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg), 4452 II(ImplicitOps, em_cpuid, cpuid), 4453 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt), 4454 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld), 4455 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N, 4456 /* 0xA8 - 0xAF */ 4457 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg), 4458 II(No64 | EmulateOnUD | ImplicitOps, em_rsm, rsm), 4459 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts), 4460 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd), 4461 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd), 4462 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul), 4463 /* 0xB0 - 0xB7 */ 4464 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg), 4465 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg), 4466 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr), 4467 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg), 4468 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg), 4469 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 4470 /* 0xB8 - 0xBF */ 4471 N, N, 4472 G(BitOp, group8), 4473 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc), 4474 I(DstReg | SrcMem | ModRM, em_bsf_c), 4475 I(DstReg | SrcMem | ModRM, em_bsr_c), 4476 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 4477 /* 0xC0 - 0xC7 */ 4478 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd), 4479 N, ID(0, &instr_dual_0f_c3), 4480 N, N, N, GD(0, &group9), 4481 /* 0xC8 - 0xCF */ 4482 X8(I(DstReg, em_bswap)), 4483 /* 0xD0 - 0xDF */ 4484 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 4485 /* 0xE0 - 0xEF */ 4486 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7), 4487 N, N, N, N, N, N, N, N, 4488 /* 0xF0 - 0xFF */ 4489 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N 4490 }; 4491 4492 static const struct instr_dual instr_dual_0f_38_f0 = { 4493 I(DstReg | SrcMem | Mov, em_movbe), N 4494 }; 4495 4496 static const struct instr_dual instr_dual_0f_38_f1 = { 4497 I(DstMem | SrcReg | Mov, em_movbe), N 4498 }; 4499 4500 static const struct gprefix three_byte_0f_38_f0 = { 4501 ID(0, &instr_dual_0f_38_f0), N, N, N 4502 }; 4503 4504 static const struct gprefix three_byte_0f_38_f1 = { 4505 ID(0, &instr_dual_0f_38_f1), N, N, N 4506 }; 4507 4508 /* 4509 * Insns below are selected by the prefix which indexed by the third opcode 4510 * byte. 4511 */ 4512 static const struct opcode opcode_map_0f_38[256] = { 4513 /* 0x00 - 0x7f */ 4514 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), 4515 /* 0x80 - 0xef */ 4516 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), 4517 /* 0xf0 - 0xf1 */ 4518 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0), 4519 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1), 4520 /* 0xf2 - 0xff */ 4521 N, N, X4(N), X8(N) 4522 }; 4523 4524 #undef D 4525 #undef N 4526 #undef G 4527 #undef GD 4528 #undef I 4529 #undef GP 4530 #undef EXT 4531 #undef MD 4532 #undef ID 4533 4534 #undef D2bv 4535 #undef D2bvIP 4536 #undef I2bv 4537 #undef I2bvIP 4538 #undef I6ALU 4539 4540 static unsigned imm_size(struct x86_emulate_ctxt *ctxt) 4541 { 4542 unsigned size; 4543 4544 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4545 if (size == 8) 4546 size = 4; 4547 return size; 4548 } 4549 4550 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, 4551 unsigned size, bool sign_extension) 4552 { 4553 int rc = X86EMUL_CONTINUE; 4554 4555 op->type = OP_IMM; 4556 op->bytes = size; 4557 op->addr.mem.ea = ctxt->_eip; 4558 /* NB. Immediates are sign-extended as necessary. */ 4559 switch (op->bytes) { 4560 case 1: 4561 op->val = insn_fetch(s8, ctxt); 4562 break; 4563 case 2: 4564 op->val = insn_fetch(s16, ctxt); 4565 break; 4566 case 4: 4567 op->val = insn_fetch(s32, ctxt); 4568 break; 4569 case 8: 4570 op->val = insn_fetch(s64, ctxt); 4571 break; 4572 } 4573 if (!sign_extension) { 4574 switch (op->bytes) { 4575 case 1: 4576 op->val &= 0xff; 4577 break; 4578 case 2: 4579 op->val &= 0xffff; 4580 break; 4581 case 4: 4582 op->val &= 0xffffffff; 4583 break; 4584 } 4585 } 4586 done: 4587 return rc; 4588 } 4589 4590 static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op, 4591 unsigned d) 4592 { 4593 int rc = X86EMUL_CONTINUE; 4594 4595 switch (d) { 4596 case OpReg: 4597 decode_register_operand(ctxt, op); 4598 break; 4599 case OpImmUByte: 4600 rc = decode_imm(ctxt, op, 1, false); 4601 break; 4602 case OpMem: 4603 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4604 mem_common: 4605 *op = ctxt->memop; 4606 ctxt->memopp = op; 4607 if (ctxt->d & BitOp) 4608 fetch_bit_operand(ctxt); 4609 op->orig_val = op->val; 4610 break; 4611 case OpMem64: 4612 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8; 4613 goto mem_common; 4614 case OpAcc: 4615 op->type = OP_REG; 4616 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4617 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 4618 fetch_register_operand(op); 4619 op->orig_val = op->val; 4620 break; 4621 case OpAccLo: 4622 op->type = OP_REG; 4623 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes; 4624 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 4625 fetch_register_operand(op); 4626 op->orig_val = op->val; 4627 break; 4628 case OpAccHi: 4629 if (ctxt->d & ByteOp) { 4630 op->type = OP_NONE; 4631 break; 4632 } 4633 op->type = OP_REG; 4634 op->bytes = ctxt->op_bytes; 4635 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 4636 fetch_register_operand(op); 4637 op->orig_val = op->val; 4638 break; 4639 case OpDI: 4640 op->type = OP_MEM; 4641 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4642 op->addr.mem.ea = 4643 register_address(ctxt, VCPU_REGS_RDI); 4644 op->addr.mem.seg = VCPU_SREG_ES; 4645 op->val = 0; 4646 op->count = 1; 4647 break; 4648 case OpDX: 4649 op->type = OP_REG; 4650 op->bytes = 2; 4651 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 4652 fetch_register_operand(op); 4653 break; 4654 case OpCL: 4655 op->type = OP_IMM; 4656 op->bytes = 1; 4657 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff; 4658 break; 4659 case OpImmByte: 4660 rc = decode_imm(ctxt, op, 1, true); 4661 break; 4662 case OpOne: 4663 op->type = OP_IMM; 4664 op->bytes = 1; 4665 op->val = 1; 4666 break; 4667 case OpImm: 4668 rc = decode_imm(ctxt, op, imm_size(ctxt), true); 4669 break; 4670 case OpImm64: 4671 rc = decode_imm(ctxt, op, ctxt->op_bytes, true); 4672 break; 4673 case OpMem8: 4674 ctxt->memop.bytes = 1; 4675 if (ctxt->memop.type == OP_REG) { 4676 ctxt->memop.addr.reg = decode_register(ctxt, 4677 ctxt->modrm_rm, true); 4678 fetch_register_operand(&ctxt->memop); 4679 } 4680 goto mem_common; 4681 case OpMem16: 4682 ctxt->memop.bytes = 2; 4683 goto mem_common; 4684 case OpMem32: 4685 ctxt->memop.bytes = 4; 4686 goto mem_common; 4687 case OpImmU16: 4688 rc = decode_imm(ctxt, op, 2, false); 4689 break; 4690 case OpImmU: 4691 rc = decode_imm(ctxt, op, imm_size(ctxt), false); 4692 break; 4693 case OpSI: 4694 op->type = OP_MEM; 4695 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4696 op->addr.mem.ea = 4697 register_address(ctxt, VCPU_REGS_RSI); 4698 op->addr.mem.seg = ctxt->seg_override; 4699 op->val = 0; 4700 op->count = 1; 4701 break; 4702 case OpXLat: 4703 op->type = OP_MEM; 4704 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4705 op->addr.mem.ea = 4706 address_mask(ctxt, 4707 reg_read(ctxt, VCPU_REGS_RBX) + 4708 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff)); 4709 op->addr.mem.seg = ctxt->seg_override; 4710 op->val = 0; 4711 break; 4712 case OpImmFAddr: 4713 op->type = OP_IMM; 4714 op->addr.mem.ea = ctxt->_eip; 4715 op->bytes = ctxt->op_bytes + 2; 4716 insn_fetch_arr(op->valptr, op->bytes, ctxt); 4717 break; 4718 case OpMemFAddr: 4719 ctxt->memop.bytes = ctxt->op_bytes + 2; 4720 goto mem_common; 4721 case OpES: 4722 op->type = OP_IMM; 4723 op->val = VCPU_SREG_ES; 4724 break; 4725 case OpCS: 4726 op->type = OP_IMM; 4727 op->val = VCPU_SREG_CS; 4728 break; 4729 case OpSS: 4730 op->type = OP_IMM; 4731 op->val = VCPU_SREG_SS; 4732 break; 4733 case OpDS: 4734 op->type = OP_IMM; 4735 op->val = VCPU_SREG_DS; 4736 break; 4737 case OpFS: 4738 op->type = OP_IMM; 4739 op->val = VCPU_SREG_FS; 4740 break; 4741 case OpGS: 4742 op->type = OP_IMM; 4743 op->val = VCPU_SREG_GS; 4744 break; 4745 case OpImplicit: 4746 /* Special instructions do their own operand decoding. */ 4747 default: 4748 op->type = OP_NONE; /* Disable writeback. */ 4749 break; 4750 } 4751 4752 done: 4753 return rc; 4754 } 4755 4756 int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len) 4757 { 4758 int rc = X86EMUL_CONTINUE; 4759 int mode = ctxt->mode; 4760 int def_op_bytes, def_ad_bytes, goffset, simd_prefix; 4761 bool op_prefix = false; 4762 bool has_seg_override = false; 4763 struct opcode opcode; 4764 4765 ctxt->memop.type = OP_NONE; 4766 ctxt->memopp = NULL; 4767 ctxt->_eip = ctxt->eip; 4768 ctxt->fetch.ptr = ctxt->fetch.data; 4769 ctxt->fetch.end = ctxt->fetch.data + insn_len; 4770 ctxt->opcode_len = 1; 4771 if (insn_len > 0) 4772 memcpy(ctxt->fetch.data, insn, insn_len); 4773 else { 4774 rc = __do_insn_fetch_bytes(ctxt, 1); 4775 if (rc != X86EMUL_CONTINUE) 4776 return rc; 4777 } 4778 4779 switch (mode) { 4780 case X86EMUL_MODE_REAL: 4781 case X86EMUL_MODE_VM86: 4782 case X86EMUL_MODE_PROT16: 4783 def_op_bytes = def_ad_bytes = 2; 4784 break; 4785 case X86EMUL_MODE_PROT32: 4786 def_op_bytes = def_ad_bytes = 4; 4787 break; 4788 #ifdef CONFIG_X86_64 4789 case X86EMUL_MODE_PROT64: 4790 def_op_bytes = 4; 4791 def_ad_bytes = 8; 4792 break; 4793 #endif 4794 default: 4795 return EMULATION_FAILED; 4796 } 4797 4798 ctxt->op_bytes = def_op_bytes; 4799 ctxt->ad_bytes = def_ad_bytes; 4800 4801 /* Legacy prefixes. */ 4802 for (;;) { 4803 switch (ctxt->b = insn_fetch(u8, ctxt)) { 4804 case 0x66: /* operand-size override */ 4805 op_prefix = true; 4806 /* switch between 2/4 bytes */ 4807 ctxt->op_bytes = def_op_bytes ^ 6; 4808 break; 4809 case 0x67: /* address-size override */ 4810 if (mode == X86EMUL_MODE_PROT64) 4811 /* switch between 4/8 bytes */ 4812 ctxt->ad_bytes = def_ad_bytes ^ 12; 4813 else 4814 /* switch between 2/4 bytes */ 4815 ctxt->ad_bytes = def_ad_bytes ^ 6; 4816 break; 4817 case 0x26: /* ES override */ 4818 case 0x2e: /* CS override */ 4819 case 0x36: /* SS override */ 4820 case 0x3e: /* DS override */ 4821 has_seg_override = true; 4822 ctxt->seg_override = (ctxt->b >> 3) & 3; 4823 break; 4824 case 0x64: /* FS override */ 4825 case 0x65: /* GS override */ 4826 has_seg_override = true; 4827 ctxt->seg_override = ctxt->b & 7; 4828 break; 4829 case 0x40 ... 0x4f: /* REX */ 4830 if (mode != X86EMUL_MODE_PROT64) 4831 goto done_prefixes; 4832 ctxt->rex_prefix = ctxt->b; 4833 continue; 4834 case 0xf0: /* LOCK */ 4835 ctxt->lock_prefix = 1; 4836 break; 4837 case 0xf2: /* REPNE/REPNZ */ 4838 case 0xf3: /* REP/REPE/REPZ */ 4839 ctxt->rep_prefix = ctxt->b; 4840 break; 4841 default: 4842 goto done_prefixes; 4843 } 4844 4845 /* Any legacy prefix after a REX prefix nullifies its effect. */ 4846 4847 ctxt->rex_prefix = 0; 4848 } 4849 4850 done_prefixes: 4851 4852 /* REX prefix. */ 4853 if (ctxt->rex_prefix & 8) 4854 ctxt->op_bytes = 8; /* REX.W */ 4855 4856 /* Opcode byte(s). */ 4857 opcode = opcode_table[ctxt->b]; 4858 /* Two-byte opcode? */ 4859 if (ctxt->b == 0x0f) { 4860 ctxt->opcode_len = 2; 4861 ctxt->b = insn_fetch(u8, ctxt); 4862 opcode = twobyte_table[ctxt->b]; 4863 4864 /* 0F_38 opcode map */ 4865 if (ctxt->b == 0x38) { 4866 ctxt->opcode_len = 3; 4867 ctxt->b = insn_fetch(u8, ctxt); 4868 opcode = opcode_map_0f_38[ctxt->b]; 4869 } 4870 } 4871 ctxt->d = opcode.flags; 4872 4873 if (ctxt->d & ModRM) 4874 ctxt->modrm = insn_fetch(u8, ctxt); 4875 4876 /* vex-prefix instructions are not implemented */ 4877 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) && 4878 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) { 4879 ctxt->d = NotImpl; 4880 } 4881 4882 while (ctxt->d & GroupMask) { 4883 switch (ctxt->d & GroupMask) { 4884 case Group: 4885 goffset = (ctxt->modrm >> 3) & 7; 4886 opcode = opcode.u.group[goffset]; 4887 break; 4888 case GroupDual: 4889 goffset = (ctxt->modrm >> 3) & 7; 4890 if ((ctxt->modrm >> 6) == 3) 4891 opcode = opcode.u.gdual->mod3[goffset]; 4892 else 4893 opcode = opcode.u.gdual->mod012[goffset]; 4894 break; 4895 case RMExt: 4896 goffset = ctxt->modrm & 7; 4897 opcode = opcode.u.group[goffset]; 4898 break; 4899 case Prefix: 4900 if (ctxt->rep_prefix && op_prefix) 4901 return EMULATION_FAILED; 4902 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix; 4903 switch (simd_prefix) { 4904 case 0x00: opcode = opcode.u.gprefix->pfx_no; break; 4905 case 0x66: opcode = opcode.u.gprefix->pfx_66; break; 4906 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break; 4907 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break; 4908 } 4909 break; 4910 case Escape: 4911 if (ctxt->modrm > 0xbf) 4912 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0]; 4913 else 4914 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7]; 4915 break; 4916 case InstrDual: 4917 if ((ctxt->modrm >> 6) == 3) 4918 opcode = opcode.u.idual->mod3; 4919 else 4920 opcode = opcode.u.idual->mod012; 4921 break; 4922 case ModeDual: 4923 if (ctxt->mode == X86EMUL_MODE_PROT64) 4924 opcode = opcode.u.mdual->mode64; 4925 else 4926 opcode = opcode.u.mdual->mode32; 4927 break; 4928 default: 4929 return EMULATION_FAILED; 4930 } 4931 4932 ctxt->d &= ~(u64)GroupMask; 4933 ctxt->d |= opcode.flags; 4934 } 4935 4936 /* Unrecognised? */ 4937 if (ctxt->d == 0) 4938 return EMULATION_FAILED; 4939 4940 ctxt->execute = opcode.u.execute; 4941 4942 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD))) 4943 return EMULATION_FAILED; 4944 4945 if (unlikely(ctxt->d & 4946 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch| 4947 No16))) { 4948 /* 4949 * These are copied unconditionally here, and checked unconditionally 4950 * in x86_emulate_insn. 4951 */ 4952 ctxt->check_perm = opcode.check_perm; 4953 ctxt->intercept = opcode.intercept; 4954 4955 if (ctxt->d & NotImpl) 4956 return EMULATION_FAILED; 4957 4958 if (mode == X86EMUL_MODE_PROT64) { 4959 if (ctxt->op_bytes == 4 && (ctxt->d & Stack)) 4960 ctxt->op_bytes = 8; 4961 else if (ctxt->d & NearBranch) 4962 ctxt->op_bytes = 8; 4963 } 4964 4965 if (ctxt->d & Op3264) { 4966 if (mode == X86EMUL_MODE_PROT64) 4967 ctxt->op_bytes = 8; 4968 else 4969 ctxt->op_bytes = 4; 4970 } 4971 4972 if ((ctxt->d & No16) && ctxt->op_bytes == 2) 4973 ctxt->op_bytes = 4; 4974 4975 if (ctxt->d & Sse) 4976 ctxt->op_bytes = 16; 4977 else if (ctxt->d & Mmx) 4978 ctxt->op_bytes = 8; 4979 } 4980 4981 /* ModRM and SIB bytes. */ 4982 if (ctxt->d & ModRM) { 4983 rc = decode_modrm(ctxt, &ctxt->memop); 4984 if (!has_seg_override) { 4985 has_seg_override = true; 4986 ctxt->seg_override = ctxt->modrm_seg; 4987 } 4988 } else if (ctxt->d & MemAbs) 4989 rc = decode_abs(ctxt, &ctxt->memop); 4990 if (rc != X86EMUL_CONTINUE) 4991 goto done; 4992 4993 if (!has_seg_override) 4994 ctxt->seg_override = VCPU_SREG_DS; 4995 4996 ctxt->memop.addr.mem.seg = ctxt->seg_override; 4997 4998 /* 4999 * Decode and fetch the source operand: register, memory 5000 * or immediate. 5001 */ 5002 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask); 5003 if (rc != X86EMUL_CONTINUE) 5004 goto done; 5005 5006 /* 5007 * Decode and fetch the second source operand: register, memory 5008 * or immediate. 5009 */ 5010 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask); 5011 if (rc != X86EMUL_CONTINUE) 5012 goto done; 5013 5014 /* Decode and fetch the destination operand: register or memory. */ 5015 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask); 5016 5017 if (ctxt->rip_relative) 5018 ctxt->memopp->addr.mem.ea = address_mask(ctxt, 5019 ctxt->memopp->addr.mem.ea + ctxt->_eip); 5020 5021 done: 5022 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK; 5023 } 5024 5025 bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt) 5026 { 5027 return ctxt->d & PageTable; 5028 } 5029 5030 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt) 5031 { 5032 /* The second termination condition only applies for REPE 5033 * and REPNE. Test if the repeat string operation prefix is 5034 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the 5035 * corresponding termination condition according to: 5036 * - if REPE/REPZ and ZF = 0 then done 5037 * - if REPNE/REPNZ and ZF = 1 then done 5038 */ 5039 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) || 5040 (ctxt->b == 0xae) || (ctxt->b == 0xaf)) 5041 && (((ctxt->rep_prefix == REPE_PREFIX) && 5042 ((ctxt->eflags & X86_EFLAGS_ZF) == 0)) 5043 || ((ctxt->rep_prefix == REPNE_PREFIX) && 5044 ((ctxt->eflags & X86_EFLAGS_ZF) == X86_EFLAGS_ZF)))) 5045 return true; 5046 5047 return false; 5048 } 5049 5050 static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt) 5051 { 5052 bool fault = false; 5053 5054 ctxt->ops->get_fpu(ctxt); 5055 asm volatile("1: fwait \n\t" 5056 "2: \n\t" 5057 ".pushsection .fixup,\"ax\" \n\t" 5058 "3: \n\t" 5059 "movb $1, %[fault] \n\t" 5060 "jmp 2b \n\t" 5061 ".popsection \n\t" 5062 _ASM_EXTABLE(1b, 3b) 5063 : [fault]"+qm"(fault)); 5064 ctxt->ops->put_fpu(ctxt); 5065 5066 if (unlikely(fault)) 5067 return emulate_exception(ctxt, MF_VECTOR, 0, false); 5068 5069 return X86EMUL_CONTINUE; 5070 } 5071 5072 static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt, 5073 struct operand *op) 5074 { 5075 if (op->type == OP_MM) 5076 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm); 5077 } 5078 5079 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *)) 5080 { 5081 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF; 5082 if (!(ctxt->d & ByteOp)) 5083 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE; 5084 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n" 5085 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags), 5086 [fastop]"+S"(fop) 5087 : "c"(ctxt->src2.val)); 5088 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK); 5089 if (!fop) /* exception is returned in fop variable */ 5090 return emulate_de(ctxt); 5091 return X86EMUL_CONTINUE; 5092 } 5093 5094 void init_decode_cache(struct x86_emulate_ctxt *ctxt) 5095 { 5096 memset(&ctxt->rip_relative, 0, 5097 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative); 5098 5099 ctxt->io_read.pos = 0; 5100 ctxt->io_read.end = 0; 5101 ctxt->mem_read.end = 0; 5102 } 5103 5104 int x86_emulate_insn(struct x86_emulate_ctxt *ctxt) 5105 { 5106 const struct x86_emulate_ops *ops = ctxt->ops; 5107 int rc = X86EMUL_CONTINUE; 5108 int saved_dst_type = ctxt->dst.type; 5109 5110 ctxt->mem_read.pos = 0; 5111 5112 /* LOCK prefix is allowed only with some instructions */ 5113 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) { 5114 rc = emulate_ud(ctxt); 5115 goto done; 5116 } 5117 5118 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) { 5119 rc = emulate_ud(ctxt); 5120 goto done; 5121 } 5122 5123 if (unlikely(ctxt->d & 5124 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) { 5125 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) || 5126 (ctxt->d & Undefined)) { 5127 rc = emulate_ud(ctxt); 5128 goto done; 5129 } 5130 5131 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM))) 5132 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) { 5133 rc = emulate_ud(ctxt); 5134 goto done; 5135 } 5136 5137 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) { 5138 rc = emulate_nm(ctxt); 5139 goto done; 5140 } 5141 5142 if (ctxt->d & Mmx) { 5143 rc = flush_pending_x87_faults(ctxt); 5144 if (rc != X86EMUL_CONTINUE) 5145 goto done; 5146 /* 5147 * Now that we know the fpu is exception safe, we can fetch 5148 * operands from it. 5149 */ 5150 fetch_possible_mmx_operand(ctxt, &ctxt->src); 5151 fetch_possible_mmx_operand(ctxt, &ctxt->src2); 5152 if (!(ctxt->d & Mov)) 5153 fetch_possible_mmx_operand(ctxt, &ctxt->dst); 5154 } 5155 5156 if (unlikely(ctxt->emul_flags & X86EMUL_GUEST_MASK) && ctxt->intercept) { 5157 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5158 X86_ICPT_PRE_EXCEPT); 5159 if (rc != X86EMUL_CONTINUE) 5160 goto done; 5161 } 5162 5163 /* Instruction can only be executed in protected mode */ 5164 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) { 5165 rc = emulate_ud(ctxt); 5166 goto done; 5167 } 5168 5169 /* Privileged instruction can be executed only in CPL=0 */ 5170 if ((ctxt->d & Priv) && ops->cpl(ctxt)) { 5171 if (ctxt->d & PrivUD) 5172 rc = emulate_ud(ctxt); 5173 else 5174 rc = emulate_gp(ctxt, 0); 5175 goto done; 5176 } 5177 5178 /* Do instruction specific permission checks */ 5179 if (ctxt->d & CheckPerm) { 5180 rc = ctxt->check_perm(ctxt); 5181 if (rc != X86EMUL_CONTINUE) 5182 goto done; 5183 } 5184 5185 if (unlikely(ctxt->emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) { 5186 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5187 X86_ICPT_POST_EXCEPT); 5188 if (rc != X86EMUL_CONTINUE) 5189 goto done; 5190 } 5191 5192 if (ctxt->rep_prefix && (ctxt->d & String)) { 5193 /* All REP prefixes have the same first termination condition */ 5194 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) { 5195 string_registers_quirk(ctxt); 5196 ctxt->eip = ctxt->_eip; 5197 ctxt->eflags &= ~X86_EFLAGS_RF; 5198 goto done; 5199 } 5200 } 5201 } 5202 5203 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) { 5204 rc = segmented_read(ctxt, ctxt->src.addr.mem, 5205 ctxt->src.valptr, ctxt->src.bytes); 5206 if (rc != X86EMUL_CONTINUE) 5207 goto done; 5208 ctxt->src.orig_val64 = ctxt->src.val64; 5209 } 5210 5211 if (ctxt->src2.type == OP_MEM) { 5212 rc = segmented_read(ctxt, ctxt->src2.addr.mem, 5213 &ctxt->src2.val, ctxt->src2.bytes); 5214 if (rc != X86EMUL_CONTINUE) 5215 goto done; 5216 } 5217 5218 if ((ctxt->d & DstMask) == ImplicitOps) 5219 goto special_insn; 5220 5221 5222 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) { 5223 /* optimisation - avoid slow emulated read if Mov */ 5224 rc = segmented_read(ctxt, ctxt->dst.addr.mem, 5225 &ctxt->dst.val, ctxt->dst.bytes); 5226 if (rc != X86EMUL_CONTINUE) { 5227 if (!(ctxt->d & NoWrite) && 5228 rc == X86EMUL_PROPAGATE_FAULT && 5229 ctxt->exception.vector == PF_VECTOR) 5230 ctxt->exception.error_code |= PFERR_WRITE_MASK; 5231 goto done; 5232 } 5233 } 5234 /* Copy full 64-bit value for CMPXCHG8B. */ 5235 ctxt->dst.orig_val64 = ctxt->dst.val64; 5236 5237 special_insn: 5238 5239 if (unlikely(ctxt->emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) { 5240 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5241 X86_ICPT_POST_MEMACCESS); 5242 if (rc != X86EMUL_CONTINUE) 5243 goto done; 5244 } 5245 5246 if (ctxt->rep_prefix && (ctxt->d & String)) 5247 ctxt->eflags |= X86_EFLAGS_RF; 5248 else 5249 ctxt->eflags &= ~X86_EFLAGS_RF; 5250 5251 if (ctxt->execute) { 5252 if (ctxt->d & Fastop) { 5253 void (*fop)(struct fastop *) = (void *)ctxt->execute; 5254 rc = fastop(ctxt, fop); 5255 if (rc != X86EMUL_CONTINUE) 5256 goto done; 5257 goto writeback; 5258 } 5259 rc = ctxt->execute(ctxt); 5260 if (rc != X86EMUL_CONTINUE) 5261 goto done; 5262 goto writeback; 5263 } 5264 5265 if (ctxt->opcode_len == 2) 5266 goto twobyte_insn; 5267 else if (ctxt->opcode_len == 3) 5268 goto threebyte_insn; 5269 5270 switch (ctxt->b) { 5271 case 0x70 ... 0x7f: /* jcc (short) */ 5272 if (test_cc(ctxt->b, ctxt->eflags)) 5273 rc = jmp_rel(ctxt, ctxt->src.val); 5274 break; 5275 case 0x8d: /* lea r16/r32, m */ 5276 ctxt->dst.val = ctxt->src.addr.mem.ea; 5277 break; 5278 case 0x90 ... 0x97: /* nop / xchg reg, rax */ 5279 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX)) 5280 ctxt->dst.type = OP_NONE; 5281 else 5282 rc = em_xchg(ctxt); 5283 break; 5284 case 0x98: /* cbw/cwde/cdqe */ 5285 switch (ctxt->op_bytes) { 5286 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break; 5287 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break; 5288 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break; 5289 } 5290 break; 5291 case 0xcc: /* int3 */ 5292 rc = emulate_int(ctxt, 3); 5293 break; 5294 case 0xcd: /* int n */ 5295 rc = emulate_int(ctxt, ctxt->src.val); 5296 break; 5297 case 0xce: /* into */ 5298 if (ctxt->eflags & X86_EFLAGS_OF) 5299 rc = emulate_int(ctxt, 4); 5300 break; 5301 case 0xe9: /* jmp rel */ 5302 case 0xeb: /* jmp rel short */ 5303 rc = jmp_rel(ctxt, ctxt->src.val); 5304 ctxt->dst.type = OP_NONE; /* Disable writeback. */ 5305 break; 5306 case 0xf4: /* hlt */ 5307 ctxt->ops->halt(ctxt); 5308 break; 5309 case 0xf5: /* cmc */ 5310 /* complement carry flag from eflags reg */ 5311 ctxt->eflags ^= X86_EFLAGS_CF; 5312 break; 5313 case 0xf8: /* clc */ 5314 ctxt->eflags &= ~X86_EFLAGS_CF; 5315 break; 5316 case 0xf9: /* stc */ 5317 ctxt->eflags |= X86_EFLAGS_CF; 5318 break; 5319 case 0xfc: /* cld */ 5320 ctxt->eflags &= ~X86_EFLAGS_DF; 5321 break; 5322 case 0xfd: /* std */ 5323 ctxt->eflags |= X86_EFLAGS_DF; 5324 break; 5325 default: 5326 goto cannot_emulate; 5327 } 5328 5329 if (rc != X86EMUL_CONTINUE) 5330 goto done; 5331 5332 writeback: 5333 if (ctxt->d & SrcWrite) { 5334 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR); 5335 rc = writeback(ctxt, &ctxt->src); 5336 if (rc != X86EMUL_CONTINUE) 5337 goto done; 5338 } 5339 if (!(ctxt->d & NoWrite)) { 5340 rc = writeback(ctxt, &ctxt->dst); 5341 if (rc != X86EMUL_CONTINUE) 5342 goto done; 5343 } 5344 5345 /* 5346 * restore dst type in case the decoding will be reused 5347 * (happens for string instruction ) 5348 */ 5349 ctxt->dst.type = saved_dst_type; 5350 5351 if ((ctxt->d & SrcMask) == SrcSI) 5352 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src); 5353 5354 if ((ctxt->d & DstMask) == DstDI) 5355 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst); 5356 5357 if (ctxt->rep_prefix && (ctxt->d & String)) { 5358 unsigned int count; 5359 struct read_cache *r = &ctxt->io_read; 5360 if ((ctxt->d & SrcMask) == SrcSI) 5361 count = ctxt->src.count; 5362 else 5363 count = ctxt->dst.count; 5364 register_address_increment(ctxt, VCPU_REGS_RCX, -count); 5365 5366 if (!string_insn_completed(ctxt)) { 5367 /* 5368 * Re-enter guest when pio read ahead buffer is empty 5369 * or, if it is not used, after each 1024 iteration. 5370 */ 5371 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) && 5372 (r->end == 0 || r->end != r->pos)) { 5373 /* 5374 * Reset read cache. Usually happens before 5375 * decode, but since instruction is restarted 5376 * we have to do it here. 5377 */ 5378 ctxt->mem_read.end = 0; 5379 writeback_registers(ctxt); 5380 return EMULATION_RESTART; 5381 } 5382 goto done; /* skip rip writeback */ 5383 } 5384 ctxt->eflags &= ~X86_EFLAGS_RF; 5385 } 5386 5387 ctxt->eip = ctxt->_eip; 5388 5389 done: 5390 if (rc == X86EMUL_PROPAGATE_FAULT) { 5391 WARN_ON(ctxt->exception.vector > 0x1f); 5392 ctxt->have_exception = true; 5393 } 5394 if (rc == X86EMUL_INTERCEPTED) 5395 return EMULATION_INTERCEPTED; 5396 5397 if (rc == X86EMUL_CONTINUE) 5398 writeback_registers(ctxt); 5399 5400 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 5401 5402 twobyte_insn: 5403 switch (ctxt->b) { 5404 case 0x09: /* wbinvd */ 5405 (ctxt->ops->wbinvd)(ctxt); 5406 break; 5407 case 0x08: /* invd */ 5408 case 0x0d: /* GrpP (prefetch) */ 5409 case 0x18: /* Grp16 (prefetch/nop) */ 5410 case 0x1f: /* nop */ 5411 break; 5412 case 0x20: /* mov cr, reg */ 5413 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg); 5414 break; 5415 case 0x21: /* mov from dr to reg */ 5416 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val); 5417 break; 5418 case 0x40 ... 0x4f: /* cmov */ 5419 if (test_cc(ctxt->b, ctxt->eflags)) 5420 ctxt->dst.val = ctxt->src.val; 5421 else if (ctxt->op_bytes != 4) 5422 ctxt->dst.type = OP_NONE; /* no writeback */ 5423 break; 5424 case 0x80 ... 0x8f: /* jnz rel, etc*/ 5425 if (test_cc(ctxt->b, ctxt->eflags)) 5426 rc = jmp_rel(ctxt, ctxt->src.val); 5427 break; 5428 case 0x90 ... 0x9f: /* setcc r/m8 */ 5429 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags); 5430 break; 5431 case 0xb6 ... 0xb7: /* movzx */ 5432 ctxt->dst.bytes = ctxt->op_bytes; 5433 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val 5434 : (u16) ctxt->src.val; 5435 break; 5436 case 0xbe ... 0xbf: /* movsx */ 5437 ctxt->dst.bytes = ctxt->op_bytes; 5438 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val : 5439 (s16) ctxt->src.val; 5440 break; 5441 default: 5442 goto cannot_emulate; 5443 } 5444 5445 threebyte_insn: 5446 5447 if (rc != X86EMUL_CONTINUE) 5448 goto done; 5449 5450 goto writeback; 5451 5452 cannot_emulate: 5453 return EMULATION_FAILED; 5454 } 5455 5456 void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt) 5457 { 5458 invalidate_registers(ctxt); 5459 } 5460 5461 void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt) 5462 { 5463 writeback_registers(ctxt); 5464 } 5465