1 // SPDX-License-Identifier: GPL-2.0-only 2 /****************************************************************************** 3 * emulate.c 4 * 5 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. 6 * 7 * Copyright (c) 2005 Keir Fraser 8 * 9 * Linux coding style, mod r/m decoder, segment base fixes, real-mode 10 * privileged instructions: 11 * 12 * Copyright (C) 2006 Qumranet 13 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 14 * 15 * Avi Kivity <avi@qumranet.com> 16 * Yaniv Kamay <yaniv@qumranet.com> 17 * 18 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 19 */ 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/kvm_host.h> 23 #include "kvm_cache_regs.h" 24 #include "kvm_emulate.h" 25 #include <linux/stringify.h> 26 #include <asm/debugreg.h> 27 #include <asm/nospec-branch.h> 28 #include <asm/ibt.h> 29 #include <asm/text-patching.h> 30 31 #include "x86.h" 32 #include "tss.h" 33 #include "mmu.h" 34 #include "pmu.h" 35 36 /* 37 * Operand types 38 */ 39 #define OpNone 0ull 40 #define OpImplicit 1ull /* No generic decode */ 41 #define OpReg 2ull /* Register */ 42 #define OpMem 3ull /* Memory */ 43 #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */ 44 #define OpDI 5ull /* ES:DI/EDI/RDI */ 45 #define OpMem64 6ull /* Memory, 64-bit */ 46 #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */ 47 #define OpDX 8ull /* DX register */ 48 #define OpCL 9ull /* CL register (for shifts) */ 49 #define OpImmByte 10ull /* 8-bit sign extended immediate */ 50 #define OpOne 11ull /* Implied 1 */ 51 #define OpImm 12ull /* Sign extended up to 32-bit immediate */ 52 #define OpMem16 13ull /* Memory operand (16-bit). */ 53 #define OpMem32 14ull /* Memory operand (32-bit). */ 54 #define OpImmU 15ull /* Immediate operand, zero extended */ 55 #define OpSI 16ull /* SI/ESI/RSI */ 56 #define OpImmFAddr 17ull /* Immediate far address */ 57 #define OpMemFAddr 18ull /* Far address in memory */ 58 #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */ 59 #define OpES 20ull /* ES */ 60 #define OpCS 21ull /* CS */ 61 #define OpSS 22ull /* SS */ 62 #define OpDS 23ull /* DS */ 63 #define OpFS 24ull /* FS */ 64 #define OpGS 25ull /* GS */ 65 #define OpMem8 26ull /* 8-bit zero extended memory operand */ 66 #define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */ 67 #define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */ 68 #define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */ 69 #define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */ 70 71 #define OpBits 5 /* Width of operand field */ 72 #define OpMask ((1ull << OpBits) - 1) 73 74 /* 75 * Opcode effective-address decode tables. 76 * Note that we only emulate instructions that have at least one memory 77 * operand (excluding implicit stack references). We assume that stack 78 * references and instruction fetches will never occur in special memory 79 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need 80 * not be handled. 81 */ 82 83 /* Operand sizes: 8-bit operands or specified/overridden size. */ 84 #define ByteOp (1<<0) /* 8-bit operands. */ 85 /* Destination operand type. */ 86 #define DstShift 1 87 #define ImplicitOps (OpImplicit << DstShift) 88 #define DstReg (OpReg << DstShift) 89 #define DstMem (OpMem << DstShift) 90 #define DstAcc (OpAcc << DstShift) 91 #define DstDI (OpDI << DstShift) 92 #define DstMem64 (OpMem64 << DstShift) 93 #define DstMem16 (OpMem16 << DstShift) 94 #define DstImmUByte (OpImmUByte << DstShift) 95 #define DstDX (OpDX << DstShift) 96 #define DstAccLo (OpAccLo << DstShift) 97 #define DstMask (OpMask << DstShift) 98 /* Source operand type. */ 99 #define SrcShift 6 100 #define SrcNone (OpNone << SrcShift) 101 #define SrcReg (OpReg << SrcShift) 102 #define SrcMem (OpMem << SrcShift) 103 #define SrcMem16 (OpMem16 << SrcShift) 104 #define SrcMem32 (OpMem32 << SrcShift) 105 #define SrcImm (OpImm << SrcShift) 106 #define SrcImmByte (OpImmByte << SrcShift) 107 #define SrcOne (OpOne << SrcShift) 108 #define SrcImmUByte (OpImmUByte << SrcShift) 109 #define SrcImmU (OpImmU << SrcShift) 110 #define SrcSI (OpSI << SrcShift) 111 #define SrcXLat (OpXLat << SrcShift) 112 #define SrcImmFAddr (OpImmFAddr << SrcShift) 113 #define SrcMemFAddr (OpMemFAddr << SrcShift) 114 #define SrcAcc (OpAcc << SrcShift) 115 #define SrcImmU16 (OpImmU16 << SrcShift) 116 #define SrcImm64 (OpImm64 << SrcShift) 117 #define SrcDX (OpDX << SrcShift) 118 #define SrcMem8 (OpMem8 << SrcShift) 119 #define SrcAccHi (OpAccHi << SrcShift) 120 #define SrcMask (OpMask << SrcShift) 121 #define BitOp (1<<11) 122 #define MemAbs (1<<12) /* Memory operand is absolute displacement */ 123 #define String (1<<13) /* String instruction (rep capable) */ 124 #define Stack (1<<14) /* Stack instruction (push/pop) */ 125 #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */ 126 #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */ 127 #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */ 128 #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */ 129 #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */ 130 #define Escape (5<<15) /* Escape to coprocessor instruction */ 131 #define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */ 132 #define ModeDual (7<<15) /* Different instruction for 32/64 bit */ 133 #define Sse (1<<18) /* SSE Vector instruction */ 134 /* Generic ModRM decode. */ 135 #define ModRM (1<<19) 136 /* Destination is only written; never read. */ 137 #define Mov (1<<20) 138 /* Misc flags */ 139 #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */ 140 #define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */ 141 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ 142 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ 143 #define Undefined (1<<25) /* No Such Instruction */ 144 #define Lock (1<<26) /* lock prefix is allowed for the instruction */ 145 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ 146 #define No64 (1<<28) 147 #define PageTable (1 << 29) /* instruction used to write page table */ 148 #define NotImpl (1 << 30) /* instruction is not implemented */ 149 /* Source 2 operand type */ 150 #define Src2Shift (31) 151 #define Src2None (OpNone << Src2Shift) 152 #define Src2Mem (OpMem << Src2Shift) 153 #define Src2CL (OpCL << Src2Shift) 154 #define Src2ImmByte (OpImmByte << Src2Shift) 155 #define Src2One (OpOne << Src2Shift) 156 #define Src2Imm (OpImm << Src2Shift) 157 #define Src2ES (OpES << Src2Shift) 158 #define Src2CS (OpCS << Src2Shift) 159 #define Src2SS (OpSS << Src2Shift) 160 #define Src2DS (OpDS << Src2Shift) 161 #define Src2FS (OpFS << Src2Shift) 162 #define Src2GS (OpGS << Src2Shift) 163 #define Src2Mask (OpMask << Src2Shift) 164 #define Mmx ((u64)1 << 40) /* MMX Vector instruction */ 165 #define AlignMask ((u64)7 << 41) 166 #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */ 167 #define Unaligned ((u64)2 << 41) /* Explicitly unaligned (e.g. MOVDQU) */ 168 #define Avx ((u64)3 << 41) /* Advanced Vector Extensions */ 169 #define Aligned16 ((u64)4 << 41) /* Aligned to 16 byte boundary (e.g. FXSAVE) */ 170 #define NoWrite ((u64)1 << 45) /* No writeback */ 171 #define SrcWrite ((u64)1 << 46) /* Write back src operand */ 172 #define NoMod ((u64)1 << 47) /* Mod field is ignored */ 173 #define Intercept ((u64)1 << 48) /* Has valid intercept field */ 174 #define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */ 175 #define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */ 176 #define NearBranch ((u64)1 << 52) /* Near branches */ 177 #define No16 ((u64)1 << 53) /* No 16 bit operand */ 178 #define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */ 179 #define TwoMemOp ((u64)1 << 55) /* Instruction has two memory operand */ 180 #define IsBranch ((u64)1 << 56) /* Instruction is considered a branch. */ 181 #define ShadowStack ((u64)1 << 57) /* Instruction affects Shadow Stacks. */ 182 183 #define DstXacc (DstAccLo | SrcAccHi | SrcWrite) 184 185 #define X2(x...) x, x 186 #define X3(x...) X2(x), x 187 #define X4(x...) X2(x), X2(x) 188 #define X5(x...) X4(x), x 189 #define X6(x...) X4(x), X2(x) 190 #define X7(x...) X4(x), X3(x) 191 #define X8(x...) X4(x), X4(x) 192 #define X16(x...) X8(x), X8(x) 193 194 struct opcode { 195 u64 flags; 196 u8 intercept; 197 u8 pad[7]; 198 union { 199 int (*execute)(struct x86_emulate_ctxt *ctxt); 200 const struct opcode *group; 201 const struct group_dual *gdual; 202 const struct gprefix *gprefix; 203 const struct escape *esc; 204 const struct instr_dual *idual; 205 const struct mode_dual *mdual; 206 } u; 207 int (*check_perm)(struct x86_emulate_ctxt *ctxt); 208 }; 209 210 struct group_dual { 211 struct opcode mod012[8]; 212 struct opcode mod3[8]; 213 }; 214 215 struct gprefix { 216 struct opcode pfx_no; 217 struct opcode pfx_66; 218 struct opcode pfx_f2; 219 struct opcode pfx_f3; 220 }; 221 222 struct escape { 223 struct opcode op[8]; 224 struct opcode high[64]; 225 }; 226 227 struct instr_dual { 228 struct opcode mod012; 229 struct opcode mod3; 230 }; 231 232 struct mode_dual { 233 struct opcode mode32; 234 struct opcode mode64; 235 }; 236 237 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a 238 239 enum x86_transfer_type { 240 X86_TRANSFER_NONE, 241 X86_TRANSFER_CALL_JMP, 242 X86_TRANSFER_RET, 243 X86_TRANSFER_TASK_SWITCH, 244 }; 245 246 static void writeback_registers(struct x86_emulate_ctxt *ctxt) 247 { 248 unsigned long dirty = ctxt->regs_dirty; 249 unsigned reg; 250 251 for_each_set_bit(reg, &dirty, NR_EMULATOR_GPRS) 252 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]); 253 } 254 255 static void invalidate_registers(struct x86_emulate_ctxt *ctxt) 256 { 257 ctxt->regs_dirty = 0; 258 ctxt->regs_valid = 0; 259 } 260 261 /* 262 * These EFLAGS bits are restored from saved value during emulation, and 263 * any changes are written back to the saved value after emulation. 264 */ 265 #define EFLAGS_MASK (X86_EFLAGS_OF|X86_EFLAGS_SF|X86_EFLAGS_ZF|X86_EFLAGS_AF|\ 266 X86_EFLAGS_PF|X86_EFLAGS_CF) 267 268 #ifdef CONFIG_X86_64 269 #define ON64(x...) x 270 #else 271 #define ON64(x...) 272 #endif 273 274 #define EM_ASM_START(op) \ 275 static int em_##op(struct x86_emulate_ctxt *ctxt) \ 276 { \ 277 unsigned long flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF; \ 278 int bytes = 1, ok = 1; \ 279 if (!(ctxt->d & ByteOp)) \ 280 bytes = ctxt->dst.bytes; \ 281 switch (bytes) { 282 283 #define __EM_ASM(str) \ 284 asm("push %[flags]; popf \n\t" \ 285 "10: " str \ 286 "pushf; pop %[flags] \n\t" \ 287 "11: \n\t" \ 288 : "+a" (ctxt->dst.val), \ 289 "+d" (ctxt->src.val), \ 290 [flags] "+D" (flags), \ 291 "+S" (ok) \ 292 : "c" (ctxt->src2.val)) 293 294 #define __EM_ASM_1(op, dst) \ 295 __EM_ASM(#op " %%" #dst " \n\t") 296 297 #define __EM_ASM_1_EX(op, dst) \ 298 __EM_ASM(#op " %%" #dst " \n\t" \ 299 _ASM_EXTABLE_TYPE_REG(10b, 11f, EX_TYPE_ZERO_REG, %%esi)) 300 301 #define __EM_ASM_2(op, dst, src) \ 302 __EM_ASM(#op " %%" #src ", %%" #dst " \n\t") 303 304 #define __EM_ASM_3(op, dst, src, src2) \ 305 __EM_ASM(#op " %%" #src2 ", %%" #src ", %%" #dst " \n\t") 306 307 #define EM_ASM_END \ 308 } \ 309 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK); \ 310 return !ok ? emulate_de(ctxt) : X86EMUL_CONTINUE; \ 311 } 312 313 /* 1-operand, using "a" (dst) */ 314 #define EM_ASM_1(op) \ 315 EM_ASM_START(op) \ 316 case 1: __EM_ASM_1(op##b, al); break; \ 317 case 2: __EM_ASM_1(op##w, ax); break; \ 318 case 4: __EM_ASM_1(op##l, eax); break; \ 319 ON64(case 8: __EM_ASM_1(op##q, rax); break;) \ 320 EM_ASM_END 321 322 /* 1-operand, using "c" (src2) */ 323 #define EM_ASM_1SRC2(op, name) \ 324 EM_ASM_START(name) \ 325 case 1: __EM_ASM_1(op##b, cl); break; \ 326 case 2: __EM_ASM_1(op##w, cx); break; \ 327 case 4: __EM_ASM_1(op##l, ecx); break; \ 328 ON64(case 8: __EM_ASM_1(op##q, rcx); break;) \ 329 EM_ASM_END 330 331 /* 1-operand, using "c" (src2) with exception */ 332 #define EM_ASM_1SRC2EX(op, name) \ 333 EM_ASM_START(name) \ 334 case 1: __EM_ASM_1_EX(op##b, cl); break; \ 335 case 2: __EM_ASM_1_EX(op##w, cx); break; \ 336 case 4: __EM_ASM_1_EX(op##l, ecx); break; \ 337 ON64(case 8: __EM_ASM_1_EX(op##q, rcx); break;) \ 338 EM_ASM_END 339 340 /* 2-operand, using "a" (dst), "d" (src) */ 341 #define EM_ASM_2(op) \ 342 EM_ASM_START(op) \ 343 case 1: __EM_ASM_2(op##b, al, dl); break; \ 344 case 2: __EM_ASM_2(op##w, ax, dx); break; \ 345 case 4: __EM_ASM_2(op##l, eax, edx); break; \ 346 ON64(case 8: __EM_ASM_2(op##q, rax, rdx); break;) \ 347 EM_ASM_END 348 349 /* 2-operand, reversed */ 350 #define EM_ASM_2R(op, name) \ 351 EM_ASM_START(name) \ 352 case 1: __EM_ASM_2(op##b, dl, al); break; \ 353 case 2: __EM_ASM_2(op##w, dx, ax); break; \ 354 case 4: __EM_ASM_2(op##l, edx, eax); break; \ 355 ON64(case 8: __EM_ASM_2(op##q, rdx, rax); break;) \ 356 EM_ASM_END 357 358 /* 2-operand, word only (no byte op) */ 359 #define EM_ASM_2W(op) \ 360 EM_ASM_START(op) \ 361 case 1: break; \ 362 case 2: __EM_ASM_2(op##w, ax, dx); break; \ 363 case 4: __EM_ASM_2(op##l, eax, edx); break; \ 364 ON64(case 8: __EM_ASM_2(op##q, rax, rdx); break;) \ 365 EM_ASM_END 366 367 /* 2-operand, using "a" (dst) and CL (src2) */ 368 #define EM_ASM_2CL(op) \ 369 EM_ASM_START(op) \ 370 case 1: __EM_ASM_2(op##b, al, cl); break; \ 371 case 2: __EM_ASM_2(op##w, ax, cl); break; \ 372 case 4: __EM_ASM_2(op##l, eax, cl); break; \ 373 ON64(case 8: __EM_ASM_2(op##q, rax, cl); break;) \ 374 EM_ASM_END 375 376 /* 3-operand, using "a" (dst), "d" (src) and CL (src2) */ 377 #define EM_ASM_3WCL(op) \ 378 EM_ASM_START(op) \ 379 case 1: break; \ 380 case 2: __EM_ASM_3(op##w, ax, dx, cl); break; \ 381 case 4: __EM_ASM_3(op##l, eax, edx, cl); break; \ 382 ON64(case 8: __EM_ASM_3(op##q, rax, rdx, cl); break;) \ 383 EM_ASM_END 384 385 static int em_salc(struct x86_emulate_ctxt *ctxt) 386 { 387 /* 388 * Set AL 0xFF if CF is set, or 0x00 when clear. 389 */ 390 ctxt->dst.val = 0xFF * !!(ctxt->eflags & X86_EFLAGS_CF); 391 return X86EMUL_CONTINUE; 392 } 393 394 /* 395 * XXX: inoutclob user must know where the argument is being expanded. 396 * Using asm goto would allow us to remove _fault. 397 */ 398 #define asm_safe(insn, inoutclob...) \ 399 ({ \ 400 int _fault = 0; \ 401 \ 402 asm volatile("1:" insn "\n" \ 403 "2:\n" \ 404 _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_ONE_REG, %[_fault]) \ 405 : [_fault] "+r"(_fault) inoutclob ); \ 406 \ 407 _fault ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; \ 408 }) 409 410 static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt, 411 enum x86_intercept intercept, 412 enum x86_intercept_stage stage) 413 { 414 struct x86_instruction_info info = { 415 .intercept = intercept, 416 .rep_prefix = ctxt->rep_prefix, 417 .modrm_mod = ctxt->modrm_mod, 418 .modrm_reg = ctxt->modrm_reg, 419 .modrm_rm = ctxt->modrm_rm, 420 .src_val = ctxt->src.val64, 421 .dst_val = ctxt->dst.val64, 422 .src_bytes = ctxt->src.bytes, 423 .dst_bytes = ctxt->dst.bytes, 424 .src_type = ctxt->src.type, 425 .dst_type = ctxt->dst.type, 426 .ad_bytes = ctxt->ad_bytes, 427 .rip = ctxt->eip, 428 .next_rip = ctxt->_eip, 429 }; 430 431 return ctxt->ops->intercept(ctxt, &info, stage); 432 } 433 434 static void assign_masked(ulong *dest, ulong src, ulong mask) 435 { 436 *dest = (*dest & ~mask) | (src & mask); 437 } 438 439 static void assign_register(unsigned long *reg, u64 val, int bytes) 440 { 441 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ 442 switch (bytes) { 443 case 1: 444 *(u8 *)reg = (u8)val; 445 break; 446 case 2: 447 *(u16 *)reg = (u16)val; 448 break; 449 case 4: 450 *reg = (u32)val; 451 break; /* 64b: zero-extend */ 452 case 8: 453 *reg = val; 454 break; 455 } 456 } 457 458 static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt) 459 { 460 return (1UL << (ctxt->ad_bytes << 3)) - 1; 461 } 462 463 static ulong stack_mask(struct x86_emulate_ctxt *ctxt) 464 { 465 u16 sel; 466 struct desc_struct ss; 467 468 if (ctxt->mode == X86EMUL_MODE_PROT64) 469 return ~0UL; 470 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS); 471 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */ 472 } 473 474 static int stack_size(struct x86_emulate_ctxt *ctxt) 475 { 476 return (__fls(stack_mask(ctxt)) + 1) >> 3; 477 } 478 479 /* Access/update address held in a register, based on addressing mode. */ 480 static inline unsigned long 481 address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg) 482 { 483 if (ctxt->ad_bytes == sizeof(unsigned long)) 484 return reg; 485 else 486 return reg & ad_mask(ctxt); 487 } 488 489 static inline unsigned long 490 register_address(struct x86_emulate_ctxt *ctxt, int reg) 491 { 492 return address_mask(ctxt, reg_read(ctxt, reg)); 493 } 494 495 static void masked_increment(ulong *reg, ulong mask, int inc) 496 { 497 assign_masked(reg, *reg + inc, mask); 498 } 499 500 static inline void 501 register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc) 502 { 503 ulong *preg = reg_rmw(ctxt, reg); 504 505 assign_register(preg, *preg + inc, ctxt->ad_bytes); 506 } 507 508 static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc) 509 { 510 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc); 511 } 512 513 static u32 desc_limit_scaled(struct desc_struct *desc) 514 { 515 u32 limit = get_desc_limit(desc); 516 517 return desc->g ? (limit << 12) | 0xfff : limit; 518 } 519 520 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) 521 { 522 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) 523 return 0; 524 525 return ctxt->ops->get_cached_segment_base(ctxt, seg); 526 } 527 528 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, 529 u32 error, bool valid) 530 { 531 if (KVM_EMULATOR_BUG_ON(vec > 0x1f, ctxt)) 532 return X86EMUL_UNHANDLEABLE; 533 534 ctxt->exception.vector = vec; 535 ctxt->exception.error_code = error; 536 ctxt->exception.error_code_valid = valid; 537 return X86EMUL_PROPAGATE_FAULT; 538 } 539 540 static int emulate_db(struct x86_emulate_ctxt *ctxt) 541 { 542 return emulate_exception(ctxt, DB_VECTOR, 0, false); 543 } 544 545 static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err) 546 { 547 return emulate_exception(ctxt, GP_VECTOR, err, true); 548 } 549 550 static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err) 551 { 552 return emulate_exception(ctxt, SS_VECTOR, err, true); 553 } 554 555 static int emulate_ud(struct x86_emulate_ctxt *ctxt) 556 { 557 return emulate_exception(ctxt, UD_VECTOR, 0, false); 558 } 559 560 static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err) 561 { 562 return emulate_exception(ctxt, TS_VECTOR, err, true); 563 } 564 565 static int emulate_de(struct x86_emulate_ctxt *ctxt) 566 { 567 return emulate_exception(ctxt, DE_VECTOR, 0, false); 568 } 569 570 static int emulate_nm(struct x86_emulate_ctxt *ctxt) 571 { 572 return emulate_exception(ctxt, NM_VECTOR, 0, false); 573 } 574 575 static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg) 576 { 577 u16 selector; 578 struct desc_struct desc; 579 580 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg); 581 return selector; 582 } 583 584 static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector, 585 unsigned seg) 586 { 587 u16 dummy; 588 u32 base3; 589 struct desc_struct desc; 590 591 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg); 592 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg); 593 } 594 595 static inline u8 ctxt_virt_addr_bits(struct x86_emulate_ctxt *ctxt) 596 { 597 return (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_LA57) ? 57 : 48; 598 } 599 600 static inline bool emul_is_noncanonical_address(u64 la, 601 struct x86_emulate_ctxt *ctxt, 602 unsigned int flags) 603 { 604 return !ctxt->ops->is_canonical_addr(ctxt, la, flags); 605 } 606 607 /* 608 * x86 defines three classes of vector instructions: explicitly 609 * aligned, explicitly unaligned, and the rest, which change behaviour 610 * depending on whether they're AVX encoded or not. 611 * 612 * Also included is CMPXCHG16B which is not a vector instruction, yet it is 613 * subject to the same check. FXSAVE and FXRSTOR are checked here too as their 614 * 512 bytes of data must be aligned to a 16 byte boundary. 615 */ 616 static unsigned insn_alignment(struct x86_emulate_ctxt *ctxt, unsigned size) 617 { 618 u64 alignment = ctxt->d & AlignMask; 619 620 if (likely(size < 16)) 621 return 1; 622 623 switch (alignment) { 624 case Unaligned: 625 case Avx: 626 return 1; 627 case Aligned16: 628 return 16; 629 case Aligned: 630 default: 631 return size; 632 } 633 } 634 635 static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt, 636 struct segmented_address addr, 637 unsigned *max_size, unsigned size, 638 enum x86emul_mode mode, ulong *linear, 639 unsigned int flags) 640 { 641 struct desc_struct desc; 642 bool usable; 643 ulong la; 644 u32 lim; 645 u16 sel; 646 u8 va_bits; 647 648 la = seg_base(ctxt, addr.seg) + addr.ea; 649 *max_size = 0; 650 switch (mode) { 651 case X86EMUL_MODE_PROT64: 652 *linear = la = ctxt->ops->get_untagged_addr(ctxt, la, flags); 653 va_bits = ctxt_virt_addr_bits(ctxt); 654 if (!__is_canonical_address(la, va_bits)) 655 goto bad; 656 657 *max_size = min_t(u64, ~0u, (1ull << va_bits) - la); 658 if (size > *max_size) 659 goto bad; 660 break; 661 default: 662 *linear = la = (u32)la; 663 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL, 664 addr.seg); 665 if (!usable) 666 goto bad; 667 /* code segment in protected mode or read-only data segment */ 668 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8)) || !(desc.type & 2)) && 669 (flags & X86EMUL_F_WRITE)) 670 goto bad; 671 /* unreadable code segment */ 672 if (!(flags & X86EMUL_F_FETCH) && (desc.type & 8) && !(desc.type & 2)) 673 goto bad; 674 lim = desc_limit_scaled(&desc); 675 if (!(desc.type & 8) && (desc.type & 4)) { 676 /* expand-down segment */ 677 if (addr.ea <= lim) 678 goto bad; 679 lim = desc.d ? 0xffffffff : 0xffff; 680 } 681 if (addr.ea > lim) 682 goto bad; 683 if (lim == 0xffffffff) 684 *max_size = ~0u; 685 else { 686 *max_size = (u64)lim + 1 - addr.ea; 687 if (size > *max_size) 688 goto bad; 689 } 690 break; 691 } 692 if (la & (insn_alignment(ctxt, size) - 1)) 693 return emulate_gp(ctxt, 0); 694 return X86EMUL_CONTINUE; 695 bad: 696 if (addr.seg == VCPU_SREG_SS) 697 return emulate_ss(ctxt, 0); 698 else 699 return emulate_gp(ctxt, 0); 700 } 701 702 static int linearize(struct x86_emulate_ctxt *ctxt, 703 struct segmented_address addr, 704 unsigned size, bool write, 705 ulong *linear) 706 { 707 unsigned max_size; 708 return __linearize(ctxt, addr, &max_size, size, ctxt->mode, linear, 709 write ? X86EMUL_F_WRITE : 0); 710 } 711 712 static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst) 713 { 714 ulong linear; 715 int rc; 716 unsigned max_size; 717 struct segmented_address addr = { .seg = VCPU_SREG_CS, 718 .ea = dst }; 719 720 if (ctxt->op_bytes != sizeof(unsigned long)) 721 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1); 722 rc = __linearize(ctxt, addr, &max_size, 1, ctxt->mode, &linear, 723 X86EMUL_F_FETCH); 724 if (rc == X86EMUL_CONTINUE) 725 ctxt->_eip = addr.ea; 726 return rc; 727 } 728 729 static inline int emulator_recalc_and_set_mode(struct x86_emulate_ctxt *ctxt) 730 { 731 u64 efer; 732 struct desc_struct cs; 733 u16 selector; 734 u32 base3; 735 736 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 737 738 if (!(ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PE)) { 739 /* Real mode. cpu must not have long mode active */ 740 if (efer & EFER_LMA) 741 return X86EMUL_UNHANDLEABLE; 742 ctxt->mode = X86EMUL_MODE_REAL; 743 return X86EMUL_CONTINUE; 744 } 745 746 if (ctxt->eflags & X86_EFLAGS_VM) { 747 /* Protected/VM86 mode. cpu must not have long mode active */ 748 if (efer & EFER_LMA) 749 return X86EMUL_UNHANDLEABLE; 750 ctxt->mode = X86EMUL_MODE_VM86; 751 return X86EMUL_CONTINUE; 752 } 753 754 if (!ctxt->ops->get_segment(ctxt, &selector, &cs, &base3, VCPU_SREG_CS)) 755 return X86EMUL_UNHANDLEABLE; 756 757 if (efer & EFER_LMA) { 758 if (cs.l) { 759 /* Proper long mode */ 760 ctxt->mode = X86EMUL_MODE_PROT64; 761 } else if (cs.d) { 762 /* 32 bit compatibility mode*/ 763 ctxt->mode = X86EMUL_MODE_PROT32; 764 } else { 765 ctxt->mode = X86EMUL_MODE_PROT16; 766 } 767 } else { 768 /* Legacy 32 bit / 16 bit mode */ 769 ctxt->mode = cs.d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; 770 } 771 772 return X86EMUL_CONTINUE; 773 } 774 775 static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst) 776 { 777 return assign_eip(ctxt, dst); 778 } 779 780 static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst) 781 { 782 int rc = emulator_recalc_and_set_mode(ctxt); 783 784 if (rc != X86EMUL_CONTINUE) 785 return rc; 786 787 return assign_eip(ctxt, dst); 788 } 789 790 static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel) 791 { 792 return assign_eip_near(ctxt, ctxt->_eip + rel); 793 } 794 795 static int linear_read_system(struct x86_emulate_ctxt *ctxt, ulong linear, 796 void *data, unsigned size) 797 { 798 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception, true); 799 } 800 801 static int linear_write_system(struct x86_emulate_ctxt *ctxt, 802 ulong linear, void *data, 803 unsigned int size) 804 { 805 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception, true); 806 } 807 808 static int segmented_read_std(struct x86_emulate_ctxt *ctxt, 809 struct segmented_address addr, 810 void *data, 811 unsigned size) 812 { 813 int rc; 814 ulong linear; 815 816 rc = linearize(ctxt, addr, size, false, &linear); 817 if (rc != X86EMUL_CONTINUE) 818 return rc; 819 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception, false); 820 } 821 822 static int segmented_write_std(struct x86_emulate_ctxt *ctxt, 823 struct segmented_address addr, 824 void *data, 825 unsigned int size) 826 { 827 int rc; 828 ulong linear; 829 830 rc = linearize(ctxt, addr, size, true, &linear); 831 if (rc != X86EMUL_CONTINUE) 832 return rc; 833 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception, false); 834 } 835 836 /* 837 * Prefetch the remaining bytes of the instruction without crossing page 838 * boundary if they are not in fetch_cache yet. 839 */ 840 static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size) 841 { 842 int rc; 843 unsigned size, max_size; 844 unsigned long linear; 845 int cur_size = ctxt->fetch.end - ctxt->fetch.data; 846 struct segmented_address addr = { .seg = VCPU_SREG_CS, 847 .ea = ctxt->eip + cur_size }; 848 849 /* 850 * We do not know exactly how many bytes will be needed, and 851 * __linearize is expensive, so fetch as much as possible. We 852 * just have to avoid going beyond the 15 byte limit, the end 853 * of the segment, or the end of the page. 854 * 855 * __linearize is called with size 0 so that it does not do any 856 * boundary check itself. Instead, we use max_size to check 857 * against op_size. 858 */ 859 rc = __linearize(ctxt, addr, &max_size, 0, ctxt->mode, &linear, 860 X86EMUL_F_FETCH); 861 if (unlikely(rc != X86EMUL_CONTINUE)) 862 return rc; 863 864 size = min_t(unsigned, 15UL ^ cur_size, max_size); 865 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear)); 866 867 /* 868 * One instruction can only straddle two pages, 869 * and one has been loaded at the beginning of 870 * x86_decode_insn. So, if not enough bytes 871 * still, we must have hit the 15-byte boundary. 872 */ 873 if (unlikely(size < op_size)) 874 return emulate_gp(ctxt, 0); 875 876 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end, 877 size, &ctxt->exception); 878 if (unlikely(rc != X86EMUL_CONTINUE)) 879 return rc; 880 ctxt->fetch.end += size; 881 return X86EMUL_CONTINUE; 882 } 883 884 static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, 885 unsigned size) 886 { 887 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr; 888 889 if (unlikely(done_size < size)) 890 return __do_insn_fetch_bytes(ctxt, size - done_size); 891 else 892 return X86EMUL_CONTINUE; 893 } 894 895 /* Fetch next part of the instruction being emulated. */ 896 #define insn_fetch(_type, _ctxt) \ 897 ({ _type _x; \ 898 \ 899 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \ 900 if (rc != X86EMUL_CONTINUE) \ 901 goto done; \ 902 ctxt->_eip += sizeof(_type); \ 903 memcpy(&_x, ctxt->fetch.ptr, sizeof(_type)); \ 904 ctxt->fetch.ptr += sizeof(_type); \ 905 _x; \ 906 }) 907 908 #define insn_fetch_arr(_arr, _size, _ctxt) \ 909 ({ \ 910 rc = do_insn_fetch_bytes(_ctxt, _size); \ 911 if (rc != X86EMUL_CONTINUE) \ 912 goto done; \ 913 ctxt->_eip += (_size); \ 914 memcpy(_arr, ctxt->fetch.ptr, _size); \ 915 ctxt->fetch.ptr += (_size); \ 916 }) 917 918 /* 919 * Given the 'reg' portion of a ModRM byte, and a register block, return a 920 * pointer into the block that addresses the relevant register. 921 * @highbyte_regs specifies whether to decode AH,CH,DH,BH. 922 */ 923 static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg, 924 int byteop) 925 { 926 void *p; 927 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop; 928 929 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) 930 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1; 931 else 932 p = reg_rmw(ctxt, modrm_reg); 933 return p; 934 } 935 936 static int read_descriptor(struct x86_emulate_ctxt *ctxt, 937 struct segmented_address addr, 938 u16 *size, unsigned long *address, int op_bytes) 939 { 940 int rc; 941 942 if (op_bytes == 2) 943 op_bytes = 3; 944 *address = 0; 945 rc = segmented_read_std(ctxt, addr, size, 2); 946 if (rc != X86EMUL_CONTINUE) 947 return rc; 948 addr.ea += 2; 949 rc = segmented_read_std(ctxt, addr, address, op_bytes); 950 return rc; 951 } 952 953 EM_ASM_2(add); 954 EM_ASM_2(or); 955 EM_ASM_2(adc); 956 EM_ASM_2(sbb); 957 EM_ASM_2(and); 958 EM_ASM_2(sub); 959 EM_ASM_2(xor); 960 EM_ASM_2(cmp); 961 EM_ASM_2(test); 962 EM_ASM_2(xadd); 963 964 EM_ASM_1SRC2(mul, mul_ex); 965 EM_ASM_1SRC2(imul, imul_ex); 966 EM_ASM_1SRC2EX(div, div_ex); 967 EM_ASM_1SRC2EX(idiv, idiv_ex); 968 969 EM_ASM_3WCL(shld); 970 EM_ASM_3WCL(shrd); 971 972 EM_ASM_2W(imul); 973 974 EM_ASM_1(not); 975 EM_ASM_1(neg); 976 EM_ASM_1(inc); 977 EM_ASM_1(dec); 978 979 EM_ASM_2CL(rol); 980 EM_ASM_2CL(ror); 981 EM_ASM_2CL(rcl); 982 EM_ASM_2CL(rcr); 983 EM_ASM_2CL(shl); 984 EM_ASM_2CL(shr); 985 EM_ASM_2CL(sar); 986 987 EM_ASM_2W(bsf); 988 EM_ASM_2W(bsr); 989 EM_ASM_2W(bt); 990 EM_ASM_2W(bts); 991 EM_ASM_2W(btr); 992 EM_ASM_2W(btc); 993 994 EM_ASM_2R(cmp, cmp_r); 995 996 static int em_bsf_c(struct x86_emulate_ctxt *ctxt) 997 { 998 /* If src is zero, do not writeback, but update flags */ 999 if (ctxt->src.val == 0) 1000 ctxt->dst.type = OP_NONE; 1001 return em_bsf(ctxt); 1002 } 1003 1004 static int em_bsr_c(struct x86_emulate_ctxt *ctxt) 1005 { 1006 /* If src is zero, do not writeback, but update flags */ 1007 if (ctxt->src.val == 0) 1008 ctxt->dst.type = OP_NONE; 1009 return em_bsr(ctxt); 1010 } 1011 1012 static __always_inline u8 test_cc(unsigned int condition, unsigned long flags) 1013 { 1014 return __emulate_cc(flags, condition & 0xf); 1015 } 1016 1017 static void fetch_register_operand(struct operand *op) 1018 { 1019 switch (op->bytes) { 1020 case 1: 1021 op->val = *(u8 *)op->addr.reg; 1022 break; 1023 case 2: 1024 op->val = *(u16 *)op->addr.reg; 1025 break; 1026 case 4: 1027 op->val = *(u32 *)op->addr.reg; 1028 break; 1029 case 8: 1030 op->val = *(u64 *)op->addr.reg; 1031 break; 1032 } 1033 } 1034 1035 static int em_fninit(struct x86_emulate_ctxt *ctxt) 1036 { 1037 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1038 return emulate_nm(ctxt); 1039 1040 kvm_fpu_get(); 1041 asm volatile("fninit"); 1042 kvm_fpu_put(); 1043 return X86EMUL_CONTINUE; 1044 } 1045 1046 static int em_fnstcw(struct x86_emulate_ctxt *ctxt) 1047 { 1048 u16 fcw; 1049 1050 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1051 return emulate_nm(ctxt); 1052 1053 kvm_fpu_get(); 1054 asm volatile("fnstcw %0": "+m"(fcw)); 1055 kvm_fpu_put(); 1056 1057 ctxt->dst.val = fcw; 1058 1059 return X86EMUL_CONTINUE; 1060 } 1061 1062 static int em_fnstsw(struct x86_emulate_ctxt *ctxt) 1063 { 1064 u16 fsw; 1065 1066 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1067 return emulate_nm(ctxt); 1068 1069 kvm_fpu_get(); 1070 asm volatile("fnstsw %0": "+m"(fsw)); 1071 kvm_fpu_put(); 1072 1073 ctxt->dst.val = fsw; 1074 1075 return X86EMUL_CONTINUE; 1076 } 1077 1078 static void decode_register_operand(struct x86_emulate_ctxt *ctxt, 1079 struct operand *op) 1080 { 1081 unsigned int reg; 1082 1083 if (ctxt->d & ModRM) 1084 reg = ctxt->modrm_reg; 1085 else 1086 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3); 1087 1088 if (ctxt->d & Sse) { 1089 op->type = OP_XMM; 1090 op->bytes = 16; 1091 op->addr.xmm = reg; 1092 kvm_read_sse_reg(reg, &op->vec_val); 1093 return; 1094 } 1095 if (ctxt->d & Mmx) { 1096 reg &= 7; 1097 op->type = OP_MM; 1098 op->bytes = 8; 1099 op->addr.mm = reg; 1100 return; 1101 } 1102 1103 op->type = OP_REG; 1104 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 1105 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp); 1106 1107 fetch_register_operand(op); 1108 op->orig_val = op->val; 1109 } 1110 1111 static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg) 1112 { 1113 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP) 1114 ctxt->modrm_seg = VCPU_SREG_SS; 1115 } 1116 1117 static int decode_modrm(struct x86_emulate_ctxt *ctxt, 1118 struct operand *op) 1119 { 1120 u8 sib; 1121 int index_reg, base_reg, scale; 1122 int rc = X86EMUL_CONTINUE; 1123 ulong modrm_ea = 0; 1124 1125 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */ 1126 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */ 1127 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */ 1128 1129 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6; 1130 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3; 1131 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07); 1132 ctxt->modrm_seg = VCPU_SREG_DS; 1133 1134 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) { 1135 op->type = OP_REG; 1136 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 1137 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, 1138 ctxt->d & ByteOp); 1139 if (ctxt->d & Sse) { 1140 op->type = OP_XMM; 1141 op->bytes = 16; 1142 op->addr.xmm = ctxt->modrm_rm; 1143 kvm_read_sse_reg(ctxt->modrm_rm, &op->vec_val); 1144 return rc; 1145 } 1146 if (ctxt->d & Mmx) { 1147 op->type = OP_MM; 1148 op->bytes = 8; 1149 op->addr.mm = ctxt->modrm_rm & 7; 1150 return rc; 1151 } 1152 fetch_register_operand(op); 1153 return rc; 1154 } 1155 1156 op->type = OP_MEM; 1157 1158 if (ctxt->ad_bytes == 2) { 1159 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX); 1160 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP); 1161 unsigned si = reg_read(ctxt, VCPU_REGS_RSI); 1162 unsigned di = reg_read(ctxt, VCPU_REGS_RDI); 1163 1164 /* 16-bit ModR/M decode. */ 1165 switch (ctxt->modrm_mod) { 1166 case 0: 1167 if (ctxt->modrm_rm == 6) 1168 modrm_ea += insn_fetch(u16, ctxt); 1169 break; 1170 case 1: 1171 modrm_ea += insn_fetch(s8, ctxt); 1172 break; 1173 case 2: 1174 modrm_ea += insn_fetch(u16, ctxt); 1175 break; 1176 } 1177 switch (ctxt->modrm_rm) { 1178 case 0: 1179 modrm_ea += bx + si; 1180 break; 1181 case 1: 1182 modrm_ea += bx + di; 1183 break; 1184 case 2: 1185 modrm_ea += bp + si; 1186 break; 1187 case 3: 1188 modrm_ea += bp + di; 1189 break; 1190 case 4: 1191 modrm_ea += si; 1192 break; 1193 case 5: 1194 modrm_ea += di; 1195 break; 1196 case 6: 1197 if (ctxt->modrm_mod != 0) 1198 modrm_ea += bp; 1199 break; 1200 case 7: 1201 modrm_ea += bx; 1202 break; 1203 } 1204 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 || 1205 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0)) 1206 ctxt->modrm_seg = VCPU_SREG_SS; 1207 modrm_ea = (u16)modrm_ea; 1208 } else { 1209 /* 32/64-bit ModR/M decode. */ 1210 if ((ctxt->modrm_rm & 7) == 4) { 1211 sib = insn_fetch(u8, ctxt); 1212 index_reg |= (sib >> 3) & 7; 1213 base_reg |= sib & 7; 1214 scale = sib >> 6; 1215 1216 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0) 1217 modrm_ea += insn_fetch(s32, ctxt); 1218 else { 1219 modrm_ea += reg_read(ctxt, base_reg); 1220 adjust_modrm_seg(ctxt, base_reg); 1221 /* Increment ESP on POP [ESP] */ 1222 if ((ctxt->d & IncSP) && 1223 base_reg == VCPU_REGS_RSP) 1224 modrm_ea += ctxt->op_bytes; 1225 } 1226 if (index_reg != 4) 1227 modrm_ea += reg_read(ctxt, index_reg) << scale; 1228 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) { 1229 modrm_ea += insn_fetch(s32, ctxt); 1230 if (ctxt->mode == X86EMUL_MODE_PROT64) 1231 ctxt->rip_relative = 1; 1232 } else { 1233 base_reg = ctxt->modrm_rm; 1234 modrm_ea += reg_read(ctxt, base_reg); 1235 adjust_modrm_seg(ctxt, base_reg); 1236 } 1237 switch (ctxt->modrm_mod) { 1238 case 1: 1239 modrm_ea += insn_fetch(s8, ctxt); 1240 break; 1241 case 2: 1242 modrm_ea += insn_fetch(s32, ctxt); 1243 break; 1244 } 1245 } 1246 op->addr.mem.ea = modrm_ea; 1247 if (ctxt->ad_bytes != 8) 1248 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea; 1249 1250 done: 1251 return rc; 1252 } 1253 1254 static int decode_abs(struct x86_emulate_ctxt *ctxt, 1255 struct operand *op) 1256 { 1257 int rc = X86EMUL_CONTINUE; 1258 1259 op->type = OP_MEM; 1260 switch (ctxt->ad_bytes) { 1261 case 2: 1262 op->addr.mem.ea = insn_fetch(u16, ctxt); 1263 break; 1264 case 4: 1265 op->addr.mem.ea = insn_fetch(u32, ctxt); 1266 break; 1267 case 8: 1268 op->addr.mem.ea = insn_fetch(u64, ctxt); 1269 break; 1270 } 1271 done: 1272 return rc; 1273 } 1274 1275 static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt) 1276 { 1277 long sv = 0, mask; 1278 1279 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) { 1280 mask = ~((long)ctxt->dst.bytes * 8 - 1); 1281 1282 if (ctxt->src.bytes == 2) 1283 sv = (s16)ctxt->src.val & (s16)mask; 1284 else if (ctxt->src.bytes == 4) 1285 sv = (s32)ctxt->src.val & (s32)mask; 1286 else 1287 sv = (s64)ctxt->src.val & (s64)mask; 1288 1289 ctxt->dst.addr.mem.ea = address_mask(ctxt, 1290 ctxt->dst.addr.mem.ea + (sv >> 3)); 1291 } 1292 1293 /* only subword offset */ 1294 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; 1295 } 1296 1297 static int read_emulated(struct x86_emulate_ctxt *ctxt, 1298 unsigned long addr, void *dest, unsigned size) 1299 { 1300 int rc; 1301 struct read_cache *mc = &ctxt->mem_read; 1302 1303 if (mc->pos < mc->end) 1304 goto read_cached; 1305 1306 if (KVM_EMULATOR_BUG_ON((mc->end + size) >= sizeof(mc->data), ctxt)) 1307 return X86EMUL_UNHANDLEABLE; 1308 1309 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size, 1310 &ctxt->exception); 1311 if (rc != X86EMUL_CONTINUE) 1312 return rc; 1313 1314 mc->end += size; 1315 1316 read_cached: 1317 memcpy(dest, mc->data + mc->pos, size); 1318 mc->pos += size; 1319 return X86EMUL_CONTINUE; 1320 } 1321 1322 static int segmented_read(struct x86_emulate_ctxt *ctxt, 1323 struct segmented_address addr, 1324 void *data, 1325 unsigned size) 1326 { 1327 int rc; 1328 ulong linear; 1329 1330 rc = linearize(ctxt, addr, size, false, &linear); 1331 if (rc != X86EMUL_CONTINUE) 1332 return rc; 1333 return read_emulated(ctxt, linear, data, size); 1334 } 1335 1336 static int segmented_write(struct x86_emulate_ctxt *ctxt, 1337 struct segmented_address addr, 1338 const void *data, 1339 unsigned size) 1340 { 1341 int rc; 1342 ulong linear; 1343 1344 rc = linearize(ctxt, addr, size, true, &linear); 1345 if (rc != X86EMUL_CONTINUE) 1346 return rc; 1347 return ctxt->ops->write_emulated(ctxt, linear, data, size, 1348 &ctxt->exception); 1349 } 1350 1351 static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt, 1352 struct segmented_address addr, 1353 const void *orig_data, const void *data, 1354 unsigned size) 1355 { 1356 int rc; 1357 ulong linear; 1358 1359 rc = linearize(ctxt, addr, size, true, &linear); 1360 if (rc != X86EMUL_CONTINUE) 1361 return rc; 1362 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data, 1363 size, &ctxt->exception); 1364 } 1365 1366 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, 1367 unsigned int size, unsigned short port, 1368 void *dest) 1369 { 1370 struct read_cache *rc = &ctxt->io_read; 1371 1372 if (rc->pos == rc->end) { /* refill pio read ahead */ 1373 unsigned int in_page, n; 1374 unsigned int count = ctxt->rep_prefix ? 1375 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1; 1376 in_page = (ctxt->eflags & X86_EFLAGS_DF) ? 1377 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) : 1378 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)); 1379 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count); 1380 if (n == 0) 1381 n = 1; 1382 rc->pos = rc->end = 0; 1383 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n)) 1384 return 0; 1385 rc->end = n * size; 1386 } 1387 1388 if (ctxt->rep_prefix && (ctxt->d & String) && 1389 !(ctxt->eflags & X86_EFLAGS_DF)) { 1390 ctxt->dst.data = rc->data + rc->pos; 1391 ctxt->dst.type = OP_MEM_STR; 1392 ctxt->dst.count = (rc->end - rc->pos) / size; 1393 rc->pos = rc->end; 1394 } else { 1395 memcpy(dest, rc->data + rc->pos, size); 1396 rc->pos += size; 1397 } 1398 return 1; 1399 } 1400 1401 static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt, 1402 u16 index, struct desc_struct *desc) 1403 { 1404 struct desc_ptr dt; 1405 ulong addr; 1406 1407 ctxt->ops->get_idt(ctxt, &dt); 1408 1409 if (dt.size < index * 8 + 7) 1410 return emulate_gp(ctxt, index << 3 | 0x2); 1411 1412 addr = dt.address + index * 8; 1413 return linear_read_system(ctxt, addr, desc, sizeof(*desc)); 1414 } 1415 1416 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, 1417 u16 selector, struct desc_ptr *dt) 1418 { 1419 const struct x86_emulate_ops *ops = ctxt->ops; 1420 u32 base3 = 0; 1421 1422 if (selector & 1 << 2) { 1423 struct desc_struct desc; 1424 u16 sel; 1425 1426 memset(dt, 0, sizeof(*dt)); 1427 if (!ops->get_segment(ctxt, &sel, &desc, &base3, 1428 VCPU_SREG_LDTR)) 1429 return; 1430 1431 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ 1432 dt->address = get_desc_base(&desc) | ((u64)base3 << 32); 1433 } else 1434 ops->get_gdt(ctxt, dt); 1435 } 1436 1437 static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt, 1438 u16 selector, ulong *desc_addr_p) 1439 { 1440 struct desc_ptr dt; 1441 u16 index = selector >> 3; 1442 ulong addr; 1443 1444 get_descriptor_table_ptr(ctxt, selector, &dt); 1445 1446 if (dt.size < index * 8 + 7) 1447 return emulate_gp(ctxt, selector & 0xfffc); 1448 1449 addr = dt.address + index * 8; 1450 1451 #ifdef CONFIG_X86_64 1452 if (addr >> 32 != 0) { 1453 u64 efer = 0; 1454 1455 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 1456 if (!(efer & EFER_LMA)) 1457 addr &= (u32)-1; 1458 } 1459 #endif 1460 1461 *desc_addr_p = addr; 1462 return X86EMUL_CONTINUE; 1463 } 1464 1465 /* allowed just for 8 bytes segments */ 1466 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1467 u16 selector, struct desc_struct *desc, 1468 ulong *desc_addr_p) 1469 { 1470 int rc; 1471 1472 rc = get_descriptor_ptr(ctxt, selector, desc_addr_p); 1473 if (rc != X86EMUL_CONTINUE) 1474 return rc; 1475 1476 return linear_read_system(ctxt, *desc_addr_p, desc, sizeof(*desc)); 1477 } 1478 1479 /* allowed just for 8 bytes segments */ 1480 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1481 u16 selector, struct desc_struct *desc) 1482 { 1483 int rc; 1484 ulong addr; 1485 1486 rc = get_descriptor_ptr(ctxt, selector, &addr); 1487 if (rc != X86EMUL_CONTINUE) 1488 return rc; 1489 1490 return linear_write_system(ctxt, addr, desc, sizeof(*desc)); 1491 } 1492 1493 static bool emulator_is_ssp_invalid(struct x86_emulate_ctxt *ctxt, u8 cpl) 1494 { 1495 const u32 MSR_IA32_X_CET = cpl == 3 ? MSR_IA32_U_CET : MSR_IA32_S_CET; 1496 u64 efer = 0, cet = 0, ssp = 0; 1497 1498 if (!(ctxt->ops->get_cr(ctxt, 4) & X86_CR4_CET)) 1499 return false; 1500 1501 if (ctxt->ops->get_msr(ctxt, MSR_EFER, &efer)) 1502 return true; 1503 1504 /* SSP is guaranteed to be valid if the vCPU was already in 32-bit mode. */ 1505 if (!(efer & EFER_LMA)) 1506 return false; 1507 1508 if (ctxt->ops->get_msr(ctxt, MSR_IA32_X_CET, &cet)) 1509 return true; 1510 1511 if (!(cet & CET_SHSTK_EN)) 1512 return false; 1513 1514 if (ctxt->ops->get_msr(ctxt, MSR_KVM_INTERNAL_GUEST_SSP, &ssp)) 1515 return true; 1516 1517 /* 1518 * On transfer from 64-bit mode to compatibility mode, SSP[63:32] must 1519 * be 0, i.e. SSP must be a 32-bit value outside of 64-bit mode. 1520 */ 1521 return ssp >> 32; 1522 } 1523 1524 static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1525 u16 selector, int seg, u8 cpl, 1526 enum x86_transfer_type transfer, 1527 struct desc_struct *desc) 1528 { 1529 struct desc_struct seg_desc, old_desc; 1530 u8 dpl, rpl; 1531 unsigned err_vec = GP_VECTOR; 1532 u32 err_code = 0; 1533 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ 1534 ulong desc_addr; 1535 int ret; 1536 u16 dummy; 1537 u32 base3 = 0; 1538 1539 memset(&seg_desc, 0, sizeof(seg_desc)); 1540 1541 if (ctxt->mode == X86EMUL_MODE_REAL) { 1542 /* set real mode segment descriptor (keep limit etc. for 1543 * unreal mode) */ 1544 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg); 1545 set_desc_base(&seg_desc, selector << 4); 1546 goto load; 1547 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) { 1548 /* VM86 needs a clean new segment descriptor */ 1549 set_desc_base(&seg_desc, selector << 4); 1550 set_desc_limit(&seg_desc, 0xffff); 1551 seg_desc.type = 3; 1552 seg_desc.p = 1; 1553 seg_desc.s = 1; 1554 seg_desc.dpl = 3; 1555 goto load; 1556 } 1557 1558 rpl = selector & 3; 1559 1560 /* TR should be in GDT only */ 1561 if (seg == VCPU_SREG_TR && (selector & (1 << 2))) 1562 goto exception; 1563 1564 /* NULL selector is not valid for TR, CS and (except for long mode) SS */ 1565 if (null_selector) { 1566 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_TR) 1567 goto exception; 1568 1569 if (seg == VCPU_SREG_SS) { 1570 if (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl) 1571 goto exception; 1572 1573 /* 1574 * ctxt->ops->set_segment expects the CPL to be in 1575 * SS.DPL, so fake an expand-up 32-bit data segment. 1576 */ 1577 seg_desc.type = 3; 1578 seg_desc.p = 1; 1579 seg_desc.s = 1; 1580 seg_desc.dpl = cpl; 1581 seg_desc.d = 1; 1582 seg_desc.g = 1; 1583 } 1584 1585 /* Skip all following checks */ 1586 goto load; 1587 } 1588 1589 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr); 1590 if (ret != X86EMUL_CONTINUE) 1591 return ret; 1592 1593 err_code = selector & 0xfffc; 1594 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR : 1595 GP_VECTOR; 1596 1597 /* can't load system descriptor into segment selector */ 1598 if (seg <= VCPU_SREG_GS && !seg_desc.s) { 1599 if (transfer == X86_TRANSFER_CALL_JMP) 1600 return X86EMUL_UNHANDLEABLE; 1601 goto exception; 1602 } 1603 1604 dpl = seg_desc.dpl; 1605 1606 switch (seg) { 1607 case VCPU_SREG_SS: 1608 /* 1609 * segment is not a writable data segment or segment 1610 * selector's RPL != CPL or DPL != CPL 1611 */ 1612 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) 1613 goto exception; 1614 break; 1615 case VCPU_SREG_CS: 1616 /* 1617 * KVM uses "none" when loading CS as part of emulating Real 1618 * Mode exceptions and IRET (handled above). In all other 1619 * cases, loading CS without a control transfer is a KVM bug. 1620 */ 1621 if (WARN_ON_ONCE(transfer == X86_TRANSFER_NONE)) 1622 goto exception; 1623 1624 if (!(seg_desc.type & 8)) 1625 goto exception; 1626 1627 if (transfer == X86_TRANSFER_RET) { 1628 /* RET can never return to an inner privilege level. */ 1629 if (rpl < cpl) 1630 goto exception; 1631 /* Outer-privilege level return is not implemented */ 1632 if (rpl > cpl) 1633 return X86EMUL_UNHANDLEABLE; 1634 } 1635 if (transfer == X86_TRANSFER_RET || transfer == X86_TRANSFER_TASK_SWITCH) { 1636 if (seg_desc.type & 4) { 1637 /* conforming */ 1638 if (dpl > rpl) 1639 goto exception; 1640 } else { 1641 /* nonconforming */ 1642 if (dpl != rpl) 1643 goto exception; 1644 } 1645 } else { /* X86_TRANSFER_CALL_JMP */ 1646 if (seg_desc.type & 4) { 1647 /* conforming */ 1648 if (dpl > cpl) 1649 goto exception; 1650 } else { 1651 /* nonconforming */ 1652 if (rpl > cpl || dpl != cpl) 1653 goto exception; 1654 } 1655 } 1656 /* in long-mode d/b must be clear if l is set */ 1657 if (seg_desc.d && seg_desc.l) { 1658 u64 efer = 0; 1659 1660 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 1661 if (efer & EFER_LMA) 1662 goto exception; 1663 } 1664 if (!seg_desc.l && emulator_is_ssp_invalid(ctxt, cpl)) { 1665 err_code = 0; 1666 goto exception; 1667 } 1668 1669 /* CS(RPL) <- CPL */ 1670 selector = (selector & 0xfffc) | cpl; 1671 break; 1672 case VCPU_SREG_TR: 1673 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) 1674 goto exception; 1675 break; 1676 case VCPU_SREG_LDTR: 1677 if (seg_desc.s || seg_desc.type != 2) 1678 goto exception; 1679 break; 1680 default: /* DS, ES, FS, or GS */ 1681 /* 1682 * segment is not a data or readable code segment or 1683 * ((segment is a data or nonconforming code segment) 1684 * and ((RPL > DPL) or (CPL > DPL))) 1685 */ 1686 if ((seg_desc.type & 0xa) == 0x8 || 1687 (((seg_desc.type & 0xc) != 0xc) && 1688 (rpl > dpl || cpl > dpl))) 1689 goto exception; 1690 break; 1691 } 1692 1693 if (!seg_desc.p) { 1694 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; 1695 goto exception; 1696 } 1697 1698 if (seg_desc.s) { 1699 /* mark segment as accessed */ 1700 if (!(seg_desc.type & 1)) { 1701 seg_desc.type |= 1; 1702 ret = write_segment_descriptor(ctxt, selector, 1703 &seg_desc); 1704 if (ret != X86EMUL_CONTINUE) 1705 return ret; 1706 } 1707 } else if (ctxt->mode == X86EMUL_MODE_PROT64) { 1708 ret = linear_read_system(ctxt, desc_addr+8, &base3, sizeof(base3)); 1709 if (ret != X86EMUL_CONTINUE) 1710 return ret; 1711 if (emul_is_noncanonical_address(get_desc_base(&seg_desc) | 1712 ((u64)base3 << 32), ctxt, 1713 X86EMUL_F_DT_LOAD)) 1714 return emulate_gp(ctxt, err_code); 1715 } 1716 1717 if (seg == VCPU_SREG_TR) { 1718 old_desc = seg_desc; 1719 seg_desc.type |= 2; /* busy */ 1720 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc, 1721 sizeof(seg_desc), &ctxt->exception); 1722 if (ret != X86EMUL_CONTINUE) 1723 return ret; 1724 } 1725 load: 1726 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg); 1727 if (desc) 1728 *desc = seg_desc; 1729 return X86EMUL_CONTINUE; 1730 exception: 1731 return emulate_exception(ctxt, err_vec, err_code, true); 1732 } 1733 1734 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1735 u16 selector, int seg) 1736 { 1737 u8 cpl = ctxt->ops->cpl(ctxt); 1738 1739 /* 1740 * None of MOV, POP and LSS can load a NULL selector in CPL=3, but 1741 * they can load it at CPL<3 (Intel's manual says only LSS can, 1742 * but it's wrong). 1743 * 1744 * However, the Intel manual says that putting IST=1/DPL=3 in 1745 * an interrupt gate will result in SS=3 (the AMD manual instead 1746 * says it doesn't), so allow SS=3 in __load_segment_descriptor 1747 * and only forbid it here. 1748 */ 1749 if (seg == VCPU_SREG_SS && selector == 3 && 1750 ctxt->mode == X86EMUL_MODE_PROT64) 1751 return emulate_exception(ctxt, GP_VECTOR, 0, true); 1752 1753 return __load_segment_descriptor(ctxt, selector, seg, cpl, 1754 X86_TRANSFER_NONE, NULL); 1755 } 1756 1757 static void write_register_operand(struct operand *op) 1758 { 1759 return assign_register(op->addr.reg, op->val, op->bytes); 1760 } 1761 1762 static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op) 1763 { 1764 switch (op->type) { 1765 case OP_REG: 1766 write_register_operand(op); 1767 break; 1768 case OP_MEM: 1769 if (ctxt->lock_prefix) 1770 return segmented_cmpxchg(ctxt, 1771 op->addr.mem, 1772 &op->orig_val, 1773 &op->val, 1774 op->bytes); 1775 else 1776 return segmented_write(ctxt, 1777 op->addr.mem, 1778 &op->val, 1779 op->bytes); 1780 case OP_MEM_STR: 1781 return segmented_write(ctxt, 1782 op->addr.mem, 1783 op->data, 1784 op->bytes * op->count); 1785 case OP_XMM: 1786 kvm_write_sse_reg(op->addr.xmm, &op->vec_val); 1787 break; 1788 case OP_MM: 1789 kvm_write_mmx_reg(op->addr.mm, &op->mm_val); 1790 break; 1791 case OP_NONE: 1792 /* no writeback */ 1793 break; 1794 default: 1795 break; 1796 } 1797 return X86EMUL_CONTINUE; 1798 } 1799 1800 static int emulate_push(struct x86_emulate_ctxt *ctxt, const void *data, int len) 1801 { 1802 struct segmented_address addr; 1803 1804 rsp_increment(ctxt, -len); 1805 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); 1806 addr.seg = VCPU_SREG_SS; 1807 1808 return segmented_write(ctxt, addr, data, len); 1809 } 1810 1811 static int em_push(struct x86_emulate_ctxt *ctxt) 1812 { 1813 /* Disable writeback. */ 1814 ctxt->dst.type = OP_NONE; 1815 return emulate_push(ctxt, &ctxt->src.val, ctxt->op_bytes); 1816 } 1817 1818 static int emulate_pop(struct x86_emulate_ctxt *ctxt, 1819 void *dest, int len) 1820 { 1821 int rc; 1822 struct segmented_address addr; 1823 1824 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); 1825 addr.seg = VCPU_SREG_SS; 1826 rc = segmented_read(ctxt, addr, dest, len); 1827 if (rc != X86EMUL_CONTINUE) 1828 return rc; 1829 1830 rsp_increment(ctxt, len); 1831 return rc; 1832 } 1833 1834 static int em_pop(struct x86_emulate_ctxt *ctxt) 1835 { 1836 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1837 } 1838 1839 static int emulate_popf(struct x86_emulate_ctxt *ctxt, 1840 void *dest, int len) 1841 { 1842 int rc; 1843 unsigned long val = 0; 1844 unsigned long change_mask; 1845 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT; 1846 int cpl = ctxt->ops->cpl(ctxt); 1847 1848 rc = emulate_pop(ctxt, &val, len); 1849 if (rc != X86EMUL_CONTINUE) 1850 return rc; 1851 1852 change_mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | 1853 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF | 1854 X86_EFLAGS_TF | X86_EFLAGS_DF | X86_EFLAGS_NT | 1855 X86_EFLAGS_AC | X86_EFLAGS_ID; 1856 1857 switch(ctxt->mode) { 1858 case X86EMUL_MODE_PROT64: 1859 case X86EMUL_MODE_PROT32: 1860 case X86EMUL_MODE_PROT16: 1861 if (cpl == 0) 1862 change_mask |= X86_EFLAGS_IOPL; 1863 if (cpl <= iopl) 1864 change_mask |= X86_EFLAGS_IF; 1865 break; 1866 case X86EMUL_MODE_VM86: 1867 if (iopl < 3) 1868 return emulate_gp(ctxt, 0); 1869 change_mask |= X86_EFLAGS_IF; 1870 break; 1871 default: /* real mode */ 1872 change_mask |= (X86_EFLAGS_IOPL | X86_EFLAGS_IF); 1873 break; 1874 } 1875 1876 *(unsigned long *)dest = 1877 (ctxt->eflags & ~change_mask) | (val & change_mask); 1878 1879 return rc; 1880 } 1881 1882 static int em_popf(struct x86_emulate_ctxt *ctxt) 1883 { 1884 ctxt->dst.type = OP_REG; 1885 ctxt->dst.addr.reg = &ctxt->eflags; 1886 ctxt->dst.bytes = ctxt->op_bytes; 1887 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1888 } 1889 1890 static int em_enter(struct x86_emulate_ctxt *ctxt) 1891 { 1892 int rc; 1893 unsigned frame_size = ctxt->src.val; 1894 unsigned nesting_level = ctxt->src2.val & 31; 1895 ulong rbp; 1896 1897 if (nesting_level) 1898 return X86EMUL_UNHANDLEABLE; 1899 1900 rbp = reg_read(ctxt, VCPU_REGS_RBP); 1901 rc = emulate_push(ctxt, &rbp, stack_size(ctxt)); 1902 if (rc != X86EMUL_CONTINUE) 1903 return rc; 1904 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP), 1905 stack_mask(ctxt)); 1906 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), 1907 reg_read(ctxt, VCPU_REGS_RSP) - frame_size, 1908 stack_mask(ctxt)); 1909 return X86EMUL_CONTINUE; 1910 } 1911 1912 static int em_leave(struct x86_emulate_ctxt *ctxt) 1913 { 1914 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP), 1915 stack_mask(ctxt)); 1916 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes); 1917 } 1918 1919 static int em_push_sreg(struct x86_emulate_ctxt *ctxt) 1920 { 1921 int seg = ctxt->src2.val; 1922 1923 ctxt->src.val = get_segment_selector(ctxt, seg); 1924 if (ctxt->op_bytes == 4) { 1925 rsp_increment(ctxt, -2); 1926 ctxt->op_bytes = 2; 1927 } 1928 1929 return em_push(ctxt); 1930 } 1931 1932 static int em_pop_sreg(struct x86_emulate_ctxt *ctxt) 1933 { 1934 int seg = ctxt->src2.val; 1935 unsigned long selector = 0; 1936 int rc; 1937 1938 rc = emulate_pop(ctxt, &selector, 2); 1939 if (rc != X86EMUL_CONTINUE) 1940 return rc; 1941 1942 if (seg == VCPU_SREG_SS) 1943 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; 1944 if (ctxt->op_bytes > 2) 1945 rsp_increment(ctxt, ctxt->op_bytes - 2); 1946 1947 rc = load_segment_descriptor(ctxt, (u16)selector, seg); 1948 return rc; 1949 } 1950 1951 static int em_pusha(struct x86_emulate_ctxt *ctxt) 1952 { 1953 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP); 1954 int rc = X86EMUL_CONTINUE; 1955 int reg = VCPU_REGS_RAX; 1956 1957 while (reg <= VCPU_REGS_RDI) { 1958 (reg == VCPU_REGS_RSP) ? 1959 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg)); 1960 1961 rc = em_push(ctxt); 1962 if (rc != X86EMUL_CONTINUE) 1963 return rc; 1964 1965 ++reg; 1966 } 1967 1968 return rc; 1969 } 1970 1971 static int em_pushf(struct x86_emulate_ctxt *ctxt) 1972 { 1973 ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM; 1974 return em_push(ctxt); 1975 } 1976 1977 static int em_popa(struct x86_emulate_ctxt *ctxt) 1978 { 1979 int rc = X86EMUL_CONTINUE; 1980 int reg = VCPU_REGS_RDI; 1981 u32 val = 0; 1982 1983 while (reg >= VCPU_REGS_RAX) { 1984 if (reg == VCPU_REGS_RSP) { 1985 rsp_increment(ctxt, ctxt->op_bytes); 1986 --reg; 1987 } 1988 1989 rc = emulate_pop(ctxt, &val, ctxt->op_bytes); 1990 if (rc != X86EMUL_CONTINUE) 1991 break; 1992 assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes); 1993 --reg; 1994 } 1995 return rc; 1996 } 1997 1998 static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) 1999 { 2000 const struct x86_emulate_ops *ops = ctxt->ops; 2001 int rc; 2002 struct desc_ptr dt; 2003 gva_t cs_addr; 2004 gva_t eip_addr; 2005 u16 cs, eip; 2006 2007 /* TODO: Add limit checks */ 2008 ctxt->src.val = ctxt->eflags; 2009 rc = em_push(ctxt); 2010 if (rc != X86EMUL_CONTINUE) 2011 return rc; 2012 2013 ctxt->eflags &= ~(X86_EFLAGS_IF | X86_EFLAGS_TF | X86_EFLAGS_AC); 2014 2015 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS); 2016 rc = em_push(ctxt); 2017 if (rc != X86EMUL_CONTINUE) 2018 return rc; 2019 2020 ctxt->src.val = ctxt->_eip; 2021 rc = em_push(ctxt); 2022 if (rc != X86EMUL_CONTINUE) 2023 return rc; 2024 2025 ops->get_idt(ctxt, &dt); 2026 2027 eip_addr = dt.address + (irq << 2); 2028 cs_addr = dt.address + (irq << 2) + 2; 2029 2030 rc = linear_read_system(ctxt, cs_addr, &cs, 2); 2031 if (rc != X86EMUL_CONTINUE) 2032 return rc; 2033 2034 rc = linear_read_system(ctxt, eip_addr, &eip, 2); 2035 if (rc != X86EMUL_CONTINUE) 2036 return rc; 2037 2038 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS); 2039 if (rc != X86EMUL_CONTINUE) 2040 return rc; 2041 2042 ctxt->_eip = eip; 2043 2044 return rc; 2045 } 2046 2047 int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) 2048 { 2049 int rc; 2050 2051 invalidate_registers(ctxt); 2052 rc = __emulate_int_real(ctxt, irq); 2053 if (rc == X86EMUL_CONTINUE) 2054 writeback_registers(ctxt); 2055 return rc; 2056 } 2057 2058 static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq) 2059 { 2060 switch(ctxt->mode) { 2061 case X86EMUL_MODE_REAL: 2062 return __emulate_int_real(ctxt, irq); 2063 case X86EMUL_MODE_VM86: 2064 case X86EMUL_MODE_PROT16: 2065 case X86EMUL_MODE_PROT32: 2066 case X86EMUL_MODE_PROT64: 2067 default: 2068 /* Protected mode interrupts unimplemented yet */ 2069 return X86EMUL_UNHANDLEABLE; 2070 } 2071 } 2072 2073 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt) 2074 { 2075 int rc = X86EMUL_CONTINUE; 2076 unsigned long temp_eip = 0; 2077 unsigned long temp_eflags = 0; 2078 unsigned long cs = 0; 2079 unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | 2080 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_TF | 2081 X86_EFLAGS_IF | X86_EFLAGS_DF | X86_EFLAGS_OF | 2082 X86_EFLAGS_IOPL | X86_EFLAGS_NT | X86_EFLAGS_RF | 2083 X86_EFLAGS_AC | X86_EFLAGS_ID | 2084 X86_EFLAGS_FIXED; 2085 unsigned long vm86_mask = X86_EFLAGS_VM | X86_EFLAGS_VIF | 2086 X86_EFLAGS_VIP; 2087 2088 /* TODO: Add stack limit check */ 2089 2090 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes); 2091 2092 if (rc != X86EMUL_CONTINUE) 2093 return rc; 2094 2095 if (temp_eip & ~0xffff) 2096 return emulate_gp(ctxt, 0); 2097 2098 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 2099 2100 if (rc != X86EMUL_CONTINUE) 2101 return rc; 2102 2103 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes); 2104 2105 if (rc != X86EMUL_CONTINUE) 2106 return rc; 2107 2108 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); 2109 2110 if (rc != X86EMUL_CONTINUE) 2111 return rc; 2112 2113 ctxt->_eip = temp_eip; 2114 2115 if (ctxt->op_bytes == 4) 2116 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); 2117 else if (ctxt->op_bytes == 2) { 2118 ctxt->eflags &= ~0xffff; 2119 ctxt->eflags |= temp_eflags; 2120 } 2121 2122 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ 2123 ctxt->eflags |= X86_EFLAGS_FIXED; 2124 ctxt->ops->set_nmi_mask(ctxt, false); 2125 2126 return rc; 2127 } 2128 2129 static int em_iret(struct x86_emulate_ctxt *ctxt) 2130 { 2131 switch(ctxt->mode) { 2132 case X86EMUL_MODE_REAL: 2133 return emulate_iret_real(ctxt); 2134 case X86EMUL_MODE_VM86: 2135 case X86EMUL_MODE_PROT16: 2136 case X86EMUL_MODE_PROT32: 2137 case X86EMUL_MODE_PROT64: 2138 default: 2139 /* iret from protected mode unimplemented yet */ 2140 return X86EMUL_UNHANDLEABLE; 2141 } 2142 } 2143 2144 static int em_jmp_far(struct x86_emulate_ctxt *ctxt) 2145 { 2146 int rc; 2147 unsigned short sel; 2148 struct desc_struct new_desc; 2149 u8 cpl = ctxt->ops->cpl(ctxt); 2150 2151 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2152 2153 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, 2154 X86_TRANSFER_CALL_JMP, 2155 &new_desc); 2156 if (rc != X86EMUL_CONTINUE) 2157 return rc; 2158 2159 rc = assign_eip_far(ctxt, ctxt->src.val); 2160 /* Error handling is not implemented. */ 2161 if (rc != X86EMUL_CONTINUE) 2162 return X86EMUL_UNHANDLEABLE; 2163 2164 return rc; 2165 } 2166 2167 static int em_jmp_abs(struct x86_emulate_ctxt *ctxt) 2168 { 2169 return assign_eip_near(ctxt, ctxt->src.val); 2170 } 2171 2172 static int em_call_near_abs(struct x86_emulate_ctxt *ctxt) 2173 { 2174 int rc; 2175 long int old_eip; 2176 2177 old_eip = ctxt->_eip; 2178 rc = assign_eip_near(ctxt, ctxt->src.val); 2179 if (rc != X86EMUL_CONTINUE) 2180 return rc; 2181 ctxt->src.val = old_eip; 2182 rc = em_push(ctxt); 2183 return rc; 2184 } 2185 2186 static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt) 2187 { 2188 u64 old = ctxt->dst.orig_val64; 2189 2190 if (ctxt->dst.bytes == 16) 2191 return X86EMUL_UNHANDLEABLE; 2192 2193 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) || 2194 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) { 2195 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0); 2196 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32); 2197 ctxt->eflags &= ~X86_EFLAGS_ZF; 2198 } else { 2199 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) | 2200 (u32) reg_read(ctxt, VCPU_REGS_RBX); 2201 2202 ctxt->eflags |= X86_EFLAGS_ZF; 2203 } 2204 return X86EMUL_CONTINUE; 2205 } 2206 2207 static int em_ret(struct x86_emulate_ctxt *ctxt) 2208 { 2209 int rc; 2210 unsigned long eip = 0; 2211 2212 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 2213 if (rc != X86EMUL_CONTINUE) 2214 return rc; 2215 2216 return assign_eip_near(ctxt, eip); 2217 } 2218 2219 static int em_ret_far(struct x86_emulate_ctxt *ctxt) 2220 { 2221 int rc; 2222 unsigned long eip = 0; 2223 unsigned long cs = 0; 2224 int cpl = ctxt->ops->cpl(ctxt); 2225 struct desc_struct new_desc; 2226 2227 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 2228 if (rc != X86EMUL_CONTINUE) 2229 return rc; 2230 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 2231 if (rc != X86EMUL_CONTINUE) 2232 return rc; 2233 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl, 2234 X86_TRANSFER_RET, 2235 &new_desc); 2236 if (rc != X86EMUL_CONTINUE) 2237 return rc; 2238 rc = assign_eip_far(ctxt, eip); 2239 /* Error handling is not implemented. */ 2240 if (rc != X86EMUL_CONTINUE) 2241 return X86EMUL_UNHANDLEABLE; 2242 2243 return rc; 2244 } 2245 2246 static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt) 2247 { 2248 int rc; 2249 2250 rc = em_ret_far(ctxt); 2251 if (rc != X86EMUL_CONTINUE) 2252 return rc; 2253 rsp_increment(ctxt, ctxt->src.val); 2254 return X86EMUL_CONTINUE; 2255 } 2256 2257 static int em_cmpxchg(struct x86_emulate_ctxt *ctxt) 2258 { 2259 /* Save real source value, then compare EAX against destination. */ 2260 ctxt->dst.orig_val = ctxt->dst.val; 2261 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX); 2262 ctxt->src.orig_val = ctxt->src.val; 2263 ctxt->src.val = ctxt->dst.orig_val; 2264 em_cmp(ctxt); 2265 2266 if (ctxt->eflags & X86_EFLAGS_ZF) { 2267 /* Success: write back to memory; no update of EAX */ 2268 ctxt->src.type = OP_NONE; 2269 ctxt->dst.val = ctxt->src.orig_val; 2270 } else { 2271 /* Failure: write the value we saw to EAX. */ 2272 ctxt->src.type = OP_REG; 2273 ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 2274 ctxt->src.val = ctxt->dst.orig_val; 2275 /* Create write-cycle to dest by writing the same value */ 2276 ctxt->dst.val = ctxt->dst.orig_val; 2277 } 2278 return X86EMUL_CONTINUE; 2279 } 2280 2281 static int em_lseg(struct x86_emulate_ctxt *ctxt) 2282 { 2283 int seg = ctxt->src2.val; 2284 unsigned short sel; 2285 int rc; 2286 2287 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2288 2289 rc = load_segment_descriptor(ctxt, sel, seg); 2290 if (rc != X86EMUL_CONTINUE) 2291 return rc; 2292 2293 ctxt->dst.val = ctxt->src.val; 2294 return rc; 2295 } 2296 2297 static int em_rsm(struct x86_emulate_ctxt *ctxt) 2298 { 2299 if (!ctxt->ops->is_smm(ctxt)) 2300 return emulate_ud(ctxt); 2301 2302 if (ctxt->ops->leave_smm(ctxt)) 2303 ctxt->ops->triple_fault(ctxt); 2304 2305 return emulator_recalc_and_set_mode(ctxt); 2306 } 2307 2308 static void 2309 setup_syscalls_segments(struct desc_struct *cs, struct desc_struct *ss) 2310 { 2311 cs->l = 0; /* will be adjusted later */ 2312 set_desc_base(cs, 0); /* flat segment */ 2313 cs->g = 1; /* 4kb granularity */ 2314 set_desc_limit(cs, 0xfffff); /* 4GB limit */ 2315 cs->type = 0x0b; /* Read, Execute, Accessed */ 2316 cs->s = 1; 2317 cs->dpl = 0; /* will be adjusted later */ 2318 cs->p = 1; 2319 cs->d = 1; 2320 cs->avl = 0; 2321 2322 set_desc_base(ss, 0); /* flat segment */ 2323 set_desc_limit(ss, 0xfffff); /* 4GB limit */ 2324 ss->g = 1; /* 4kb granularity */ 2325 ss->s = 1; 2326 ss->type = 0x03; /* Read/Write, Accessed */ 2327 ss->d = 1; /* 32bit stack segment */ 2328 ss->dpl = 0; 2329 ss->p = 1; 2330 ss->l = 0; 2331 ss->avl = 0; 2332 } 2333 2334 static int em_syscall(struct x86_emulate_ctxt *ctxt) 2335 { 2336 const struct x86_emulate_ops *ops = ctxt->ops; 2337 struct desc_struct cs, ss; 2338 u64 msr_data; 2339 u16 cs_sel, ss_sel; 2340 u64 efer = 0; 2341 2342 /* syscall is not available in real mode */ 2343 if (ctxt->mode == X86EMUL_MODE_REAL || 2344 ctxt->mode == X86EMUL_MODE_VM86) 2345 return emulate_ud(ctxt); 2346 2347 /* 2348 * Intel compatible CPUs only support SYSCALL in 64-bit mode, whereas 2349 * AMD allows SYSCALL in any flavor of protected mode. Note, it's 2350 * infeasible to emulate Intel behavior when running on AMD hardware, 2351 * as SYSCALL won't fault in the "wrong" mode, i.e. there is no #UD 2352 * for KVM to trap-and-emulate, unlike emulating AMD on Intel. 2353 */ 2354 if (ctxt->mode != X86EMUL_MODE_PROT64 && 2355 ctxt->ops->guest_cpuid_is_intel_compatible(ctxt)) 2356 return emulate_ud(ctxt); 2357 2358 ops->get_msr(ctxt, MSR_EFER, &efer); 2359 if (!(efer & EFER_SCE)) 2360 return emulate_ud(ctxt); 2361 2362 setup_syscalls_segments(&cs, &ss); 2363 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2364 msr_data >>= 32; 2365 cs_sel = (u16)(msr_data & 0xfffc); 2366 ss_sel = (u16)(msr_data + 8); 2367 2368 if (efer & EFER_LMA) { 2369 cs.d = 0; 2370 cs.l = 1; 2371 } 2372 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2373 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2374 2375 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip; 2376 if (efer & EFER_LMA) { 2377 #ifdef CONFIG_X86_64 2378 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags; 2379 2380 ops->get_msr(ctxt, 2381 ctxt->mode == X86EMUL_MODE_PROT64 ? 2382 MSR_LSTAR : MSR_CSTAR, &msr_data); 2383 ctxt->_eip = msr_data; 2384 2385 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data); 2386 ctxt->eflags &= ~msr_data; 2387 ctxt->eflags |= X86_EFLAGS_FIXED; 2388 #endif 2389 } else { 2390 /* legacy mode */ 2391 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2392 ctxt->_eip = (u32)msr_data; 2393 2394 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF); 2395 } 2396 2397 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 2398 return X86EMUL_CONTINUE; 2399 } 2400 2401 static int em_sysenter(struct x86_emulate_ctxt *ctxt) 2402 { 2403 const struct x86_emulate_ops *ops = ctxt->ops; 2404 struct desc_struct cs, ss; 2405 u64 msr_data; 2406 u16 cs_sel, ss_sel; 2407 u64 efer = 0; 2408 2409 ops->get_msr(ctxt, MSR_EFER, &efer); 2410 /* inject #GP if in real mode */ 2411 if (ctxt->mode == X86EMUL_MODE_REAL) 2412 return emulate_gp(ctxt, 0); 2413 2414 /* 2415 * Intel's architecture allows SYSENTER in compatibility mode, but AMD 2416 * does not. Note, AMD does allow SYSENTER in legacy protected mode. 2417 */ 2418 if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA) && 2419 !ctxt->ops->guest_cpuid_is_intel_compatible(ctxt)) 2420 return emulate_ud(ctxt); 2421 2422 /* sysenter/sysexit have not been tested in 64bit mode. */ 2423 if (ctxt->mode == X86EMUL_MODE_PROT64) 2424 return X86EMUL_UNHANDLEABLE; 2425 2426 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2427 if ((msr_data & 0xfffc) == 0x0) 2428 return emulate_gp(ctxt, 0); 2429 2430 setup_syscalls_segments(&cs, &ss); 2431 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF); 2432 cs_sel = (u16)msr_data & ~SEGMENT_RPL_MASK; 2433 ss_sel = cs_sel + 8; 2434 if (efer & EFER_LMA) { 2435 cs.d = 0; 2436 cs.l = 1; 2437 } 2438 2439 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2440 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2441 2442 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data); 2443 ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data; 2444 2445 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data); 2446 *reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data : 2447 (u32)msr_data; 2448 if (efer & EFER_LMA) 2449 ctxt->mode = X86EMUL_MODE_PROT64; 2450 2451 return X86EMUL_CONTINUE; 2452 } 2453 2454 static int em_sysexit(struct x86_emulate_ctxt *ctxt) 2455 { 2456 const struct x86_emulate_ops *ops = ctxt->ops; 2457 struct desc_struct cs, ss; 2458 u64 msr_data, rcx, rdx; 2459 int usermode; 2460 u16 cs_sel = 0, ss_sel = 0; 2461 2462 /* inject #GP if in real mode or Virtual 8086 mode */ 2463 if (ctxt->mode == X86EMUL_MODE_REAL || 2464 ctxt->mode == X86EMUL_MODE_VM86) 2465 return emulate_gp(ctxt, 0); 2466 2467 setup_syscalls_segments(&cs, &ss); 2468 2469 if ((ctxt->rex_prefix & 0x8) != 0x0) 2470 usermode = X86EMUL_MODE_PROT64; 2471 else 2472 usermode = X86EMUL_MODE_PROT32; 2473 2474 rcx = reg_read(ctxt, VCPU_REGS_RCX); 2475 rdx = reg_read(ctxt, VCPU_REGS_RDX); 2476 2477 cs.dpl = 3; 2478 ss.dpl = 3; 2479 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2480 switch (usermode) { 2481 case X86EMUL_MODE_PROT32: 2482 cs_sel = (u16)(msr_data + 16); 2483 if ((msr_data & 0xfffc) == 0x0) 2484 return emulate_gp(ctxt, 0); 2485 ss_sel = (u16)(msr_data + 24); 2486 rcx = (u32)rcx; 2487 rdx = (u32)rdx; 2488 break; 2489 case X86EMUL_MODE_PROT64: 2490 cs_sel = (u16)(msr_data + 32); 2491 if (msr_data == 0x0) 2492 return emulate_gp(ctxt, 0); 2493 ss_sel = cs_sel + 8; 2494 cs.d = 0; 2495 cs.l = 1; 2496 if (emul_is_noncanonical_address(rcx, ctxt, 0) || 2497 emul_is_noncanonical_address(rdx, ctxt, 0)) 2498 return emulate_gp(ctxt, 0); 2499 break; 2500 } 2501 cs_sel |= SEGMENT_RPL_MASK; 2502 ss_sel |= SEGMENT_RPL_MASK; 2503 2504 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2505 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2506 2507 ctxt->_eip = rdx; 2508 ctxt->mode = usermode; 2509 *reg_write(ctxt, VCPU_REGS_RSP) = rcx; 2510 2511 return X86EMUL_CONTINUE; 2512 } 2513 2514 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt) 2515 { 2516 int iopl; 2517 if (ctxt->mode == X86EMUL_MODE_REAL) 2518 return false; 2519 if (ctxt->mode == X86EMUL_MODE_VM86) 2520 return true; 2521 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT; 2522 return ctxt->ops->cpl(ctxt) > iopl; 2523 } 2524 2525 #define VMWARE_PORT_VMPORT (0x5658) 2526 #define VMWARE_PORT_VMRPC (0x5659) 2527 2528 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, 2529 u16 port, u16 len) 2530 { 2531 const struct x86_emulate_ops *ops = ctxt->ops; 2532 struct desc_struct tr_seg; 2533 u32 base3; 2534 int r; 2535 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7; 2536 unsigned mask = (1 << len) - 1; 2537 unsigned long base; 2538 2539 /* 2540 * VMware allows access to these ports even if denied 2541 * by TSS I/O permission bitmap. Mimic behavior. 2542 */ 2543 if (enable_vmware_backdoor && 2544 ((port == VMWARE_PORT_VMPORT) || (port == VMWARE_PORT_VMRPC))) 2545 return true; 2546 2547 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR); 2548 if (!tr_seg.p) 2549 return false; 2550 if (desc_limit_scaled(&tr_seg) < 103) 2551 return false; 2552 base = get_desc_base(&tr_seg); 2553 #ifdef CONFIG_X86_64 2554 base |= ((u64)base3) << 32; 2555 #endif 2556 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL, true); 2557 if (r != X86EMUL_CONTINUE) 2558 return false; 2559 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) 2560 return false; 2561 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL, true); 2562 if (r != X86EMUL_CONTINUE) 2563 return false; 2564 if ((perm >> bit_idx) & mask) 2565 return false; 2566 return true; 2567 } 2568 2569 static bool emulator_io_permitted(struct x86_emulate_ctxt *ctxt, 2570 u16 port, u16 len) 2571 { 2572 if (ctxt->perm_ok) 2573 return true; 2574 2575 if (emulator_bad_iopl(ctxt)) 2576 if (!emulator_io_port_access_allowed(ctxt, port, len)) 2577 return false; 2578 2579 ctxt->perm_ok = true; 2580 2581 return true; 2582 } 2583 2584 static void string_registers_quirk(struct x86_emulate_ctxt *ctxt) 2585 { 2586 /* 2587 * Intel CPUs mask the counter and pointers in quite strange 2588 * manner when ECX is zero due to REP-string optimizations. 2589 */ 2590 #ifdef CONFIG_X86_64 2591 u32 eax, ebx, ecx, edx; 2592 2593 if (ctxt->ad_bytes != 4) 2594 return; 2595 2596 eax = ecx = 0; 2597 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, true); 2598 if (!is_guest_vendor_intel(ebx, ecx, edx)) 2599 return; 2600 2601 *reg_write(ctxt, VCPU_REGS_RCX) = 0; 2602 2603 switch (ctxt->b) { 2604 case 0xa4: /* movsb */ 2605 case 0xa5: /* movsd/w */ 2606 *reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1; 2607 fallthrough; 2608 case 0xaa: /* stosb */ 2609 case 0xab: /* stosd/w */ 2610 *reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1; 2611 } 2612 #endif 2613 } 2614 2615 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, 2616 struct tss_segment_16 *tss) 2617 { 2618 tss->ip = ctxt->_eip; 2619 tss->flag = ctxt->eflags; 2620 tss->ax = reg_read(ctxt, VCPU_REGS_RAX); 2621 tss->cx = reg_read(ctxt, VCPU_REGS_RCX); 2622 tss->dx = reg_read(ctxt, VCPU_REGS_RDX); 2623 tss->bx = reg_read(ctxt, VCPU_REGS_RBX); 2624 tss->sp = reg_read(ctxt, VCPU_REGS_RSP); 2625 tss->bp = reg_read(ctxt, VCPU_REGS_RBP); 2626 tss->si = reg_read(ctxt, VCPU_REGS_RSI); 2627 tss->di = reg_read(ctxt, VCPU_REGS_RDI); 2628 2629 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 2630 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 2631 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 2632 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 2633 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR); 2634 } 2635 2636 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, 2637 struct tss_segment_16 *tss) 2638 { 2639 int ret; 2640 u8 cpl; 2641 2642 ctxt->_eip = tss->ip; 2643 ctxt->eflags = tss->flag | 2; 2644 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax; 2645 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx; 2646 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx; 2647 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx; 2648 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp; 2649 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp; 2650 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si; 2651 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di; 2652 2653 /* 2654 * SDM says that segment selectors are loaded before segment 2655 * descriptors 2656 */ 2657 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR); 2658 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 2659 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 2660 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 2661 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 2662 2663 cpl = tss->cs & 3; 2664 2665 /* 2666 * Now load segment descriptors. If fault happens at this stage 2667 * it is handled in a context of new task 2668 */ 2669 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, 2670 X86_TRANSFER_TASK_SWITCH, NULL); 2671 if (ret != X86EMUL_CONTINUE) 2672 return ret; 2673 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, 2674 X86_TRANSFER_TASK_SWITCH, NULL); 2675 if (ret != X86EMUL_CONTINUE) 2676 return ret; 2677 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, 2678 X86_TRANSFER_TASK_SWITCH, NULL); 2679 if (ret != X86EMUL_CONTINUE) 2680 return ret; 2681 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, 2682 X86_TRANSFER_TASK_SWITCH, NULL); 2683 if (ret != X86EMUL_CONTINUE) 2684 return ret; 2685 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, 2686 X86_TRANSFER_TASK_SWITCH, NULL); 2687 if (ret != X86EMUL_CONTINUE) 2688 return ret; 2689 2690 return X86EMUL_CONTINUE; 2691 } 2692 2693 static int task_switch_16(struct x86_emulate_ctxt *ctxt, u16 old_tss_sel, 2694 ulong old_tss_base, struct desc_struct *new_desc) 2695 { 2696 struct tss_segment_16 tss_seg; 2697 int ret; 2698 u32 new_tss_base = get_desc_base(new_desc); 2699 2700 ret = linear_read_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg)); 2701 if (ret != X86EMUL_CONTINUE) 2702 return ret; 2703 2704 save_state_to_tss16(ctxt, &tss_seg); 2705 2706 ret = linear_write_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg)); 2707 if (ret != X86EMUL_CONTINUE) 2708 return ret; 2709 2710 ret = linear_read_system(ctxt, new_tss_base, &tss_seg, sizeof(tss_seg)); 2711 if (ret != X86EMUL_CONTINUE) 2712 return ret; 2713 2714 if (old_tss_sel != 0xffff) { 2715 tss_seg.prev_task_link = old_tss_sel; 2716 2717 ret = linear_write_system(ctxt, new_tss_base, 2718 &tss_seg.prev_task_link, 2719 sizeof(tss_seg.prev_task_link)); 2720 if (ret != X86EMUL_CONTINUE) 2721 return ret; 2722 } 2723 2724 return load_state_from_tss16(ctxt, &tss_seg); 2725 } 2726 2727 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, 2728 struct tss_segment_32 *tss) 2729 { 2730 /* CR3 and ldt selector are not saved intentionally */ 2731 tss->eip = ctxt->_eip; 2732 tss->eflags = ctxt->eflags; 2733 tss->eax = reg_read(ctxt, VCPU_REGS_RAX); 2734 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX); 2735 tss->edx = reg_read(ctxt, VCPU_REGS_RDX); 2736 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX); 2737 tss->esp = reg_read(ctxt, VCPU_REGS_RSP); 2738 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP); 2739 tss->esi = reg_read(ctxt, VCPU_REGS_RSI); 2740 tss->edi = reg_read(ctxt, VCPU_REGS_RDI); 2741 2742 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 2743 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 2744 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 2745 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 2746 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS); 2747 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS); 2748 } 2749 2750 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, 2751 struct tss_segment_32 *tss) 2752 { 2753 int ret; 2754 u8 cpl; 2755 2756 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3)) 2757 return emulate_gp(ctxt, 0); 2758 ctxt->_eip = tss->eip; 2759 ctxt->eflags = tss->eflags | 2; 2760 2761 /* General purpose registers */ 2762 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax; 2763 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx; 2764 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx; 2765 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx; 2766 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp; 2767 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp; 2768 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi; 2769 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi; 2770 2771 /* 2772 * SDM says that segment selectors are loaded before segment 2773 * descriptors. This is important because CPL checks will 2774 * use CS.RPL. 2775 */ 2776 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); 2777 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 2778 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 2779 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 2780 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 2781 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS); 2782 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS); 2783 2784 /* 2785 * If we're switching between Protected Mode and VM86, we need to make 2786 * sure to update the mode before loading the segment descriptors so 2787 * that the selectors are interpreted correctly. 2788 */ 2789 if (ctxt->eflags & X86_EFLAGS_VM) { 2790 ctxt->mode = X86EMUL_MODE_VM86; 2791 cpl = 3; 2792 } else { 2793 ctxt->mode = X86EMUL_MODE_PROT32; 2794 cpl = tss->cs & 3; 2795 } 2796 2797 /* 2798 * Now load segment descriptors. If fault happens at this stage 2799 * it is handled in a context of new task 2800 */ 2801 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, 2802 cpl, X86_TRANSFER_TASK_SWITCH, NULL); 2803 if (ret != X86EMUL_CONTINUE) 2804 return ret; 2805 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, 2806 X86_TRANSFER_TASK_SWITCH, NULL); 2807 if (ret != X86EMUL_CONTINUE) 2808 return ret; 2809 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, 2810 X86_TRANSFER_TASK_SWITCH, NULL); 2811 if (ret != X86EMUL_CONTINUE) 2812 return ret; 2813 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, 2814 X86_TRANSFER_TASK_SWITCH, NULL); 2815 if (ret != X86EMUL_CONTINUE) 2816 return ret; 2817 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, 2818 X86_TRANSFER_TASK_SWITCH, NULL); 2819 if (ret != X86EMUL_CONTINUE) 2820 return ret; 2821 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, 2822 X86_TRANSFER_TASK_SWITCH, NULL); 2823 if (ret != X86EMUL_CONTINUE) 2824 return ret; 2825 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, 2826 X86_TRANSFER_TASK_SWITCH, NULL); 2827 2828 return ret; 2829 } 2830 2831 static int task_switch_32(struct x86_emulate_ctxt *ctxt, u16 old_tss_sel, 2832 ulong old_tss_base, struct desc_struct *new_desc) 2833 { 2834 struct tss_segment_32 tss_seg; 2835 int ret; 2836 u32 new_tss_base = get_desc_base(new_desc); 2837 u32 eip_offset = offsetof(struct tss_segment_32, eip); 2838 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector); 2839 2840 ret = linear_read_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg)); 2841 if (ret != X86EMUL_CONTINUE) 2842 return ret; 2843 2844 save_state_to_tss32(ctxt, &tss_seg); 2845 2846 /* Only GP registers and segment selectors are saved */ 2847 ret = linear_write_system(ctxt, old_tss_base + eip_offset, &tss_seg.eip, 2848 ldt_sel_offset - eip_offset); 2849 if (ret != X86EMUL_CONTINUE) 2850 return ret; 2851 2852 ret = linear_read_system(ctxt, new_tss_base, &tss_seg, sizeof(tss_seg)); 2853 if (ret != X86EMUL_CONTINUE) 2854 return ret; 2855 2856 if (old_tss_sel != 0xffff) { 2857 tss_seg.prev_task_link = old_tss_sel; 2858 2859 ret = linear_write_system(ctxt, new_tss_base, 2860 &tss_seg.prev_task_link, 2861 sizeof(tss_seg.prev_task_link)); 2862 if (ret != X86EMUL_CONTINUE) 2863 return ret; 2864 } 2865 2866 return load_state_from_tss32(ctxt, &tss_seg); 2867 } 2868 2869 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, 2870 u16 tss_selector, int idt_index, int reason, 2871 bool has_error_code, u32 error_code) 2872 { 2873 const struct x86_emulate_ops *ops = ctxt->ops; 2874 struct desc_struct curr_tss_desc, next_tss_desc; 2875 int ret; 2876 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR); 2877 ulong old_tss_base = 2878 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR); 2879 u32 desc_limit; 2880 ulong desc_addr, dr7; 2881 2882 /* FIXME: old_tss_base == ~0 ? */ 2883 2884 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr); 2885 if (ret != X86EMUL_CONTINUE) 2886 return ret; 2887 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr); 2888 if (ret != X86EMUL_CONTINUE) 2889 return ret; 2890 2891 /* FIXME: check that next_tss_desc is tss */ 2892 2893 /* 2894 * Check privileges. The three cases are task switch caused by... 2895 * 2896 * 1. jmp/call/int to task gate: Check against DPL of the task gate 2897 * 2. Exception/IRQ/iret: No check is performed 2898 * 3. jmp/call to TSS/task-gate: No check is performed since the 2899 * hardware checks it before exiting. 2900 */ 2901 if (reason == TASK_SWITCH_GATE) { 2902 if (idt_index != -1) { 2903 /* Software interrupts */ 2904 struct desc_struct task_gate_desc; 2905 int dpl; 2906 2907 ret = read_interrupt_descriptor(ctxt, idt_index, 2908 &task_gate_desc); 2909 if (ret != X86EMUL_CONTINUE) 2910 return ret; 2911 2912 dpl = task_gate_desc.dpl; 2913 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) 2914 return emulate_gp(ctxt, (idt_index << 3) | 0x2); 2915 } 2916 } 2917 2918 desc_limit = desc_limit_scaled(&next_tss_desc); 2919 if (!next_tss_desc.p || 2920 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || 2921 desc_limit < 0x2b)) { 2922 return emulate_ts(ctxt, tss_selector & 0xfffc); 2923 } 2924 2925 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { 2926 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ 2927 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); 2928 } 2929 2930 if (reason == TASK_SWITCH_IRET) 2931 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; 2932 2933 /* set back link to prev task only if NT bit is set in eflags 2934 note that old_tss_sel is not used after this point */ 2935 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) 2936 old_tss_sel = 0xffff; 2937 2938 if (next_tss_desc.type & 8) 2939 ret = task_switch_32(ctxt, old_tss_sel, old_tss_base, &next_tss_desc); 2940 else 2941 ret = task_switch_16(ctxt, old_tss_sel, 2942 old_tss_base, &next_tss_desc); 2943 if (ret != X86EMUL_CONTINUE) 2944 return ret; 2945 2946 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) 2947 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; 2948 2949 if (reason != TASK_SWITCH_IRET) { 2950 next_tss_desc.type |= (1 << 1); /* set busy flag */ 2951 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc); 2952 } 2953 2954 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS); 2955 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR); 2956 2957 if (has_error_code) { 2958 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; 2959 ctxt->lock_prefix = 0; 2960 ctxt->src.val = (unsigned long) error_code; 2961 ret = em_push(ctxt); 2962 } 2963 2964 dr7 = ops->get_dr(ctxt, 7); 2965 ops->set_dr(ctxt, 7, dr7 & ~(DR_LOCAL_ENABLE_MASK | DR_LOCAL_SLOWDOWN)); 2966 2967 return ret; 2968 } 2969 2970 int emulator_task_switch(struct x86_emulate_ctxt *ctxt, 2971 u16 tss_selector, int idt_index, int reason, 2972 bool has_error_code, u32 error_code) 2973 { 2974 int rc; 2975 2976 invalidate_registers(ctxt); 2977 ctxt->_eip = ctxt->eip; 2978 ctxt->dst.type = OP_NONE; 2979 2980 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason, 2981 has_error_code, error_code); 2982 2983 if (rc == X86EMUL_CONTINUE) { 2984 ctxt->eip = ctxt->_eip; 2985 writeback_registers(ctxt); 2986 } 2987 2988 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 2989 } 2990 2991 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg, 2992 struct operand *op) 2993 { 2994 int df = (ctxt->eflags & X86_EFLAGS_DF) ? -op->count : op->count; 2995 2996 register_address_increment(ctxt, reg, df * op->bytes); 2997 op->addr.mem.ea = register_address(ctxt, reg); 2998 } 2999 3000 static int em_das(struct x86_emulate_ctxt *ctxt) 3001 { 3002 u8 al, old_al; 3003 bool af, cf, old_cf; 3004 3005 cf = ctxt->eflags & X86_EFLAGS_CF; 3006 al = ctxt->dst.val; 3007 3008 old_al = al; 3009 old_cf = cf; 3010 cf = false; 3011 af = ctxt->eflags & X86_EFLAGS_AF; 3012 if ((al & 0x0f) > 9 || af) { 3013 al -= 6; 3014 cf = old_cf | (al >= 250); 3015 af = true; 3016 } else { 3017 af = false; 3018 } 3019 if (old_al > 0x99 || old_cf) { 3020 al -= 0x60; 3021 cf = true; 3022 } 3023 3024 ctxt->dst.val = al; 3025 /* Set PF, ZF, SF */ 3026 ctxt->src.type = OP_IMM; 3027 ctxt->src.val = 0; 3028 ctxt->src.bytes = 1; 3029 em_or(ctxt); 3030 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); 3031 if (cf) 3032 ctxt->eflags |= X86_EFLAGS_CF; 3033 if (af) 3034 ctxt->eflags |= X86_EFLAGS_AF; 3035 return X86EMUL_CONTINUE; 3036 } 3037 3038 static int em_aam(struct x86_emulate_ctxt *ctxt) 3039 { 3040 u8 al, ah; 3041 3042 if (ctxt->src.val == 0) 3043 return emulate_de(ctxt); 3044 3045 al = ctxt->dst.val & 0xff; 3046 ah = al / ctxt->src.val; 3047 al %= ctxt->src.val; 3048 3049 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8); 3050 3051 /* Set PF, ZF, SF */ 3052 ctxt->src.type = OP_IMM; 3053 ctxt->src.val = 0; 3054 ctxt->src.bytes = 1; 3055 em_or(ctxt); 3056 3057 return X86EMUL_CONTINUE; 3058 } 3059 3060 static int em_aad(struct x86_emulate_ctxt *ctxt) 3061 { 3062 u8 al = ctxt->dst.val & 0xff; 3063 u8 ah = (ctxt->dst.val >> 8) & 0xff; 3064 3065 al = (al + (ah * ctxt->src.val)) & 0xff; 3066 3067 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al; 3068 3069 /* Set PF, ZF, SF */ 3070 ctxt->src.type = OP_IMM; 3071 ctxt->src.val = 0; 3072 ctxt->src.bytes = 1; 3073 em_or(ctxt); 3074 3075 return X86EMUL_CONTINUE; 3076 } 3077 3078 static int em_call(struct x86_emulate_ctxt *ctxt) 3079 { 3080 int rc; 3081 long rel = ctxt->src.val; 3082 3083 ctxt->src.val = (unsigned long)ctxt->_eip; 3084 rc = jmp_rel(ctxt, rel); 3085 if (rc != X86EMUL_CONTINUE) 3086 return rc; 3087 return em_push(ctxt); 3088 } 3089 3090 static int em_call_far(struct x86_emulate_ctxt *ctxt) 3091 { 3092 u16 sel, old_cs; 3093 ulong old_eip; 3094 int rc; 3095 struct desc_struct old_desc, new_desc; 3096 const struct x86_emulate_ops *ops = ctxt->ops; 3097 int cpl = ctxt->ops->cpl(ctxt); 3098 enum x86emul_mode prev_mode = ctxt->mode; 3099 3100 old_eip = ctxt->_eip; 3101 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS); 3102 3103 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 3104 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, 3105 X86_TRANSFER_CALL_JMP, &new_desc); 3106 if (rc != X86EMUL_CONTINUE) 3107 return rc; 3108 3109 rc = assign_eip_far(ctxt, ctxt->src.val); 3110 if (rc != X86EMUL_CONTINUE) 3111 goto fail; 3112 3113 ctxt->src.val = old_cs; 3114 rc = em_push(ctxt); 3115 if (rc != X86EMUL_CONTINUE) 3116 goto fail; 3117 3118 ctxt->src.val = old_eip; 3119 rc = em_push(ctxt); 3120 /* If we failed, we tainted the memory, but the very least we should 3121 restore cs */ 3122 if (rc != X86EMUL_CONTINUE) { 3123 pr_warn_once("faulting far call emulation tainted memory\n"); 3124 goto fail; 3125 } 3126 return rc; 3127 fail: 3128 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS); 3129 ctxt->mode = prev_mode; 3130 return rc; 3131 3132 } 3133 3134 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) 3135 { 3136 int rc; 3137 unsigned long eip = 0; 3138 3139 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 3140 if (rc != X86EMUL_CONTINUE) 3141 return rc; 3142 rc = assign_eip_near(ctxt, eip); 3143 if (rc != X86EMUL_CONTINUE) 3144 return rc; 3145 rsp_increment(ctxt, ctxt->src.val); 3146 return X86EMUL_CONTINUE; 3147 } 3148 3149 static int em_xchg(struct x86_emulate_ctxt *ctxt) 3150 { 3151 /* Write back the register source. */ 3152 ctxt->src.val = ctxt->dst.val; 3153 write_register_operand(&ctxt->src); 3154 3155 /* Write back the memory destination with implicit LOCK prefix. */ 3156 ctxt->dst.val = ctxt->src.orig_val; 3157 ctxt->lock_prefix = 1; 3158 return X86EMUL_CONTINUE; 3159 } 3160 3161 static int em_imul_3op(struct x86_emulate_ctxt *ctxt) 3162 { 3163 ctxt->dst.val = ctxt->src2.val; 3164 return em_imul(ctxt); 3165 } 3166 3167 static int em_cwd(struct x86_emulate_ctxt *ctxt) 3168 { 3169 ctxt->dst.type = OP_REG; 3170 ctxt->dst.bytes = ctxt->src.bytes; 3171 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 3172 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1); 3173 3174 return X86EMUL_CONTINUE; 3175 } 3176 3177 static int em_rdpid(struct x86_emulate_ctxt *ctxt) 3178 { 3179 u64 tsc_aux = 0; 3180 3181 if (!ctxt->ops->guest_has_rdpid(ctxt)) 3182 return emulate_ud(ctxt); 3183 3184 ctxt->ops->get_msr(ctxt, MSR_TSC_AUX, &tsc_aux); 3185 ctxt->dst.val = tsc_aux; 3186 return X86EMUL_CONTINUE; 3187 } 3188 3189 static int em_rdtsc(struct x86_emulate_ctxt *ctxt) 3190 { 3191 u64 tsc = 0; 3192 3193 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc); 3194 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc; 3195 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32; 3196 return X86EMUL_CONTINUE; 3197 } 3198 3199 static int em_rdpmc(struct x86_emulate_ctxt *ctxt) 3200 { 3201 u64 pmc; 3202 3203 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc)) 3204 return emulate_gp(ctxt, 0); 3205 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc; 3206 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32; 3207 return X86EMUL_CONTINUE; 3208 } 3209 3210 static int em_mov(struct x86_emulate_ctxt *ctxt) 3211 { 3212 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr)); 3213 return X86EMUL_CONTINUE; 3214 } 3215 3216 static int em_movbe(struct x86_emulate_ctxt *ctxt) 3217 { 3218 u16 tmp; 3219 3220 if (!ctxt->ops->guest_has_movbe(ctxt)) 3221 return emulate_ud(ctxt); 3222 3223 switch (ctxt->op_bytes) { 3224 case 2: 3225 /* 3226 * From MOVBE definition: "...When the operand size is 16 bits, 3227 * the upper word of the destination register remains unchanged 3228 * ..." 3229 * 3230 * Both casting ->valptr and ->val to u16 breaks strict aliasing 3231 * rules so we have to do the operation almost per hand. 3232 */ 3233 tmp = (u16)ctxt->src.val; 3234 ctxt->dst.val &= ~0xffffUL; 3235 ctxt->dst.val |= (unsigned long)swab16(tmp); 3236 break; 3237 case 4: 3238 ctxt->dst.val = swab32((u32)ctxt->src.val); 3239 break; 3240 case 8: 3241 ctxt->dst.val = swab64(ctxt->src.val); 3242 break; 3243 default: 3244 BUG(); 3245 } 3246 return X86EMUL_CONTINUE; 3247 } 3248 3249 static int em_cr_write(struct x86_emulate_ctxt *ctxt) 3250 { 3251 int cr_num = ctxt->modrm_reg; 3252 int r; 3253 3254 if (ctxt->ops->set_cr(ctxt, cr_num, ctxt->src.val)) 3255 return emulate_gp(ctxt, 0); 3256 3257 /* Disable writeback. */ 3258 ctxt->dst.type = OP_NONE; 3259 3260 if (cr_num == 0) { 3261 /* 3262 * CR0 write might have updated CR0.PE and/or CR0.PG 3263 * which can affect the cpu's execution mode. 3264 */ 3265 r = emulator_recalc_and_set_mode(ctxt); 3266 if (r != X86EMUL_CONTINUE) 3267 return r; 3268 } 3269 3270 return X86EMUL_CONTINUE; 3271 } 3272 3273 static int em_dr_write(struct x86_emulate_ctxt *ctxt) 3274 { 3275 unsigned long val; 3276 3277 if (ctxt->mode == X86EMUL_MODE_PROT64) 3278 val = ctxt->src.val & ~0ULL; 3279 else 3280 val = ctxt->src.val & ~0U; 3281 3282 /* #UD condition is already handled. */ 3283 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0) 3284 return emulate_gp(ctxt, 0); 3285 3286 /* Disable writeback. */ 3287 ctxt->dst.type = OP_NONE; 3288 return X86EMUL_CONTINUE; 3289 } 3290 3291 static int em_wrmsr(struct x86_emulate_ctxt *ctxt) 3292 { 3293 u64 msr_index = reg_read(ctxt, VCPU_REGS_RCX); 3294 u64 msr_data; 3295 int r; 3296 3297 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX) 3298 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32); 3299 r = ctxt->ops->set_msr_with_filter(ctxt, msr_index, msr_data); 3300 3301 if (r == X86EMUL_PROPAGATE_FAULT) 3302 return emulate_gp(ctxt, 0); 3303 3304 return r; 3305 } 3306 3307 static int em_rdmsr(struct x86_emulate_ctxt *ctxt) 3308 { 3309 u64 msr_index = reg_read(ctxt, VCPU_REGS_RCX); 3310 u64 msr_data; 3311 int r; 3312 3313 r = ctxt->ops->get_msr_with_filter(ctxt, msr_index, &msr_data); 3314 3315 if (r == X86EMUL_PROPAGATE_FAULT) 3316 return emulate_gp(ctxt, 0); 3317 3318 if (r == X86EMUL_CONTINUE) { 3319 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data; 3320 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32; 3321 } 3322 return r; 3323 } 3324 3325 static int em_store_sreg(struct x86_emulate_ctxt *ctxt, int segment) 3326 { 3327 if (segment > VCPU_SREG_GS && 3328 (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) && 3329 ctxt->ops->cpl(ctxt) > 0) 3330 return emulate_gp(ctxt, 0); 3331 3332 ctxt->dst.val = get_segment_selector(ctxt, segment); 3333 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM) 3334 ctxt->dst.bytes = 2; 3335 return X86EMUL_CONTINUE; 3336 } 3337 3338 static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt) 3339 { 3340 if (ctxt->modrm_reg > VCPU_SREG_GS) 3341 return emulate_ud(ctxt); 3342 3343 return em_store_sreg(ctxt, ctxt->modrm_reg); 3344 } 3345 3346 static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt) 3347 { 3348 u16 sel = ctxt->src.val; 3349 3350 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS) 3351 return emulate_ud(ctxt); 3352 3353 if (ctxt->modrm_reg == VCPU_SREG_SS) 3354 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; 3355 3356 /* Disable writeback. */ 3357 ctxt->dst.type = OP_NONE; 3358 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg); 3359 } 3360 3361 static int em_sldt(struct x86_emulate_ctxt *ctxt) 3362 { 3363 return em_store_sreg(ctxt, VCPU_SREG_LDTR); 3364 } 3365 3366 static int em_lldt(struct x86_emulate_ctxt *ctxt) 3367 { 3368 u16 sel = ctxt->src.val; 3369 3370 /* Disable writeback. */ 3371 ctxt->dst.type = OP_NONE; 3372 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR); 3373 } 3374 3375 static int em_str(struct x86_emulate_ctxt *ctxt) 3376 { 3377 return em_store_sreg(ctxt, VCPU_SREG_TR); 3378 } 3379 3380 static int em_ltr(struct x86_emulate_ctxt *ctxt) 3381 { 3382 u16 sel = ctxt->src.val; 3383 3384 /* Disable writeback. */ 3385 ctxt->dst.type = OP_NONE; 3386 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR); 3387 } 3388 3389 static int em_invlpg(struct x86_emulate_ctxt *ctxt) 3390 { 3391 int rc; 3392 ulong linear; 3393 unsigned int max_size; 3394 3395 rc = __linearize(ctxt, ctxt->src.addr.mem, &max_size, 1, ctxt->mode, 3396 &linear, X86EMUL_F_INVLPG); 3397 if (rc == X86EMUL_CONTINUE) 3398 ctxt->ops->invlpg(ctxt, linear); 3399 /* Disable writeback. */ 3400 ctxt->dst.type = OP_NONE; 3401 return X86EMUL_CONTINUE; 3402 } 3403 3404 static int em_clts(struct x86_emulate_ctxt *ctxt) 3405 { 3406 ulong cr0; 3407 3408 cr0 = ctxt->ops->get_cr(ctxt, 0); 3409 cr0 &= ~X86_CR0_TS; 3410 ctxt->ops->set_cr(ctxt, 0, cr0); 3411 return X86EMUL_CONTINUE; 3412 } 3413 3414 static int em_hypercall(struct x86_emulate_ctxt *ctxt) 3415 { 3416 int rc = ctxt->ops->fix_hypercall(ctxt); 3417 3418 if (rc != X86EMUL_CONTINUE) 3419 return rc; 3420 3421 /* Let the processor re-execute the fixed hypercall */ 3422 ctxt->_eip = ctxt->eip; 3423 /* Disable writeback. */ 3424 ctxt->dst.type = OP_NONE; 3425 return X86EMUL_CONTINUE; 3426 } 3427 3428 static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt, 3429 void (*get)(struct x86_emulate_ctxt *ctxt, 3430 struct desc_ptr *ptr)) 3431 { 3432 struct desc_ptr desc_ptr; 3433 3434 if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) && 3435 ctxt->ops->cpl(ctxt) > 0) 3436 return emulate_gp(ctxt, 0); 3437 3438 if (ctxt->mode == X86EMUL_MODE_PROT64) 3439 ctxt->op_bytes = 8; 3440 get(ctxt, &desc_ptr); 3441 if (ctxt->op_bytes == 2) { 3442 ctxt->op_bytes = 4; 3443 desc_ptr.address &= 0x00ffffff; 3444 } 3445 /* Disable writeback. */ 3446 ctxt->dst.type = OP_NONE; 3447 return segmented_write_std(ctxt, ctxt->dst.addr.mem, 3448 &desc_ptr, 2 + ctxt->op_bytes); 3449 } 3450 3451 static int em_sgdt(struct x86_emulate_ctxt *ctxt) 3452 { 3453 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt); 3454 } 3455 3456 static int em_sidt(struct x86_emulate_ctxt *ctxt) 3457 { 3458 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt); 3459 } 3460 3461 static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt) 3462 { 3463 struct desc_ptr desc_ptr; 3464 int rc; 3465 3466 if (ctxt->mode == X86EMUL_MODE_PROT64) 3467 ctxt->op_bytes = 8; 3468 rc = read_descriptor(ctxt, ctxt->src.addr.mem, 3469 &desc_ptr.size, &desc_ptr.address, 3470 ctxt->op_bytes); 3471 if (rc != X86EMUL_CONTINUE) 3472 return rc; 3473 if (ctxt->mode == X86EMUL_MODE_PROT64 && 3474 emul_is_noncanonical_address(desc_ptr.address, ctxt, 3475 X86EMUL_F_DT_LOAD)) 3476 return emulate_gp(ctxt, 0); 3477 if (lgdt) 3478 ctxt->ops->set_gdt(ctxt, &desc_ptr); 3479 else 3480 ctxt->ops->set_idt(ctxt, &desc_ptr); 3481 /* Disable writeback. */ 3482 ctxt->dst.type = OP_NONE; 3483 return X86EMUL_CONTINUE; 3484 } 3485 3486 static int em_lgdt(struct x86_emulate_ctxt *ctxt) 3487 { 3488 return em_lgdt_lidt(ctxt, true); 3489 } 3490 3491 static int em_lidt(struct x86_emulate_ctxt *ctxt) 3492 { 3493 return em_lgdt_lidt(ctxt, false); 3494 } 3495 3496 static int em_smsw(struct x86_emulate_ctxt *ctxt) 3497 { 3498 if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) && 3499 ctxt->ops->cpl(ctxt) > 0) 3500 return emulate_gp(ctxt, 0); 3501 3502 if (ctxt->dst.type == OP_MEM) 3503 ctxt->dst.bytes = 2; 3504 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0); 3505 return X86EMUL_CONTINUE; 3506 } 3507 3508 static int em_lmsw(struct x86_emulate_ctxt *ctxt) 3509 { 3510 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul) 3511 | (ctxt->src.val & 0x0f)); 3512 ctxt->dst.type = OP_NONE; 3513 return X86EMUL_CONTINUE; 3514 } 3515 3516 static int em_loop(struct x86_emulate_ctxt *ctxt) 3517 { 3518 int rc = X86EMUL_CONTINUE; 3519 3520 register_address_increment(ctxt, VCPU_REGS_RCX, -1); 3521 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) && 3522 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags))) 3523 rc = jmp_rel(ctxt, ctxt->src.val); 3524 3525 return rc; 3526 } 3527 3528 static int em_jcxz(struct x86_emulate_ctxt *ctxt) 3529 { 3530 int rc = X86EMUL_CONTINUE; 3531 3532 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) 3533 rc = jmp_rel(ctxt, ctxt->src.val); 3534 3535 return rc; 3536 } 3537 3538 static int em_in(struct x86_emulate_ctxt *ctxt) 3539 { 3540 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val, 3541 &ctxt->dst.val)) 3542 return X86EMUL_IO_NEEDED; 3543 3544 return X86EMUL_CONTINUE; 3545 } 3546 3547 static int em_out(struct x86_emulate_ctxt *ctxt) 3548 { 3549 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val, 3550 &ctxt->src.val, 1); 3551 /* Disable writeback. */ 3552 ctxt->dst.type = OP_NONE; 3553 return X86EMUL_CONTINUE; 3554 } 3555 3556 static int em_cli(struct x86_emulate_ctxt *ctxt) 3557 { 3558 if (emulator_bad_iopl(ctxt)) 3559 return emulate_gp(ctxt, 0); 3560 3561 ctxt->eflags &= ~X86_EFLAGS_IF; 3562 return X86EMUL_CONTINUE; 3563 } 3564 3565 static int em_sti(struct x86_emulate_ctxt *ctxt) 3566 { 3567 if (emulator_bad_iopl(ctxt)) 3568 return emulate_gp(ctxt, 0); 3569 3570 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; 3571 ctxt->eflags |= X86_EFLAGS_IF; 3572 return X86EMUL_CONTINUE; 3573 } 3574 3575 static int em_cpuid(struct x86_emulate_ctxt *ctxt) 3576 { 3577 u32 eax, ebx, ecx, edx; 3578 u64 msr = 0; 3579 3580 ctxt->ops->get_msr(ctxt, MSR_MISC_FEATURES_ENABLES, &msr); 3581 if (msr & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 3582 ctxt->ops->cpl(ctxt)) { 3583 return emulate_gp(ctxt, 0); 3584 } 3585 3586 eax = reg_read(ctxt, VCPU_REGS_RAX); 3587 ecx = reg_read(ctxt, VCPU_REGS_RCX); 3588 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false); 3589 *reg_write(ctxt, VCPU_REGS_RAX) = eax; 3590 *reg_write(ctxt, VCPU_REGS_RBX) = ebx; 3591 *reg_write(ctxt, VCPU_REGS_RCX) = ecx; 3592 *reg_write(ctxt, VCPU_REGS_RDX) = edx; 3593 return X86EMUL_CONTINUE; 3594 } 3595 3596 static int em_sahf(struct x86_emulate_ctxt *ctxt) 3597 { 3598 u32 flags; 3599 3600 flags = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF | 3601 X86_EFLAGS_SF; 3602 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8; 3603 3604 ctxt->eflags &= ~0xffUL; 3605 ctxt->eflags |= flags | X86_EFLAGS_FIXED; 3606 return X86EMUL_CONTINUE; 3607 } 3608 3609 static int em_lahf(struct x86_emulate_ctxt *ctxt) 3610 { 3611 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL; 3612 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8; 3613 return X86EMUL_CONTINUE; 3614 } 3615 3616 static int em_bswap(struct x86_emulate_ctxt *ctxt) 3617 { 3618 switch (ctxt->op_bytes) { 3619 #ifdef CONFIG_X86_64 3620 case 8: 3621 asm("bswap %0" : "+r"(ctxt->dst.val)); 3622 break; 3623 #endif 3624 default: 3625 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val)); 3626 break; 3627 } 3628 return X86EMUL_CONTINUE; 3629 } 3630 3631 static int em_clflush(struct x86_emulate_ctxt *ctxt) 3632 { 3633 /* emulating clflush regardless of cpuid */ 3634 return X86EMUL_CONTINUE; 3635 } 3636 3637 static int em_clflushopt(struct x86_emulate_ctxt *ctxt) 3638 { 3639 /* emulating clflushopt regardless of cpuid */ 3640 return X86EMUL_CONTINUE; 3641 } 3642 3643 static int em_movsxd(struct x86_emulate_ctxt *ctxt) 3644 { 3645 ctxt->dst.val = (s32) ctxt->src.val; 3646 return X86EMUL_CONTINUE; 3647 } 3648 3649 static int check_fxsr(struct x86_emulate_ctxt *ctxt) 3650 { 3651 if (!ctxt->ops->guest_has_fxsr(ctxt)) 3652 return emulate_ud(ctxt); 3653 3654 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 3655 return emulate_nm(ctxt); 3656 3657 /* 3658 * Don't emulate a case that should never be hit, instead of working 3659 * around a lack of fxsave64/fxrstor64 on old compilers. 3660 */ 3661 if (ctxt->mode >= X86EMUL_MODE_PROT64) 3662 return X86EMUL_UNHANDLEABLE; 3663 3664 return X86EMUL_CONTINUE; 3665 } 3666 3667 /* 3668 * Hardware doesn't save and restore XMM 0-7 without CR4.OSFXSR, but does save 3669 * and restore MXCSR. 3670 */ 3671 static size_t __fxstate_size(int nregs) 3672 { 3673 return offsetof(struct fxregs_state, xmm_space[0]) + nregs * 16; 3674 } 3675 3676 static inline size_t fxstate_size(struct x86_emulate_ctxt *ctxt) 3677 { 3678 bool cr4_osfxsr; 3679 if (ctxt->mode == X86EMUL_MODE_PROT64) 3680 return __fxstate_size(16); 3681 3682 cr4_osfxsr = ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR; 3683 return __fxstate_size(cr4_osfxsr ? 8 : 0); 3684 } 3685 3686 /* 3687 * FXSAVE and FXRSTOR have 4 different formats depending on execution mode, 3688 * 1) 16 bit mode 3689 * 2) 32 bit mode 3690 * - like (1), but FIP and FDP (foo) are only 16 bit. At least Intel CPUs 3691 * preserve whole 32 bit values, though, so (1) and (2) are the same wrt. 3692 * save and restore 3693 * 3) 64-bit mode with REX.W prefix 3694 * - like (2), but XMM 8-15 are being saved and restored 3695 * 4) 64-bit mode without REX.W prefix 3696 * - like (3), but FIP and FDP are 64 bit 3697 * 3698 * Emulation uses (3) for (1) and (2) and preserves XMM 8-15 to reach the 3699 * desired result. (4) is not emulated. 3700 * 3701 * Note: Guest and host CPUID.(EAX=07H,ECX=0H):EBX[bit 13] (deprecate FPU CS 3702 * and FPU DS) should match. 3703 */ 3704 static int em_fxsave(struct x86_emulate_ctxt *ctxt) 3705 { 3706 struct fxregs_state fx_state; 3707 int rc; 3708 3709 rc = check_fxsr(ctxt); 3710 if (rc != X86EMUL_CONTINUE) 3711 return rc; 3712 3713 kvm_fpu_get(); 3714 3715 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_state)); 3716 3717 kvm_fpu_put(); 3718 3719 if (rc != X86EMUL_CONTINUE) 3720 return rc; 3721 3722 return segmented_write_std(ctxt, ctxt->memop.addr.mem, &fx_state, 3723 fxstate_size(ctxt)); 3724 } 3725 3726 /* 3727 * FXRSTOR might restore XMM registers not provided by the guest. Fill 3728 * in the host registers (via FXSAVE) instead, so they won't be modified. 3729 * (preemption has to stay disabled until FXRSTOR). 3730 * 3731 * Use noinline to keep the stack for other functions called by callers small. 3732 */ 3733 static noinline int fxregs_fixup(struct fxregs_state *fx_state, 3734 const size_t used_size) 3735 { 3736 struct fxregs_state fx_tmp; 3737 int rc; 3738 3739 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_tmp)); 3740 memcpy((void *)fx_state + used_size, (void *)&fx_tmp + used_size, 3741 __fxstate_size(16) - used_size); 3742 3743 return rc; 3744 } 3745 3746 static int em_fxrstor(struct x86_emulate_ctxt *ctxt) 3747 { 3748 struct fxregs_state fx_state; 3749 int rc; 3750 size_t size; 3751 3752 rc = check_fxsr(ctxt); 3753 if (rc != X86EMUL_CONTINUE) 3754 return rc; 3755 3756 size = fxstate_size(ctxt); 3757 rc = segmented_read_std(ctxt, ctxt->memop.addr.mem, &fx_state, size); 3758 if (rc != X86EMUL_CONTINUE) 3759 return rc; 3760 3761 kvm_fpu_get(); 3762 3763 if (size < __fxstate_size(16)) { 3764 rc = fxregs_fixup(&fx_state, size); 3765 if (rc != X86EMUL_CONTINUE) 3766 goto out; 3767 } 3768 3769 if (fx_state.mxcsr >> 16) { 3770 rc = emulate_gp(ctxt, 0); 3771 goto out; 3772 } 3773 3774 if (rc == X86EMUL_CONTINUE) 3775 rc = asm_safe("fxrstor %[fx]", : [fx] "m"(fx_state)); 3776 3777 out: 3778 kvm_fpu_put(); 3779 3780 return rc; 3781 } 3782 3783 static int em_xsetbv(struct x86_emulate_ctxt *ctxt) 3784 { 3785 u32 eax, ecx, edx; 3786 3787 if (!(ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSXSAVE)) 3788 return emulate_ud(ctxt); 3789 3790 eax = reg_read(ctxt, VCPU_REGS_RAX); 3791 edx = reg_read(ctxt, VCPU_REGS_RDX); 3792 ecx = reg_read(ctxt, VCPU_REGS_RCX); 3793 3794 if (ctxt->ops->set_xcr(ctxt, ecx, ((u64)edx << 32) | eax)) 3795 return emulate_gp(ctxt, 0); 3796 3797 return X86EMUL_CONTINUE; 3798 } 3799 3800 static bool valid_cr(int nr) 3801 { 3802 switch (nr) { 3803 case 0: 3804 case 2 ... 4: 3805 case 8: 3806 return true; 3807 default: 3808 return false; 3809 } 3810 } 3811 3812 static int check_cr_access(struct x86_emulate_ctxt *ctxt) 3813 { 3814 if (!valid_cr(ctxt->modrm_reg)) 3815 return emulate_ud(ctxt); 3816 3817 return X86EMUL_CONTINUE; 3818 } 3819 3820 static int check_dr_read(struct x86_emulate_ctxt *ctxt) 3821 { 3822 int dr = ctxt->modrm_reg; 3823 u64 cr4; 3824 3825 if (dr > 7) 3826 return emulate_ud(ctxt); 3827 3828 cr4 = ctxt->ops->get_cr(ctxt, 4); 3829 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5)) 3830 return emulate_ud(ctxt); 3831 3832 if (ctxt->ops->get_dr(ctxt, 7) & DR7_GD) { 3833 ulong dr6; 3834 3835 dr6 = ctxt->ops->get_dr(ctxt, 6); 3836 dr6 &= ~DR_TRAP_BITS; 3837 dr6 |= DR6_BD | DR6_ACTIVE_LOW; 3838 ctxt->ops->set_dr(ctxt, 6, dr6); 3839 return emulate_db(ctxt); 3840 } 3841 3842 return X86EMUL_CONTINUE; 3843 } 3844 3845 static int check_dr_write(struct x86_emulate_ctxt *ctxt) 3846 { 3847 u64 new_val = ctxt->src.val64; 3848 int dr = ctxt->modrm_reg; 3849 3850 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL)) 3851 return emulate_gp(ctxt, 0); 3852 3853 return check_dr_read(ctxt); 3854 } 3855 3856 static int check_svme(struct x86_emulate_ctxt *ctxt) 3857 { 3858 u64 efer = 0; 3859 3860 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 3861 3862 if (!(efer & EFER_SVME)) 3863 return emulate_ud(ctxt); 3864 3865 return X86EMUL_CONTINUE; 3866 } 3867 3868 static int check_svme_pa(struct x86_emulate_ctxt *ctxt) 3869 { 3870 u64 rax = reg_read(ctxt, VCPU_REGS_RAX); 3871 3872 /* Valid physical address? */ 3873 if (rax & 0xffff000000000000ULL) 3874 return emulate_gp(ctxt, 0); 3875 3876 return check_svme(ctxt); 3877 } 3878 3879 static int check_rdtsc(struct x86_emulate_ctxt *ctxt) 3880 { 3881 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 3882 3883 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt)) 3884 return emulate_gp(ctxt, 0); 3885 3886 return X86EMUL_CONTINUE; 3887 } 3888 3889 static int check_rdpmc(struct x86_emulate_ctxt *ctxt) 3890 { 3891 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 3892 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX); 3893 3894 /* 3895 * VMware allows access to these Pseduo-PMCs even when read via RDPMC 3896 * in Ring3 when CR4.PCE=0. 3897 */ 3898 if (enable_vmware_backdoor && is_vmware_backdoor_pmc(rcx)) 3899 return X86EMUL_CONTINUE; 3900 3901 /* 3902 * If CR4.PCE is set, the SDM requires CPL=0 or CR0.PE=0. The CR0.PE 3903 * check however is unnecessary because CPL is always 0 outside 3904 * protected mode. 3905 */ 3906 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) || 3907 ctxt->ops->check_rdpmc_early(ctxt, rcx)) 3908 return emulate_gp(ctxt, 0); 3909 3910 return X86EMUL_CONTINUE; 3911 } 3912 3913 static int check_perm_in(struct x86_emulate_ctxt *ctxt) 3914 { 3915 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u); 3916 if (!emulator_io_permitted(ctxt, ctxt->src.val, ctxt->dst.bytes)) 3917 return emulate_gp(ctxt, 0); 3918 3919 return X86EMUL_CONTINUE; 3920 } 3921 3922 static int check_perm_out(struct x86_emulate_ctxt *ctxt) 3923 { 3924 ctxt->src.bytes = min(ctxt->src.bytes, 4u); 3925 if (!emulator_io_permitted(ctxt, ctxt->dst.val, ctxt->src.bytes)) 3926 return emulate_gp(ctxt, 0); 3927 3928 return X86EMUL_CONTINUE; 3929 } 3930 3931 #define D(_y) { .flags = (_y) } 3932 #define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i } 3933 #define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \ 3934 .intercept = x86_intercept_##_i, .check_perm = (_p) } 3935 #define N D(NotImpl) 3936 #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) } 3937 #define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) } 3938 #define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) } 3939 #define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) } 3940 #define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) } 3941 #define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) } 3942 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } 3943 #define II(_f, _e, _i) \ 3944 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i } 3945 #define IIP(_f, _e, _i, _p) \ 3946 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \ 3947 .intercept = x86_intercept_##_i, .check_perm = (_p) } 3948 #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) } 3949 3950 #define D2bv(_f) D((_f) | ByteOp), D(_f) 3951 #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p) 3952 #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) 3953 #define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e) 3954 #define I2bvIP(_f, _e, _i, _p) \ 3955 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p) 3956 3957 #define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \ 3958 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \ 3959 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e) 3960 3961 static const struct opcode group7_rm0[] = { 3962 N, 3963 I(SrcNone | Priv | EmulateOnUD, em_hypercall), 3964 N, N, N, N, N, N, 3965 }; 3966 3967 static const struct opcode group7_rm1[] = { 3968 DI(SrcNone | Priv, monitor), 3969 DI(SrcNone | Priv, mwait), 3970 N, N, N, N, N, N, 3971 }; 3972 3973 static const struct opcode group7_rm2[] = { 3974 N, 3975 II(ImplicitOps | Priv, em_xsetbv, xsetbv), 3976 N, N, N, N, N, N, 3977 }; 3978 3979 static const struct opcode group7_rm3[] = { 3980 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa), 3981 II(SrcNone | Prot | EmulateOnUD, em_hypercall, vmmcall), 3982 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa), 3983 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa), 3984 DIP(SrcNone | Prot | Priv, stgi, check_svme), 3985 DIP(SrcNone | Prot | Priv, clgi, check_svme), 3986 DIP(SrcNone | Prot | Priv, skinit, check_svme), 3987 DIP(SrcNone | Prot | Priv, invlpga, check_svme), 3988 }; 3989 3990 static const struct opcode group7_rm7[] = { 3991 N, 3992 DIP(SrcNone, rdtscp, check_rdtsc), 3993 N, N, N, N, N, N, 3994 }; 3995 3996 static const struct opcode group1[] = { 3997 I(Lock, em_add), 3998 I(Lock | PageTable, em_or), 3999 I(Lock, em_adc), 4000 I(Lock, em_sbb), 4001 I(Lock | PageTable, em_and), 4002 I(Lock, em_sub), 4003 I(Lock, em_xor), 4004 I(NoWrite, em_cmp), 4005 }; 4006 4007 static const struct opcode group1A[] = { 4008 I(DstMem | SrcNone | Mov | Stack | IncSP | TwoMemOp, em_pop), N, N, N, N, N, N, N, 4009 }; 4010 4011 static const struct opcode group2[] = { 4012 I(DstMem | ModRM, em_rol), 4013 I(DstMem | ModRM, em_ror), 4014 I(DstMem | ModRM, em_rcl), 4015 I(DstMem | ModRM, em_rcr), 4016 I(DstMem | ModRM, em_shl), 4017 I(DstMem | ModRM, em_shr), 4018 I(DstMem | ModRM, em_shl), 4019 I(DstMem | ModRM, em_sar), 4020 }; 4021 4022 static const struct opcode group3[] = { 4023 I(DstMem | SrcImm | NoWrite, em_test), 4024 I(DstMem | SrcImm | NoWrite, em_test), 4025 I(DstMem | SrcNone | Lock, em_not), 4026 I(DstMem | SrcNone | Lock, em_neg), 4027 I(DstXacc | Src2Mem, em_mul_ex), 4028 I(DstXacc | Src2Mem, em_imul_ex), 4029 I(DstXacc | Src2Mem, em_div_ex), 4030 I(DstXacc | Src2Mem, em_idiv_ex), 4031 }; 4032 4033 static const struct opcode group4[] = { 4034 I(ByteOp | DstMem | SrcNone | Lock, em_inc), 4035 I(ByteOp | DstMem | SrcNone | Lock, em_dec), 4036 N, N, N, N, N, N, 4037 }; 4038 4039 static const struct opcode group5[] = { 4040 I(DstMem | SrcNone | Lock, em_inc), 4041 I(DstMem | SrcNone | Lock, em_dec), 4042 I(SrcMem | NearBranch | IsBranch | ShadowStack, em_call_near_abs), 4043 I(SrcMemFAddr | ImplicitOps | IsBranch | ShadowStack, em_call_far), 4044 I(SrcMem | NearBranch | IsBranch, em_jmp_abs), 4045 I(SrcMemFAddr | ImplicitOps | IsBranch, em_jmp_far), 4046 I(SrcMem | Stack | TwoMemOp, em_push), D(Undefined), 4047 }; 4048 4049 static const struct opcode group6[] = { 4050 II(Prot | DstMem, em_sldt, sldt), 4051 II(Prot | DstMem, em_str, str), 4052 II(Prot | Priv | SrcMem16, em_lldt, lldt), 4053 II(Prot | Priv | SrcMem16, em_ltr, ltr), 4054 N, N, N, N, 4055 }; 4056 4057 static const struct group_dual group7 = { { 4058 II(Mov | DstMem, em_sgdt, sgdt), 4059 II(Mov | DstMem, em_sidt, sidt), 4060 II(SrcMem | Priv, em_lgdt, lgdt), 4061 II(SrcMem | Priv, em_lidt, lidt), 4062 II(SrcNone | DstMem | Mov, em_smsw, smsw), N, 4063 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), 4064 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg), 4065 }, { 4066 EXT(0, group7_rm0), 4067 EXT(0, group7_rm1), 4068 EXT(0, group7_rm2), 4069 EXT(0, group7_rm3), 4070 II(SrcNone | DstMem | Mov, em_smsw, smsw), N, 4071 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), 4072 EXT(0, group7_rm7), 4073 } }; 4074 4075 static const struct opcode group8[] = { 4076 N, N, N, N, 4077 I(DstMem | SrcImmByte | NoWrite, em_bt), 4078 I(DstMem | SrcImmByte | Lock | PageTable, em_bts), 4079 I(DstMem | SrcImmByte | Lock, em_btr), 4080 I(DstMem | SrcImmByte | Lock | PageTable, em_btc), 4081 }; 4082 4083 /* 4084 * The "memory" destination is actually always a register, since we come 4085 * from the register case of group9. 4086 */ 4087 static const struct gprefix pfx_0f_c7_7 = { 4088 N, N, N, II(DstMem | ModRM | Op3264 | EmulateOnUD, em_rdpid, rdpid), 4089 }; 4090 4091 4092 static const struct group_dual group9 = { { 4093 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N, 4094 }, { 4095 N, N, N, N, N, N, N, 4096 GP(0, &pfx_0f_c7_7), 4097 } }; 4098 4099 static const struct opcode group11[] = { 4100 I(DstMem | SrcImm | Mov | PageTable, em_mov), 4101 X7(D(Undefined)), 4102 }; 4103 4104 static const struct gprefix pfx_0f_ae_7 = { 4105 I(SrcMem | ByteOp, em_clflush), I(SrcMem | ByteOp, em_clflushopt), N, N, 4106 }; 4107 4108 static const struct group_dual group15 = { { 4109 I(ModRM | Aligned16, em_fxsave), 4110 I(ModRM | Aligned16, em_fxrstor), 4111 N, N, N, N, N, GP(0, &pfx_0f_ae_7), 4112 }, { 4113 N, N, N, N, N, N, N, N, 4114 } }; 4115 4116 static const struct gprefix pfx_0f_6f_0f_7f = { 4117 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov), 4118 }; 4119 4120 static const struct instr_dual instr_dual_0f_2b = { 4121 I(0, em_mov), N 4122 }; 4123 4124 static const struct gprefix pfx_0f_2b = { 4125 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N, 4126 }; 4127 4128 static const struct gprefix pfx_0f_10_0f_11 = { 4129 I(Unaligned, em_mov), I(Unaligned, em_mov), N, N, 4130 }; 4131 4132 static const struct gprefix pfx_0f_28_0f_29 = { 4133 I(Aligned, em_mov), I(Aligned, em_mov), N, N, 4134 }; 4135 4136 static const struct gprefix pfx_0f_e7 = { 4137 N, I(Sse, em_mov), N, N, 4138 }; 4139 4140 static const struct escape escape_d9 = { { 4141 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw), 4142 }, { 4143 /* 0xC0 - 0xC7 */ 4144 N, N, N, N, N, N, N, N, 4145 /* 0xC8 - 0xCF */ 4146 N, N, N, N, N, N, N, N, 4147 /* 0xD0 - 0xC7 */ 4148 N, N, N, N, N, N, N, N, 4149 /* 0xD8 - 0xDF */ 4150 N, N, N, N, N, N, N, N, 4151 /* 0xE0 - 0xE7 */ 4152 N, N, N, N, N, N, N, N, 4153 /* 0xE8 - 0xEF */ 4154 N, N, N, N, N, N, N, N, 4155 /* 0xF0 - 0xF7 */ 4156 N, N, N, N, N, N, N, N, 4157 /* 0xF8 - 0xFF */ 4158 N, N, N, N, N, N, N, N, 4159 } }; 4160 4161 static const struct escape escape_db = { { 4162 N, N, N, N, N, N, N, N, 4163 }, { 4164 /* 0xC0 - 0xC7 */ 4165 N, N, N, N, N, N, N, N, 4166 /* 0xC8 - 0xCF */ 4167 N, N, N, N, N, N, N, N, 4168 /* 0xD0 - 0xC7 */ 4169 N, N, N, N, N, N, N, N, 4170 /* 0xD8 - 0xDF */ 4171 N, N, N, N, N, N, N, N, 4172 /* 0xE0 - 0xE7 */ 4173 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N, 4174 /* 0xE8 - 0xEF */ 4175 N, N, N, N, N, N, N, N, 4176 /* 0xF0 - 0xF7 */ 4177 N, N, N, N, N, N, N, N, 4178 /* 0xF8 - 0xFF */ 4179 N, N, N, N, N, N, N, N, 4180 } }; 4181 4182 static const struct escape escape_dd = { { 4183 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw), 4184 }, { 4185 /* 0xC0 - 0xC7 */ 4186 N, N, N, N, N, N, N, N, 4187 /* 0xC8 - 0xCF */ 4188 N, N, N, N, N, N, N, N, 4189 /* 0xD0 - 0xC7 */ 4190 N, N, N, N, N, N, N, N, 4191 /* 0xD8 - 0xDF */ 4192 N, N, N, N, N, N, N, N, 4193 /* 0xE0 - 0xE7 */ 4194 N, N, N, N, N, N, N, N, 4195 /* 0xE8 - 0xEF */ 4196 N, N, N, N, N, N, N, N, 4197 /* 0xF0 - 0xF7 */ 4198 N, N, N, N, N, N, N, N, 4199 /* 0xF8 - 0xFF */ 4200 N, N, N, N, N, N, N, N, 4201 } }; 4202 4203 static const struct instr_dual instr_dual_0f_c3 = { 4204 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N 4205 }; 4206 4207 static const struct mode_dual mode_dual_63 = { 4208 N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd) 4209 }; 4210 4211 static const struct instr_dual instr_dual_8d = { 4212 D(DstReg | SrcMem | ModRM | NoAccess), N 4213 }; 4214 4215 static const struct opcode opcode_table[256] = { 4216 /* 0x00 - 0x07 */ 4217 I6ALU(Lock, em_add), 4218 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg), 4219 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg), 4220 /* 0x08 - 0x0F */ 4221 I6ALU(Lock | PageTable, em_or), 4222 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg), 4223 N, 4224 /* 0x10 - 0x17 */ 4225 I6ALU(Lock, em_adc), 4226 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg), 4227 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg), 4228 /* 0x18 - 0x1F */ 4229 I6ALU(Lock, em_sbb), 4230 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg), 4231 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg), 4232 /* 0x20 - 0x27 */ 4233 I6ALU(Lock | PageTable, em_and), N, N, 4234 /* 0x28 - 0x2F */ 4235 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das), 4236 /* 0x30 - 0x37 */ 4237 I6ALU(Lock, em_xor), N, N, 4238 /* 0x38 - 0x3F */ 4239 I6ALU(NoWrite, em_cmp), N, N, 4240 /* 0x40 - 0x4F */ 4241 X8(I(DstReg, em_inc)), X8(I(DstReg, em_dec)), 4242 /* 0x50 - 0x57 */ 4243 X8(I(SrcReg | Stack, em_push)), 4244 /* 0x58 - 0x5F */ 4245 X8(I(DstReg | Stack, em_pop)), 4246 /* 0x60 - 0x67 */ 4247 I(ImplicitOps | Stack | No64, em_pusha), 4248 I(ImplicitOps | Stack | No64, em_popa), 4249 N, MD(ModRM, &mode_dual_63), 4250 N, N, N, N, 4251 /* 0x68 - 0x6F */ 4252 I(SrcImm | Mov | Stack, em_push), 4253 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), 4254 I(SrcImmByte | Mov | Stack, em_push), 4255 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), 4256 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */ 4257 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */ 4258 /* 0x70 - 0x7F */ 4259 X16(D(SrcImmByte | NearBranch | IsBranch)), 4260 /* 0x80 - 0x87 */ 4261 G(ByteOp | DstMem | SrcImm, group1), 4262 G(DstMem | SrcImm, group1), 4263 G(ByteOp | DstMem | SrcImm | No64, group1), 4264 G(DstMem | SrcImmByte, group1), 4265 I2bv(DstMem | SrcReg | ModRM | NoWrite, em_test), 4266 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg), 4267 /* 0x88 - 0x8F */ 4268 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov), 4269 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov), 4270 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg), 4271 ID(0, &instr_dual_8d), 4272 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm), 4273 G(0, group1A), 4274 /* 0x90 - 0x97 */ 4275 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)), 4276 /* 0x98 - 0x9F */ 4277 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), 4278 I(SrcImmFAddr | No64 | IsBranch | ShadowStack, em_call_far), N, 4279 II(ImplicitOps | Stack, em_pushf, pushf), 4280 II(ImplicitOps | Stack, em_popf, popf), 4281 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf), 4282 /* 0xA0 - 0xA7 */ 4283 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), 4284 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov), 4285 I2bv(SrcSI | DstDI | Mov | String | TwoMemOp, em_mov), 4286 I2bv(SrcSI | DstDI | String | NoWrite | TwoMemOp, em_cmp_r), 4287 /* 0xA8 - 0xAF */ 4288 I2bv(DstAcc | SrcImm | NoWrite, em_test), 4289 I2bv(SrcAcc | DstDI | Mov | String, em_mov), 4290 I2bv(SrcSI | DstAcc | Mov | String, em_mov), 4291 I2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r), 4292 /* 0xB0 - 0xB7 */ 4293 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), 4294 /* 0xB8 - 0xBF */ 4295 X8(I(DstReg | SrcImm64 | Mov, em_mov)), 4296 /* 0xC0 - 0xC7 */ 4297 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2), 4298 I(ImplicitOps | NearBranch | SrcImmU16 | IsBranch | ShadowStack, em_ret_near_imm), 4299 I(ImplicitOps | NearBranch | IsBranch | ShadowStack, em_ret), 4300 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg), 4301 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg), 4302 G(ByteOp, group11), G(0, group11), 4303 /* 0xC8 - 0xCF */ 4304 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), 4305 I(Stack, em_leave), 4306 I(ImplicitOps | SrcImmU16 | IsBranch | ShadowStack, em_ret_far_imm), 4307 I(ImplicitOps | IsBranch | ShadowStack, em_ret_far), 4308 D(ImplicitOps | IsBranch), DI(SrcImmByte | IsBranch | ShadowStack, intn), 4309 D(ImplicitOps | No64 | IsBranch), 4310 II(ImplicitOps | IsBranch | ShadowStack, em_iret, iret), 4311 /* 0xD0 - 0xD7 */ 4312 G(Src2One | ByteOp, group2), G(Src2One, group2), 4313 G(Src2CL | ByteOp, group2), G(Src2CL, group2), 4314 I(DstAcc | SrcImmUByte | No64, em_aam), 4315 I(DstAcc | SrcImmUByte | No64, em_aad), 4316 I(DstAcc | ByteOp | No64, em_salc), 4317 I(DstAcc | SrcXLat | ByteOp, em_mov), 4318 /* 0xD8 - 0xDF */ 4319 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N, 4320 /* 0xE0 - 0xE7 */ 4321 X3(I(SrcImmByte | NearBranch | IsBranch, em_loop)), 4322 I(SrcImmByte | NearBranch | IsBranch, em_jcxz), 4323 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in), 4324 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out), 4325 /* 0xE8 - 0xEF */ 4326 I(SrcImm | NearBranch | IsBranch | ShadowStack, em_call), 4327 D(SrcImm | ImplicitOps | NearBranch | IsBranch), 4328 I(SrcImmFAddr | No64 | IsBranch, em_jmp_far), 4329 D(SrcImmByte | ImplicitOps | NearBranch | IsBranch), 4330 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in), 4331 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out), 4332 /* 0xF0 - 0xF7 */ 4333 N, DI(ImplicitOps, icebp), N, N, 4334 DI(ImplicitOps | Priv, hlt), D(ImplicitOps), 4335 G(ByteOp, group3), G(0, group3), 4336 /* 0xF8 - 0xFF */ 4337 D(ImplicitOps), D(ImplicitOps), 4338 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti), 4339 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), 4340 }; 4341 4342 static const struct opcode twobyte_table[256] = { 4343 /* 0x00 - 0x0F */ 4344 G(0, group6), GD(0, &group7), N, N, 4345 N, I(ImplicitOps | EmulateOnUD | IsBranch | ShadowStack, em_syscall), 4346 II(ImplicitOps | Priv, em_clts, clts), N, 4347 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, 4348 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N, 4349 /* 0x10 - 0x1F */ 4350 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_10_0f_11), 4351 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_10_0f_11), 4352 N, N, N, N, N, N, 4353 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 4 * prefetch + 4 * reserved NOP */ 4354 D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N, 4355 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */ 4356 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */ 4357 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */ 4358 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* NOP + 7 * reserved NOP */ 4359 /* 0x20 - 0x2F */ 4360 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_access), 4361 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read), 4362 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write, 4363 check_cr_access), 4364 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write, 4365 check_dr_write), 4366 N, N, N, N, 4367 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29), 4368 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29), 4369 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b), 4370 N, N, N, N, 4371 /* 0x30 - 0x3F */ 4372 II(ImplicitOps | Priv, em_wrmsr, wrmsr), 4373 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc), 4374 II(ImplicitOps | Priv, em_rdmsr, rdmsr), 4375 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc), 4376 I(ImplicitOps | EmulateOnUD | IsBranch | ShadowStack, em_sysenter), 4377 I(ImplicitOps | Priv | EmulateOnUD | IsBranch | ShadowStack, em_sysexit), 4378 N, N, 4379 N, N, N, N, N, N, N, N, 4380 /* 0x40 - 0x4F */ 4381 X16(D(DstReg | SrcMem | ModRM)), 4382 /* 0x50 - 0x5F */ 4383 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 4384 /* 0x60 - 0x6F */ 4385 N, N, N, N, 4386 N, N, N, N, 4387 N, N, N, N, 4388 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f), 4389 /* 0x70 - 0x7F */ 4390 N, N, N, N, 4391 N, N, N, N, 4392 N, N, N, N, 4393 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f), 4394 /* 0x80 - 0x8F */ 4395 X16(D(SrcImm | NearBranch | IsBranch)), 4396 /* 0x90 - 0x9F */ 4397 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), 4398 /* 0xA0 - 0xA7 */ 4399 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg), 4400 II(ImplicitOps, em_cpuid, cpuid), 4401 I(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt), 4402 I(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld), 4403 I(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N, 4404 /* 0xA8 - 0xAF */ 4405 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg), 4406 II(EmulateOnUD | ImplicitOps, em_rsm, rsm), 4407 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts), 4408 I(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd), 4409 I(DstMem | SrcReg | Src2CL | ModRM, em_shrd), 4410 GD(0, &group15), I(DstReg | SrcMem | ModRM, em_imul), 4411 /* 0xB0 - 0xB7 */ 4412 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg), 4413 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg), 4414 I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr), 4415 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg), 4416 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg), 4417 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 4418 /* 0xB8 - 0xBF */ 4419 N, N, 4420 G(BitOp, group8), 4421 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc), 4422 I(DstReg | SrcMem | ModRM, em_bsf_c), 4423 I(DstReg | SrcMem | ModRM, em_bsr_c), 4424 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 4425 /* 0xC0 - 0xC7 */ 4426 I2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd), 4427 N, ID(0, &instr_dual_0f_c3), 4428 N, N, N, GD(0, &group9), 4429 /* 0xC8 - 0xCF */ 4430 X8(I(DstReg, em_bswap)), 4431 /* 0xD0 - 0xDF */ 4432 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 4433 /* 0xE0 - 0xEF */ 4434 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7), 4435 N, N, N, N, N, N, N, N, 4436 /* 0xF0 - 0xFF */ 4437 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N 4438 }; 4439 4440 static const struct instr_dual instr_dual_0f_38_f0 = { 4441 I(DstReg | SrcMem | Mov, em_movbe), N 4442 }; 4443 4444 static const struct instr_dual instr_dual_0f_38_f1 = { 4445 I(DstMem | SrcReg | Mov, em_movbe), N 4446 }; 4447 4448 static const struct gprefix three_byte_0f_38_f0 = { 4449 ID(0, &instr_dual_0f_38_f0), ID(0, &instr_dual_0f_38_f0), N, N 4450 }; 4451 4452 static const struct gprefix three_byte_0f_38_f1 = { 4453 ID(0, &instr_dual_0f_38_f1), ID(0, &instr_dual_0f_38_f1), N, N 4454 }; 4455 4456 /* 4457 * Insns below are selected by the prefix which indexed by the third opcode 4458 * byte. 4459 */ 4460 static const struct opcode opcode_map_0f_38[256] = { 4461 /* 0x00 - 0x7f */ 4462 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), 4463 /* 0x80 - 0xef */ 4464 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), 4465 /* 0xf0 - 0xf1 */ 4466 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0), 4467 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1), 4468 /* 0xf2 - 0xff */ 4469 N, N, X4(N), X8(N) 4470 }; 4471 4472 #undef D 4473 #undef N 4474 #undef G 4475 #undef GD 4476 #undef I 4477 #undef GP 4478 #undef EXT 4479 #undef MD 4480 #undef ID 4481 4482 #undef D2bv 4483 #undef D2bvIP 4484 #undef I2bv 4485 #undef I2bvIP 4486 #undef I6ALU 4487 4488 static bool is_shstk_instruction(struct x86_emulate_ctxt *ctxt) 4489 { 4490 return ctxt->d & ShadowStack; 4491 } 4492 4493 static bool is_ibt_instruction(struct x86_emulate_ctxt *ctxt) 4494 { 4495 u64 flags = ctxt->d; 4496 4497 if (!(flags & IsBranch)) 4498 return false; 4499 4500 /* 4501 * All far JMPs and CALLs (including SYSCALL, SYSENTER, and INTn) are 4502 * indirect and thus affect IBT state. All far RETs (including SYSEXIT 4503 * and IRET) are protected via Shadow Stacks and thus don't affect IBT 4504 * state. IRET #GPs when returning to virtual-8086 and IBT or SHSTK is 4505 * enabled, but that should be handled by IRET emulation (in the very 4506 * unlikely scenario that KVM adds support for fully emulating IRET). 4507 */ 4508 if (!(flags & NearBranch)) 4509 return ctxt->execute != em_iret && 4510 ctxt->execute != em_ret_far && 4511 ctxt->execute != em_ret_far_imm && 4512 ctxt->execute != em_sysexit; 4513 4514 switch (flags & SrcMask) { 4515 case SrcReg: 4516 case SrcMem: 4517 case SrcMem16: 4518 case SrcMem32: 4519 return true; 4520 case SrcMemFAddr: 4521 case SrcImmFAddr: 4522 /* Far branches should be handled above. */ 4523 WARN_ON_ONCE(1); 4524 return true; 4525 case SrcNone: 4526 case SrcImm: 4527 case SrcImmByte: 4528 /* 4529 * Note, ImmU16 is used only for the stack adjustment operand on ENTER 4530 * and RET instructions. ENTER isn't a branch and RET FAR is handled 4531 * by the NearBranch check above. RET itself isn't an indirect branch. 4532 */ 4533 case SrcImmU16: 4534 return false; 4535 default: 4536 WARN_ONCE(1, "Unexpected Src operand '%llx' on branch", 4537 flags & SrcMask); 4538 return false; 4539 } 4540 } 4541 4542 static unsigned imm_size(struct x86_emulate_ctxt *ctxt) 4543 { 4544 unsigned size; 4545 4546 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4547 if (size == 8) 4548 size = 4; 4549 return size; 4550 } 4551 4552 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, 4553 unsigned size, bool sign_extension) 4554 { 4555 int rc = X86EMUL_CONTINUE; 4556 4557 op->type = OP_IMM; 4558 op->bytes = size; 4559 op->addr.mem.ea = ctxt->_eip; 4560 /* NB. Immediates are sign-extended as necessary. */ 4561 switch (op->bytes) { 4562 case 1: 4563 op->val = insn_fetch(s8, ctxt); 4564 break; 4565 case 2: 4566 op->val = insn_fetch(s16, ctxt); 4567 break; 4568 case 4: 4569 op->val = insn_fetch(s32, ctxt); 4570 break; 4571 case 8: 4572 op->val = insn_fetch(s64, ctxt); 4573 break; 4574 } 4575 if (!sign_extension) { 4576 switch (op->bytes) { 4577 case 1: 4578 op->val &= 0xff; 4579 break; 4580 case 2: 4581 op->val &= 0xffff; 4582 break; 4583 case 4: 4584 op->val &= 0xffffffff; 4585 break; 4586 } 4587 } 4588 done: 4589 return rc; 4590 } 4591 4592 static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op, 4593 unsigned d) 4594 { 4595 int rc = X86EMUL_CONTINUE; 4596 4597 switch (d) { 4598 case OpReg: 4599 decode_register_operand(ctxt, op); 4600 break; 4601 case OpImmUByte: 4602 rc = decode_imm(ctxt, op, 1, false); 4603 break; 4604 case OpMem: 4605 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4606 mem_common: 4607 *op = ctxt->memop; 4608 ctxt->memopp = op; 4609 if (ctxt->d & BitOp) 4610 fetch_bit_operand(ctxt); 4611 op->orig_val = op->val; 4612 break; 4613 case OpMem64: 4614 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8; 4615 goto mem_common; 4616 case OpAcc: 4617 op->type = OP_REG; 4618 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4619 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 4620 fetch_register_operand(op); 4621 op->orig_val = op->val; 4622 break; 4623 case OpAccLo: 4624 op->type = OP_REG; 4625 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes; 4626 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 4627 fetch_register_operand(op); 4628 op->orig_val = op->val; 4629 break; 4630 case OpAccHi: 4631 if (ctxt->d & ByteOp) { 4632 op->type = OP_NONE; 4633 break; 4634 } 4635 op->type = OP_REG; 4636 op->bytes = ctxt->op_bytes; 4637 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 4638 fetch_register_operand(op); 4639 op->orig_val = op->val; 4640 break; 4641 case OpDI: 4642 op->type = OP_MEM; 4643 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4644 op->addr.mem.ea = 4645 register_address(ctxt, VCPU_REGS_RDI); 4646 op->addr.mem.seg = VCPU_SREG_ES; 4647 op->val = 0; 4648 op->count = 1; 4649 break; 4650 case OpDX: 4651 op->type = OP_REG; 4652 op->bytes = 2; 4653 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 4654 fetch_register_operand(op); 4655 break; 4656 case OpCL: 4657 op->type = OP_IMM; 4658 op->bytes = 1; 4659 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff; 4660 break; 4661 case OpImmByte: 4662 rc = decode_imm(ctxt, op, 1, true); 4663 break; 4664 case OpOne: 4665 op->type = OP_IMM; 4666 op->bytes = 1; 4667 op->val = 1; 4668 break; 4669 case OpImm: 4670 rc = decode_imm(ctxt, op, imm_size(ctxt), true); 4671 break; 4672 case OpImm64: 4673 rc = decode_imm(ctxt, op, ctxt->op_bytes, true); 4674 break; 4675 case OpMem8: 4676 ctxt->memop.bytes = 1; 4677 if (ctxt->memop.type == OP_REG) { 4678 ctxt->memop.addr.reg = decode_register(ctxt, 4679 ctxt->modrm_rm, true); 4680 fetch_register_operand(&ctxt->memop); 4681 } 4682 goto mem_common; 4683 case OpMem16: 4684 ctxt->memop.bytes = 2; 4685 goto mem_common; 4686 case OpMem32: 4687 ctxt->memop.bytes = 4; 4688 goto mem_common; 4689 case OpImmU16: 4690 rc = decode_imm(ctxt, op, 2, false); 4691 break; 4692 case OpImmU: 4693 rc = decode_imm(ctxt, op, imm_size(ctxt), false); 4694 break; 4695 case OpSI: 4696 op->type = OP_MEM; 4697 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4698 op->addr.mem.ea = 4699 register_address(ctxt, VCPU_REGS_RSI); 4700 op->addr.mem.seg = ctxt->seg_override; 4701 op->val = 0; 4702 op->count = 1; 4703 break; 4704 case OpXLat: 4705 op->type = OP_MEM; 4706 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4707 op->addr.mem.ea = 4708 address_mask(ctxt, 4709 reg_read(ctxt, VCPU_REGS_RBX) + 4710 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff)); 4711 op->addr.mem.seg = ctxt->seg_override; 4712 op->val = 0; 4713 break; 4714 case OpImmFAddr: 4715 op->type = OP_IMM; 4716 op->addr.mem.ea = ctxt->_eip; 4717 op->bytes = ctxt->op_bytes + 2; 4718 insn_fetch_arr(op->valptr, op->bytes, ctxt); 4719 break; 4720 case OpMemFAddr: 4721 ctxt->memop.bytes = ctxt->op_bytes + 2; 4722 goto mem_common; 4723 case OpES: 4724 op->type = OP_IMM; 4725 op->val = VCPU_SREG_ES; 4726 break; 4727 case OpCS: 4728 op->type = OP_IMM; 4729 op->val = VCPU_SREG_CS; 4730 break; 4731 case OpSS: 4732 op->type = OP_IMM; 4733 op->val = VCPU_SREG_SS; 4734 break; 4735 case OpDS: 4736 op->type = OP_IMM; 4737 op->val = VCPU_SREG_DS; 4738 break; 4739 case OpFS: 4740 op->type = OP_IMM; 4741 op->val = VCPU_SREG_FS; 4742 break; 4743 case OpGS: 4744 op->type = OP_IMM; 4745 op->val = VCPU_SREG_GS; 4746 break; 4747 case OpImplicit: 4748 /* Special instructions do their own operand decoding. */ 4749 default: 4750 op->type = OP_NONE; /* Disable writeback. */ 4751 break; 4752 } 4753 4754 done: 4755 return rc; 4756 } 4757 4758 int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len, int emulation_type) 4759 { 4760 int rc = X86EMUL_CONTINUE; 4761 int mode = ctxt->mode; 4762 int def_op_bytes, def_ad_bytes, goffset, simd_prefix; 4763 bool op_prefix = false; 4764 bool has_seg_override = false; 4765 struct opcode opcode; 4766 u16 dummy; 4767 struct desc_struct desc; 4768 4769 ctxt->memop.type = OP_NONE; 4770 ctxt->memopp = NULL; 4771 ctxt->_eip = ctxt->eip; 4772 ctxt->fetch.ptr = ctxt->fetch.data; 4773 ctxt->fetch.end = ctxt->fetch.data + insn_len; 4774 ctxt->opcode_len = 1; 4775 ctxt->intercept = x86_intercept_none; 4776 if (insn_len > 0) 4777 memcpy(ctxt->fetch.data, insn, insn_len); 4778 else { 4779 rc = __do_insn_fetch_bytes(ctxt, 1); 4780 if (rc != X86EMUL_CONTINUE) 4781 goto done; 4782 } 4783 4784 switch (mode) { 4785 case X86EMUL_MODE_REAL: 4786 case X86EMUL_MODE_VM86: 4787 def_op_bytes = def_ad_bytes = 2; 4788 ctxt->ops->get_segment(ctxt, &dummy, &desc, NULL, VCPU_SREG_CS); 4789 if (desc.d) 4790 def_op_bytes = def_ad_bytes = 4; 4791 break; 4792 case X86EMUL_MODE_PROT16: 4793 def_op_bytes = def_ad_bytes = 2; 4794 break; 4795 case X86EMUL_MODE_PROT32: 4796 def_op_bytes = def_ad_bytes = 4; 4797 break; 4798 #ifdef CONFIG_X86_64 4799 case X86EMUL_MODE_PROT64: 4800 def_op_bytes = 4; 4801 def_ad_bytes = 8; 4802 break; 4803 #endif 4804 default: 4805 return EMULATION_FAILED; 4806 } 4807 4808 ctxt->op_bytes = def_op_bytes; 4809 ctxt->ad_bytes = def_ad_bytes; 4810 4811 /* Legacy prefixes. */ 4812 for (;;) { 4813 switch (ctxt->b = insn_fetch(u8, ctxt)) { 4814 case 0x66: /* operand-size override */ 4815 op_prefix = true; 4816 /* switch between 2/4 bytes */ 4817 ctxt->op_bytes = def_op_bytes ^ 6; 4818 break; 4819 case 0x67: /* address-size override */ 4820 if (mode == X86EMUL_MODE_PROT64) 4821 /* switch between 4/8 bytes */ 4822 ctxt->ad_bytes = def_ad_bytes ^ 12; 4823 else 4824 /* switch between 2/4 bytes */ 4825 ctxt->ad_bytes = def_ad_bytes ^ 6; 4826 break; 4827 case 0x26: /* ES override */ 4828 has_seg_override = true; 4829 ctxt->seg_override = VCPU_SREG_ES; 4830 break; 4831 case 0x2e: /* CS override */ 4832 has_seg_override = true; 4833 ctxt->seg_override = VCPU_SREG_CS; 4834 break; 4835 case 0x36: /* SS override */ 4836 has_seg_override = true; 4837 ctxt->seg_override = VCPU_SREG_SS; 4838 break; 4839 case 0x3e: /* DS override */ 4840 has_seg_override = true; 4841 ctxt->seg_override = VCPU_SREG_DS; 4842 break; 4843 case 0x64: /* FS override */ 4844 has_seg_override = true; 4845 ctxt->seg_override = VCPU_SREG_FS; 4846 break; 4847 case 0x65: /* GS override */ 4848 has_seg_override = true; 4849 ctxt->seg_override = VCPU_SREG_GS; 4850 break; 4851 case 0x40 ... 0x4f: /* REX */ 4852 if (mode != X86EMUL_MODE_PROT64) 4853 goto done_prefixes; 4854 ctxt->rex_prefix = ctxt->b; 4855 continue; 4856 case 0xf0: /* LOCK */ 4857 ctxt->lock_prefix = 1; 4858 break; 4859 case 0xf2: /* REPNE/REPNZ */ 4860 case 0xf3: /* REP/REPE/REPZ */ 4861 ctxt->rep_prefix = ctxt->b; 4862 break; 4863 default: 4864 goto done_prefixes; 4865 } 4866 4867 /* Any legacy prefix after a REX prefix nullifies its effect. */ 4868 4869 ctxt->rex_prefix = 0; 4870 } 4871 4872 done_prefixes: 4873 4874 /* REX prefix. */ 4875 if (ctxt->rex_prefix & 8) 4876 ctxt->op_bytes = 8; /* REX.W */ 4877 4878 /* Opcode byte(s). */ 4879 opcode = opcode_table[ctxt->b]; 4880 /* Two-byte opcode? */ 4881 if (ctxt->b == 0x0f) { 4882 ctxt->opcode_len = 2; 4883 ctxt->b = insn_fetch(u8, ctxt); 4884 opcode = twobyte_table[ctxt->b]; 4885 4886 /* 0F_38 opcode map */ 4887 if (ctxt->b == 0x38) { 4888 ctxt->opcode_len = 3; 4889 ctxt->b = insn_fetch(u8, ctxt); 4890 opcode = opcode_map_0f_38[ctxt->b]; 4891 } 4892 } 4893 ctxt->d = opcode.flags; 4894 4895 if (ctxt->d & ModRM) 4896 ctxt->modrm = insn_fetch(u8, ctxt); 4897 4898 /* vex-prefix instructions are not implemented */ 4899 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) && 4900 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) { 4901 ctxt->d = NotImpl; 4902 } 4903 4904 while (ctxt->d & GroupMask) { 4905 switch (ctxt->d & GroupMask) { 4906 case Group: 4907 goffset = (ctxt->modrm >> 3) & 7; 4908 opcode = opcode.u.group[goffset]; 4909 break; 4910 case GroupDual: 4911 goffset = (ctxt->modrm >> 3) & 7; 4912 if ((ctxt->modrm >> 6) == 3) 4913 opcode = opcode.u.gdual->mod3[goffset]; 4914 else 4915 opcode = opcode.u.gdual->mod012[goffset]; 4916 break; 4917 case RMExt: 4918 goffset = ctxt->modrm & 7; 4919 opcode = opcode.u.group[goffset]; 4920 break; 4921 case Prefix: 4922 if (ctxt->rep_prefix && op_prefix) 4923 return EMULATION_FAILED; 4924 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix; 4925 switch (simd_prefix) { 4926 case 0x00: opcode = opcode.u.gprefix->pfx_no; break; 4927 case 0x66: opcode = opcode.u.gprefix->pfx_66; break; 4928 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break; 4929 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break; 4930 } 4931 break; 4932 case Escape: 4933 if (ctxt->modrm > 0xbf) { 4934 size_t size = ARRAY_SIZE(opcode.u.esc->high); 4935 u32 index = array_index_nospec( 4936 ctxt->modrm - 0xc0, size); 4937 4938 opcode = opcode.u.esc->high[index]; 4939 } else { 4940 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7]; 4941 } 4942 break; 4943 case InstrDual: 4944 if ((ctxt->modrm >> 6) == 3) 4945 opcode = opcode.u.idual->mod3; 4946 else 4947 opcode = opcode.u.idual->mod012; 4948 break; 4949 case ModeDual: 4950 if (ctxt->mode == X86EMUL_MODE_PROT64) 4951 opcode = opcode.u.mdual->mode64; 4952 else 4953 opcode = opcode.u.mdual->mode32; 4954 break; 4955 default: 4956 return EMULATION_FAILED; 4957 } 4958 4959 ctxt->d &= ~(u64)GroupMask; 4960 ctxt->d |= opcode.flags; 4961 } 4962 4963 ctxt->is_branch = opcode.flags & IsBranch; 4964 4965 /* Unrecognised? */ 4966 if (ctxt->d == 0) 4967 return EMULATION_FAILED; 4968 4969 ctxt->execute = opcode.u.execute; 4970 4971 /* 4972 * Reject emulation if KVM might need to emulate shadow stack updates 4973 * and/or indirect branch tracking enforcement, which the emulator 4974 * doesn't support. 4975 */ 4976 if ((is_ibt_instruction(ctxt) || is_shstk_instruction(ctxt)) && 4977 ctxt->ops->get_cr(ctxt, 4) & X86_CR4_CET) { 4978 u64 u_cet = 0, s_cet = 0; 4979 4980 /* 4981 * Check both User and Supervisor on far transfers as inter- 4982 * privilege level transfers are impacted by CET at the target 4983 * privilege level, and that is not known at this time. The 4984 * expectation is that the guest will not require emulation of 4985 * any CET-affected instructions at any privilege level. 4986 */ 4987 if (!(ctxt->d & NearBranch)) 4988 u_cet = s_cet = CET_SHSTK_EN | CET_ENDBR_EN; 4989 else if (ctxt->ops->cpl(ctxt) == 3) 4990 u_cet = CET_SHSTK_EN | CET_ENDBR_EN; 4991 else 4992 s_cet = CET_SHSTK_EN | CET_ENDBR_EN; 4993 4994 if ((u_cet && ctxt->ops->get_msr(ctxt, MSR_IA32_U_CET, &u_cet)) || 4995 (s_cet && ctxt->ops->get_msr(ctxt, MSR_IA32_S_CET, &s_cet))) 4996 return EMULATION_FAILED; 4997 4998 if ((u_cet | s_cet) & CET_SHSTK_EN && is_shstk_instruction(ctxt)) 4999 return EMULATION_FAILED; 5000 5001 if ((u_cet | s_cet) & CET_ENDBR_EN && is_ibt_instruction(ctxt)) 5002 return EMULATION_FAILED; 5003 } 5004 5005 if (unlikely(emulation_type & EMULTYPE_TRAP_UD) && 5006 likely(!(ctxt->d & EmulateOnUD))) 5007 return EMULATION_FAILED; 5008 5009 if (unlikely(ctxt->d & 5010 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch| 5011 No16))) { 5012 /* 5013 * These are copied unconditionally here, and checked unconditionally 5014 * in x86_emulate_insn. 5015 */ 5016 ctxt->check_perm = opcode.check_perm; 5017 ctxt->intercept = opcode.intercept; 5018 5019 if (ctxt->d & NotImpl) 5020 return EMULATION_FAILED; 5021 5022 if (mode == X86EMUL_MODE_PROT64) { 5023 if (ctxt->op_bytes == 4 && (ctxt->d & Stack)) 5024 ctxt->op_bytes = 8; 5025 else if (ctxt->d & NearBranch) 5026 ctxt->op_bytes = 8; 5027 } 5028 5029 if (ctxt->d & Op3264) { 5030 if (mode == X86EMUL_MODE_PROT64) 5031 ctxt->op_bytes = 8; 5032 else 5033 ctxt->op_bytes = 4; 5034 } 5035 5036 if ((ctxt->d & No16) && ctxt->op_bytes == 2) 5037 ctxt->op_bytes = 4; 5038 5039 if (ctxt->d & Sse) 5040 ctxt->op_bytes = 16; 5041 else if (ctxt->d & Mmx) 5042 ctxt->op_bytes = 8; 5043 } 5044 5045 /* ModRM and SIB bytes. */ 5046 if (ctxt->d & ModRM) { 5047 rc = decode_modrm(ctxt, &ctxt->memop); 5048 if (!has_seg_override) { 5049 has_seg_override = true; 5050 ctxt->seg_override = ctxt->modrm_seg; 5051 } 5052 } else if (ctxt->d & MemAbs) 5053 rc = decode_abs(ctxt, &ctxt->memop); 5054 if (rc != X86EMUL_CONTINUE) 5055 goto done; 5056 5057 if (!has_seg_override) 5058 ctxt->seg_override = VCPU_SREG_DS; 5059 5060 ctxt->memop.addr.mem.seg = ctxt->seg_override; 5061 5062 /* 5063 * Decode and fetch the source operand: register, memory 5064 * or immediate. 5065 */ 5066 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask); 5067 if (rc != X86EMUL_CONTINUE) 5068 goto done; 5069 5070 /* 5071 * Decode and fetch the second source operand: register, memory 5072 * or immediate. 5073 */ 5074 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask); 5075 if (rc != X86EMUL_CONTINUE) 5076 goto done; 5077 5078 /* Decode and fetch the destination operand: register or memory. */ 5079 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask); 5080 5081 if (ctxt->rip_relative && likely(ctxt->memopp)) 5082 ctxt->memopp->addr.mem.ea = address_mask(ctxt, 5083 ctxt->memopp->addr.mem.ea + ctxt->_eip); 5084 5085 done: 5086 if (rc == X86EMUL_PROPAGATE_FAULT) 5087 ctxt->have_exception = true; 5088 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK; 5089 } 5090 5091 bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt) 5092 { 5093 return ctxt->d & PageTable; 5094 } 5095 5096 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt) 5097 { 5098 /* The second termination condition only applies for REPE 5099 * and REPNE. Test if the repeat string operation prefix is 5100 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the 5101 * corresponding termination condition according to: 5102 * - if REPE/REPZ and ZF = 0 then done 5103 * - if REPNE/REPNZ and ZF = 1 then done 5104 */ 5105 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) || 5106 (ctxt->b == 0xae) || (ctxt->b == 0xaf)) 5107 && (((ctxt->rep_prefix == REPE_PREFIX) && 5108 ((ctxt->eflags & X86_EFLAGS_ZF) == 0)) 5109 || ((ctxt->rep_prefix == REPNE_PREFIX) && 5110 ((ctxt->eflags & X86_EFLAGS_ZF) == X86_EFLAGS_ZF)))) 5111 return true; 5112 5113 return false; 5114 } 5115 5116 static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt) 5117 { 5118 int rc; 5119 5120 kvm_fpu_get(); 5121 rc = asm_safe("fwait"); 5122 kvm_fpu_put(); 5123 5124 if (unlikely(rc != X86EMUL_CONTINUE)) 5125 return emulate_exception(ctxt, MF_VECTOR, 0, false); 5126 5127 return X86EMUL_CONTINUE; 5128 } 5129 5130 static void fetch_possible_mmx_operand(struct operand *op) 5131 { 5132 if (op->type == OP_MM) 5133 kvm_read_mmx_reg(op->addr.mm, &op->mm_val); 5134 } 5135 5136 void init_decode_cache(struct x86_emulate_ctxt *ctxt) 5137 { 5138 /* Clear fields that are set conditionally but read without a guard. */ 5139 ctxt->rip_relative = false; 5140 ctxt->rex_prefix = 0; 5141 ctxt->lock_prefix = 0; 5142 ctxt->rep_prefix = 0; 5143 ctxt->regs_valid = 0; 5144 ctxt->regs_dirty = 0; 5145 5146 ctxt->io_read.pos = 0; 5147 ctxt->io_read.end = 0; 5148 ctxt->mem_read.end = 0; 5149 } 5150 5151 int x86_emulate_insn(struct x86_emulate_ctxt *ctxt, bool check_intercepts) 5152 { 5153 const struct x86_emulate_ops *ops = ctxt->ops; 5154 int rc = X86EMUL_CONTINUE; 5155 int saved_dst_type = ctxt->dst.type; 5156 5157 ctxt->mem_read.pos = 0; 5158 5159 /* LOCK prefix is allowed only with some instructions */ 5160 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) { 5161 rc = emulate_ud(ctxt); 5162 goto done; 5163 } 5164 5165 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) { 5166 rc = emulate_ud(ctxt); 5167 goto done; 5168 } 5169 5170 if (unlikely(ctxt->d & 5171 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) { 5172 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) || 5173 (ctxt->d & Undefined)) { 5174 rc = emulate_ud(ctxt); 5175 goto done; 5176 } 5177 5178 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM))) 5179 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) { 5180 rc = emulate_ud(ctxt); 5181 goto done; 5182 } 5183 5184 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) { 5185 rc = emulate_nm(ctxt); 5186 goto done; 5187 } 5188 5189 if (ctxt->d & Mmx) { 5190 rc = flush_pending_x87_faults(ctxt); 5191 if (rc != X86EMUL_CONTINUE) 5192 goto done; 5193 /* 5194 * Now that we know the fpu is exception safe, we can fetch 5195 * operands from it. 5196 */ 5197 fetch_possible_mmx_operand(&ctxt->src); 5198 fetch_possible_mmx_operand(&ctxt->src2); 5199 if (!(ctxt->d & Mov)) 5200 fetch_possible_mmx_operand(&ctxt->dst); 5201 } 5202 5203 if (unlikely(check_intercepts) && ctxt->intercept) { 5204 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5205 X86_ICPT_PRE_EXCEPT); 5206 if (rc != X86EMUL_CONTINUE) 5207 goto done; 5208 } 5209 5210 /* Instruction can only be executed in protected mode */ 5211 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) { 5212 rc = emulate_ud(ctxt); 5213 goto done; 5214 } 5215 5216 /* Privileged instruction can be executed only in CPL=0 */ 5217 if ((ctxt->d & Priv) && ops->cpl(ctxt)) { 5218 if (ctxt->d & PrivUD) 5219 rc = emulate_ud(ctxt); 5220 else 5221 rc = emulate_gp(ctxt, 0); 5222 goto done; 5223 } 5224 5225 /* Do instruction specific permission checks */ 5226 if (ctxt->d & CheckPerm) { 5227 rc = ctxt->check_perm(ctxt); 5228 if (rc != X86EMUL_CONTINUE) 5229 goto done; 5230 } 5231 5232 if (unlikely(check_intercepts) && (ctxt->d & Intercept)) { 5233 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5234 X86_ICPT_POST_EXCEPT); 5235 if (rc != X86EMUL_CONTINUE) 5236 goto done; 5237 } 5238 5239 if (ctxt->rep_prefix && (ctxt->d & String)) { 5240 /* All REP prefixes have the same first termination condition */ 5241 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) { 5242 string_registers_quirk(ctxt); 5243 ctxt->eip = ctxt->_eip; 5244 ctxt->eflags &= ~X86_EFLAGS_RF; 5245 goto done; 5246 } 5247 } 5248 } 5249 5250 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) { 5251 rc = segmented_read(ctxt, ctxt->src.addr.mem, 5252 ctxt->src.valptr, ctxt->src.bytes); 5253 if (rc != X86EMUL_CONTINUE) 5254 goto done; 5255 ctxt->src.orig_val64 = ctxt->src.val64; 5256 } 5257 5258 if (ctxt->src2.type == OP_MEM) { 5259 rc = segmented_read(ctxt, ctxt->src2.addr.mem, 5260 &ctxt->src2.val, ctxt->src2.bytes); 5261 if (rc != X86EMUL_CONTINUE) 5262 goto done; 5263 } 5264 5265 if ((ctxt->d & DstMask) == ImplicitOps) 5266 goto special_insn; 5267 5268 5269 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) { 5270 /* optimisation - avoid slow emulated read if Mov */ 5271 rc = segmented_read(ctxt, ctxt->dst.addr.mem, 5272 &ctxt->dst.val, ctxt->dst.bytes); 5273 if (rc != X86EMUL_CONTINUE) { 5274 if (!(ctxt->d & NoWrite) && 5275 rc == X86EMUL_PROPAGATE_FAULT && 5276 ctxt->exception.vector == PF_VECTOR) 5277 ctxt->exception.error_code |= PFERR_WRITE_MASK; 5278 goto done; 5279 } 5280 } 5281 /* Copy full 64-bit value for CMPXCHG8B. */ 5282 ctxt->dst.orig_val64 = ctxt->dst.val64; 5283 5284 special_insn: 5285 5286 if (unlikely(check_intercepts) && (ctxt->d & Intercept)) { 5287 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5288 X86_ICPT_POST_MEMACCESS); 5289 if (rc != X86EMUL_CONTINUE) 5290 goto done; 5291 } 5292 5293 if (ctxt->rep_prefix && (ctxt->d & String)) 5294 ctxt->eflags |= X86_EFLAGS_RF; 5295 else 5296 ctxt->eflags &= ~X86_EFLAGS_RF; 5297 5298 if (ctxt->execute) { 5299 rc = ctxt->execute(ctxt); 5300 if (rc != X86EMUL_CONTINUE) 5301 goto done; 5302 goto writeback; 5303 } 5304 5305 if (ctxt->opcode_len == 2) 5306 goto twobyte_insn; 5307 else if (ctxt->opcode_len == 3) 5308 goto threebyte_insn; 5309 5310 switch (ctxt->b) { 5311 case 0x70 ... 0x7f: /* jcc (short) */ 5312 if (test_cc(ctxt->b, ctxt->eflags)) 5313 rc = jmp_rel(ctxt, ctxt->src.val); 5314 break; 5315 case 0x8d: /* lea r16/r32, m */ 5316 ctxt->dst.val = ctxt->src.addr.mem.ea; 5317 break; 5318 case 0x90 ... 0x97: /* nop / xchg reg, rax */ 5319 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX)) 5320 ctxt->dst.type = OP_NONE; 5321 else 5322 rc = em_xchg(ctxt); 5323 break; 5324 case 0x98: /* cbw/cwde/cdqe */ 5325 switch (ctxt->op_bytes) { 5326 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break; 5327 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break; 5328 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break; 5329 } 5330 break; 5331 case 0xcc: /* int3 */ 5332 rc = emulate_int(ctxt, 3); 5333 break; 5334 case 0xcd: /* int n */ 5335 rc = emulate_int(ctxt, ctxt->src.val); 5336 break; 5337 case 0xce: /* into */ 5338 if (ctxt->eflags & X86_EFLAGS_OF) 5339 rc = emulate_int(ctxt, 4); 5340 break; 5341 case 0xe9: /* jmp rel */ 5342 case 0xeb: /* jmp rel short */ 5343 rc = jmp_rel(ctxt, ctxt->src.val); 5344 ctxt->dst.type = OP_NONE; /* Disable writeback. */ 5345 break; 5346 case 0xf4: /* hlt */ 5347 ctxt->ops->halt(ctxt); 5348 break; 5349 case 0xf5: /* cmc */ 5350 /* complement carry flag from eflags reg */ 5351 ctxt->eflags ^= X86_EFLAGS_CF; 5352 break; 5353 case 0xf8: /* clc */ 5354 ctxt->eflags &= ~X86_EFLAGS_CF; 5355 break; 5356 case 0xf9: /* stc */ 5357 ctxt->eflags |= X86_EFLAGS_CF; 5358 break; 5359 case 0xfc: /* cld */ 5360 ctxt->eflags &= ~X86_EFLAGS_DF; 5361 break; 5362 case 0xfd: /* std */ 5363 ctxt->eflags |= X86_EFLAGS_DF; 5364 break; 5365 default: 5366 goto cannot_emulate; 5367 } 5368 5369 if (rc != X86EMUL_CONTINUE) 5370 goto done; 5371 5372 writeback: 5373 if (ctxt->d & SrcWrite) { 5374 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR); 5375 rc = writeback(ctxt, &ctxt->src); 5376 if (rc != X86EMUL_CONTINUE) 5377 goto done; 5378 } 5379 if (!(ctxt->d & NoWrite)) { 5380 rc = writeback(ctxt, &ctxt->dst); 5381 if (rc != X86EMUL_CONTINUE) 5382 goto done; 5383 } 5384 5385 /* 5386 * restore dst type in case the decoding will be reused 5387 * (happens for string instruction ) 5388 */ 5389 ctxt->dst.type = saved_dst_type; 5390 5391 if ((ctxt->d & SrcMask) == SrcSI) 5392 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src); 5393 5394 if ((ctxt->d & DstMask) == DstDI) 5395 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst); 5396 5397 if (ctxt->rep_prefix && (ctxt->d & String)) { 5398 unsigned int count; 5399 struct read_cache *r = &ctxt->io_read; 5400 if ((ctxt->d & SrcMask) == SrcSI) 5401 count = ctxt->src.count; 5402 else 5403 count = ctxt->dst.count; 5404 register_address_increment(ctxt, VCPU_REGS_RCX, -count); 5405 5406 if (!string_insn_completed(ctxt)) { 5407 /* 5408 * Re-enter guest when pio read ahead buffer is empty 5409 * or, if it is not used, after each 1024 iteration. 5410 */ 5411 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) && 5412 (r->end == 0 || r->end != r->pos)) { 5413 /* 5414 * Reset read cache. Usually happens before 5415 * decode, but since instruction is restarted 5416 * we have to do it here. 5417 */ 5418 ctxt->mem_read.end = 0; 5419 writeback_registers(ctxt); 5420 return EMULATION_RESTART; 5421 } 5422 goto done; /* skip rip writeback */ 5423 } 5424 ctxt->eflags &= ~X86_EFLAGS_RF; 5425 } 5426 5427 ctxt->eip = ctxt->_eip; 5428 if (ctxt->mode != X86EMUL_MODE_PROT64) 5429 ctxt->eip = (u32)ctxt->_eip; 5430 5431 done: 5432 if (rc == X86EMUL_PROPAGATE_FAULT) { 5433 if (KVM_EMULATOR_BUG_ON(ctxt->exception.vector > 0x1f, ctxt)) 5434 return EMULATION_FAILED; 5435 ctxt->have_exception = true; 5436 } 5437 if (rc == X86EMUL_INTERCEPTED) 5438 return EMULATION_INTERCEPTED; 5439 5440 if (rc == X86EMUL_CONTINUE) 5441 writeback_registers(ctxt); 5442 5443 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 5444 5445 twobyte_insn: 5446 switch (ctxt->b) { 5447 case 0x09: /* wbinvd */ 5448 (ctxt->ops->wbinvd)(ctxt); 5449 break; 5450 case 0x08: /* invd */ 5451 case 0x0d: /* GrpP (prefetch) */ 5452 case 0x18: /* Grp16 (prefetch/nop) */ 5453 case 0x1f: /* nop */ 5454 break; 5455 case 0x20: /* mov cr, reg */ 5456 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg); 5457 break; 5458 case 0x21: /* mov from dr to reg */ 5459 ctxt->dst.val = ops->get_dr(ctxt, ctxt->modrm_reg); 5460 break; 5461 case 0x40 ... 0x4f: /* cmov */ 5462 if (test_cc(ctxt->b, ctxt->eflags)) 5463 ctxt->dst.val = ctxt->src.val; 5464 else if (ctxt->op_bytes != 4) 5465 ctxt->dst.type = OP_NONE; /* no writeback */ 5466 break; 5467 case 0x80 ... 0x8f: /* jnz rel, etc*/ 5468 if (test_cc(ctxt->b, ctxt->eflags)) 5469 rc = jmp_rel(ctxt, ctxt->src.val); 5470 break; 5471 case 0x90 ... 0x9f: /* setcc r/m8 */ 5472 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags); 5473 break; 5474 case 0xb6 ... 0xb7: /* movzx */ 5475 ctxt->dst.bytes = ctxt->op_bytes; 5476 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val 5477 : (u16) ctxt->src.val; 5478 break; 5479 case 0xbe ... 0xbf: /* movsx */ 5480 ctxt->dst.bytes = ctxt->op_bytes; 5481 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val : 5482 (s16) ctxt->src.val; 5483 break; 5484 default: 5485 goto cannot_emulate; 5486 } 5487 5488 threebyte_insn: 5489 5490 if (rc != X86EMUL_CONTINUE) 5491 goto done; 5492 5493 goto writeback; 5494 5495 cannot_emulate: 5496 return EMULATION_FAILED; 5497 } 5498 5499 void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt) 5500 { 5501 invalidate_registers(ctxt); 5502 } 5503 5504 void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt) 5505 { 5506 writeback_registers(ctxt); 5507 } 5508 5509 bool emulator_can_use_gpa(struct x86_emulate_ctxt *ctxt) 5510 { 5511 if (ctxt->rep_prefix && (ctxt->d & String)) 5512 return false; 5513 5514 if (ctxt->d & TwoMemOp) 5515 return false; 5516 5517 return true; 5518 } 5519