1 /****************************************************************************** 2 * emulate.c 3 * 4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. 5 * 6 * Copyright (c) 2005 Keir Fraser 7 * 8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode 9 * privileged instructions: 10 * 11 * Copyright (C) 2006 Qumranet 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 13 * 14 * Avi Kivity <avi@qumranet.com> 15 * Yaniv Kamay <yaniv@qumranet.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 21 */ 22 23 #include <linux/kvm_host.h> 24 #include "kvm_cache_regs.h" 25 #include <asm/kvm_emulate.h> 26 #include <linux/stringify.h> 27 #include <asm/debugreg.h> 28 29 #include "x86.h" 30 #include "tss.h" 31 #include "mmu.h" 32 33 /* 34 * Operand types 35 */ 36 #define OpNone 0ull 37 #define OpImplicit 1ull /* No generic decode */ 38 #define OpReg 2ull /* Register */ 39 #define OpMem 3ull /* Memory */ 40 #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */ 41 #define OpDI 5ull /* ES:DI/EDI/RDI */ 42 #define OpMem64 6ull /* Memory, 64-bit */ 43 #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */ 44 #define OpDX 8ull /* DX register */ 45 #define OpCL 9ull /* CL register (for shifts) */ 46 #define OpImmByte 10ull /* 8-bit sign extended immediate */ 47 #define OpOne 11ull /* Implied 1 */ 48 #define OpImm 12ull /* Sign extended up to 32-bit immediate */ 49 #define OpMem16 13ull /* Memory operand (16-bit). */ 50 #define OpMem32 14ull /* Memory operand (32-bit). */ 51 #define OpImmU 15ull /* Immediate operand, zero extended */ 52 #define OpSI 16ull /* SI/ESI/RSI */ 53 #define OpImmFAddr 17ull /* Immediate far address */ 54 #define OpMemFAddr 18ull /* Far address in memory */ 55 #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */ 56 #define OpES 20ull /* ES */ 57 #define OpCS 21ull /* CS */ 58 #define OpSS 22ull /* SS */ 59 #define OpDS 23ull /* DS */ 60 #define OpFS 24ull /* FS */ 61 #define OpGS 25ull /* GS */ 62 #define OpMem8 26ull /* 8-bit zero extended memory operand */ 63 #define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */ 64 #define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */ 65 #define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */ 66 #define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */ 67 68 #define OpBits 5 /* Width of operand field */ 69 #define OpMask ((1ull << OpBits) - 1) 70 71 /* 72 * Opcode effective-address decode tables. 73 * Note that we only emulate instructions that have at least one memory 74 * operand (excluding implicit stack references). We assume that stack 75 * references and instruction fetches will never occur in special memory 76 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need 77 * not be handled. 78 */ 79 80 /* Operand sizes: 8-bit operands or specified/overridden size. */ 81 #define ByteOp (1<<0) /* 8-bit operands. */ 82 /* Destination operand type. */ 83 #define DstShift 1 84 #define ImplicitOps (OpImplicit << DstShift) 85 #define DstReg (OpReg << DstShift) 86 #define DstMem (OpMem << DstShift) 87 #define DstAcc (OpAcc << DstShift) 88 #define DstDI (OpDI << DstShift) 89 #define DstMem64 (OpMem64 << DstShift) 90 #define DstMem16 (OpMem16 << DstShift) 91 #define DstImmUByte (OpImmUByte << DstShift) 92 #define DstDX (OpDX << DstShift) 93 #define DstAccLo (OpAccLo << DstShift) 94 #define DstMask (OpMask << DstShift) 95 /* Source operand type. */ 96 #define SrcShift 6 97 #define SrcNone (OpNone << SrcShift) 98 #define SrcReg (OpReg << SrcShift) 99 #define SrcMem (OpMem << SrcShift) 100 #define SrcMem16 (OpMem16 << SrcShift) 101 #define SrcMem32 (OpMem32 << SrcShift) 102 #define SrcImm (OpImm << SrcShift) 103 #define SrcImmByte (OpImmByte << SrcShift) 104 #define SrcOne (OpOne << SrcShift) 105 #define SrcImmUByte (OpImmUByte << SrcShift) 106 #define SrcImmU (OpImmU << SrcShift) 107 #define SrcSI (OpSI << SrcShift) 108 #define SrcXLat (OpXLat << SrcShift) 109 #define SrcImmFAddr (OpImmFAddr << SrcShift) 110 #define SrcMemFAddr (OpMemFAddr << SrcShift) 111 #define SrcAcc (OpAcc << SrcShift) 112 #define SrcImmU16 (OpImmU16 << SrcShift) 113 #define SrcImm64 (OpImm64 << SrcShift) 114 #define SrcDX (OpDX << SrcShift) 115 #define SrcMem8 (OpMem8 << SrcShift) 116 #define SrcAccHi (OpAccHi << SrcShift) 117 #define SrcMask (OpMask << SrcShift) 118 #define BitOp (1<<11) 119 #define MemAbs (1<<12) /* Memory operand is absolute displacement */ 120 #define String (1<<13) /* String instruction (rep capable) */ 121 #define Stack (1<<14) /* Stack instruction (push/pop) */ 122 #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */ 123 #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */ 124 #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */ 125 #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */ 126 #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */ 127 #define Escape (5<<15) /* Escape to coprocessor instruction */ 128 #define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */ 129 #define ModeDual (7<<15) /* Different instruction for 32/64 bit */ 130 #define Sse (1<<18) /* SSE Vector instruction */ 131 /* Generic ModRM decode. */ 132 #define ModRM (1<<19) 133 /* Destination is only written; never read. */ 134 #define Mov (1<<20) 135 /* Misc flags */ 136 #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */ 137 #define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */ 138 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ 139 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ 140 #define Undefined (1<<25) /* No Such Instruction */ 141 #define Lock (1<<26) /* lock prefix is allowed for the instruction */ 142 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ 143 #define No64 (1<<28) 144 #define PageTable (1 << 29) /* instruction used to write page table */ 145 #define NotImpl (1 << 30) /* instruction is not implemented */ 146 /* Source 2 operand type */ 147 #define Src2Shift (31) 148 #define Src2None (OpNone << Src2Shift) 149 #define Src2Mem (OpMem << Src2Shift) 150 #define Src2CL (OpCL << Src2Shift) 151 #define Src2ImmByte (OpImmByte << Src2Shift) 152 #define Src2One (OpOne << Src2Shift) 153 #define Src2Imm (OpImm << Src2Shift) 154 #define Src2ES (OpES << Src2Shift) 155 #define Src2CS (OpCS << Src2Shift) 156 #define Src2SS (OpSS << Src2Shift) 157 #define Src2DS (OpDS << Src2Shift) 158 #define Src2FS (OpFS << Src2Shift) 159 #define Src2GS (OpGS << Src2Shift) 160 #define Src2Mask (OpMask << Src2Shift) 161 #define Mmx ((u64)1 << 40) /* MMX Vector instruction */ 162 #define AlignMask ((u64)7 << 41) 163 #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */ 164 #define Unaligned ((u64)2 << 41) /* Explicitly unaligned (e.g. MOVDQU) */ 165 #define Avx ((u64)3 << 41) /* Advanced Vector Extensions */ 166 #define Aligned16 ((u64)4 << 41) /* Aligned to 16 byte boundary (e.g. FXSAVE) */ 167 #define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */ 168 #define NoWrite ((u64)1 << 45) /* No writeback */ 169 #define SrcWrite ((u64)1 << 46) /* Write back src operand */ 170 #define NoMod ((u64)1 << 47) /* Mod field is ignored */ 171 #define Intercept ((u64)1 << 48) /* Has valid intercept field */ 172 #define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */ 173 #define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */ 174 #define NearBranch ((u64)1 << 52) /* Near branches */ 175 #define No16 ((u64)1 << 53) /* No 16 bit operand */ 176 #define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */ 177 #define TwoMemOp ((u64)1 << 55) /* Instruction has two memory operand */ 178 179 #define DstXacc (DstAccLo | SrcAccHi | SrcWrite) 180 181 #define X2(x...) x, x 182 #define X3(x...) X2(x), x 183 #define X4(x...) X2(x), X2(x) 184 #define X5(x...) X4(x), x 185 #define X6(x...) X4(x), X2(x) 186 #define X7(x...) X4(x), X3(x) 187 #define X8(x...) X4(x), X4(x) 188 #define X16(x...) X8(x), X8(x) 189 190 #define NR_FASTOP (ilog2(sizeof(ulong)) + 1) 191 #define FASTOP_SIZE 8 192 193 /* 194 * fastop functions have a special calling convention: 195 * 196 * dst: rax (in/out) 197 * src: rdx (in/out) 198 * src2: rcx (in) 199 * flags: rflags (in/out) 200 * ex: rsi (in:fastop pointer, out:zero if exception) 201 * 202 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for 203 * different operand sizes can be reached by calculation, rather than a jump 204 * table (which would be bigger than the code). 205 * 206 * fastop functions are declared as taking a never-defined fastop parameter, 207 * so they can't be called from C directly. 208 */ 209 210 struct fastop; 211 212 struct opcode { 213 u64 flags : 56; 214 u64 intercept : 8; 215 union { 216 int (*execute)(struct x86_emulate_ctxt *ctxt); 217 const struct opcode *group; 218 const struct group_dual *gdual; 219 const struct gprefix *gprefix; 220 const struct escape *esc; 221 const struct instr_dual *idual; 222 const struct mode_dual *mdual; 223 void (*fastop)(struct fastop *fake); 224 } u; 225 int (*check_perm)(struct x86_emulate_ctxt *ctxt); 226 }; 227 228 struct group_dual { 229 struct opcode mod012[8]; 230 struct opcode mod3[8]; 231 }; 232 233 struct gprefix { 234 struct opcode pfx_no; 235 struct opcode pfx_66; 236 struct opcode pfx_f2; 237 struct opcode pfx_f3; 238 }; 239 240 struct escape { 241 struct opcode op[8]; 242 struct opcode high[64]; 243 }; 244 245 struct instr_dual { 246 struct opcode mod012; 247 struct opcode mod3; 248 }; 249 250 struct mode_dual { 251 struct opcode mode32; 252 struct opcode mode64; 253 }; 254 255 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a 256 257 enum x86_transfer_type { 258 X86_TRANSFER_NONE, 259 X86_TRANSFER_CALL_JMP, 260 X86_TRANSFER_RET, 261 X86_TRANSFER_TASK_SWITCH, 262 }; 263 264 static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr) 265 { 266 if (!(ctxt->regs_valid & (1 << nr))) { 267 ctxt->regs_valid |= 1 << nr; 268 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr); 269 } 270 return ctxt->_regs[nr]; 271 } 272 273 static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr) 274 { 275 ctxt->regs_valid |= 1 << nr; 276 ctxt->regs_dirty |= 1 << nr; 277 return &ctxt->_regs[nr]; 278 } 279 280 static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr) 281 { 282 reg_read(ctxt, nr); 283 return reg_write(ctxt, nr); 284 } 285 286 static void writeback_registers(struct x86_emulate_ctxt *ctxt) 287 { 288 unsigned reg; 289 290 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16) 291 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]); 292 } 293 294 static void invalidate_registers(struct x86_emulate_ctxt *ctxt) 295 { 296 ctxt->regs_dirty = 0; 297 ctxt->regs_valid = 0; 298 } 299 300 /* 301 * These EFLAGS bits are restored from saved value during emulation, and 302 * any changes are written back to the saved value after emulation. 303 */ 304 #define EFLAGS_MASK (X86_EFLAGS_OF|X86_EFLAGS_SF|X86_EFLAGS_ZF|X86_EFLAGS_AF|\ 305 X86_EFLAGS_PF|X86_EFLAGS_CF) 306 307 #ifdef CONFIG_X86_64 308 #define ON64(x) x 309 #else 310 #define ON64(x) 311 #endif 312 313 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *)); 314 315 #define FOP_FUNC(name) \ 316 ".align " __stringify(FASTOP_SIZE) " \n\t" \ 317 ".type " name ", @function \n\t" \ 318 name ":\n\t" 319 320 #define FOP_RET "ret \n\t" 321 322 #define FOP_START(op) \ 323 extern void em_##op(struct fastop *fake); \ 324 asm(".pushsection .text, \"ax\" \n\t" \ 325 ".global em_" #op " \n\t" \ 326 FOP_FUNC("em_" #op) 327 328 #define FOP_END \ 329 ".popsection") 330 331 #define FOPNOP() \ 332 FOP_FUNC(__stringify(__UNIQUE_ID(nop))) \ 333 FOP_RET 334 335 #define FOP1E(op, dst) \ 336 FOP_FUNC(#op "_" #dst) \ 337 "10: " #op " %" #dst " \n\t" FOP_RET 338 339 #define FOP1EEX(op, dst) \ 340 FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception) 341 342 #define FASTOP1(op) \ 343 FOP_START(op) \ 344 FOP1E(op##b, al) \ 345 FOP1E(op##w, ax) \ 346 FOP1E(op##l, eax) \ 347 ON64(FOP1E(op##q, rax)) \ 348 FOP_END 349 350 /* 1-operand, using src2 (for MUL/DIV r/m) */ 351 #define FASTOP1SRC2(op, name) \ 352 FOP_START(name) \ 353 FOP1E(op, cl) \ 354 FOP1E(op, cx) \ 355 FOP1E(op, ecx) \ 356 ON64(FOP1E(op, rcx)) \ 357 FOP_END 358 359 /* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */ 360 #define FASTOP1SRC2EX(op, name) \ 361 FOP_START(name) \ 362 FOP1EEX(op, cl) \ 363 FOP1EEX(op, cx) \ 364 FOP1EEX(op, ecx) \ 365 ON64(FOP1EEX(op, rcx)) \ 366 FOP_END 367 368 #define FOP2E(op, dst, src) \ 369 FOP_FUNC(#op "_" #dst "_" #src) \ 370 #op " %" #src ", %" #dst " \n\t" FOP_RET 371 372 #define FASTOP2(op) \ 373 FOP_START(op) \ 374 FOP2E(op##b, al, dl) \ 375 FOP2E(op##w, ax, dx) \ 376 FOP2E(op##l, eax, edx) \ 377 ON64(FOP2E(op##q, rax, rdx)) \ 378 FOP_END 379 380 /* 2 operand, word only */ 381 #define FASTOP2W(op) \ 382 FOP_START(op) \ 383 FOPNOP() \ 384 FOP2E(op##w, ax, dx) \ 385 FOP2E(op##l, eax, edx) \ 386 ON64(FOP2E(op##q, rax, rdx)) \ 387 FOP_END 388 389 /* 2 operand, src is CL */ 390 #define FASTOP2CL(op) \ 391 FOP_START(op) \ 392 FOP2E(op##b, al, cl) \ 393 FOP2E(op##w, ax, cl) \ 394 FOP2E(op##l, eax, cl) \ 395 ON64(FOP2E(op##q, rax, cl)) \ 396 FOP_END 397 398 /* 2 operand, src and dest are reversed */ 399 #define FASTOP2R(op, name) \ 400 FOP_START(name) \ 401 FOP2E(op##b, dl, al) \ 402 FOP2E(op##w, dx, ax) \ 403 FOP2E(op##l, edx, eax) \ 404 ON64(FOP2E(op##q, rdx, rax)) \ 405 FOP_END 406 407 #define FOP3E(op, dst, src, src2) \ 408 FOP_FUNC(#op "_" #dst "_" #src "_" #src2) \ 409 #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET 410 411 /* 3-operand, word-only, src2=cl */ 412 #define FASTOP3WCL(op) \ 413 FOP_START(op) \ 414 FOPNOP() \ 415 FOP3E(op##w, ax, dx, cl) \ 416 FOP3E(op##l, eax, edx, cl) \ 417 ON64(FOP3E(op##q, rax, rdx, cl)) \ 418 FOP_END 419 420 /* Special case for SETcc - 1 instruction per cc */ 421 #define FOP_SETCC(op) \ 422 ".align 4 \n\t" \ 423 ".type " #op ", @function \n\t" \ 424 #op ": \n\t" \ 425 #op " %al \n\t" \ 426 FOP_RET 427 428 asm(".global kvm_fastop_exception \n" 429 "kvm_fastop_exception: xor %esi, %esi; ret"); 430 431 FOP_START(setcc) 432 FOP_SETCC(seto) 433 FOP_SETCC(setno) 434 FOP_SETCC(setc) 435 FOP_SETCC(setnc) 436 FOP_SETCC(setz) 437 FOP_SETCC(setnz) 438 FOP_SETCC(setbe) 439 FOP_SETCC(setnbe) 440 FOP_SETCC(sets) 441 FOP_SETCC(setns) 442 FOP_SETCC(setp) 443 FOP_SETCC(setnp) 444 FOP_SETCC(setl) 445 FOP_SETCC(setnl) 446 FOP_SETCC(setle) 447 FOP_SETCC(setnle) 448 FOP_END; 449 450 FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET 451 FOP_END; 452 453 /* 454 * XXX: inoutclob user must know where the argument is being expanded. 455 * Relying on CC_HAVE_ASM_GOTO would allow us to remove _fault. 456 */ 457 #define asm_safe(insn, inoutclob...) \ 458 ({ \ 459 int _fault = 0; \ 460 \ 461 asm volatile("1:" insn "\n" \ 462 "2:\n" \ 463 ".pushsection .fixup, \"ax\"\n" \ 464 "3: movl $1, %[_fault]\n" \ 465 " jmp 2b\n" \ 466 ".popsection\n" \ 467 _ASM_EXTABLE(1b, 3b) \ 468 : [_fault] "+qm"(_fault) inoutclob ); \ 469 \ 470 _fault ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; \ 471 }) 472 473 static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt, 474 enum x86_intercept intercept, 475 enum x86_intercept_stage stage) 476 { 477 struct x86_instruction_info info = { 478 .intercept = intercept, 479 .rep_prefix = ctxt->rep_prefix, 480 .modrm_mod = ctxt->modrm_mod, 481 .modrm_reg = ctxt->modrm_reg, 482 .modrm_rm = ctxt->modrm_rm, 483 .src_val = ctxt->src.val64, 484 .dst_val = ctxt->dst.val64, 485 .src_bytes = ctxt->src.bytes, 486 .dst_bytes = ctxt->dst.bytes, 487 .ad_bytes = ctxt->ad_bytes, 488 .next_rip = ctxt->eip, 489 }; 490 491 return ctxt->ops->intercept(ctxt, &info, stage); 492 } 493 494 static void assign_masked(ulong *dest, ulong src, ulong mask) 495 { 496 *dest = (*dest & ~mask) | (src & mask); 497 } 498 499 static void assign_register(unsigned long *reg, u64 val, int bytes) 500 { 501 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ 502 switch (bytes) { 503 case 1: 504 *(u8 *)reg = (u8)val; 505 break; 506 case 2: 507 *(u16 *)reg = (u16)val; 508 break; 509 case 4: 510 *reg = (u32)val; 511 break; /* 64b: zero-extend */ 512 case 8: 513 *reg = val; 514 break; 515 } 516 } 517 518 static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt) 519 { 520 return (1UL << (ctxt->ad_bytes << 3)) - 1; 521 } 522 523 static ulong stack_mask(struct x86_emulate_ctxt *ctxt) 524 { 525 u16 sel; 526 struct desc_struct ss; 527 528 if (ctxt->mode == X86EMUL_MODE_PROT64) 529 return ~0UL; 530 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS); 531 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */ 532 } 533 534 static int stack_size(struct x86_emulate_ctxt *ctxt) 535 { 536 return (__fls(stack_mask(ctxt)) + 1) >> 3; 537 } 538 539 /* Access/update address held in a register, based on addressing mode. */ 540 static inline unsigned long 541 address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg) 542 { 543 if (ctxt->ad_bytes == sizeof(unsigned long)) 544 return reg; 545 else 546 return reg & ad_mask(ctxt); 547 } 548 549 static inline unsigned long 550 register_address(struct x86_emulate_ctxt *ctxt, int reg) 551 { 552 return address_mask(ctxt, reg_read(ctxt, reg)); 553 } 554 555 static void masked_increment(ulong *reg, ulong mask, int inc) 556 { 557 assign_masked(reg, *reg + inc, mask); 558 } 559 560 static inline void 561 register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc) 562 { 563 ulong *preg = reg_rmw(ctxt, reg); 564 565 assign_register(preg, *preg + inc, ctxt->ad_bytes); 566 } 567 568 static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc) 569 { 570 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc); 571 } 572 573 static u32 desc_limit_scaled(struct desc_struct *desc) 574 { 575 u32 limit = get_desc_limit(desc); 576 577 return desc->g ? (limit << 12) | 0xfff : limit; 578 } 579 580 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) 581 { 582 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) 583 return 0; 584 585 return ctxt->ops->get_cached_segment_base(ctxt, seg); 586 } 587 588 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, 589 u32 error, bool valid) 590 { 591 WARN_ON(vec > 0x1f); 592 ctxt->exception.vector = vec; 593 ctxt->exception.error_code = error; 594 ctxt->exception.error_code_valid = valid; 595 return X86EMUL_PROPAGATE_FAULT; 596 } 597 598 static int emulate_db(struct x86_emulate_ctxt *ctxt) 599 { 600 return emulate_exception(ctxt, DB_VECTOR, 0, false); 601 } 602 603 static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err) 604 { 605 return emulate_exception(ctxt, GP_VECTOR, err, true); 606 } 607 608 static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err) 609 { 610 return emulate_exception(ctxt, SS_VECTOR, err, true); 611 } 612 613 static int emulate_ud(struct x86_emulate_ctxt *ctxt) 614 { 615 return emulate_exception(ctxt, UD_VECTOR, 0, false); 616 } 617 618 static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err) 619 { 620 return emulate_exception(ctxt, TS_VECTOR, err, true); 621 } 622 623 static int emulate_de(struct x86_emulate_ctxt *ctxt) 624 { 625 return emulate_exception(ctxt, DE_VECTOR, 0, false); 626 } 627 628 static int emulate_nm(struct x86_emulate_ctxt *ctxt) 629 { 630 return emulate_exception(ctxt, NM_VECTOR, 0, false); 631 } 632 633 static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg) 634 { 635 u16 selector; 636 struct desc_struct desc; 637 638 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg); 639 return selector; 640 } 641 642 static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector, 643 unsigned seg) 644 { 645 u16 dummy; 646 u32 base3; 647 struct desc_struct desc; 648 649 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg); 650 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg); 651 } 652 653 /* 654 * x86 defines three classes of vector instructions: explicitly 655 * aligned, explicitly unaligned, and the rest, which change behaviour 656 * depending on whether they're AVX encoded or not. 657 * 658 * Also included is CMPXCHG16B which is not a vector instruction, yet it is 659 * subject to the same check. FXSAVE and FXRSTOR are checked here too as their 660 * 512 bytes of data must be aligned to a 16 byte boundary. 661 */ 662 static unsigned insn_alignment(struct x86_emulate_ctxt *ctxt, unsigned size) 663 { 664 u64 alignment = ctxt->d & AlignMask; 665 666 if (likely(size < 16)) 667 return 1; 668 669 switch (alignment) { 670 case Unaligned: 671 case Avx: 672 return 1; 673 case Aligned16: 674 return 16; 675 case Aligned: 676 default: 677 return size; 678 } 679 } 680 681 static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt, 682 struct segmented_address addr, 683 unsigned *max_size, unsigned size, 684 bool write, bool fetch, 685 enum x86emul_mode mode, ulong *linear) 686 { 687 struct desc_struct desc; 688 bool usable; 689 ulong la; 690 u32 lim; 691 u16 sel; 692 u8 va_bits; 693 694 la = seg_base(ctxt, addr.seg) + addr.ea; 695 *max_size = 0; 696 switch (mode) { 697 case X86EMUL_MODE_PROT64: 698 *linear = la; 699 va_bits = ctxt_virt_addr_bits(ctxt); 700 if (get_canonical(la, va_bits) != la) 701 goto bad; 702 703 *max_size = min_t(u64, ~0u, (1ull << va_bits) - la); 704 if (size > *max_size) 705 goto bad; 706 break; 707 default: 708 *linear = la = (u32)la; 709 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL, 710 addr.seg); 711 if (!usable) 712 goto bad; 713 /* code segment in protected mode or read-only data segment */ 714 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8)) 715 || !(desc.type & 2)) && write) 716 goto bad; 717 /* unreadable code segment */ 718 if (!fetch && (desc.type & 8) && !(desc.type & 2)) 719 goto bad; 720 lim = desc_limit_scaled(&desc); 721 if (!(desc.type & 8) && (desc.type & 4)) { 722 /* expand-down segment */ 723 if (addr.ea <= lim) 724 goto bad; 725 lim = desc.d ? 0xffffffff : 0xffff; 726 } 727 if (addr.ea > lim) 728 goto bad; 729 if (lim == 0xffffffff) 730 *max_size = ~0u; 731 else { 732 *max_size = (u64)lim + 1 - addr.ea; 733 if (size > *max_size) 734 goto bad; 735 } 736 break; 737 } 738 if (la & (insn_alignment(ctxt, size) - 1)) 739 return emulate_gp(ctxt, 0); 740 return X86EMUL_CONTINUE; 741 bad: 742 if (addr.seg == VCPU_SREG_SS) 743 return emulate_ss(ctxt, 0); 744 else 745 return emulate_gp(ctxt, 0); 746 } 747 748 static int linearize(struct x86_emulate_ctxt *ctxt, 749 struct segmented_address addr, 750 unsigned size, bool write, 751 ulong *linear) 752 { 753 unsigned max_size; 754 return __linearize(ctxt, addr, &max_size, size, write, false, 755 ctxt->mode, linear); 756 } 757 758 static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst, 759 enum x86emul_mode mode) 760 { 761 ulong linear; 762 int rc; 763 unsigned max_size; 764 struct segmented_address addr = { .seg = VCPU_SREG_CS, 765 .ea = dst }; 766 767 if (ctxt->op_bytes != sizeof(unsigned long)) 768 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1); 769 rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear); 770 if (rc == X86EMUL_CONTINUE) 771 ctxt->_eip = addr.ea; 772 return rc; 773 } 774 775 static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst) 776 { 777 return assign_eip(ctxt, dst, ctxt->mode); 778 } 779 780 static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst, 781 const struct desc_struct *cs_desc) 782 { 783 enum x86emul_mode mode = ctxt->mode; 784 int rc; 785 786 #ifdef CONFIG_X86_64 787 if (ctxt->mode >= X86EMUL_MODE_PROT16) { 788 if (cs_desc->l) { 789 u64 efer = 0; 790 791 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 792 if (efer & EFER_LMA) 793 mode = X86EMUL_MODE_PROT64; 794 } else 795 mode = X86EMUL_MODE_PROT32; /* temporary value */ 796 } 797 #endif 798 if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32) 799 mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; 800 rc = assign_eip(ctxt, dst, mode); 801 if (rc == X86EMUL_CONTINUE) 802 ctxt->mode = mode; 803 return rc; 804 } 805 806 static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel) 807 { 808 return assign_eip_near(ctxt, ctxt->_eip + rel); 809 } 810 811 static int segmented_read_std(struct x86_emulate_ctxt *ctxt, 812 struct segmented_address addr, 813 void *data, 814 unsigned size) 815 { 816 int rc; 817 ulong linear; 818 819 rc = linearize(ctxt, addr, size, false, &linear); 820 if (rc != X86EMUL_CONTINUE) 821 return rc; 822 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception); 823 } 824 825 static int segmented_write_std(struct x86_emulate_ctxt *ctxt, 826 struct segmented_address addr, 827 void *data, 828 unsigned int size) 829 { 830 int rc; 831 ulong linear; 832 833 rc = linearize(ctxt, addr, size, true, &linear); 834 if (rc != X86EMUL_CONTINUE) 835 return rc; 836 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception); 837 } 838 839 /* 840 * Prefetch the remaining bytes of the instruction without crossing page 841 * boundary if they are not in fetch_cache yet. 842 */ 843 static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size) 844 { 845 int rc; 846 unsigned size, max_size; 847 unsigned long linear; 848 int cur_size = ctxt->fetch.end - ctxt->fetch.data; 849 struct segmented_address addr = { .seg = VCPU_SREG_CS, 850 .ea = ctxt->eip + cur_size }; 851 852 /* 853 * We do not know exactly how many bytes will be needed, and 854 * __linearize is expensive, so fetch as much as possible. We 855 * just have to avoid going beyond the 15 byte limit, the end 856 * of the segment, or the end of the page. 857 * 858 * __linearize is called with size 0 so that it does not do any 859 * boundary check itself. Instead, we use max_size to check 860 * against op_size. 861 */ 862 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode, 863 &linear); 864 if (unlikely(rc != X86EMUL_CONTINUE)) 865 return rc; 866 867 size = min_t(unsigned, 15UL ^ cur_size, max_size); 868 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear)); 869 870 /* 871 * One instruction can only straddle two pages, 872 * and one has been loaded at the beginning of 873 * x86_decode_insn. So, if not enough bytes 874 * still, we must have hit the 15-byte boundary. 875 */ 876 if (unlikely(size < op_size)) 877 return emulate_gp(ctxt, 0); 878 879 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end, 880 size, &ctxt->exception); 881 if (unlikely(rc != X86EMUL_CONTINUE)) 882 return rc; 883 ctxt->fetch.end += size; 884 return X86EMUL_CONTINUE; 885 } 886 887 static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, 888 unsigned size) 889 { 890 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr; 891 892 if (unlikely(done_size < size)) 893 return __do_insn_fetch_bytes(ctxt, size - done_size); 894 else 895 return X86EMUL_CONTINUE; 896 } 897 898 /* Fetch next part of the instruction being emulated. */ 899 #define insn_fetch(_type, _ctxt) \ 900 ({ _type _x; \ 901 \ 902 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \ 903 if (rc != X86EMUL_CONTINUE) \ 904 goto done; \ 905 ctxt->_eip += sizeof(_type); \ 906 memcpy(&_x, ctxt->fetch.ptr, sizeof(_type)); \ 907 ctxt->fetch.ptr += sizeof(_type); \ 908 _x; \ 909 }) 910 911 #define insn_fetch_arr(_arr, _size, _ctxt) \ 912 ({ \ 913 rc = do_insn_fetch_bytes(_ctxt, _size); \ 914 if (rc != X86EMUL_CONTINUE) \ 915 goto done; \ 916 ctxt->_eip += (_size); \ 917 memcpy(_arr, ctxt->fetch.ptr, _size); \ 918 ctxt->fetch.ptr += (_size); \ 919 }) 920 921 /* 922 * Given the 'reg' portion of a ModRM byte, and a register block, return a 923 * pointer into the block that addresses the relevant register. 924 * @highbyte_regs specifies whether to decode AH,CH,DH,BH. 925 */ 926 static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg, 927 int byteop) 928 { 929 void *p; 930 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop; 931 932 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) 933 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1; 934 else 935 p = reg_rmw(ctxt, modrm_reg); 936 return p; 937 } 938 939 static int read_descriptor(struct x86_emulate_ctxt *ctxt, 940 struct segmented_address addr, 941 u16 *size, unsigned long *address, int op_bytes) 942 { 943 int rc; 944 945 if (op_bytes == 2) 946 op_bytes = 3; 947 *address = 0; 948 rc = segmented_read_std(ctxt, addr, size, 2); 949 if (rc != X86EMUL_CONTINUE) 950 return rc; 951 addr.ea += 2; 952 rc = segmented_read_std(ctxt, addr, address, op_bytes); 953 return rc; 954 } 955 956 FASTOP2(add); 957 FASTOP2(or); 958 FASTOP2(adc); 959 FASTOP2(sbb); 960 FASTOP2(and); 961 FASTOP2(sub); 962 FASTOP2(xor); 963 FASTOP2(cmp); 964 FASTOP2(test); 965 966 FASTOP1SRC2(mul, mul_ex); 967 FASTOP1SRC2(imul, imul_ex); 968 FASTOP1SRC2EX(div, div_ex); 969 FASTOP1SRC2EX(idiv, idiv_ex); 970 971 FASTOP3WCL(shld); 972 FASTOP3WCL(shrd); 973 974 FASTOP2W(imul); 975 976 FASTOP1(not); 977 FASTOP1(neg); 978 FASTOP1(inc); 979 FASTOP1(dec); 980 981 FASTOP2CL(rol); 982 FASTOP2CL(ror); 983 FASTOP2CL(rcl); 984 FASTOP2CL(rcr); 985 FASTOP2CL(shl); 986 FASTOP2CL(shr); 987 FASTOP2CL(sar); 988 989 FASTOP2W(bsf); 990 FASTOP2W(bsr); 991 FASTOP2W(bt); 992 FASTOP2W(bts); 993 FASTOP2W(btr); 994 FASTOP2W(btc); 995 996 FASTOP2(xadd); 997 998 FASTOP2R(cmp, cmp_r); 999 1000 static int em_bsf_c(struct x86_emulate_ctxt *ctxt) 1001 { 1002 /* If src is zero, do not writeback, but update flags */ 1003 if (ctxt->src.val == 0) 1004 ctxt->dst.type = OP_NONE; 1005 return fastop(ctxt, em_bsf); 1006 } 1007 1008 static int em_bsr_c(struct x86_emulate_ctxt *ctxt) 1009 { 1010 /* If src is zero, do not writeback, but update flags */ 1011 if (ctxt->src.val == 0) 1012 ctxt->dst.type = OP_NONE; 1013 return fastop(ctxt, em_bsr); 1014 } 1015 1016 static __always_inline u8 test_cc(unsigned int condition, unsigned long flags) 1017 { 1018 u8 rc; 1019 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf); 1020 1021 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF; 1022 asm("push %[flags]; popf; call *%[fastop]" 1023 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags)); 1024 return rc; 1025 } 1026 1027 static void fetch_register_operand(struct operand *op) 1028 { 1029 switch (op->bytes) { 1030 case 1: 1031 op->val = *(u8 *)op->addr.reg; 1032 break; 1033 case 2: 1034 op->val = *(u16 *)op->addr.reg; 1035 break; 1036 case 4: 1037 op->val = *(u32 *)op->addr.reg; 1038 break; 1039 case 8: 1040 op->val = *(u64 *)op->addr.reg; 1041 break; 1042 } 1043 } 1044 1045 static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg) 1046 { 1047 ctxt->ops->get_fpu(ctxt); 1048 switch (reg) { 1049 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break; 1050 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break; 1051 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break; 1052 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break; 1053 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break; 1054 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break; 1055 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break; 1056 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break; 1057 #ifdef CONFIG_X86_64 1058 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break; 1059 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break; 1060 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break; 1061 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break; 1062 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break; 1063 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break; 1064 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break; 1065 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break; 1066 #endif 1067 default: BUG(); 1068 } 1069 ctxt->ops->put_fpu(ctxt); 1070 } 1071 1072 static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, 1073 int reg) 1074 { 1075 ctxt->ops->get_fpu(ctxt); 1076 switch (reg) { 1077 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break; 1078 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break; 1079 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break; 1080 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break; 1081 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break; 1082 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break; 1083 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break; 1084 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break; 1085 #ifdef CONFIG_X86_64 1086 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break; 1087 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break; 1088 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break; 1089 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break; 1090 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break; 1091 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break; 1092 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break; 1093 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break; 1094 #endif 1095 default: BUG(); 1096 } 1097 ctxt->ops->put_fpu(ctxt); 1098 } 1099 1100 static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) 1101 { 1102 ctxt->ops->get_fpu(ctxt); 1103 switch (reg) { 1104 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break; 1105 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break; 1106 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break; 1107 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break; 1108 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break; 1109 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break; 1110 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break; 1111 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break; 1112 default: BUG(); 1113 } 1114 ctxt->ops->put_fpu(ctxt); 1115 } 1116 1117 static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) 1118 { 1119 ctxt->ops->get_fpu(ctxt); 1120 switch (reg) { 1121 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break; 1122 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break; 1123 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break; 1124 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break; 1125 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break; 1126 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break; 1127 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break; 1128 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break; 1129 default: BUG(); 1130 } 1131 ctxt->ops->put_fpu(ctxt); 1132 } 1133 1134 static int em_fninit(struct x86_emulate_ctxt *ctxt) 1135 { 1136 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1137 return emulate_nm(ctxt); 1138 1139 ctxt->ops->get_fpu(ctxt); 1140 asm volatile("fninit"); 1141 ctxt->ops->put_fpu(ctxt); 1142 return X86EMUL_CONTINUE; 1143 } 1144 1145 static int em_fnstcw(struct x86_emulate_ctxt *ctxt) 1146 { 1147 u16 fcw; 1148 1149 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1150 return emulate_nm(ctxt); 1151 1152 ctxt->ops->get_fpu(ctxt); 1153 asm volatile("fnstcw %0": "+m"(fcw)); 1154 ctxt->ops->put_fpu(ctxt); 1155 1156 ctxt->dst.val = fcw; 1157 1158 return X86EMUL_CONTINUE; 1159 } 1160 1161 static int em_fnstsw(struct x86_emulate_ctxt *ctxt) 1162 { 1163 u16 fsw; 1164 1165 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1166 return emulate_nm(ctxt); 1167 1168 ctxt->ops->get_fpu(ctxt); 1169 asm volatile("fnstsw %0": "+m"(fsw)); 1170 ctxt->ops->put_fpu(ctxt); 1171 1172 ctxt->dst.val = fsw; 1173 1174 return X86EMUL_CONTINUE; 1175 } 1176 1177 static void decode_register_operand(struct x86_emulate_ctxt *ctxt, 1178 struct operand *op) 1179 { 1180 unsigned reg = ctxt->modrm_reg; 1181 1182 if (!(ctxt->d & ModRM)) 1183 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3); 1184 1185 if (ctxt->d & Sse) { 1186 op->type = OP_XMM; 1187 op->bytes = 16; 1188 op->addr.xmm = reg; 1189 read_sse_reg(ctxt, &op->vec_val, reg); 1190 return; 1191 } 1192 if (ctxt->d & Mmx) { 1193 reg &= 7; 1194 op->type = OP_MM; 1195 op->bytes = 8; 1196 op->addr.mm = reg; 1197 return; 1198 } 1199 1200 op->type = OP_REG; 1201 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 1202 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp); 1203 1204 fetch_register_operand(op); 1205 op->orig_val = op->val; 1206 } 1207 1208 static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg) 1209 { 1210 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP) 1211 ctxt->modrm_seg = VCPU_SREG_SS; 1212 } 1213 1214 static int decode_modrm(struct x86_emulate_ctxt *ctxt, 1215 struct operand *op) 1216 { 1217 u8 sib; 1218 int index_reg, base_reg, scale; 1219 int rc = X86EMUL_CONTINUE; 1220 ulong modrm_ea = 0; 1221 1222 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */ 1223 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */ 1224 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */ 1225 1226 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6; 1227 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3; 1228 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07); 1229 ctxt->modrm_seg = VCPU_SREG_DS; 1230 1231 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) { 1232 op->type = OP_REG; 1233 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 1234 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, 1235 ctxt->d & ByteOp); 1236 if (ctxt->d & Sse) { 1237 op->type = OP_XMM; 1238 op->bytes = 16; 1239 op->addr.xmm = ctxt->modrm_rm; 1240 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm); 1241 return rc; 1242 } 1243 if (ctxt->d & Mmx) { 1244 op->type = OP_MM; 1245 op->bytes = 8; 1246 op->addr.mm = ctxt->modrm_rm & 7; 1247 return rc; 1248 } 1249 fetch_register_operand(op); 1250 return rc; 1251 } 1252 1253 op->type = OP_MEM; 1254 1255 if (ctxt->ad_bytes == 2) { 1256 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX); 1257 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP); 1258 unsigned si = reg_read(ctxt, VCPU_REGS_RSI); 1259 unsigned di = reg_read(ctxt, VCPU_REGS_RDI); 1260 1261 /* 16-bit ModR/M decode. */ 1262 switch (ctxt->modrm_mod) { 1263 case 0: 1264 if (ctxt->modrm_rm == 6) 1265 modrm_ea += insn_fetch(u16, ctxt); 1266 break; 1267 case 1: 1268 modrm_ea += insn_fetch(s8, ctxt); 1269 break; 1270 case 2: 1271 modrm_ea += insn_fetch(u16, ctxt); 1272 break; 1273 } 1274 switch (ctxt->modrm_rm) { 1275 case 0: 1276 modrm_ea += bx + si; 1277 break; 1278 case 1: 1279 modrm_ea += bx + di; 1280 break; 1281 case 2: 1282 modrm_ea += bp + si; 1283 break; 1284 case 3: 1285 modrm_ea += bp + di; 1286 break; 1287 case 4: 1288 modrm_ea += si; 1289 break; 1290 case 5: 1291 modrm_ea += di; 1292 break; 1293 case 6: 1294 if (ctxt->modrm_mod != 0) 1295 modrm_ea += bp; 1296 break; 1297 case 7: 1298 modrm_ea += bx; 1299 break; 1300 } 1301 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 || 1302 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0)) 1303 ctxt->modrm_seg = VCPU_SREG_SS; 1304 modrm_ea = (u16)modrm_ea; 1305 } else { 1306 /* 32/64-bit ModR/M decode. */ 1307 if ((ctxt->modrm_rm & 7) == 4) { 1308 sib = insn_fetch(u8, ctxt); 1309 index_reg |= (sib >> 3) & 7; 1310 base_reg |= sib & 7; 1311 scale = sib >> 6; 1312 1313 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0) 1314 modrm_ea += insn_fetch(s32, ctxt); 1315 else { 1316 modrm_ea += reg_read(ctxt, base_reg); 1317 adjust_modrm_seg(ctxt, base_reg); 1318 /* Increment ESP on POP [ESP] */ 1319 if ((ctxt->d & IncSP) && 1320 base_reg == VCPU_REGS_RSP) 1321 modrm_ea += ctxt->op_bytes; 1322 } 1323 if (index_reg != 4) 1324 modrm_ea += reg_read(ctxt, index_reg) << scale; 1325 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) { 1326 modrm_ea += insn_fetch(s32, ctxt); 1327 if (ctxt->mode == X86EMUL_MODE_PROT64) 1328 ctxt->rip_relative = 1; 1329 } else { 1330 base_reg = ctxt->modrm_rm; 1331 modrm_ea += reg_read(ctxt, base_reg); 1332 adjust_modrm_seg(ctxt, base_reg); 1333 } 1334 switch (ctxt->modrm_mod) { 1335 case 1: 1336 modrm_ea += insn_fetch(s8, ctxt); 1337 break; 1338 case 2: 1339 modrm_ea += insn_fetch(s32, ctxt); 1340 break; 1341 } 1342 } 1343 op->addr.mem.ea = modrm_ea; 1344 if (ctxt->ad_bytes != 8) 1345 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea; 1346 1347 done: 1348 return rc; 1349 } 1350 1351 static int decode_abs(struct x86_emulate_ctxt *ctxt, 1352 struct operand *op) 1353 { 1354 int rc = X86EMUL_CONTINUE; 1355 1356 op->type = OP_MEM; 1357 switch (ctxt->ad_bytes) { 1358 case 2: 1359 op->addr.mem.ea = insn_fetch(u16, ctxt); 1360 break; 1361 case 4: 1362 op->addr.mem.ea = insn_fetch(u32, ctxt); 1363 break; 1364 case 8: 1365 op->addr.mem.ea = insn_fetch(u64, ctxt); 1366 break; 1367 } 1368 done: 1369 return rc; 1370 } 1371 1372 static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt) 1373 { 1374 long sv = 0, mask; 1375 1376 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) { 1377 mask = ~((long)ctxt->dst.bytes * 8 - 1); 1378 1379 if (ctxt->src.bytes == 2) 1380 sv = (s16)ctxt->src.val & (s16)mask; 1381 else if (ctxt->src.bytes == 4) 1382 sv = (s32)ctxt->src.val & (s32)mask; 1383 else 1384 sv = (s64)ctxt->src.val & (s64)mask; 1385 1386 ctxt->dst.addr.mem.ea = address_mask(ctxt, 1387 ctxt->dst.addr.mem.ea + (sv >> 3)); 1388 } 1389 1390 /* only subword offset */ 1391 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; 1392 } 1393 1394 static int read_emulated(struct x86_emulate_ctxt *ctxt, 1395 unsigned long addr, void *dest, unsigned size) 1396 { 1397 int rc; 1398 struct read_cache *mc = &ctxt->mem_read; 1399 1400 if (mc->pos < mc->end) 1401 goto read_cached; 1402 1403 WARN_ON((mc->end + size) >= sizeof(mc->data)); 1404 1405 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size, 1406 &ctxt->exception); 1407 if (rc != X86EMUL_CONTINUE) 1408 return rc; 1409 1410 mc->end += size; 1411 1412 read_cached: 1413 memcpy(dest, mc->data + mc->pos, size); 1414 mc->pos += size; 1415 return X86EMUL_CONTINUE; 1416 } 1417 1418 static int segmented_read(struct x86_emulate_ctxt *ctxt, 1419 struct segmented_address addr, 1420 void *data, 1421 unsigned size) 1422 { 1423 int rc; 1424 ulong linear; 1425 1426 rc = linearize(ctxt, addr, size, false, &linear); 1427 if (rc != X86EMUL_CONTINUE) 1428 return rc; 1429 return read_emulated(ctxt, linear, data, size); 1430 } 1431 1432 static int segmented_write(struct x86_emulate_ctxt *ctxt, 1433 struct segmented_address addr, 1434 const void *data, 1435 unsigned size) 1436 { 1437 int rc; 1438 ulong linear; 1439 1440 rc = linearize(ctxt, addr, size, true, &linear); 1441 if (rc != X86EMUL_CONTINUE) 1442 return rc; 1443 return ctxt->ops->write_emulated(ctxt, linear, data, size, 1444 &ctxt->exception); 1445 } 1446 1447 static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt, 1448 struct segmented_address addr, 1449 const void *orig_data, const void *data, 1450 unsigned size) 1451 { 1452 int rc; 1453 ulong linear; 1454 1455 rc = linearize(ctxt, addr, size, true, &linear); 1456 if (rc != X86EMUL_CONTINUE) 1457 return rc; 1458 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data, 1459 size, &ctxt->exception); 1460 } 1461 1462 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, 1463 unsigned int size, unsigned short port, 1464 void *dest) 1465 { 1466 struct read_cache *rc = &ctxt->io_read; 1467 1468 if (rc->pos == rc->end) { /* refill pio read ahead */ 1469 unsigned int in_page, n; 1470 unsigned int count = ctxt->rep_prefix ? 1471 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1; 1472 in_page = (ctxt->eflags & X86_EFLAGS_DF) ? 1473 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) : 1474 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)); 1475 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count); 1476 if (n == 0) 1477 n = 1; 1478 rc->pos = rc->end = 0; 1479 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n)) 1480 return 0; 1481 rc->end = n * size; 1482 } 1483 1484 if (ctxt->rep_prefix && (ctxt->d & String) && 1485 !(ctxt->eflags & X86_EFLAGS_DF)) { 1486 ctxt->dst.data = rc->data + rc->pos; 1487 ctxt->dst.type = OP_MEM_STR; 1488 ctxt->dst.count = (rc->end - rc->pos) / size; 1489 rc->pos = rc->end; 1490 } else { 1491 memcpy(dest, rc->data + rc->pos, size); 1492 rc->pos += size; 1493 } 1494 return 1; 1495 } 1496 1497 static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt, 1498 u16 index, struct desc_struct *desc) 1499 { 1500 struct desc_ptr dt; 1501 ulong addr; 1502 1503 ctxt->ops->get_idt(ctxt, &dt); 1504 1505 if (dt.size < index * 8 + 7) 1506 return emulate_gp(ctxt, index << 3 | 0x2); 1507 1508 addr = dt.address + index * 8; 1509 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc, 1510 &ctxt->exception); 1511 } 1512 1513 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, 1514 u16 selector, struct desc_ptr *dt) 1515 { 1516 const struct x86_emulate_ops *ops = ctxt->ops; 1517 u32 base3 = 0; 1518 1519 if (selector & 1 << 2) { 1520 struct desc_struct desc; 1521 u16 sel; 1522 1523 memset (dt, 0, sizeof *dt); 1524 if (!ops->get_segment(ctxt, &sel, &desc, &base3, 1525 VCPU_SREG_LDTR)) 1526 return; 1527 1528 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ 1529 dt->address = get_desc_base(&desc) | ((u64)base3 << 32); 1530 } else 1531 ops->get_gdt(ctxt, dt); 1532 } 1533 1534 static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt, 1535 u16 selector, ulong *desc_addr_p) 1536 { 1537 struct desc_ptr dt; 1538 u16 index = selector >> 3; 1539 ulong addr; 1540 1541 get_descriptor_table_ptr(ctxt, selector, &dt); 1542 1543 if (dt.size < index * 8 + 7) 1544 return emulate_gp(ctxt, selector & 0xfffc); 1545 1546 addr = dt.address + index * 8; 1547 1548 #ifdef CONFIG_X86_64 1549 if (addr >> 32 != 0) { 1550 u64 efer = 0; 1551 1552 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 1553 if (!(efer & EFER_LMA)) 1554 addr &= (u32)-1; 1555 } 1556 #endif 1557 1558 *desc_addr_p = addr; 1559 return X86EMUL_CONTINUE; 1560 } 1561 1562 /* allowed just for 8 bytes segments */ 1563 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1564 u16 selector, struct desc_struct *desc, 1565 ulong *desc_addr_p) 1566 { 1567 int rc; 1568 1569 rc = get_descriptor_ptr(ctxt, selector, desc_addr_p); 1570 if (rc != X86EMUL_CONTINUE) 1571 return rc; 1572 1573 return ctxt->ops->read_std(ctxt, *desc_addr_p, desc, sizeof(*desc), 1574 &ctxt->exception); 1575 } 1576 1577 /* allowed just for 8 bytes segments */ 1578 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1579 u16 selector, struct desc_struct *desc) 1580 { 1581 int rc; 1582 ulong addr; 1583 1584 rc = get_descriptor_ptr(ctxt, selector, &addr); 1585 if (rc != X86EMUL_CONTINUE) 1586 return rc; 1587 1588 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc, 1589 &ctxt->exception); 1590 } 1591 1592 static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1593 u16 selector, int seg, u8 cpl, 1594 enum x86_transfer_type transfer, 1595 struct desc_struct *desc) 1596 { 1597 struct desc_struct seg_desc, old_desc; 1598 u8 dpl, rpl; 1599 unsigned err_vec = GP_VECTOR; 1600 u32 err_code = 0; 1601 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ 1602 ulong desc_addr; 1603 int ret; 1604 u16 dummy; 1605 u32 base3 = 0; 1606 1607 memset(&seg_desc, 0, sizeof seg_desc); 1608 1609 if (ctxt->mode == X86EMUL_MODE_REAL) { 1610 /* set real mode segment descriptor (keep limit etc. for 1611 * unreal mode) */ 1612 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg); 1613 set_desc_base(&seg_desc, selector << 4); 1614 goto load; 1615 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) { 1616 /* VM86 needs a clean new segment descriptor */ 1617 set_desc_base(&seg_desc, selector << 4); 1618 set_desc_limit(&seg_desc, 0xffff); 1619 seg_desc.type = 3; 1620 seg_desc.p = 1; 1621 seg_desc.s = 1; 1622 seg_desc.dpl = 3; 1623 goto load; 1624 } 1625 1626 rpl = selector & 3; 1627 1628 /* TR should be in GDT only */ 1629 if (seg == VCPU_SREG_TR && (selector & (1 << 2))) 1630 goto exception; 1631 1632 /* NULL selector is not valid for TR, CS and (except for long mode) SS */ 1633 if (null_selector) { 1634 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_TR) 1635 goto exception; 1636 1637 if (seg == VCPU_SREG_SS) { 1638 if (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl) 1639 goto exception; 1640 1641 /* 1642 * ctxt->ops->set_segment expects the CPL to be in 1643 * SS.DPL, so fake an expand-up 32-bit data segment. 1644 */ 1645 seg_desc.type = 3; 1646 seg_desc.p = 1; 1647 seg_desc.s = 1; 1648 seg_desc.dpl = cpl; 1649 seg_desc.d = 1; 1650 seg_desc.g = 1; 1651 } 1652 1653 /* Skip all following checks */ 1654 goto load; 1655 } 1656 1657 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr); 1658 if (ret != X86EMUL_CONTINUE) 1659 return ret; 1660 1661 err_code = selector & 0xfffc; 1662 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR : 1663 GP_VECTOR; 1664 1665 /* can't load system descriptor into segment selector */ 1666 if (seg <= VCPU_SREG_GS && !seg_desc.s) { 1667 if (transfer == X86_TRANSFER_CALL_JMP) 1668 return X86EMUL_UNHANDLEABLE; 1669 goto exception; 1670 } 1671 1672 if (!seg_desc.p) { 1673 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; 1674 goto exception; 1675 } 1676 1677 dpl = seg_desc.dpl; 1678 1679 switch (seg) { 1680 case VCPU_SREG_SS: 1681 /* 1682 * segment is not a writable data segment or segment 1683 * selector's RPL != CPL or segment selector's RPL != CPL 1684 */ 1685 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) 1686 goto exception; 1687 break; 1688 case VCPU_SREG_CS: 1689 if (!(seg_desc.type & 8)) 1690 goto exception; 1691 1692 if (seg_desc.type & 4) { 1693 /* conforming */ 1694 if (dpl > cpl) 1695 goto exception; 1696 } else { 1697 /* nonconforming */ 1698 if (rpl > cpl || dpl != cpl) 1699 goto exception; 1700 } 1701 /* in long-mode d/b must be clear if l is set */ 1702 if (seg_desc.d && seg_desc.l) { 1703 u64 efer = 0; 1704 1705 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 1706 if (efer & EFER_LMA) 1707 goto exception; 1708 } 1709 1710 /* CS(RPL) <- CPL */ 1711 selector = (selector & 0xfffc) | cpl; 1712 break; 1713 case VCPU_SREG_TR: 1714 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) 1715 goto exception; 1716 old_desc = seg_desc; 1717 seg_desc.type |= 2; /* busy */ 1718 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc, 1719 sizeof(seg_desc), &ctxt->exception); 1720 if (ret != X86EMUL_CONTINUE) 1721 return ret; 1722 break; 1723 case VCPU_SREG_LDTR: 1724 if (seg_desc.s || seg_desc.type != 2) 1725 goto exception; 1726 break; 1727 default: /* DS, ES, FS, or GS */ 1728 /* 1729 * segment is not a data or readable code segment or 1730 * ((segment is a data or nonconforming code segment) 1731 * and (both RPL and CPL > DPL)) 1732 */ 1733 if ((seg_desc.type & 0xa) == 0x8 || 1734 (((seg_desc.type & 0xc) != 0xc) && 1735 (rpl > dpl && cpl > dpl))) 1736 goto exception; 1737 break; 1738 } 1739 1740 if (seg_desc.s) { 1741 /* mark segment as accessed */ 1742 if (!(seg_desc.type & 1)) { 1743 seg_desc.type |= 1; 1744 ret = write_segment_descriptor(ctxt, selector, 1745 &seg_desc); 1746 if (ret != X86EMUL_CONTINUE) 1747 return ret; 1748 } 1749 } else if (ctxt->mode == X86EMUL_MODE_PROT64) { 1750 ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3, 1751 sizeof(base3), &ctxt->exception); 1752 if (ret != X86EMUL_CONTINUE) 1753 return ret; 1754 if (emul_is_noncanonical_address(get_desc_base(&seg_desc) | 1755 ((u64)base3 << 32), ctxt)) 1756 return emulate_gp(ctxt, 0); 1757 } 1758 load: 1759 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg); 1760 if (desc) 1761 *desc = seg_desc; 1762 return X86EMUL_CONTINUE; 1763 exception: 1764 return emulate_exception(ctxt, err_vec, err_code, true); 1765 } 1766 1767 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1768 u16 selector, int seg) 1769 { 1770 u8 cpl = ctxt->ops->cpl(ctxt); 1771 1772 /* 1773 * None of MOV, POP and LSS can load a NULL selector in CPL=3, but 1774 * they can load it at CPL<3 (Intel's manual says only LSS can, 1775 * but it's wrong). 1776 * 1777 * However, the Intel manual says that putting IST=1/DPL=3 in 1778 * an interrupt gate will result in SS=3 (the AMD manual instead 1779 * says it doesn't), so allow SS=3 in __load_segment_descriptor 1780 * and only forbid it here. 1781 */ 1782 if (seg == VCPU_SREG_SS && selector == 3 && 1783 ctxt->mode == X86EMUL_MODE_PROT64) 1784 return emulate_exception(ctxt, GP_VECTOR, 0, true); 1785 1786 return __load_segment_descriptor(ctxt, selector, seg, cpl, 1787 X86_TRANSFER_NONE, NULL); 1788 } 1789 1790 static void write_register_operand(struct operand *op) 1791 { 1792 return assign_register(op->addr.reg, op->val, op->bytes); 1793 } 1794 1795 static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op) 1796 { 1797 switch (op->type) { 1798 case OP_REG: 1799 write_register_operand(op); 1800 break; 1801 case OP_MEM: 1802 if (ctxt->lock_prefix) 1803 return segmented_cmpxchg(ctxt, 1804 op->addr.mem, 1805 &op->orig_val, 1806 &op->val, 1807 op->bytes); 1808 else 1809 return segmented_write(ctxt, 1810 op->addr.mem, 1811 &op->val, 1812 op->bytes); 1813 break; 1814 case OP_MEM_STR: 1815 return segmented_write(ctxt, 1816 op->addr.mem, 1817 op->data, 1818 op->bytes * op->count); 1819 break; 1820 case OP_XMM: 1821 write_sse_reg(ctxt, &op->vec_val, op->addr.xmm); 1822 break; 1823 case OP_MM: 1824 write_mmx_reg(ctxt, &op->mm_val, op->addr.mm); 1825 break; 1826 case OP_NONE: 1827 /* no writeback */ 1828 break; 1829 default: 1830 break; 1831 } 1832 return X86EMUL_CONTINUE; 1833 } 1834 1835 static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes) 1836 { 1837 struct segmented_address addr; 1838 1839 rsp_increment(ctxt, -bytes); 1840 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); 1841 addr.seg = VCPU_SREG_SS; 1842 1843 return segmented_write(ctxt, addr, data, bytes); 1844 } 1845 1846 static int em_push(struct x86_emulate_ctxt *ctxt) 1847 { 1848 /* Disable writeback. */ 1849 ctxt->dst.type = OP_NONE; 1850 return push(ctxt, &ctxt->src.val, ctxt->op_bytes); 1851 } 1852 1853 static int emulate_pop(struct x86_emulate_ctxt *ctxt, 1854 void *dest, int len) 1855 { 1856 int rc; 1857 struct segmented_address addr; 1858 1859 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); 1860 addr.seg = VCPU_SREG_SS; 1861 rc = segmented_read(ctxt, addr, dest, len); 1862 if (rc != X86EMUL_CONTINUE) 1863 return rc; 1864 1865 rsp_increment(ctxt, len); 1866 return rc; 1867 } 1868 1869 static int em_pop(struct x86_emulate_ctxt *ctxt) 1870 { 1871 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1872 } 1873 1874 static int emulate_popf(struct x86_emulate_ctxt *ctxt, 1875 void *dest, int len) 1876 { 1877 int rc; 1878 unsigned long val, change_mask; 1879 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT; 1880 int cpl = ctxt->ops->cpl(ctxt); 1881 1882 rc = emulate_pop(ctxt, &val, len); 1883 if (rc != X86EMUL_CONTINUE) 1884 return rc; 1885 1886 change_mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | 1887 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF | 1888 X86_EFLAGS_TF | X86_EFLAGS_DF | X86_EFLAGS_NT | 1889 X86_EFLAGS_AC | X86_EFLAGS_ID; 1890 1891 switch(ctxt->mode) { 1892 case X86EMUL_MODE_PROT64: 1893 case X86EMUL_MODE_PROT32: 1894 case X86EMUL_MODE_PROT16: 1895 if (cpl == 0) 1896 change_mask |= X86_EFLAGS_IOPL; 1897 if (cpl <= iopl) 1898 change_mask |= X86_EFLAGS_IF; 1899 break; 1900 case X86EMUL_MODE_VM86: 1901 if (iopl < 3) 1902 return emulate_gp(ctxt, 0); 1903 change_mask |= X86_EFLAGS_IF; 1904 break; 1905 default: /* real mode */ 1906 change_mask |= (X86_EFLAGS_IOPL | X86_EFLAGS_IF); 1907 break; 1908 } 1909 1910 *(unsigned long *)dest = 1911 (ctxt->eflags & ~change_mask) | (val & change_mask); 1912 1913 return rc; 1914 } 1915 1916 static int em_popf(struct x86_emulate_ctxt *ctxt) 1917 { 1918 ctxt->dst.type = OP_REG; 1919 ctxt->dst.addr.reg = &ctxt->eflags; 1920 ctxt->dst.bytes = ctxt->op_bytes; 1921 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1922 } 1923 1924 static int em_enter(struct x86_emulate_ctxt *ctxt) 1925 { 1926 int rc; 1927 unsigned frame_size = ctxt->src.val; 1928 unsigned nesting_level = ctxt->src2.val & 31; 1929 ulong rbp; 1930 1931 if (nesting_level) 1932 return X86EMUL_UNHANDLEABLE; 1933 1934 rbp = reg_read(ctxt, VCPU_REGS_RBP); 1935 rc = push(ctxt, &rbp, stack_size(ctxt)); 1936 if (rc != X86EMUL_CONTINUE) 1937 return rc; 1938 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP), 1939 stack_mask(ctxt)); 1940 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), 1941 reg_read(ctxt, VCPU_REGS_RSP) - frame_size, 1942 stack_mask(ctxt)); 1943 return X86EMUL_CONTINUE; 1944 } 1945 1946 static int em_leave(struct x86_emulate_ctxt *ctxt) 1947 { 1948 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP), 1949 stack_mask(ctxt)); 1950 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes); 1951 } 1952 1953 static int em_push_sreg(struct x86_emulate_ctxt *ctxt) 1954 { 1955 int seg = ctxt->src2.val; 1956 1957 ctxt->src.val = get_segment_selector(ctxt, seg); 1958 if (ctxt->op_bytes == 4) { 1959 rsp_increment(ctxt, -2); 1960 ctxt->op_bytes = 2; 1961 } 1962 1963 return em_push(ctxt); 1964 } 1965 1966 static int em_pop_sreg(struct x86_emulate_ctxt *ctxt) 1967 { 1968 int seg = ctxt->src2.val; 1969 unsigned long selector; 1970 int rc; 1971 1972 rc = emulate_pop(ctxt, &selector, 2); 1973 if (rc != X86EMUL_CONTINUE) 1974 return rc; 1975 1976 if (ctxt->modrm_reg == VCPU_SREG_SS) 1977 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; 1978 if (ctxt->op_bytes > 2) 1979 rsp_increment(ctxt, ctxt->op_bytes - 2); 1980 1981 rc = load_segment_descriptor(ctxt, (u16)selector, seg); 1982 return rc; 1983 } 1984 1985 static int em_pusha(struct x86_emulate_ctxt *ctxt) 1986 { 1987 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP); 1988 int rc = X86EMUL_CONTINUE; 1989 int reg = VCPU_REGS_RAX; 1990 1991 while (reg <= VCPU_REGS_RDI) { 1992 (reg == VCPU_REGS_RSP) ? 1993 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg)); 1994 1995 rc = em_push(ctxt); 1996 if (rc != X86EMUL_CONTINUE) 1997 return rc; 1998 1999 ++reg; 2000 } 2001 2002 return rc; 2003 } 2004 2005 static int em_pushf(struct x86_emulate_ctxt *ctxt) 2006 { 2007 ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM; 2008 return em_push(ctxt); 2009 } 2010 2011 static int em_popa(struct x86_emulate_ctxt *ctxt) 2012 { 2013 int rc = X86EMUL_CONTINUE; 2014 int reg = VCPU_REGS_RDI; 2015 u32 val; 2016 2017 while (reg >= VCPU_REGS_RAX) { 2018 if (reg == VCPU_REGS_RSP) { 2019 rsp_increment(ctxt, ctxt->op_bytes); 2020 --reg; 2021 } 2022 2023 rc = emulate_pop(ctxt, &val, ctxt->op_bytes); 2024 if (rc != X86EMUL_CONTINUE) 2025 break; 2026 assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes); 2027 --reg; 2028 } 2029 return rc; 2030 } 2031 2032 static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) 2033 { 2034 const struct x86_emulate_ops *ops = ctxt->ops; 2035 int rc; 2036 struct desc_ptr dt; 2037 gva_t cs_addr; 2038 gva_t eip_addr; 2039 u16 cs, eip; 2040 2041 /* TODO: Add limit checks */ 2042 ctxt->src.val = ctxt->eflags; 2043 rc = em_push(ctxt); 2044 if (rc != X86EMUL_CONTINUE) 2045 return rc; 2046 2047 ctxt->eflags &= ~(X86_EFLAGS_IF | X86_EFLAGS_TF | X86_EFLAGS_AC); 2048 2049 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS); 2050 rc = em_push(ctxt); 2051 if (rc != X86EMUL_CONTINUE) 2052 return rc; 2053 2054 ctxt->src.val = ctxt->_eip; 2055 rc = em_push(ctxt); 2056 if (rc != X86EMUL_CONTINUE) 2057 return rc; 2058 2059 ops->get_idt(ctxt, &dt); 2060 2061 eip_addr = dt.address + (irq << 2); 2062 cs_addr = dt.address + (irq << 2) + 2; 2063 2064 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception); 2065 if (rc != X86EMUL_CONTINUE) 2066 return rc; 2067 2068 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception); 2069 if (rc != X86EMUL_CONTINUE) 2070 return rc; 2071 2072 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS); 2073 if (rc != X86EMUL_CONTINUE) 2074 return rc; 2075 2076 ctxt->_eip = eip; 2077 2078 return rc; 2079 } 2080 2081 int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) 2082 { 2083 int rc; 2084 2085 invalidate_registers(ctxt); 2086 rc = __emulate_int_real(ctxt, irq); 2087 if (rc == X86EMUL_CONTINUE) 2088 writeback_registers(ctxt); 2089 return rc; 2090 } 2091 2092 static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq) 2093 { 2094 switch(ctxt->mode) { 2095 case X86EMUL_MODE_REAL: 2096 return __emulate_int_real(ctxt, irq); 2097 case X86EMUL_MODE_VM86: 2098 case X86EMUL_MODE_PROT16: 2099 case X86EMUL_MODE_PROT32: 2100 case X86EMUL_MODE_PROT64: 2101 default: 2102 /* Protected mode interrupts unimplemented yet */ 2103 return X86EMUL_UNHANDLEABLE; 2104 } 2105 } 2106 2107 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt) 2108 { 2109 int rc = X86EMUL_CONTINUE; 2110 unsigned long temp_eip = 0; 2111 unsigned long temp_eflags = 0; 2112 unsigned long cs = 0; 2113 unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | 2114 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_TF | 2115 X86_EFLAGS_IF | X86_EFLAGS_DF | X86_EFLAGS_OF | 2116 X86_EFLAGS_IOPL | X86_EFLAGS_NT | X86_EFLAGS_RF | 2117 X86_EFLAGS_AC | X86_EFLAGS_ID | 2118 X86_EFLAGS_FIXED; 2119 unsigned long vm86_mask = X86_EFLAGS_VM | X86_EFLAGS_VIF | 2120 X86_EFLAGS_VIP; 2121 2122 /* TODO: Add stack limit check */ 2123 2124 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes); 2125 2126 if (rc != X86EMUL_CONTINUE) 2127 return rc; 2128 2129 if (temp_eip & ~0xffff) 2130 return emulate_gp(ctxt, 0); 2131 2132 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 2133 2134 if (rc != X86EMUL_CONTINUE) 2135 return rc; 2136 2137 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes); 2138 2139 if (rc != X86EMUL_CONTINUE) 2140 return rc; 2141 2142 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); 2143 2144 if (rc != X86EMUL_CONTINUE) 2145 return rc; 2146 2147 ctxt->_eip = temp_eip; 2148 2149 if (ctxt->op_bytes == 4) 2150 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); 2151 else if (ctxt->op_bytes == 2) { 2152 ctxt->eflags &= ~0xffff; 2153 ctxt->eflags |= temp_eflags; 2154 } 2155 2156 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ 2157 ctxt->eflags |= X86_EFLAGS_FIXED; 2158 ctxt->ops->set_nmi_mask(ctxt, false); 2159 2160 return rc; 2161 } 2162 2163 static int em_iret(struct x86_emulate_ctxt *ctxt) 2164 { 2165 switch(ctxt->mode) { 2166 case X86EMUL_MODE_REAL: 2167 return emulate_iret_real(ctxt); 2168 case X86EMUL_MODE_VM86: 2169 case X86EMUL_MODE_PROT16: 2170 case X86EMUL_MODE_PROT32: 2171 case X86EMUL_MODE_PROT64: 2172 default: 2173 /* iret from protected mode unimplemented yet */ 2174 return X86EMUL_UNHANDLEABLE; 2175 } 2176 } 2177 2178 static int em_jmp_far(struct x86_emulate_ctxt *ctxt) 2179 { 2180 int rc; 2181 unsigned short sel; 2182 struct desc_struct new_desc; 2183 u8 cpl = ctxt->ops->cpl(ctxt); 2184 2185 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2186 2187 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, 2188 X86_TRANSFER_CALL_JMP, 2189 &new_desc); 2190 if (rc != X86EMUL_CONTINUE) 2191 return rc; 2192 2193 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc); 2194 /* Error handling is not implemented. */ 2195 if (rc != X86EMUL_CONTINUE) 2196 return X86EMUL_UNHANDLEABLE; 2197 2198 return rc; 2199 } 2200 2201 static int em_jmp_abs(struct x86_emulate_ctxt *ctxt) 2202 { 2203 return assign_eip_near(ctxt, ctxt->src.val); 2204 } 2205 2206 static int em_call_near_abs(struct x86_emulate_ctxt *ctxt) 2207 { 2208 int rc; 2209 long int old_eip; 2210 2211 old_eip = ctxt->_eip; 2212 rc = assign_eip_near(ctxt, ctxt->src.val); 2213 if (rc != X86EMUL_CONTINUE) 2214 return rc; 2215 ctxt->src.val = old_eip; 2216 rc = em_push(ctxt); 2217 return rc; 2218 } 2219 2220 static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt) 2221 { 2222 u64 old = ctxt->dst.orig_val64; 2223 2224 if (ctxt->dst.bytes == 16) 2225 return X86EMUL_UNHANDLEABLE; 2226 2227 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) || 2228 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) { 2229 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0); 2230 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32); 2231 ctxt->eflags &= ~X86_EFLAGS_ZF; 2232 } else { 2233 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) | 2234 (u32) reg_read(ctxt, VCPU_REGS_RBX); 2235 2236 ctxt->eflags |= X86_EFLAGS_ZF; 2237 } 2238 return X86EMUL_CONTINUE; 2239 } 2240 2241 static int em_ret(struct x86_emulate_ctxt *ctxt) 2242 { 2243 int rc; 2244 unsigned long eip; 2245 2246 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 2247 if (rc != X86EMUL_CONTINUE) 2248 return rc; 2249 2250 return assign_eip_near(ctxt, eip); 2251 } 2252 2253 static int em_ret_far(struct x86_emulate_ctxt *ctxt) 2254 { 2255 int rc; 2256 unsigned long eip, cs; 2257 int cpl = ctxt->ops->cpl(ctxt); 2258 struct desc_struct new_desc; 2259 2260 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 2261 if (rc != X86EMUL_CONTINUE) 2262 return rc; 2263 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 2264 if (rc != X86EMUL_CONTINUE) 2265 return rc; 2266 /* Outer-privilege level return is not implemented */ 2267 if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl) 2268 return X86EMUL_UNHANDLEABLE; 2269 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl, 2270 X86_TRANSFER_RET, 2271 &new_desc); 2272 if (rc != X86EMUL_CONTINUE) 2273 return rc; 2274 rc = assign_eip_far(ctxt, eip, &new_desc); 2275 /* Error handling is not implemented. */ 2276 if (rc != X86EMUL_CONTINUE) 2277 return X86EMUL_UNHANDLEABLE; 2278 2279 return rc; 2280 } 2281 2282 static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt) 2283 { 2284 int rc; 2285 2286 rc = em_ret_far(ctxt); 2287 if (rc != X86EMUL_CONTINUE) 2288 return rc; 2289 rsp_increment(ctxt, ctxt->src.val); 2290 return X86EMUL_CONTINUE; 2291 } 2292 2293 static int em_cmpxchg(struct x86_emulate_ctxt *ctxt) 2294 { 2295 /* Save real source value, then compare EAX against destination. */ 2296 ctxt->dst.orig_val = ctxt->dst.val; 2297 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX); 2298 ctxt->src.orig_val = ctxt->src.val; 2299 ctxt->src.val = ctxt->dst.orig_val; 2300 fastop(ctxt, em_cmp); 2301 2302 if (ctxt->eflags & X86_EFLAGS_ZF) { 2303 /* Success: write back to memory; no update of EAX */ 2304 ctxt->src.type = OP_NONE; 2305 ctxt->dst.val = ctxt->src.orig_val; 2306 } else { 2307 /* Failure: write the value we saw to EAX. */ 2308 ctxt->src.type = OP_REG; 2309 ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 2310 ctxt->src.val = ctxt->dst.orig_val; 2311 /* Create write-cycle to dest by writing the same value */ 2312 ctxt->dst.val = ctxt->dst.orig_val; 2313 } 2314 return X86EMUL_CONTINUE; 2315 } 2316 2317 static int em_lseg(struct x86_emulate_ctxt *ctxt) 2318 { 2319 int seg = ctxt->src2.val; 2320 unsigned short sel; 2321 int rc; 2322 2323 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2324 2325 rc = load_segment_descriptor(ctxt, sel, seg); 2326 if (rc != X86EMUL_CONTINUE) 2327 return rc; 2328 2329 ctxt->dst.val = ctxt->src.val; 2330 return rc; 2331 } 2332 2333 static int emulator_has_longmode(struct x86_emulate_ctxt *ctxt) 2334 { 2335 u32 eax, ebx, ecx, edx; 2336 2337 eax = 0x80000001; 2338 ecx = 0; 2339 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false); 2340 return edx & bit(X86_FEATURE_LM); 2341 } 2342 2343 #define GET_SMSTATE(type, smbase, offset) \ 2344 ({ \ 2345 type __val; \ 2346 int r = ctxt->ops->read_phys(ctxt, smbase + offset, &__val, \ 2347 sizeof(__val)); \ 2348 if (r != X86EMUL_CONTINUE) \ 2349 return X86EMUL_UNHANDLEABLE; \ 2350 __val; \ 2351 }) 2352 2353 static void rsm_set_desc_flags(struct desc_struct *desc, u32 flags) 2354 { 2355 desc->g = (flags >> 23) & 1; 2356 desc->d = (flags >> 22) & 1; 2357 desc->l = (flags >> 21) & 1; 2358 desc->avl = (flags >> 20) & 1; 2359 desc->p = (flags >> 15) & 1; 2360 desc->dpl = (flags >> 13) & 3; 2361 desc->s = (flags >> 12) & 1; 2362 desc->type = (flags >> 8) & 15; 2363 } 2364 2365 static int rsm_load_seg_32(struct x86_emulate_ctxt *ctxt, u64 smbase, int n) 2366 { 2367 struct desc_struct desc; 2368 int offset; 2369 u16 selector; 2370 2371 selector = GET_SMSTATE(u32, smbase, 0x7fa8 + n * 4); 2372 2373 if (n < 3) 2374 offset = 0x7f84 + n * 12; 2375 else 2376 offset = 0x7f2c + (n - 3) * 12; 2377 2378 set_desc_base(&desc, GET_SMSTATE(u32, smbase, offset + 8)); 2379 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, offset + 4)); 2380 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, offset)); 2381 ctxt->ops->set_segment(ctxt, selector, &desc, 0, n); 2382 return X86EMUL_CONTINUE; 2383 } 2384 2385 static int rsm_load_seg_64(struct x86_emulate_ctxt *ctxt, u64 smbase, int n) 2386 { 2387 struct desc_struct desc; 2388 int offset; 2389 u16 selector; 2390 u32 base3; 2391 2392 offset = 0x7e00 + n * 16; 2393 2394 selector = GET_SMSTATE(u16, smbase, offset); 2395 rsm_set_desc_flags(&desc, GET_SMSTATE(u16, smbase, offset + 2) << 8); 2396 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, offset + 4)); 2397 set_desc_base(&desc, GET_SMSTATE(u32, smbase, offset + 8)); 2398 base3 = GET_SMSTATE(u32, smbase, offset + 12); 2399 2400 ctxt->ops->set_segment(ctxt, selector, &desc, base3, n); 2401 return X86EMUL_CONTINUE; 2402 } 2403 2404 static int rsm_enter_protected_mode(struct x86_emulate_ctxt *ctxt, 2405 u64 cr0, u64 cr4) 2406 { 2407 int bad; 2408 2409 /* 2410 * First enable PAE, long mode needs it before CR0.PG = 1 is set. 2411 * Then enable protected mode. However, PCID cannot be enabled 2412 * if EFER.LMA=0, so set it separately. 2413 */ 2414 bad = ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE); 2415 if (bad) 2416 return X86EMUL_UNHANDLEABLE; 2417 2418 bad = ctxt->ops->set_cr(ctxt, 0, cr0); 2419 if (bad) 2420 return X86EMUL_UNHANDLEABLE; 2421 2422 if (cr4 & X86_CR4_PCIDE) { 2423 bad = ctxt->ops->set_cr(ctxt, 4, cr4); 2424 if (bad) 2425 return X86EMUL_UNHANDLEABLE; 2426 } 2427 2428 return X86EMUL_CONTINUE; 2429 } 2430 2431 static int rsm_load_state_32(struct x86_emulate_ctxt *ctxt, u64 smbase) 2432 { 2433 struct desc_struct desc; 2434 struct desc_ptr dt; 2435 u16 selector; 2436 u32 val, cr0, cr4; 2437 int i; 2438 2439 cr0 = GET_SMSTATE(u32, smbase, 0x7ffc); 2440 ctxt->ops->set_cr(ctxt, 3, GET_SMSTATE(u32, smbase, 0x7ff8)); 2441 ctxt->eflags = GET_SMSTATE(u32, smbase, 0x7ff4) | X86_EFLAGS_FIXED; 2442 ctxt->_eip = GET_SMSTATE(u32, smbase, 0x7ff0); 2443 2444 for (i = 0; i < 8; i++) 2445 *reg_write(ctxt, i) = GET_SMSTATE(u32, smbase, 0x7fd0 + i * 4); 2446 2447 val = GET_SMSTATE(u32, smbase, 0x7fcc); 2448 ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1); 2449 val = GET_SMSTATE(u32, smbase, 0x7fc8); 2450 ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1); 2451 2452 selector = GET_SMSTATE(u32, smbase, 0x7fc4); 2453 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7f64)); 2454 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7f60)); 2455 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7f5c)); 2456 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_TR); 2457 2458 selector = GET_SMSTATE(u32, smbase, 0x7fc0); 2459 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7f80)); 2460 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7f7c)); 2461 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7f78)); 2462 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_LDTR); 2463 2464 dt.address = GET_SMSTATE(u32, smbase, 0x7f74); 2465 dt.size = GET_SMSTATE(u32, smbase, 0x7f70); 2466 ctxt->ops->set_gdt(ctxt, &dt); 2467 2468 dt.address = GET_SMSTATE(u32, smbase, 0x7f58); 2469 dt.size = GET_SMSTATE(u32, smbase, 0x7f54); 2470 ctxt->ops->set_idt(ctxt, &dt); 2471 2472 for (i = 0; i < 6; i++) { 2473 int r = rsm_load_seg_32(ctxt, smbase, i); 2474 if (r != X86EMUL_CONTINUE) 2475 return r; 2476 } 2477 2478 cr4 = GET_SMSTATE(u32, smbase, 0x7f14); 2479 2480 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smbase, 0x7ef8)); 2481 2482 return rsm_enter_protected_mode(ctxt, cr0, cr4); 2483 } 2484 2485 static int rsm_load_state_64(struct x86_emulate_ctxt *ctxt, u64 smbase) 2486 { 2487 struct desc_struct desc; 2488 struct desc_ptr dt; 2489 u64 val, cr0, cr4; 2490 u32 base3; 2491 u16 selector; 2492 int i, r; 2493 2494 for (i = 0; i < 16; i++) 2495 *reg_write(ctxt, i) = GET_SMSTATE(u64, smbase, 0x7ff8 - i * 8); 2496 2497 ctxt->_eip = GET_SMSTATE(u64, smbase, 0x7f78); 2498 ctxt->eflags = GET_SMSTATE(u32, smbase, 0x7f70) | X86_EFLAGS_FIXED; 2499 2500 val = GET_SMSTATE(u32, smbase, 0x7f68); 2501 ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1); 2502 val = GET_SMSTATE(u32, smbase, 0x7f60); 2503 ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1); 2504 2505 cr0 = GET_SMSTATE(u64, smbase, 0x7f58); 2506 ctxt->ops->set_cr(ctxt, 3, GET_SMSTATE(u64, smbase, 0x7f50)); 2507 cr4 = GET_SMSTATE(u64, smbase, 0x7f48); 2508 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smbase, 0x7f00)); 2509 val = GET_SMSTATE(u64, smbase, 0x7ed0); 2510 ctxt->ops->set_msr(ctxt, MSR_EFER, val & ~EFER_LMA); 2511 2512 selector = GET_SMSTATE(u32, smbase, 0x7e90); 2513 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7e92) << 8); 2514 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7e94)); 2515 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7e98)); 2516 base3 = GET_SMSTATE(u32, smbase, 0x7e9c); 2517 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_TR); 2518 2519 dt.size = GET_SMSTATE(u32, smbase, 0x7e84); 2520 dt.address = GET_SMSTATE(u64, smbase, 0x7e88); 2521 ctxt->ops->set_idt(ctxt, &dt); 2522 2523 selector = GET_SMSTATE(u32, smbase, 0x7e70); 2524 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, 0x7e72) << 8); 2525 set_desc_limit(&desc, GET_SMSTATE(u32, smbase, 0x7e74)); 2526 set_desc_base(&desc, GET_SMSTATE(u32, smbase, 0x7e78)); 2527 base3 = GET_SMSTATE(u32, smbase, 0x7e7c); 2528 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_LDTR); 2529 2530 dt.size = GET_SMSTATE(u32, smbase, 0x7e64); 2531 dt.address = GET_SMSTATE(u64, smbase, 0x7e68); 2532 ctxt->ops->set_gdt(ctxt, &dt); 2533 2534 r = rsm_enter_protected_mode(ctxt, cr0, cr4); 2535 if (r != X86EMUL_CONTINUE) 2536 return r; 2537 2538 for (i = 0; i < 6; i++) { 2539 r = rsm_load_seg_64(ctxt, smbase, i); 2540 if (r != X86EMUL_CONTINUE) 2541 return r; 2542 } 2543 2544 return X86EMUL_CONTINUE; 2545 } 2546 2547 static int em_rsm(struct x86_emulate_ctxt *ctxt) 2548 { 2549 unsigned long cr0, cr4, efer; 2550 u64 smbase; 2551 int ret; 2552 2553 if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_MASK) == 0) 2554 return emulate_ud(ctxt); 2555 2556 /* 2557 * Get back to real mode, to prepare a safe state in which to load 2558 * CR0/CR3/CR4/EFER. It's all a bit more complicated if the vCPU 2559 * supports long mode. 2560 */ 2561 cr4 = ctxt->ops->get_cr(ctxt, 4); 2562 if (emulator_has_longmode(ctxt)) { 2563 struct desc_struct cs_desc; 2564 2565 /* Zero CR4.PCIDE before CR0.PG. */ 2566 if (cr4 & X86_CR4_PCIDE) { 2567 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE); 2568 cr4 &= ~X86_CR4_PCIDE; 2569 } 2570 2571 /* A 32-bit code segment is required to clear EFER.LMA. */ 2572 memset(&cs_desc, 0, sizeof(cs_desc)); 2573 cs_desc.type = 0xb; 2574 cs_desc.s = cs_desc.g = cs_desc.p = 1; 2575 ctxt->ops->set_segment(ctxt, 0, &cs_desc, 0, VCPU_SREG_CS); 2576 } 2577 2578 /* For the 64-bit case, this will clear EFER.LMA. */ 2579 cr0 = ctxt->ops->get_cr(ctxt, 0); 2580 if (cr0 & X86_CR0_PE) 2581 ctxt->ops->set_cr(ctxt, 0, cr0 & ~(X86_CR0_PG | X86_CR0_PE)); 2582 2583 /* Now clear CR4.PAE (which must be done before clearing EFER.LME). */ 2584 if (cr4 & X86_CR4_PAE) 2585 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PAE); 2586 2587 /* And finally go back to 32-bit mode. */ 2588 efer = 0; 2589 ctxt->ops->set_msr(ctxt, MSR_EFER, efer); 2590 2591 smbase = ctxt->ops->get_smbase(ctxt); 2592 if (emulator_has_longmode(ctxt)) 2593 ret = rsm_load_state_64(ctxt, smbase + 0x8000); 2594 else 2595 ret = rsm_load_state_32(ctxt, smbase + 0x8000); 2596 2597 if (ret != X86EMUL_CONTINUE) { 2598 /* FIXME: should triple fault */ 2599 return X86EMUL_UNHANDLEABLE; 2600 } 2601 2602 if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_INSIDE_NMI_MASK) == 0) 2603 ctxt->ops->set_nmi_mask(ctxt, false); 2604 2605 ctxt->ops->set_hflags(ctxt, ctxt->ops->get_hflags(ctxt) & 2606 ~(X86EMUL_SMM_INSIDE_NMI_MASK | X86EMUL_SMM_MASK)); 2607 return X86EMUL_CONTINUE; 2608 } 2609 2610 static void 2611 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, 2612 struct desc_struct *cs, struct desc_struct *ss) 2613 { 2614 cs->l = 0; /* will be adjusted later */ 2615 set_desc_base(cs, 0); /* flat segment */ 2616 cs->g = 1; /* 4kb granularity */ 2617 set_desc_limit(cs, 0xfffff); /* 4GB limit */ 2618 cs->type = 0x0b; /* Read, Execute, Accessed */ 2619 cs->s = 1; 2620 cs->dpl = 0; /* will be adjusted later */ 2621 cs->p = 1; 2622 cs->d = 1; 2623 cs->avl = 0; 2624 2625 set_desc_base(ss, 0); /* flat segment */ 2626 set_desc_limit(ss, 0xfffff); /* 4GB limit */ 2627 ss->g = 1; /* 4kb granularity */ 2628 ss->s = 1; 2629 ss->type = 0x03; /* Read/Write, Accessed */ 2630 ss->d = 1; /* 32bit stack segment */ 2631 ss->dpl = 0; 2632 ss->p = 1; 2633 ss->l = 0; 2634 ss->avl = 0; 2635 } 2636 2637 static bool vendor_intel(struct x86_emulate_ctxt *ctxt) 2638 { 2639 u32 eax, ebx, ecx, edx; 2640 2641 eax = ecx = 0; 2642 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false); 2643 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx 2644 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx 2645 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx; 2646 } 2647 2648 static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt) 2649 { 2650 const struct x86_emulate_ops *ops = ctxt->ops; 2651 u32 eax, ebx, ecx, edx; 2652 2653 /* 2654 * syscall should always be enabled in longmode - so only become 2655 * vendor specific (cpuid) if other modes are active... 2656 */ 2657 if (ctxt->mode == X86EMUL_MODE_PROT64) 2658 return true; 2659 2660 eax = 0x00000000; 2661 ecx = 0x00000000; 2662 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false); 2663 /* 2664 * Intel ("GenuineIntel") 2665 * remark: Intel CPUs only support "syscall" in 64bit 2666 * longmode. Also an 64bit guest with a 2667 * 32bit compat-app running will #UD !! While this 2668 * behaviour can be fixed (by emulating) into AMD 2669 * response - CPUs of AMD can't behave like Intel. 2670 */ 2671 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx && 2672 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx && 2673 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx) 2674 return false; 2675 2676 /* AMD ("AuthenticAMD") */ 2677 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx && 2678 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx && 2679 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx) 2680 return true; 2681 2682 /* AMD ("AMDisbetter!") */ 2683 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx && 2684 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx && 2685 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx) 2686 return true; 2687 2688 /* default: (not Intel, not AMD), apply Intel's stricter rules... */ 2689 return false; 2690 } 2691 2692 static int em_syscall(struct x86_emulate_ctxt *ctxt) 2693 { 2694 const struct x86_emulate_ops *ops = ctxt->ops; 2695 struct desc_struct cs, ss; 2696 u64 msr_data; 2697 u16 cs_sel, ss_sel; 2698 u64 efer = 0; 2699 2700 /* syscall is not available in real mode */ 2701 if (ctxt->mode == X86EMUL_MODE_REAL || 2702 ctxt->mode == X86EMUL_MODE_VM86) 2703 return emulate_ud(ctxt); 2704 2705 if (!(em_syscall_is_enabled(ctxt))) 2706 return emulate_ud(ctxt); 2707 2708 ops->get_msr(ctxt, MSR_EFER, &efer); 2709 setup_syscalls_segments(ctxt, &cs, &ss); 2710 2711 if (!(efer & EFER_SCE)) 2712 return emulate_ud(ctxt); 2713 2714 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2715 msr_data >>= 32; 2716 cs_sel = (u16)(msr_data & 0xfffc); 2717 ss_sel = (u16)(msr_data + 8); 2718 2719 if (efer & EFER_LMA) { 2720 cs.d = 0; 2721 cs.l = 1; 2722 } 2723 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2724 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2725 2726 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip; 2727 if (efer & EFER_LMA) { 2728 #ifdef CONFIG_X86_64 2729 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags; 2730 2731 ops->get_msr(ctxt, 2732 ctxt->mode == X86EMUL_MODE_PROT64 ? 2733 MSR_LSTAR : MSR_CSTAR, &msr_data); 2734 ctxt->_eip = msr_data; 2735 2736 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data); 2737 ctxt->eflags &= ~msr_data; 2738 ctxt->eflags |= X86_EFLAGS_FIXED; 2739 #endif 2740 } else { 2741 /* legacy mode */ 2742 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2743 ctxt->_eip = (u32)msr_data; 2744 2745 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF); 2746 } 2747 2748 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 2749 return X86EMUL_CONTINUE; 2750 } 2751 2752 static int em_sysenter(struct x86_emulate_ctxt *ctxt) 2753 { 2754 const struct x86_emulate_ops *ops = ctxt->ops; 2755 struct desc_struct cs, ss; 2756 u64 msr_data; 2757 u16 cs_sel, ss_sel; 2758 u64 efer = 0; 2759 2760 ops->get_msr(ctxt, MSR_EFER, &efer); 2761 /* inject #GP if in real mode */ 2762 if (ctxt->mode == X86EMUL_MODE_REAL) 2763 return emulate_gp(ctxt, 0); 2764 2765 /* 2766 * Not recognized on AMD in compat mode (but is recognized in legacy 2767 * mode). 2768 */ 2769 if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA) 2770 && !vendor_intel(ctxt)) 2771 return emulate_ud(ctxt); 2772 2773 /* sysenter/sysexit have not been tested in 64bit mode. */ 2774 if (ctxt->mode == X86EMUL_MODE_PROT64) 2775 return X86EMUL_UNHANDLEABLE; 2776 2777 setup_syscalls_segments(ctxt, &cs, &ss); 2778 2779 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2780 if ((msr_data & 0xfffc) == 0x0) 2781 return emulate_gp(ctxt, 0); 2782 2783 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF); 2784 cs_sel = (u16)msr_data & ~SEGMENT_RPL_MASK; 2785 ss_sel = cs_sel + 8; 2786 if (efer & EFER_LMA) { 2787 cs.d = 0; 2788 cs.l = 1; 2789 } 2790 2791 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2792 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2793 2794 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data); 2795 ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data; 2796 2797 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data); 2798 *reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data : 2799 (u32)msr_data; 2800 2801 return X86EMUL_CONTINUE; 2802 } 2803 2804 static int em_sysexit(struct x86_emulate_ctxt *ctxt) 2805 { 2806 const struct x86_emulate_ops *ops = ctxt->ops; 2807 struct desc_struct cs, ss; 2808 u64 msr_data, rcx, rdx; 2809 int usermode; 2810 u16 cs_sel = 0, ss_sel = 0; 2811 2812 /* inject #GP if in real mode or Virtual 8086 mode */ 2813 if (ctxt->mode == X86EMUL_MODE_REAL || 2814 ctxt->mode == X86EMUL_MODE_VM86) 2815 return emulate_gp(ctxt, 0); 2816 2817 setup_syscalls_segments(ctxt, &cs, &ss); 2818 2819 if ((ctxt->rex_prefix & 0x8) != 0x0) 2820 usermode = X86EMUL_MODE_PROT64; 2821 else 2822 usermode = X86EMUL_MODE_PROT32; 2823 2824 rcx = reg_read(ctxt, VCPU_REGS_RCX); 2825 rdx = reg_read(ctxt, VCPU_REGS_RDX); 2826 2827 cs.dpl = 3; 2828 ss.dpl = 3; 2829 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2830 switch (usermode) { 2831 case X86EMUL_MODE_PROT32: 2832 cs_sel = (u16)(msr_data + 16); 2833 if ((msr_data & 0xfffc) == 0x0) 2834 return emulate_gp(ctxt, 0); 2835 ss_sel = (u16)(msr_data + 24); 2836 rcx = (u32)rcx; 2837 rdx = (u32)rdx; 2838 break; 2839 case X86EMUL_MODE_PROT64: 2840 cs_sel = (u16)(msr_data + 32); 2841 if (msr_data == 0x0) 2842 return emulate_gp(ctxt, 0); 2843 ss_sel = cs_sel + 8; 2844 cs.d = 0; 2845 cs.l = 1; 2846 if (emul_is_noncanonical_address(rcx, ctxt) || 2847 emul_is_noncanonical_address(rdx, ctxt)) 2848 return emulate_gp(ctxt, 0); 2849 break; 2850 } 2851 cs_sel |= SEGMENT_RPL_MASK; 2852 ss_sel |= SEGMENT_RPL_MASK; 2853 2854 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2855 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2856 2857 ctxt->_eip = rdx; 2858 *reg_write(ctxt, VCPU_REGS_RSP) = rcx; 2859 2860 return X86EMUL_CONTINUE; 2861 } 2862 2863 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt) 2864 { 2865 int iopl; 2866 if (ctxt->mode == X86EMUL_MODE_REAL) 2867 return false; 2868 if (ctxt->mode == X86EMUL_MODE_VM86) 2869 return true; 2870 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT; 2871 return ctxt->ops->cpl(ctxt) > iopl; 2872 } 2873 2874 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, 2875 u16 port, u16 len) 2876 { 2877 const struct x86_emulate_ops *ops = ctxt->ops; 2878 struct desc_struct tr_seg; 2879 u32 base3; 2880 int r; 2881 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7; 2882 unsigned mask = (1 << len) - 1; 2883 unsigned long base; 2884 2885 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR); 2886 if (!tr_seg.p) 2887 return false; 2888 if (desc_limit_scaled(&tr_seg) < 103) 2889 return false; 2890 base = get_desc_base(&tr_seg); 2891 #ifdef CONFIG_X86_64 2892 base |= ((u64)base3) << 32; 2893 #endif 2894 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL); 2895 if (r != X86EMUL_CONTINUE) 2896 return false; 2897 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) 2898 return false; 2899 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL); 2900 if (r != X86EMUL_CONTINUE) 2901 return false; 2902 if ((perm >> bit_idx) & mask) 2903 return false; 2904 return true; 2905 } 2906 2907 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, 2908 u16 port, u16 len) 2909 { 2910 if (ctxt->perm_ok) 2911 return true; 2912 2913 if (emulator_bad_iopl(ctxt)) 2914 if (!emulator_io_port_access_allowed(ctxt, port, len)) 2915 return false; 2916 2917 ctxt->perm_ok = true; 2918 2919 return true; 2920 } 2921 2922 static void string_registers_quirk(struct x86_emulate_ctxt *ctxt) 2923 { 2924 /* 2925 * Intel CPUs mask the counter and pointers in quite strange 2926 * manner when ECX is zero due to REP-string optimizations. 2927 */ 2928 #ifdef CONFIG_X86_64 2929 if (ctxt->ad_bytes != 4 || !vendor_intel(ctxt)) 2930 return; 2931 2932 *reg_write(ctxt, VCPU_REGS_RCX) = 0; 2933 2934 switch (ctxt->b) { 2935 case 0xa4: /* movsb */ 2936 case 0xa5: /* movsd/w */ 2937 *reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1; 2938 /* fall through */ 2939 case 0xaa: /* stosb */ 2940 case 0xab: /* stosd/w */ 2941 *reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1; 2942 } 2943 #endif 2944 } 2945 2946 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, 2947 struct tss_segment_16 *tss) 2948 { 2949 tss->ip = ctxt->_eip; 2950 tss->flag = ctxt->eflags; 2951 tss->ax = reg_read(ctxt, VCPU_REGS_RAX); 2952 tss->cx = reg_read(ctxt, VCPU_REGS_RCX); 2953 tss->dx = reg_read(ctxt, VCPU_REGS_RDX); 2954 tss->bx = reg_read(ctxt, VCPU_REGS_RBX); 2955 tss->sp = reg_read(ctxt, VCPU_REGS_RSP); 2956 tss->bp = reg_read(ctxt, VCPU_REGS_RBP); 2957 tss->si = reg_read(ctxt, VCPU_REGS_RSI); 2958 tss->di = reg_read(ctxt, VCPU_REGS_RDI); 2959 2960 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 2961 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 2962 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 2963 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 2964 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR); 2965 } 2966 2967 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, 2968 struct tss_segment_16 *tss) 2969 { 2970 int ret; 2971 u8 cpl; 2972 2973 ctxt->_eip = tss->ip; 2974 ctxt->eflags = tss->flag | 2; 2975 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax; 2976 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx; 2977 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx; 2978 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx; 2979 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp; 2980 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp; 2981 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si; 2982 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di; 2983 2984 /* 2985 * SDM says that segment selectors are loaded before segment 2986 * descriptors 2987 */ 2988 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR); 2989 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 2990 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 2991 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 2992 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 2993 2994 cpl = tss->cs & 3; 2995 2996 /* 2997 * Now load segment descriptors. If fault happens at this stage 2998 * it is handled in a context of new task 2999 */ 3000 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, 3001 X86_TRANSFER_TASK_SWITCH, NULL); 3002 if (ret != X86EMUL_CONTINUE) 3003 return ret; 3004 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, 3005 X86_TRANSFER_TASK_SWITCH, NULL); 3006 if (ret != X86EMUL_CONTINUE) 3007 return ret; 3008 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, 3009 X86_TRANSFER_TASK_SWITCH, NULL); 3010 if (ret != X86EMUL_CONTINUE) 3011 return ret; 3012 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, 3013 X86_TRANSFER_TASK_SWITCH, NULL); 3014 if (ret != X86EMUL_CONTINUE) 3015 return ret; 3016 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, 3017 X86_TRANSFER_TASK_SWITCH, NULL); 3018 if (ret != X86EMUL_CONTINUE) 3019 return ret; 3020 3021 return X86EMUL_CONTINUE; 3022 } 3023 3024 static int task_switch_16(struct x86_emulate_ctxt *ctxt, 3025 u16 tss_selector, u16 old_tss_sel, 3026 ulong old_tss_base, struct desc_struct *new_desc) 3027 { 3028 const struct x86_emulate_ops *ops = ctxt->ops; 3029 struct tss_segment_16 tss_seg; 3030 int ret; 3031 u32 new_tss_base = get_desc_base(new_desc); 3032 3033 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, 3034 &ctxt->exception); 3035 if (ret != X86EMUL_CONTINUE) 3036 return ret; 3037 3038 save_state_to_tss16(ctxt, &tss_seg); 3039 3040 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, 3041 &ctxt->exception); 3042 if (ret != X86EMUL_CONTINUE) 3043 return ret; 3044 3045 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, 3046 &ctxt->exception); 3047 if (ret != X86EMUL_CONTINUE) 3048 return ret; 3049 3050 if (old_tss_sel != 0xffff) { 3051 tss_seg.prev_task_link = old_tss_sel; 3052 3053 ret = ops->write_std(ctxt, new_tss_base, 3054 &tss_seg.prev_task_link, 3055 sizeof tss_seg.prev_task_link, 3056 &ctxt->exception); 3057 if (ret != X86EMUL_CONTINUE) 3058 return ret; 3059 } 3060 3061 return load_state_from_tss16(ctxt, &tss_seg); 3062 } 3063 3064 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, 3065 struct tss_segment_32 *tss) 3066 { 3067 /* CR3 and ldt selector are not saved intentionally */ 3068 tss->eip = ctxt->_eip; 3069 tss->eflags = ctxt->eflags; 3070 tss->eax = reg_read(ctxt, VCPU_REGS_RAX); 3071 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX); 3072 tss->edx = reg_read(ctxt, VCPU_REGS_RDX); 3073 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX); 3074 tss->esp = reg_read(ctxt, VCPU_REGS_RSP); 3075 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP); 3076 tss->esi = reg_read(ctxt, VCPU_REGS_RSI); 3077 tss->edi = reg_read(ctxt, VCPU_REGS_RDI); 3078 3079 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 3080 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 3081 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 3082 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 3083 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS); 3084 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS); 3085 } 3086 3087 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, 3088 struct tss_segment_32 *tss) 3089 { 3090 int ret; 3091 u8 cpl; 3092 3093 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3)) 3094 return emulate_gp(ctxt, 0); 3095 ctxt->_eip = tss->eip; 3096 ctxt->eflags = tss->eflags | 2; 3097 3098 /* General purpose registers */ 3099 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax; 3100 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx; 3101 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx; 3102 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx; 3103 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp; 3104 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp; 3105 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi; 3106 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi; 3107 3108 /* 3109 * SDM says that segment selectors are loaded before segment 3110 * descriptors. This is important because CPL checks will 3111 * use CS.RPL. 3112 */ 3113 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); 3114 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 3115 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 3116 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 3117 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 3118 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS); 3119 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS); 3120 3121 /* 3122 * If we're switching between Protected Mode and VM86, we need to make 3123 * sure to update the mode before loading the segment descriptors so 3124 * that the selectors are interpreted correctly. 3125 */ 3126 if (ctxt->eflags & X86_EFLAGS_VM) { 3127 ctxt->mode = X86EMUL_MODE_VM86; 3128 cpl = 3; 3129 } else { 3130 ctxt->mode = X86EMUL_MODE_PROT32; 3131 cpl = tss->cs & 3; 3132 } 3133 3134 /* 3135 * Now load segment descriptors. If fault happenes at this stage 3136 * it is handled in a context of new task 3137 */ 3138 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, 3139 cpl, X86_TRANSFER_TASK_SWITCH, NULL); 3140 if (ret != X86EMUL_CONTINUE) 3141 return ret; 3142 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, 3143 X86_TRANSFER_TASK_SWITCH, NULL); 3144 if (ret != X86EMUL_CONTINUE) 3145 return ret; 3146 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, 3147 X86_TRANSFER_TASK_SWITCH, NULL); 3148 if (ret != X86EMUL_CONTINUE) 3149 return ret; 3150 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, 3151 X86_TRANSFER_TASK_SWITCH, NULL); 3152 if (ret != X86EMUL_CONTINUE) 3153 return ret; 3154 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, 3155 X86_TRANSFER_TASK_SWITCH, NULL); 3156 if (ret != X86EMUL_CONTINUE) 3157 return ret; 3158 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, 3159 X86_TRANSFER_TASK_SWITCH, NULL); 3160 if (ret != X86EMUL_CONTINUE) 3161 return ret; 3162 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, 3163 X86_TRANSFER_TASK_SWITCH, NULL); 3164 3165 return ret; 3166 } 3167 3168 static int task_switch_32(struct x86_emulate_ctxt *ctxt, 3169 u16 tss_selector, u16 old_tss_sel, 3170 ulong old_tss_base, struct desc_struct *new_desc) 3171 { 3172 const struct x86_emulate_ops *ops = ctxt->ops; 3173 struct tss_segment_32 tss_seg; 3174 int ret; 3175 u32 new_tss_base = get_desc_base(new_desc); 3176 u32 eip_offset = offsetof(struct tss_segment_32, eip); 3177 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector); 3178 3179 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, 3180 &ctxt->exception); 3181 if (ret != X86EMUL_CONTINUE) 3182 return ret; 3183 3184 save_state_to_tss32(ctxt, &tss_seg); 3185 3186 /* Only GP registers and segment selectors are saved */ 3187 ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip, 3188 ldt_sel_offset - eip_offset, &ctxt->exception); 3189 if (ret != X86EMUL_CONTINUE) 3190 return ret; 3191 3192 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, 3193 &ctxt->exception); 3194 if (ret != X86EMUL_CONTINUE) 3195 return ret; 3196 3197 if (old_tss_sel != 0xffff) { 3198 tss_seg.prev_task_link = old_tss_sel; 3199 3200 ret = ops->write_std(ctxt, new_tss_base, 3201 &tss_seg.prev_task_link, 3202 sizeof tss_seg.prev_task_link, 3203 &ctxt->exception); 3204 if (ret != X86EMUL_CONTINUE) 3205 return ret; 3206 } 3207 3208 return load_state_from_tss32(ctxt, &tss_seg); 3209 } 3210 3211 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, 3212 u16 tss_selector, int idt_index, int reason, 3213 bool has_error_code, u32 error_code) 3214 { 3215 const struct x86_emulate_ops *ops = ctxt->ops; 3216 struct desc_struct curr_tss_desc, next_tss_desc; 3217 int ret; 3218 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR); 3219 ulong old_tss_base = 3220 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR); 3221 u32 desc_limit; 3222 ulong desc_addr, dr7; 3223 3224 /* FIXME: old_tss_base == ~0 ? */ 3225 3226 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr); 3227 if (ret != X86EMUL_CONTINUE) 3228 return ret; 3229 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr); 3230 if (ret != X86EMUL_CONTINUE) 3231 return ret; 3232 3233 /* FIXME: check that next_tss_desc is tss */ 3234 3235 /* 3236 * Check privileges. The three cases are task switch caused by... 3237 * 3238 * 1. jmp/call/int to task gate: Check against DPL of the task gate 3239 * 2. Exception/IRQ/iret: No check is performed 3240 * 3. jmp/call to TSS/task-gate: No check is performed since the 3241 * hardware checks it before exiting. 3242 */ 3243 if (reason == TASK_SWITCH_GATE) { 3244 if (idt_index != -1) { 3245 /* Software interrupts */ 3246 struct desc_struct task_gate_desc; 3247 int dpl; 3248 3249 ret = read_interrupt_descriptor(ctxt, idt_index, 3250 &task_gate_desc); 3251 if (ret != X86EMUL_CONTINUE) 3252 return ret; 3253 3254 dpl = task_gate_desc.dpl; 3255 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) 3256 return emulate_gp(ctxt, (idt_index << 3) | 0x2); 3257 } 3258 } 3259 3260 desc_limit = desc_limit_scaled(&next_tss_desc); 3261 if (!next_tss_desc.p || 3262 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || 3263 desc_limit < 0x2b)) { 3264 return emulate_ts(ctxt, tss_selector & 0xfffc); 3265 } 3266 3267 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { 3268 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ 3269 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); 3270 } 3271 3272 if (reason == TASK_SWITCH_IRET) 3273 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; 3274 3275 /* set back link to prev task only if NT bit is set in eflags 3276 note that old_tss_sel is not used after this point */ 3277 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) 3278 old_tss_sel = 0xffff; 3279 3280 if (next_tss_desc.type & 8) 3281 ret = task_switch_32(ctxt, tss_selector, old_tss_sel, 3282 old_tss_base, &next_tss_desc); 3283 else 3284 ret = task_switch_16(ctxt, tss_selector, old_tss_sel, 3285 old_tss_base, &next_tss_desc); 3286 if (ret != X86EMUL_CONTINUE) 3287 return ret; 3288 3289 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) 3290 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; 3291 3292 if (reason != TASK_SWITCH_IRET) { 3293 next_tss_desc.type |= (1 << 1); /* set busy flag */ 3294 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc); 3295 } 3296 3297 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS); 3298 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR); 3299 3300 if (has_error_code) { 3301 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; 3302 ctxt->lock_prefix = 0; 3303 ctxt->src.val = (unsigned long) error_code; 3304 ret = em_push(ctxt); 3305 } 3306 3307 ops->get_dr(ctxt, 7, &dr7); 3308 ops->set_dr(ctxt, 7, dr7 & ~(DR_LOCAL_ENABLE_MASK | DR_LOCAL_SLOWDOWN)); 3309 3310 return ret; 3311 } 3312 3313 int emulator_task_switch(struct x86_emulate_ctxt *ctxt, 3314 u16 tss_selector, int idt_index, int reason, 3315 bool has_error_code, u32 error_code) 3316 { 3317 int rc; 3318 3319 invalidate_registers(ctxt); 3320 ctxt->_eip = ctxt->eip; 3321 ctxt->dst.type = OP_NONE; 3322 3323 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason, 3324 has_error_code, error_code); 3325 3326 if (rc == X86EMUL_CONTINUE) { 3327 ctxt->eip = ctxt->_eip; 3328 writeback_registers(ctxt); 3329 } 3330 3331 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 3332 } 3333 3334 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg, 3335 struct operand *op) 3336 { 3337 int df = (ctxt->eflags & X86_EFLAGS_DF) ? -op->count : op->count; 3338 3339 register_address_increment(ctxt, reg, df * op->bytes); 3340 op->addr.mem.ea = register_address(ctxt, reg); 3341 } 3342 3343 static int em_das(struct x86_emulate_ctxt *ctxt) 3344 { 3345 u8 al, old_al; 3346 bool af, cf, old_cf; 3347 3348 cf = ctxt->eflags & X86_EFLAGS_CF; 3349 al = ctxt->dst.val; 3350 3351 old_al = al; 3352 old_cf = cf; 3353 cf = false; 3354 af = ctxt->eflags & X86_EFLAGS_AF; 3355 if ((al & 0x0f) > 9 || af) { 3356 al -= 6; 3357 cf = old_cf | (al >= 250); 3358 af = true; 3359 } else { 3360 af = false; 3361 } 3362 if (old_al > 0x99 || old_cf) { 3363 al -= 0x60; 3364 cf = true; 3365 } 3366 3367 ctxt->dst.val = al; 3368 /* Set PF, ZF, SF */ 3369 ctxt->src.type = OP_IMM; 3370 ctxt->src.val = 0; 3371 ctxt->src.bytes = 1; 3372 fastop(ctxt, em_or); 3373 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); 3374 if (cf) 3375 ctxt->eflags |= X86_EFLAGS_CF; 3376 if (af) 3377 ctxt->eflags |= X86_EFLAGS_AF; 3378 return X86EMUL_CONTINUE; 3379 } 3380 3381 static int em_aam(struct x86_emulate_ctxt *ctxt) 3382 { 3383 u8 al, ah; 3384 3385 if (ctxt->src.val == 0) 3386 return emulate_de(ctxt); 3387 3388 al = ctxt->dst.val & 0xff; 3389 ah = al / ctxt->src.val; 3390 al %= ctxt->src.val; 3391 3392 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8); 3393 3394 /* Set PF, ZF, SF */ 3395 ctxt->src.type = OP_IMM; 3396 ctxt->src.val = 0; 3397 ctxt->src.bytes = 1; 3398 fastop(ctxt, em_or); 3399 3400 return X86EMUL_CONTINUE; 3401 } 3402 3403 static int em_aad(struct x86_emulate_ctxt *ctxt) 3404 { 3405 u8 al = ctxt->dst.val & 0xff; 3406 u8 ah = (ctxt->dst.val >> 8) & 0xff; 3407 3408 al = (al + (ah * ctxt->src.val)) & 0xff; 3409 3410 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al; 3411 3412 /* Set PF, ZF, SF */ 3413 ctxt->src.type = OP_IMM; 3414 ctxt->src.val = 0; 3415 ctxt->src.bytes = 1; 3416 fastop(ctxt, em_or); 3417 3418 return X86EMUL_CONTINUE; 3419 } 3420 3421 static int em_call(struct x86_emulate_ctxt *ctxt) 3422 { 3423 int rc; 3424 long rel = ctxt->src.val; 3425 3426 ctxt->src.val = (unsigned long)ctxt->_eip; 3427 rc = jmp_rel(ctxt, rel); 3428 if (rc != X86EMUL_CONTINUE) 3429 return rc; 3430 return em_push(ctxt); 3431 } 3432 3433 static int em_call_far(struct x86_emulate_ctxt *ctxt) 3434 { 3435 u16 sel, old_cs; 3436 ulong old_eip; 3437 int rc; 3438 struct desc_struct old_desc, new_desc; 3439 const struct x86_emulate_ops *ops = ctxt->ops; 3440 int cpl = ctxt->ops->cpl(ctxt); 3441 enum x86emul_mode prev_mode = ctxt->mode; 3442 3443 old_eip = ctxt->_eip; 3444 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS); 3445 3446 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 3447 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, 3448 X86_TRANSFER_CALL_JMP, &new_desc); 3449 if (rc != X86EMUL_CONTINUE) 3450 return rc; 3451 3452 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc); 3453 if (rc != X86EMUL_CONTINUE) 3454 goto fail; 3455 3456 ctxt->src.val = old_cs; 3457 rc = em_push(ctxt); 3458 if (rc != X86EMUL_CONTINUE) 3459 goto fail; 3460 3461 ctxt->src.val = old_eip; 3462 rc = em_push(ctxt); 3463 /* If we failed, we tainted the memory, but the very least we should 3464 restore cs */ 3465 if (rc != X86EMUL_CONTINUE) { 3466 pr_warn_once("faulting far call emulation tainted memory\n"); 3467 goto fail; 3468 } 3469 return rc; 3470 fail: 3471 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS); 3472 ctxt->mode = prev_mode; 3473 return rc; 3474 3475 } 3476 3477 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) 3478 { 3479 int rc; 3480 unsigned long eip; 3481 3482 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 3483 if (rc != X86EMUL_CONTINUE) 3484 return rc; 3485 rc = assign_eip_near(ctxt, eip); 3486 if (rc != X86EMUL_CONTINUE) 3487 return rc; 3488 rsp_increment(ctxt, ctxt->src.val); 3489 return X86EMUL_CONTINUE; 3490 } 3491 3492 static int em_xchg(struct x86_emulate_ctxt *ctxt) 3493 { 3494 /* Write back the register source. */ 3495 ctxt->src.val = ctxt->dst.val; 3496 write_register_operand(&ctxt->src); 3497 3498 /* Write back the memory destination with implicit LOCK prefix. */ 3499 ctxt->dst.val = ctxt->src.orig_val; 3500 ctxt->lock_prefix = 1; 3501 return X86EMUL_CONTINUE; 3502 } 3503 3504 static int em_imul_3op(struct x86_emulate_ctxt *ctxt) 3505 { 3506 ctxt->dst.val = ctxt->src2.val; 3507 return fastop(ctxt, em_imul); 3508 } 3509 3510 static int em_cwd(struct x86_emulate_ctxt *ctxt) 3511 { 3512 ctxt->dst.type = OP_REG; 3513 ctxt->dst.bytes = ctxt->src.bytes; 3514 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 3515 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1); 3516 3517 return X86EMUL_CONTINUE; 3518 } 3519 3520 static int em_rdtsc(struct x86_emulate_ctxt *ctxt) 3521 { 3522 u64 tsc = 0; 3523 3524 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc); 3525 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc; 3526 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32; 3527 return X86EMUL_CONTINUE; 3528 } 3529 3530 static int em_rdpmc(struct x86_emulate_ctxt *ctxt) 3531 { 3532 u64 pmc; 3533 3534 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc)) 3535 return emulate_gp(ctxt, 0); 3536 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc; 3537 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32; 3538 return X86EMUL_CONTINUE; 3539 } 3540 3541 static int em_mov(struct x86_emulate_ctxt *ctxt) 3542 { 3543 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr)); 3544 return X86EMUL_CONTINUE; 3545 } 3546 3547 #define FFL(x) bit(X86_FEATURE_##x) 3548 3549 static int em_movbe(struct x86_emulate_ctxt *ctxt) 3550 { 3551 u32 ebx, ecx, edx, eax = 1; 3552 u16 tmp; 3553 3554 /* 3555 * Check MOVBE is set in the guest-visible CPUID leaf. 3556 */ 3557 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false); 3558 if (!(ecx & FFL(MOVBE))) 3559 return emulate_ud(ctxt); 3560 3561 switch (ctxt->op_bytes) { 3562 case 2: 3563 /* 3564 * From MOVBE definition: "...When the operand size is 16 bits, 3565 * the upper word of the destination register remains unchanged 3566 * ..." 3567 * 3568 * Both casting ->valptr and ->val to u16 breaks strict aliasing 3569 * rules so we have to do the operation almost per hand. 3570 */ 3571 tmp = (u16)ctxt->src.val; 3572 ctxt->dst.val &= ~0xffffUL; 3573 ctxt->dst.val |= (unsigned long)swab16(tmp); 3574 break; 3575 case 4: 3576 ctxt->dst.val = swab32((u32)ctxt->src.val); 3577 break; 3578 case 8: 3579 ctxt->dst.val = swab64(ctxt->src.val); 3580 break; 3581 default: 3582 BUG(); 3583 } 3584 return X86EMUL_CONTINUE; 3585 } 3586 3587 static int em_cr_write(struct x86_emulate_ctxt *ctxt) 3588 { 3589 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) 3590 return emulate_gp(ctxt, 0); 3591 3592 /* Disable writeback. */ 3593 ctxt->dst.type = OP_NONE; 3594 return X86EMUL_CONTINUE; 3595 } 3596 3597 static int em_dr_write(struct x86_emulate_ctxt *ctxt) 3598 { 3599 unsigned long val; 3600 3601 if (ctxt->mode == X86EMUL_MODE_PROT64) 3602 val = ctxt->src.val & ~0ULL; 3603 else 3604 val = ctxt->src.val & ~0U; 3605 3606 /* #UD condition is already handled. */ 3607 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0) 3608 return emulate_gp(ctxt, 0); 3609 3610 /* Disable writeback. */ 3611 ctxt->dst.type = OP_NONE; 3612 return X86EMUL_CONTINUE; 3613 } 3614 3615 static int em_wrmsr(struct x86_emulate_ctxt *ctxt) 3616 { 3617 u64 msr_data; 3618 3619 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX) 3620 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32); 3621 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data)) 3622 return emulate_gp(ctxt, 0); 3623 3624 return X86EMUL_CONTINUE; 3625 } 3626 3627 static int em_rdmsr(struct x86_emulate_ctxt *ctxt) 3628 { 3629 u64 msr_data; 3630 3631 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data)) 3632 return emulate_gp(ctxt, 0); 3633 3634 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data; 3635 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32; 3636 return X86EMUL_CONTINUE; 3637 } 3638 3639 static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt) 3640 { 3641 if (ctxt->modrm_reg > VCPU_SREG_GS) 3642 return emulate_ud(ctxt); 3643 3644 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg); 3645 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM) 3646 ctxt->dst.bytes = 2; 3647 return X86EMUL_CONTINUE; 3648 } 3649 3650 static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt) 3651 { 3652 u16 sel = ctxt->src.val; 3653 3654 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS) 3655 return emulate_ud(ctxt); 3656 3657 if (ctxt->modrm_reg == VCPU_SREG_SS) 3658 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; 3659 3660 /* Disable writeback. */ 3661 ctxt->dst.type = OP_NONE; 3662 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg); 3663 } 3664 3665 static int em_lldt(struct x86_emulate_ctxt *ctxt) 3666 { 3667 u16 sel = ctxt->src.val; 3668 3669 /* Disable writeback. */ 3670 ctxt->dst.type = OP_NONE; 3671 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR); 3672 } 3673 3674 static int em_ltr(struct x86_emulate_ctxt *ctxt) 3675 { 3676 u16 sel = ctxt->src.val; 3677 3678 /* Disable writeback. */ 3679 ctxt->dst.type = OP_NONE; 3680 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR); 3681 } 3682 3683 static int em_invlpg(struct x86_emulate_ctxt *ctxt) 3684 { 3685 int rc; 3686 ulong linear; 3687 3688 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear); 3689 if (rc == X86EMUL_CONTINUE) 3690 ctxt->ops->invlpg(ctxt, linear); 3691 /* Disable writeback. */ 3692 ctxt->dst.type = OP_NONE; 3693 return X86EMUL_CONTINUE; 3694 } 3695 3696 static int em_clts(struct x86_emulate_ctxt *ctxt) 3697 { 3698 ulong cr0; 3699 3700 cr0 = ctxt->ops->get_cr(ctxt, 0); 3701 cr0 &= ~X86_CR0_TS; 3702 ctxt->ops->set_cr(ctxt, 0, cr0); 3703 return X86EMUL_CONTINUE; 3704 } 3705 3706 static int em_hypercall(struct x86_emulate_ctxt *ctxt) 3707 { 3708 int rc = ctxt->ops->fix_hypercall(ctxt); 3709 3710 if (rc != X86EMUL_CONTINUE) 3711 return rc; 3712 3713 /* Let the processor re-execute the fixed hypercall */ 3714 ctxt->_eip = ctxt->eip; 3715 /* Disable writeback. */ 3716 ctxt->dst.type = OP_NONE; 3717 return X86EMUL_CONTINUE; 3718 } 3719 3720 static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt, 3721 void (*get)(struct x86_emulate_ctxt *ctxt, 3722 struct desc_ptr *ptr)) 3723 { 3724 struct desc_ptr desc_ptr; 3725 3726 if (ctxt->mode == X86EMUL_MODE_PROT64) 3727 ctxt->op_bytes = 8; 3728 get(ctxt, &desc_ptr); 3729 if (ctxt->op_bytes == 2) { 3730 ctxt->op_bytes = 4; 3731 desc_ptr.address &= 0x00ffffff; 3732 } 3733 /* Disable writeback. */ 3734 ctxt->dst.type = OP_NONE; 3735 return segmented_write_std(ctxt, ctxt->dst.addr.mem, 3736 &desc_ptr, 2 + ctxt->op_bytes); 3737 } 3738 3739 static int em_sgdt(struct x86_emulate_ctxt *ctxt) 3740 { 3741 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt); 3742 } 3743 3744 static int em_sidt(struct x86_emulate_ctxt *ctxt) 3745 { 3746 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt); 3747 } 3748 3749 static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt) 3750 { 3751 struct desc_ptr desc_ptr; 3752 int rc; 3753 3754 if (ctxt->mode == X86EMUL_MODE_PROT64) 3755 ctxt->op_bytes = 8; 3756 rc = read_descriptor(ctxt, ctxt->src.addr.mem, 3757 &desc_ptr.size, &desc_ptr.address, 3758 ctxt->op_bytes); 3759 if (rc != X86EMUL_CONTINUE) 3760 return rc; 3761 if (ctxt->mode == X86EMUL_MODE_PROT64 && 3762 emul_is_noncanonical_address(desc_ptr.address, ctxt)) 3763 return emulate_gp(ctxt, 0); 3764 if (lgdt) 3765 ctxt->ops->set_gdt(ctxt, &desc_ptr); 3766 else 3767 ctxt->ops->set_idt(ctxt, &desc_ptr); 3768 /* Disable writeback. */ 3769 ctxt->dst.type = OP_NONE; 3770 return X86EMUL_CONTINUE; 3771 } 3772 3773 static int em_lgdt(struct x86_emulate_ctxt *ctxt) 3774 { 3775 return em_lgdt_lidt(ctxt, true); 3776 } 3777 3778 static int em_lidt(struct x86_emulate_ctxt *ctxt) 3779 { 3780 return em_lgdt_lidt(ctxt, false); 3781 } 3782 3783 static int em_smsw(struct x86_emulate_ctxt *ctxt) 3784 { 3785 if (ctxt->dst.type == OP_MEM) 3786 ctxt->dst.bytes = 2; 3787 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0); 3788 return X86EMUL_CONTINUE; 3789 } 3790 3791 static int em_lmsw(struct x86_emulate_ctxt *ctxt) 3792 { 3793 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul) 3794 | (ctxt->src.val & 0x0f)); 3795 ctxt->dst.type = OP_NONE; 3796 return X86EMUL_CONTINUE; 3797 } 3798 3799 static int em_loop(struct x86_emulate_ctxt *ctxt) 3800 { 3801 int rc = X86EMUL_CONTINUE; 3802 3803 register_address_increment(ctxt, VCPU_REGS_RCX, -1); 3804 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) && 3805 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags))) 3806 rc = jmp_rel(ctxt, ctxt->src.val); 3807 3808 return rc; 3809 } 3810 3811 static int em_jcxz(struct x86_emulate_ctxt *ctxt) 3812 { 3813 int rc = X86EMUL_CONTINUE; 3814 3815 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) 3816 rc = jmp_rel(ctxt, ctxt->src.val); 3817 3818 return rc; 3819 } 3820 3821 static int em_in(struct x86_emulate_ctxt *ctxt) 3822 { 3823 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val, 3824 &ctxt->dst.val)) 3825 return X86EMUL_IO_NEEDED; 3826 3827 return X86EMUL_CONTINUE; 3828 } 3829 3830 static int em_out(struct x86_emulate_ctxt *ctxt) 3831 { 3832 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val, 3833 &ctxt->src.val, 1); 3834 /* Disable writeback. */ 3835 ctxt->dst.type = OP_NONE; 3836 return X86EMUL_CONTINUE; 3837 } 3838 3839 static int em_cli(struct x86_emulate_ctxt *ctxt) 3840 { 3841 if (emulator_bad_iopl(ctxt)) 3842 return emulate_gp(ctxt, 0); 3843 3844 ctxt->eflags &= ~X86_EFLAGS_IF; 3845 return X86EMUL_CONTINUE; 3846 } 3847 3848 static int em_sti(struct x86_emulate_ctxt *ctxt) 3849 { 3850 if (emulator_bad_iopl(ctxt)) 3851 return emulate_gp(ctxt, 0); 3852 3853 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; 3854 ctxt->eflags |= X86_EFLAGS_IF; 3855 return X86EMUL_CONTINUE; 3856 } 3857 3858 static int em_cpuid(struct x86_emulate_ctxt *ctxt) 3859 { 3860 u32 eax, ebx, ecx, edx; 3861 u64 msr = 0; 3862 3863 ctxt->ops->get_msr(ctxt, MSR_MISC_FEATURES_ENABLES, &msr); 3864 if (msr & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 3865 ctxt->ops->cpl(ctxt)) { 3866 return emulate_gp(ctxt, 0); 3867 } 3868 3869 eax = reg_read(ctxt, VCPU_REGS_RAX); 3870 ecx = reg_read(ctxt, VCPU_REGS_RCX); 3871 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, true); 3872 *reg_write(ctxt, VCPU_REGS_RAX) = eax; 3873 *reg_write(ctxt, VCPU_REGS_RBX) = ebx; 3874 *reg_write(ctxt, VCPU_REGS_RCX) = ecx; 3875 *reg_write(ctxt, VCPU_REGS_RDX) = edx; 3876 return X86EMUL_CONTINUE; 3877 } 3878 3879 static int em_sahf(struct x86_emulate_ctxt *ctxt) 3880 { 3881 u32 flags; 3882 3883 flags = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF | 3884 X86_EFLAGS_SF; 3885 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8; 3886 3887 ctxt->eflags &= ~0xffUL; 3888 ctxt->eflags |= flags | X86_EFLAGS_FIXED; 3889 return X86EMUL_CONTINUE; 3890 } 3891 3892 static int em_lahf(struct x86_emulate_ctxt *ctxt) 3893 { 3894 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL; 3895 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8; 3896 return X86EMUL_CONTINUE; 3897 } 3898 3899 static int em_bswap(struct x86_emulate_ctxt *ctxt) 3900 { 3901 switch (ctxt->op_bytes) { 3902 #ifdef CONFIG_X86_64 3903 case 8: 3904 asm("bswap %0" : "+r"(ctxt->dst.val)); 3905 break; 3906 #endif 3907 default: 3908 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val)); 3909 break; 3910 } 3911 return X86EMUL_CONTINUE; 3912 } 3913 3914 static int em_clflush(struct x86_emulate_ctxt *ctxt) 3915 { 3916 /* emulating clflush regardless of cpuid */ 3917 return X86EMUL_CONTINUE; 3918 } 3919 3920 static int em_movsxd(struct x86_emulate_ctxt *ctxt) 3921 { 3922 ctxt->dst.val = (s32) ctxt->src.val; 3923 return X86EMUL_CONTINUE; 3924 } 3925 3926 static int check_fxsr(struct x86_emulate_ctxt *ctxt) 3927 { 3928 u32 eax = 1, ebx, ecx = 0, edx; 3929 3930 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false); 3931 if (!(edx & FFL(FXSR))) 3932 return emulate_ud(ctxt); 3933 3934 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 3935 return emulate_nm(ctxt); 3936 3937 /* 3938 * Don't emulate a case that should never be hit, instead of working 3939 * around a lack of fxsave64/fxrstor64 on old compilers. 3940 */ 3941 if (ctxt->mode >= X86EMUL_MODE_PROT64) 3942 return X86EMUL_UNHANDLEABLE; 3943 3944 return X86EMUL_CONTINUE; 3945 } 3946 3947 /* 3948 * Hardware doesn't save and restore XMM 0-7 without CR4.OSFXSR, but does save 3949 * and restore MXCSR. 3950 */ 3951 static size_t __fxstate_size(int nregs) 3952 { 3953 return offsetof(struct fxregs_state, xmm_space[0]) + nregs * 16; 3954 } 3955 3956 static inline size_t fxstate_size(struct x86_emulate_ctxt *ctxt) 3957 { 3958 bool cr4_osfxsr; 3959 if (ctxt->mode == X86EMUL_MODE_PROT64) 3960 return __fxstate_size(16); 3961 3962 cr4_osfxsr = ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR; 3963 return __fxstate_size(cr4_osfxsr ? 8 : 0); 3964 } 3965 3966 /* 3967 * FXSAVE and FXRSTOR have 4 different formats depending on execution mode, 3968 * 1) 16 bit mode 3969 * 2) 32 bit mode 3970 * - like (1), but FIP and FDP (foo) are only 16 bit. At least Intel CPUs 3971 * preserve whole 32 bit values, though, so (1) and (2) are the same wrt. 3972 * save and restore 3973 * 3) 64-bit mode with REX.W prefix 3974 * - like (2), but XMM 8-15 are being saved and restored 3975 * 4) 64-bit mode without REX.W prefix 3976 * - like (3), but FIP and FDP are 64 bit 3977 * 3978 * Emulation uses (3) for (1) and (2) and preserves XMM 8-15 to reach the 3979 * desired result. (4) is not emulated. 3980 * 3981 * Note: Guest and host CPUID.(EAX=07H,ECX=0H):EBX[bit 13] (deprecate FPU CS 3982 * and FPU DS) should match. 3983 */ 3984 static int em_fxsave(struct x86_emulate_ctxt *ctxt) 3985 { 3986 struct fxregs_state fx_state; 3987 int rc; 3988 3989 rc = check_fxsr(ctxt); 3990 if (rc != X86EMUL_CONTINUE) 3991 return rc; 3992 3993 ctxt->ops->get_fpu(ctxt); 3994 3995 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_state)); 3996 3997 ctxt->ops->put_fpu(ctxt); 3998 3999 if (rc != X86EMUL_CONTINUE) 4000 return rc; 4001 4002 return segmented_write_std(ctxt, ctxt->memop.addr.mem, &fx_state, 4003 fxstate_size(ctxt)); 4004 } 4005 4006 static int em_fxrstor(struct x86_emulate_ctxt *ctxt) 4007 { 4008 struct fxregs_state fx_state; 4009 int rc; 4010 size_t size; 4011 4012 rc = check_fxsr(ctxt); 4013 if (rc != X86EMUL_CONTINUE) 4014 return rc; 4015 4016 ctxt->ops->get_fpu(ctxt); 4017 4018 size = fxstate_size(ctxt); 4019 if (size < __fxstate_size(16)) { 4020 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_state)); 4021 if (rc != X86EMUL_CONTINUE) 4022 goto out; 4023 } 4024 4025 rc = segmented_read_std(ctxt, ctxt->memop.addr.mem, &fx_state, size); 4026 if (rc != X86EMUL_CONTINUE) 4027 goto out; 4028 4029 if (fx_state.mxcsr >> 16) { 4030 rc = emulate_gp(ctxt, 0); 4031 goto out; 4032 } 4033 4034 if (rc == X86EMUL_CONTINUE) 4035 rc = asm_safe("fxrstor %[fx]", : [fx] "m"(fx_state)); 4036 4037 out: 4038 ctxt->ops->put_fpu(ctxt); 4039 4040 return rc; 4041 } 4042 4043 static bool valid_cr(int nr) 4044 { 4045 switch (nr) { 4046 case 0: 4047 case 2 ... 4: 4048 case 8: 4049 return true; 4050 default: 4051 return false; 4052 } 4053 } 4054 4055 static int check_cr_read(struct x86_emulate_ctxt *ctxt) 4056 { 4057 if (!valid_cr(ctxt->modrm_reg)) 4058 return emulate_ud(ctxt); 4059 4060 return X86EMUL_CONTINUE; 4061 } 4062 4063 static int check_cr_write(struct x86_emulate_ctxt *ctxt) 4064 { 4065 u64 new_val = ctxt->src.val64; 4066 int cr = ctxt->modrm_reg; 4067 u64 efer = 0; 4068 4069 static u64 cr_reserved_bits[] = { 4070 0xffffffff00000000ULL, 4071 0, 0, 0, /* CR3 checked later */ 4072 CR4_RESERVED_BITS, 4073 0, 0, 0, 4074 CR8_RESERVED_BITS, 4075 }; 4076 4077 if (!valid_cr(cr)) 4078 return emulate_ud(ctxt); 4079 4080 if (new_val & cr_reserved_bits[cr]) 4081 return emulate_gp(ctxt, 0); 4082 4083 switch (cr) { 4084 case 0: { 4085 u64 cr4; 4086 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) || 4087 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD))) 4088 return emulate_gp(ctxt, 0); 4089 4090 cr4 = ctxt->ops->get_cr(ctxt, 4); 4091 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 4092 4093 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) && 4094 !(cr4 & X86_CR4_PAE)) 4095 return emulate_gp(ctxt, 0); 4096 4097 break; 4098 } 4099 case 3: { 4100 u64 rsvd = 0; 4101 4102 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 4103 if (efer & EFER_LMA) { 4104 u64 maxphyaddr; 4105 u32 eax = 0x80000008; 4106 4107 if (ctxt->ops->get_cpuid(ctxt, &eax, NULL, NULL, 4108 NULL, false)) 4109 maxphyaddr = eax & 0xff; 4110 else 4111 maxphyaddr = 36; 4112 rsvd = rsvd_bits(maxphyaddr, 62); 4113 } 4114 4115 if (new_val & rsvd) 4116 return emulate_gp(ctxt, 0); 4117 4118 break; 4119 } 4120 case 4: { 4121 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 4122 4123 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE)) 4124 return emulate_gp(ctxt, 0); 4125 4126 break; 4127 } 4128 } 4129 4130 return X86EMUL_CONTINUE; 4131 } 4132 4133 static int check_dr7_gd(struct x86_emulate_ctxt *ctxt) 4134 { 4135 unsigned long dr7; 4136 4137 ctxt->ops->get_dr(ctxt, 7, &dr7); 4138 4139 /* Check if DR7.Global_Enable is set */ 4140 return dr7 & (1 << 13); 4141 } 4142 4143 static int check_dr_read(struct x86_emulate_ctxt *ctxt) 4144 { 4145 int dr = ctxt->modrm_reg; 4146 u64 cr4; 4147 4148 if (dr > 7) 4149 return emulate_ud(ctxt); 4150 4151 cr4 = ctxt->ops->get_cr(ctxt, 4); 4152 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5)) 4153 return emulate_ud(ctxt); 4154 4155 if (check_dr7_gd(ctxt)) { 4156 ulong dr6; 4157 4158 ctxt->ops->get_dr(ctxt, 6, &dr6); 4159 dr6 &= ~15; 4160 dr6 |= DR6_BD | DR6_RTM; 4161 ctxt->ops->set_dr(ctxt, 6, dr6); 4162 return emulate_db(ctxt); 4163 } 4164 4165 return X86EMUL_CONTINUE; 4166 } 4167 4168 static int check_dr_write(struct x86_emulate_ctxt *ctxt) 4169 { 4170 u64 new_val = ctxt->src.val64; 4171 int dr = ctxt->modrm_reg; 4172 4173 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL)) 4174 return emulate_gp(ctxt, 0); 4175 4176 return check_dr_read(ctxt); 4177 } 4178 4179 static int check_svme(struct x86_emulate_ctxt *ctxt) 4180 { 4181 u64 efer = 0; 4182 4183 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 4184 4185 if (!(efer & EFER_SVME)) 4186 return emulate_ud(ctxt); 4187 4188 return X86EMUL_CONTINUE; 4189 } 4190 4191 static int check_svme_pa(struct x86_emulate_ctxt *ctxt) 4192 { 4193 u64 rax = reg_read(ctxt, VCPU_REGS_RAX); 4194 4195 /* Valid physical address? */ 4196 if (rax & 0xffff000000000000ULL) 4197 return emulate_gp(ctxt, 0); 4198 4199 return check_svme(ctxt); 4200 } 4201 4202 static int check_rdtsc(struct x86_emulate_ctxt *ctxt) 4203 { 4204 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 4205 4206 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt)) 4207 return emulate_ud(ctxt); 4208 4209 return X86EMUL_CONTINUE; 4210 } 4211 4212 static int check_rdpmc(struct x86_emulate_ctxt *ctxt) 4213 { 4214 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 4215 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX); 4216 4217 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) || 4218 ctxt->ops->check_pmc(ctxt, rcx)) 4219 return emulate_gp(ctxt, 0); 4220 4221 return X86EMUL_CONTINUE; 4222 } 4223 4224 static int check_perm_in(struct x86_emulate_ctxt *ctxt) 4225 { 4226 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u); 4227 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes)) 4228 return emulate_gp(ctxt, 0); 4229 4230 return X86EMUL_CONTINUE; 4231 } 4232 4233 static int check_perm_out(struct x86_emulate_ctxt *ctxt) 4234 { 4235 ctxt->src.bytes = min(ctxt->src.bytes, 4u); 4236 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes)) 4237 return emulate_gp(ctxt, 0); 4238 4239 return X86EMUL_CONTINUE; 4240 } 4241 4242 #define D(_y) { .flags = (_y) } 4243 #define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i } 4244 #define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \ 4245 .intercept = x86_intercept_##_i, .check_perm = (_p) } 4246 #define N D(NotImpl) 4247 #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) } 4248 #define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) } 4249 #define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) } 4250 #define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) } 4251 #define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) } 4252 #define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) } 4253 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } 4254 #define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) } 4255 #define II(_f, _e, _i) \ 4256 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i } 4257 #define IIP(_f, _e, _i, _p) \ 4258 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \ 4259 .intercept = x86_intercept_##_i, .check_perm = (_p) } 4260 #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) } 4261 4262 #define D2bv(_f) D((_f) | ByteOp), D(_f) 4263 #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p) 4264 #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) 4265 #define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e) 4266 #define I2bvIP(_f, _e, _i, _p) \ 4267 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p) 4268 4269 #define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \ 4270 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \ 4271 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e) 4272 4273 static const struct opcode group7_rm0[] = { 4274 N, 4275 I(SrcNone | Priv | EmulateOnUD, em_hypercall), 4276 N, N, N, N, N, N, 4277 }; 4278 4279 static const struct opcode group7_rm1[] = { 4280 DI(SrcNone | Priv, monitor), 4281 DI(SrcNone | Priv, mwait), 4282 N, N, N, N, N, N, 4283 }; 4284 4285 static const struct opcode group7_rm3[] = { 4286 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa), 4287 II(SrcNone | Prot | EmulateOnUD, em_hypercall, vmmcall), 4288 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa), 4289 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa), 4290 DIP(SrcNone | Prot | Priv, stgi, check_svme), 4291 DIP(SrcNone | Prot | Priv, clgi, check_svme), 4292 DIP(SrcNone | Prot | Priv, skinit, check_svme), 4293 DIP(SrcNone | Prot | Priv, invlpga, check_svme), 4294 }; 4295 4296 static const struct opcode group7_rm7[] = { 4297 N, 4298 DIP(SrcNone, rdtscp, check_rdtsc), 4299 N, N, N, N, N, N, 4300 }; 4301 4302 static const struct opcode group1[] = { 4303 F(Lock, em_add), 4304 F(Lock | PageTable, em_or), 4305 F(Lock, em_adc), 4306 F(Lock, em_sbb), 4307 F(Lock | PageTable, em_and), 4308 F(Lock, em_sub), 4309 F(Lock, em_xor), 4310 F(NoWrite, em_cmp), 4311 }; 4312 4313 static const struct opcode group1A[] = { 4314 I(DstMem | SrcNone | Mov | Stack | IncSP | TwoMemOp, em_pop), N, N, N, N, N, N, N, 4315 }; 4316 4317 static const struct opcode group2[] = { 4318 F(DstMem | ModRM, em_rol), 4319 F(DstMem | ModRM, em_ror), 4320 F(DstMem | ModRM, em_rcl), 4321 F(DstMem | ModRM, em_rcr), 4322 F(DstMem | ModRM, em_shl), 4323 F(DstMem | ModRM, em_shr), 4324 F(DstMem | ModRM, em_shl), 4325 F(DstMem | ModRM, em_sar), 4326 }; 4327 4328 static const struct opcode group3[] = { 4329 F(DstMem | SrcImm | NoWrite, em_test), 4330 F(DstMem | SrcImm | NoWrite, em_test), 4331 F(DstMem | SrcNone | Lock, em_not), 4332 F(DstMem | SrcNone | Lock, em_neg), 4333 F(DstXacc | Src2Mem, em_mul_ex), 4334 F(DstXacc | Src2Mem, em_imul_ex), 4335 F(DstXacc | Src2Mem, em_div_ex), 4336 F(DstXacc | Src2Mem, em_idiv_ex), 4337 }; 4338 4339 static const struct opcode group4[] = { 4340 F(ByteOp | DstMem | SrcNone | Lock, em_inc), 4341 F(ByteOp | DstMem | SrcNone | Lock, em_dec), 4342 N, N, N, N, N, N, 4343 }; 4344 4345 static const struct opcode group5[] = { 4346 F(DstMem | SrcNone | Lock, em_inc), 4347 F(DstMem | SrcNone | Lock, em_dec), 4348 I(SrcMem | NearBranch, em_call_near_abs), 4349 I(SrcMemFAddr | ImplicitOps, em_call_far), 4350 I(SrcMem | NearBranch, em_jmp_abs), 4351 I(SrcMemFAddr | ImplicitOps, em_jmp_far), 4352 I(SrcMem | Stack | TwoMemOp, em_push), D(Undefined), 4353 }; 4354 4355 static const struct opcode group6[] = { 4356 DI(Prot | DstMem, sldt), 4357 DI(Prot | DstMem, str), 4358 II(Prot | Priv | SrcMem16, em_lldt, lldt), 4359 II(Prot | Priv | SrcMem16, em_ltr, ltr), 4360 N, N, N, N, 4361 }; 4362 4363 static const struct group_dual group7 = { { 4364 II(Mov | DstMem, em_sgdt, sgdt), 4365 II(Mov | DstMem, em_sidt, sidt), 4366 II(SrcMem | Priv, em_lgdt, lgdt), 4367 II(SrcMem | Priv, em_lidt, lidt), 4368 II(SrcNone | DstMem | Mov, em_smsw, smsw), N, 4369 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), 4370 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg), 4371 }, { 4372 EXT(0, group7_rm0), 4373 EXT(0, group7_rm1), 4374 N, EXT(0, group7_rm3), 4375 II(SrcNone | DstMem | Mov, em_smsw, smsw), N, 4376 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), 4377 EXT(0, group7_rm7), 4378 } }; 4379 4380 static const struct opcode group8[] = { 4381 N, N, N, N, 4382 F(DstMem | SrcImmByte | NoWrite, em_bt), 4383 F(DstMem | SrcImmByte | Lock | PageTable, em_bts), 4384 F(DstMem | SrcImmByte | Lock, em_btr), 4385 F(DstMem | SrcImmByte | Lock | PageTable, em_btc), 4386 }; 4387 4388 static const struct group_dual group9 = { { 4389 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N, 4390 }, { 4391 N, N, N, N, N, N, N, N, 4392 } }; 4393 4394 static const struct opcode group11[] = { 4395 I(DstMem | SrcImm | Mov | PageTable, em_mov), 4396 X7(D(Undefined)), 4397 }; 4398 4399 static const struct gprefix pfx_0f_ae_7 = { 4400 I(SrcMem | ByteOp, em_clflush), N, N, N, 4401 }; 4402 4403 static const struct group_dual group15 = { { 4404 I(ModRM | Aligned16, em_fxsave), 4405 I(ModRM | Aligned16, em_fxrstor), 4406 N, N, N, N, N, GP(0, &pfx_0f_ae_7), 4407 }, { 4408 N, N, N, N, N, N, N, N, 4409 } }; 4410 4411 static const struct gprefix pfx_0f_6f_0f_7f = { 4412 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov), 4413 }; 4414 4415 static const struct instr_dual instr_dual_0f_2b = { 4416 I(0, em_mov), N 4417 }; 4418 4419 static const struct gprefix pfx_0f_2b = { 4420 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N, 4421 }; 4422 4423 static const struct gprefix pfx_0f_28_0f_29 = { 4424 I(Aligned, em_mov), I(Aligned, em_mov), N, N, 4425 }; 4426 4427 static const struct gprefix pfx_0f_e7 = { 4428 N, I(Sse, em_mov), N, N, 4429 }; 4430 4431 static const struct escape escape_d9 = { { 4432 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw), 4433 }, { 4434 /* 0xC0 - 0xC7 */ 4435 N, N, N, N, N, N, N, N, 4436 /* 0xC8 - 0xCF */ 4437 N, N, N, N, N, N, N, N, 4438 /* 0xD0 - 0xC7 */ 4439 N, N, N, N, N, N, N, N, 4440 /* 0xD8 - 0xDF */ 4441 N, N, N, N, N, N, N, N, 4442 /* 0xE0 - 0xE7 */ 4443 N, N, N, N, N, N, N, N, 4444 /* 0xE8 - 0xEF */ 4445 N, N, N, N, N, N, N, N, 4446 /* 0xF0 - 0xF7 */ 4447 N, N, N, N, N, N, N, N, 4448 /* 0xF8 - 0xFF */ 4449 N, N, N, N, N, N, N, N, 4450 } }; 4451 4452 static const struct escape escape_db = { { 4453 N, N, N, N, N, N, N, N, 4454 }, { 4455 /* 0xC0 - 0xC7 */ 4456 N, N, N, N, N, N, N, N, 4457 /* 0xC8 - 0xCF */ 4458 N, N, N, N, N, N, N, N, 4459 /* 0xD0 - 0xC7 */ 4460 N, N, N, N, N, N, N, N, 4461 /* 0xD8 - 0xDF */ 4462 N, N, N, N, N, N, N, N, 4463 /* 0xE0 - 0xE7 */ 4464 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N, 4465 /* 0xE8 - 0xEF */ 4466 N, N, N, N, N, N, N, N, 4467 /* 0xF0 - 0xF7 */ 4468 N, N, N, N, N, N, N, N, 4469 /* 0xF8 - 0xFF */ 4470 N, N, N, N, N, N, N, N, 4471 } }; 4472 4473 static const struct escape escape_dd = { { 4474 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw), 4475 }, { 4476 /* 0xC0 - 0xC7 */ 4477 N, N, N, N, N, N, N, N, 4478 /* 0xC8 - 0xCF */ 4479 N, N, N, N, N, N, N, N, 4480 /* 0xD0 - 0xC7 */ 4481 N, N, N, N, N, N, N, N, 4482 /* 0xD8 - 0xDF */ 4483 N, N, N, N, N, N, N, N, 4484 /* 0xE0 - 0xE7 */ 4485 N, N, N, N, N, N, N, N, 4486 /* 0xE8 - 0xEF */ 4487 N, N, N, N, N, N, N, N, 4488 /* 0xF0 - 0xF7 */ 4489 N, N, N, N, N, N, N, N, 4490 /* 0xF8 - 0xFF */ 4491 N, N, N, N, N, N, N, N, 4492 } }; 4493 4494 static const struct instr_dual instr_dual_0f_c3 = { 4495 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N 4496 }; 4497 4498 static const struct mode_dual mode_dual_63 = { 4499 N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd) 4500 }; 4501 4502 static const struct opcode opcode_table[256] = { 4503 /* 0x00 - 0x07 */ 4504 F6ALU(Lock, em_add), 4505 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg), 4506 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg), 4507 /* 0x08 - 0x0F */ 4508 F6ALU(Lock | PageTable, em_or), 4509 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg), 4510 N, 4511 /* 0x10 - 0x17 */ 4512 F6ALU(Lock, em_adc), 4513 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg), 4514 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg), 4515 /* 0x18 - 0x1F */ 4516 F6ALU(Lock, em_sbb), 4517 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg), 4518 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg), 4519 /* 0x20 - 0x27 */ 4520 F6ALU(Lock | PageTable, em_and), N, N, 4521 /* 0x28 - 0x2F */ 4522 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das), 4523 /* 0x30 - 0x37 */ 4524 F6ALU(Lock, em_xor), N, N, 4525 /* 0x38 - 0x3F */ 4526 F6ALU(NoWrite, em_cmp), N, N, 4527 /* 0x40 - 0x4F */ 4528 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)), 4529 /* 0x50 - 0x57 */ 4530 X8(I(SrcReg | Stack, em_push)), 4531 /* 0x58 - 0x5F */ 4532 X8(I(DstReg | Stack, em_pop)), 4533 /* 0x60 - 0x67 */ 4534 I(ImplicitOps | Stack | No64, em_pusha), 4535 I(ImplicitOps | Stack | No64, em_popa), 4536 N, MD(ModRM, &mode_dual_63), 4537 N, N, N, N, 4538 /* 0x68 - 0x6F */ 4539 I(SrcImm | Mov | Stack, em_push), 4540 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), 4541 I(SrcImmByte | Mov | Stack, em_push), 4542 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), 4543 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */ 4544 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */ 4545 /* 0x70 - 0x7F */ 4546 X16(D(SrcImmByte | NearBranch)), 4547 /* 0x80 - 0x87 */ 4548 G(ByteOp | DstMem | SrcImm, group1), 4549 G(DstMem | SrcImm, group1), 4550 G(ByteOp | DstMem | SrcImm | No64, group1), 4551 G(DstMem | SrcImmByte, group1), 4552 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test), 4553 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg), 4554 /* 0x88 - 0x8F */ 4555 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov), 4556 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov), 4557 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg), 4558 D(ModRM | SrcMem | NoAccess | DstReg), 4559 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm), 4560 G(0, group1A), 4561 /* 0x90 - 0x97 */ 4562 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)), 4563 /* 0x98 - 0x9F */ 4564 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), 4565 I(SrcImmFAddr | No64, em_call_far), N, 4566 II(ImplicitOps | Stack, em_pushf, pushf), 4567 II(ImplicitOps | Stack, em_popf, popf), 4568 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf), 4569 /* 0xA0 - 0xA7 */ 4570 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), 4571 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov), 4572 I2bv(SrcSI | DstDI | Mov | String | TwoMemOp, em_mov), 4573 F2bv(SrcSI | DstDI | String | NoWrite | TwoMemOp, em_cmp_r), 4574 /* 0xA8 - 0xAF */ 4575 F2bv(DstAcc | SrcImm | NoWrite, em_test), 4576 I2bv(SrcAcc | DstDI | Mov | String, em_mov), 4577 I2bv(SrcSI | DstAcc | Mov | String, em_mov), 4578 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r), 4579 /* 0xB0 - 0xB7 */ 4580 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), 4581 /* 0xB8 - 0xBF */ 4582 X8(I(DstReg | SrcImm64 | Mov, em_mov)), 4583 /* 0xC0 - 0xC7 */ 4584 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2), 4585 I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm), 4586 I(ImplicitOps | NearBranch, em_ret), 4587 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg), 4588 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg), 4589 G(ByteOp, group11), G(0, group11), 4590 /* 0xC8 - 0xCF */ 4591 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave), 4592 I(ImplicitOps | SrcImmU16, em_ret_far_imm), 4593 I(ImplicitOps, em_ret_far), 4594 D(ImplicitOps), DI(SrcImmByte, intn), 4595 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret), 4596 /* 0xD0 - 0xD7 */ 4597 G(Src2One | ByteOp, group2), G(Src2One, group2), 4598 G(Src2CL | ByteOp, group2), G(Src2CL, group2), 4599 I(DstAcc | SrcImmUByte | No64, em_aam), 4600 I(DstAcc | SrcImmUByte | No64, em_aad), 4601 F(DstAcc | ByteOp | No64, em_salc), 4602 I(DstAcc | SrcXLat | ByteOp, em_mov), 4603 /* 0xD8 - 0xDF */ 4604 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N, 4605 /* 0xE0 - 0xE7 */ 4606 X3(I(SrcImmByte | NearBranch, em_loop)), 4607 I(SrcImmByte | NearBranch, em_jcxz), 4608 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in), 4609 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out), 4610 /* 0xE8 - 0xEF */ 4611 I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch), 4612 I(SrcImmFAddr | No64, em_jmp_far), 4613 D(SrcImmByte | ImplicitOps | NearBranch), 4614 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in), 4615 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out), 4616 /* 0xF0 - 0xF7 */ 4617 N, DI(ImplicitOps, icebp), N, N, 4618 DI(ImplicitOps | Priv, hlt), D(ImplicitOps), 4619 G(ByteOp, group3), G(0, group3), 4620 /* 0xF8 - 0xFF */ 4621 D(ImplicitOps), D(ImplicitOps), 4622 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti), 4623 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), 4624 }; 4625 4626 static const struct opcode twobyte_table[256] = { 4627 /* 0x00 - 0x0F */ 4628 G(0, group6), GD(0, &group7), N, N, 4629 N, I(ImplicitOps | EmulateOnUD, em_syscall), 4630 II(ImplicitOps | Priv, em_clts, clts), N, 4631 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, 4632 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N, 4633 /* 0x10 - 0x1F */ 4634 N, N, N, N, N, N, N, N, 4635 D(ImplicitOps | ModRM | SrcMem | NoAccess), 4636 N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess), 4637 /* 0x20 - 0x2F */ 4638 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read), 4639 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read), 4640 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write, 4641 check_cr_write), 4642 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write, 4643 check_dr_write), 4644 N, N, N, N, 4645 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29), 4646 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29), 4647 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b), 4648 N, N, N, N, 4649 /* 0x30 - 0x3F */ 4650 II(ImplicitOps | Priv, em_wrmsr, wrmsr), 4651 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc), 4652 II(ImplicitOps | Priv, em_rdmsr, rdmsr), 4653 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc), 4654 I(ImplicitOps | EmulateOnUD, em_sysenter), 4655 I(ImplicitOps | Priv | EmulateOnUD, em_sysexit), 4656 N, N, 4657 N, N, N, N, N, N, N, N, 4658 /* 0x40 - 0x4F */ 4659 X16(D(DstReg | SrcMem | ModRM)), 4660 /* 0x50 - 0x5F */ 4661 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 4662 /* 0x60 - 0x6F */ 4663 N, N, N, N, 4664 N, N, N, N, 4665 N, N, N, N, 4666 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f), 4667 /* 0x70 - 0x7F */ 4668 N, N, N, N, 4669 N, N, N, N, 4670 N, N, N, N, 4671 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f), 4672 /* 0x80 - 0x8F */ 4673 X16(D(SrcImm | NearBranch)), 4674 /* 0x90 - 0x9F */ 4675 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), 4676 /* 0xA0 - 0xA7 */ 4677 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg), 4678 II(ImplicitOps, em_cpuid, cpuid), 4679 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt), 4680 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld), 4681 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N, 4682 /* 0xA8 - 0xAF */ 4683 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg), 4684 II(EmulateOnUD | ImplicitOps, em_rsm, rsm), 4685 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts), 4686 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd), 4687 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd), 4688 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul), 4689 /* 0xB0 - 0xB7 */ 4690 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg), 4691 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg), 4692 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr), 4693 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg), 4694 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg), 4695 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 4696 /* 0xB8 - 0xBF */ 4697 N, N, 4698 G(BitOp, group8), 4699 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc), 4700 I(DstReg | SrcMem | ModRM, em_bsf_c), 4701 I(DstReg | SrcMem | ModRM, em_bsr_c), 4702 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 4703 /* 0xC0 - 0xC7 */ 4704 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd), 4705 N, ID(0, &instr_dual_0f_c3), 4706 N, N, N, GD(0, &group9), 4707 /* 0xC8 - 0xCF */ 4708 X8(I(DstReg, em_bswap)), 4709 /* 0xD0 - 0xDF */ 4710 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 4711 /* 0xE0 - 0xEF */ 4712 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7), 4713 N, N, N, N, N, N, N, N, 4714 /* 0xF0 - 0xFF */ 4715 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N 4716 }; 4717 4718 static const struct instr_dual instr_dual_0f_38_f0 = { 4719 I(DstReg | SrcMem | Mov, em_movbe), N 4720 }; 4721 4722 static const struct instr_dual instr_dual_0f_38_f1 = { 4723 I(DstMem | SrcReg | Mov, em_movbe), N 4724 }; 4725 4726 static const struct gprefix three_byte_0f_38_f0 = { 4727 ID(0, &instr_dual_0f_38_f0), N, N, N 4728 }; 4729 4730 static const struct gprefix three_byte_0f_38_f1 = { 4731 ID(0, &instr_dual_0f_38_f1), N, N, N 4732 }; 4733 4734 /* 4735 * Insns below are selected by the prefix which indexed by the third opcode 4736 * byte. 4737 */ 4738 static const struct opcode opcode_map_0f_38[256] = { 4739 /* 0x00 - 0x7f */ 4740 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), 4741 /* 0x80 - 0xef */ 4742 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), 4743 /* 0xf0 - 0xf1 */ 4744 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0), 4745 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1), 4746 /* 0xf2 - 0xff */ 4747 N, N, X4(N), X8(N) 4748 }; 4749 4750 #undef D 4751 #undef N 4752 #undef G 4753 #undef GD 4754 #undef I 4755 #undef GP 4756 #undef EXT 4757 #undef MD 4758 #undef ID 4759 4760 #undef D2bv 4761 #undef D2bvIP 4762 #undef I2bv 4763 #undef I2bvIP 4764 #undef I6ALU 4765 4766 static unsigned imm_size(struct x86_emulate_ctxt *ctxt) 4767 { 4768 unsigned size; 4769 4770 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4771 if (size == 8) 4772 size = 4; 4773 return size; 4774 } 4775 4776 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, 4777 unsigned size, bool sign_extension) 4778 { 4779 int rc = X86EMUL_CONTINUE; 4780 4781 op->type = OP_IMM; 4782 op->bytes = size; 4783 op->addr.mem.ea = ctxt->_eip; 4784 /* NB. Immediates are sign-extended as necessary. */ 4785 switch (op->bytes) { 4786 case 1: 4787 op->val = insn_fetch(s8, ctxt); 4788 break; 4789 case 2: 4790 op->val = insn_fetch(s16, ctxt); 4791 break; 4792 case 4: 4793 op->val = insn_fetch(s32, ctxt); 4794 break; 4795 case 8: 4796 op->val = insn_fetch(s64, ctxt); 4797 break; 4798 } 4799 if (!sign_extension) { 4800 switch (op->bytes) { 4801 case 1: 4802 op->val &= 0xff; 4803 break; 4804 case 2: 4805 op->val &= 0xffff; 4806 break; 4807 case 4: 4808 op->val &= 0xffffffff; 4809 break; 4810 } 4811 } 4812 done: 4813 return rc; 4814 } 4815 4816 static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op, 4817 unsigned d) 4818 { 4819 int rc = X86EMUL_CONTINUE; 4820 4821 switch (d) { 4822 case OpReg: 4823 decode_register_operand(ctxt, op); 4824 break; 4825 case OpImmUByte: 4826 rc = decode_imm(ctxt, op, 1, false); 4827 break; 4828 case OpMem: 4829 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4830 mem_common: 4831 *op = ctxt->memop; 4832 ctxt->memopp = op; 4833 if (ctxt->d & BitOp) 4834 fetch_bit_operand(ctxt); 4835 op->orig_val = op->val; 4836 break; 4837 case OpMem64: 4838 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8; 4839 goto mem_common; 4840 case OpAcc: 4841 op->type = OP_REG; 4842 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4843 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 4844 fetch_register_operand(op); 4845 op->orig_val = op->val; 4846 break; 4847 case OpAccLo: 4848 op->type = OP_REG; 4849 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes; 4850 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 4851 fetch_register_operand(op); 4852 op->orig_val = op->val; 4853 break; 4854 case OpAccHi: 4855 if (ctxt->d & ByteOp) { 4856 op->type = OP_NONE; 4857 break; 4858 } 4859 op->type = OP_REG; 4860 op->bytes = ctxt->op_bytes; 4861 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 4862 fetch_register_operand(op); 4863 op->orig_val = op->val; 4864 break; 4865 case OpDI: 4866 op->type = OP_MEM; 4867 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4868 op->addr.mem.ea = 4869 register_address(ctxt, VCPU_REGS_RDI); 4870 op->addr.mem.seg = VCPU_SREG_ES; 4871 op->val = 0; 4872 op->count = 1; 4873 break; 4874 case OpDX: 4875 op->type = OP_REG; 4876 op->bytes = 2; 4877 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 4878 fetch_register_operand(op); 4879 break; 4880 case OpCL: 4881 op->type = OP_IMM; 4882 op->bytes = 1; 4883 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff; 4884 break; 4885 case OpImmByte: 4886 rc = decode_imm(ctxt, op, 1, true); 4887 break; 4888 case OpOne: 4889 op->type = OP_IMM; 4890 op->bytes = 1; 4891 op->val = 1; 4892 break; 4893 case OpImm: 4894 rc = decode_imm(ctxt, op, imm_size(ctxt), true); 4895 break; 4896 case OpImm64: 4897 rc = decode_imm(ctxt, op, ctxt->op_bytes, true); 4898 break; 4899 case OpMem8: 4900 ctxt->memop.bytes = 1; 4901 if (ctxt->memop.type == OP_REG) { 4902 ctxt->memop.addr.reg = decode_register(ctxt, 4903 ctxt->modrm_rm, true); 4904 fetch_register_operand(&ctxt->memop); 4905 } 4906 goto mem_common; 4907 case OpMem16: 4908 ctxt->memop.bytes = 2; 4909 goto mem_common; 4910 case OpMem32: 4911 ctxt->memop.bytes = 4; 4912 goto mem_common; 4913 case OpImmU16: 4914 rc = decode_imm(ctxt, op, 2, false); 4915 break; 4916 case OpImmU: 4917 rc = decode_imm(ctxt, op, imm_size(ctxt), false); 4918 break; 4919 case OpSI: 4920 op->type = OP_MEM; 4921 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4922 op->addr.mem.ea = 4923 register_address(ctxt, VCPU_REGS_RSI); 4924 op->addr.mem.seg = ctxt->seg_override; 4925 op->val = 0; 4926 op->count = 1; 4927 break; 4928 case OpXLat: 4929 op->type = OP_MEM; 4930 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4931 op->addr.mem.ea = 4932 address_mask(ctxt, 4933 reg_read(ctxt, VCPU_REGS_RBX) + 4934 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff)); 4935 op->addr.mem.seg = ctxt->seg_override; 4936 op->val = 0; 4937 break; 4938 case OpImmFAddr: 4939 op->type = OP_IMM; 4940 op->addr.mem.ea = ctxt->_eip; 4941 op->bytes = ctxt->op_bytes + 2; 4942 insn_fetch_arr(op->valptr, op->bytes, ctxt); 4943 break; 4944 case OpMemFAddr: 4945 ctxt->memop.bytes = ctxt->op_bytes + 2; 4946 goto mem_common; 4947 case OpES: 4948 op->type = OP_IMM; 4949 op->val = VCPU_SREG_ES; 4950 break; 4951 case OpCS: 4952 op->type = OP_IMM; 4953 op->val = VCPU_SREG_CS; 4954 break; 4955 case OpSS: 4956 op->type = OP_IMM; 4957 op->val = VCPU_SREG_SS; 4958 break; 4959 case OpDS: 4960 op->type = OP_IMM; 4961 op->val = VCPU_SREG_DS; 4962 break; 4963 case OpFS: 4964 op->type = OP_IMM; 4965 op->val = VCPU_SREG_FS; 4966 break; 4967 case OpGS: 4968 op->type = OP_IMM; 4969 op->val = VCPU_SREG_GS; 4970 break; 4971 case OpImplicit: 4972 /* Special instructions do their own operand decoding. */ 4973 default: 4974 op->type = OP_NONE; /* Disable writeback. */ 4975 break; 4976 } 4977 4978 done: 4979 return rc; 4980 } 4981 4982 int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len) 4983 { 4984 int rc = X86EMUL_CONTINUE; 4985 int mode = ctxt->mode; 4986 int def_op_bytes, def_ad_bytes, goffset, simd_prefix; 4987 bool op_prefix = false; 4988 bool has_seg_override = false; 4989 struct opcode opcode; 4990 4991 ctxt->memop.type = OP_NONE; 4992 ctxt->memopp = NULL; 4993 ctxt->_eip = ctxt->eip; 4994 ctxt->fetch.ptr = ctxt->fetch.data; 4995 ctxt->fetch.end = ctxt->fetch.data + insn_len; 4996 ctxt->opcode_len = 1; 4997 if (insn_len > 0) 4998 memcpy(ctxt->fetch.data, insn, insn_len); 4999 else { 5000 rc = __do_insn_fetch_bytes(ctxt, 1); 5001 if (rc != X86EMUL_CONTINUE) 5002 return rc; 5003 } 5004 5005 switch (mode) { 5006 case X86EMUL_MODE_REAL: 5007 case X86EMUL_MODE_VM86: 5008 case X86EMUL_MODE_PROT16: 5009 def_op_bytes = def_ad_bytes = 2; 5010 break; 5011 case X86EMUL_MODE_PROT32: 5012 def_op_bytes = def_ad_bytes = 4; 5013 break; 5014 #ifdef CONFIG_X86_64 5015 case X86EMUL_MODE_PROT64: 5016 def_op_bytes = 4; 5017 def_ad_bytes = 8; 5018 break; 5019 #endif 5020 default: 5021 return EMULATION_FAILED; 5022 } 5023 5024 ctxt->op_bytes = def_op_bytes; 5025 ctxt->ad_bytes = def_ad_bytes; 5026 5027 /* Legacy prefixes. */ 5028 for (;;) { 5029 switch (ctxt->b = insn_fetch(u8, ctxt)) { 5030 case 0x66: /* operand-size override */ 5031 op_prefix = true; 5032 /* switch between 2/4 bytes */ 5033 ctxt->op_bytes = def_op_bytes ^ 6; 5034 break; 5035 case 0x67: /* address-size override */ 5036 if (mode == X86EMUL_MODE_PROT64) 5037 /* switch between 4/8 bytes */ 5038 ctxt->ad_bytes = def_ad_bytes ^ 12; 5039 else 5040 /* switch between 2/4 bytes */ 5041 ctxt->ad_bytes = def_ad_bytes ^ 6; 5042 break; 5043 case 0x26: /* ES override */ 5044 case 0x2e: /* CS override */ 5045 case 0x36: /* SS override */ 5046 case 0x3e: /* DS override */ 5047 has_seg_override = true; 5048 ctxt->seg_override = (ctxt->b >> 3) & 3; 5049 break; 5050 case 0x64: /* FS override */ 5051 case 0x65: /* GS override */ 5052 has_seg_override = true; 5053 ctxt->seg_override = ctxt->b & 7; 5054 break; 5055 case 0x40 ... 0x4f: /* REX */ 5056 if (mode != X86EMUL_MODE_PROT64) 5057 goto done_prefixes; 5058 ctxt->rex_prefix = ctxt->b; 5059 continue; 5060 case 0xf0: /* LOCK */ 5061 ctxt->lock_prefix = 1; 5062 break; 5063 case 0xf2: /* REPNE/REPNZ */ 5064 case 0xf3: /* REP/REPE/REPZ */ 5065 ctxt->rep_prefix = ctxt->b; 5066 break; 5067 default: 5068 goto done_prefixes; 5069 } 5070 5071 /* Any legacy prefix after a REX prefix nullifies its effect. */ 5072 5073 ctxt->rex_prefix = 0; 5074 } 5075 5076 done_prefixes: 5077 5078 /* REX prefix. */ 5079 if (ctxt->rex_prefix & 8) 5080 ctxt->op_bytes = 8; /* REX.W */ 5081 5082 /* Opcode byte(s). */ 5083 opcode = opcode_table[ctxt->b]; 5084 /* Two-byte opcode? */ 5085 if (ctxt->b == 0x0f) { 5086 ctxt->opcode_len = 2; 5087 ctxt->b = insn_fetch(u8, ctxt); 5088 opcode = twobyte_table[ctxt->b]; 5089 5090 /* 0F_38 opcode map */ 5091 if (ctxt->b == 0x38) { 5092 ctxt->opcode_len = 3; 5093 ctxt->b = insn_fetch(u8, ctxt); 5094 opcode = opcode_map_0f_38[ctxt->b]; 5095 } 5096 } 5097 ctxt->d = opcode.flags; 5098 5099 if (ctxt->d & ModRM) 5100 ctxt->modrm = insn_fetch(u8, ctxt); 5101 5102 /* vex-prefix instructions are not implemented */ 5103 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) && 5104 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) { 5105 ctxt->d = NotImpl; 5106 } 5107 5108 while (ctxt->d & GroupMask) { 5109 switch (ctxt->d & GroupMask) { 5110 case Group: 5111 goffset = (ctxt->modrm >> 3) & 7; 5112 opcode = opcode.u.group[goffset]; 5113 break; 5114 case GroupDual: 5115 goffset = (ctxt->modrm >> 3) & 7; 5116 if ((ctxt->modrm >> 6) == 3) 5117 opcode = opcode.u.gdual->mod3[goffset]; 5118 else 5119 opcode = opcode.u.gdual->mod012[goffset]; 5120 break; 5121 case RMExt: 5122 goffset = ctxt->modrm & 7; 5123 opcode = opcode.u.group[goffset]; 5124 break; 5125 case Prefix: 5126 if (ctxt->rep_prefix && op_prefix) 5127 return EMULATION_FAILED; 5128 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix; 5129 switch (simd_prefix) { 5130 case 0x00: opcode = opcode.u.gprefix->pfx_no; break; 5131 case 0x66: opcode = opcode.u.gprefix->pfx_66; break; 5132 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break; 5133 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break; 5134 } 5135 break; 5136 case Escape: 5137 if (ctxt->modrm > 0xbf) 5138 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0]; 5139 else 5140 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7]; 5141 break; 5142 case InstrDual: 5143 if ((ctxt->modrm >> 6) == 3) 5144 opcode = opcode.u.idual->mod3; 5145 else 5146 opcode = opcode.u.idual->mod012; 5147 break; 5148 case ModeDual: 5149 if (ctxt->mode == X86EMUL_MODE_PROT64) 5150 opcode = opcode.u.mdual->mode64; 5151 else 5152 opcode = opcode.u.mdual->mode32; 5153 break; 5154 default: 5155 return EMULATION_FAILED; 5156 } 5157 5158 ctxt->d &= ~(u64)GroupMask; 5159 ctxt->d |= opcode.flags; 5160 } 5161 5162 /* Unrecognised? */ 5163 if (ctxt->d == 0) 5164 return EMULATION_FAILED; 5165 5166 ctxt->execute = opcode.u.execute; 5167 5168 if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD))) 5169 return EMULATION_FAILED; 5170 5171 if (unlikely(ctxt->d & 5172 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch| 5173 No16))) { 5174 /* 5175 * These are copied unconditionally here, and checked unconditionally 5176 * in x86_emulate_insn. 5177 */ 5178 ctxt->check_perm = opcode.check_perm; 5179 ctxt->intercept = opcode.intercept; 5180 5181 if (ctxt->d & NotImpl) 5182 return EMULATION_FAILED; 5183 5184 if (mode == X86EMUL_MODE_PROT64) { 5185 if (ctxt->op_bytes == 4 && (ctxt->d & Stack)) 5186 ctxt->op_bytes = 8; 5187 else if (ctxt->d & NearBranch) 5188 ctxt->op_bytes = 8; 5189 } 5190 5191 if (ctxt->d & Op3264) { 5192 if (mode == X86EMUL_MODE_PROT64) 5193 ctxt->op_bytes = 8; 5194 else 5195 ctxt->op_bytes = 4; 5196 } 5197 5198 if ((ctxt->d & No16) && ctxt->op_bytes == 2) 5199 ctxt->op_bytes = 4; 5200 5201 if (ctxt->d & Sse) 5202 ctxt->op_bytes = 16; 5203 else if (ctxt->d & Mmx) 5204 ctxt->op_bytes = 8; 5205 } 5206 5207 /* ModRM and SIB bytes. */ 5208 if (ctxt->d & ModRM) { 5209 rc = decode_modrm(ctxt, &ctxt->memop); 5210 if (!has_seg_override) { 5211 has_seg_override = true; 5212 ctxt->seg_override = ctxt->modrm_seg; 5213 } 5214 } else if (ctxt->d & MemAbs) 5215 rc = decode_abs(ctxt, &ctxt->memop); 5216 if (rc != X86EMUL_CONTINUE) 5217 goto done; 5218 5219 if (!has_seg_override) 5220 ctxt->seg_override = VCPU_SREG_DS; 5221 5222 ctxt->memop.addr.mem.seg = ctxt->seg_override; 5223 5224 /* 5225 * Decode and fetch the source operand: register, memory 5226 * or immediate. 5227 */ 5228 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask); 5229 if (rc != X86EMUL_CONTINUE) 5230 goto done; 5231 5232 /* 5233 * Decode and fetch the second source operand: register, memory 5234 * or immediate. 5235 */ 5236 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask); 5237 if (rc != X86EMUL_CONTINUE) 5238 goto done; 5239 5240 /* Decode and fetch the destination operand: register or memory. */ 5241 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask); 5242 5243 if (ctxt->rip_relative && likely(ctxt->memopp)) 5244 ctxt->memopp->addr.mem.ea = address_mask(ctxt, 5245 ctxt->memopp->addr.mem.ea + ctxt->_eip); 5246 5247 done: 5248 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK; 5249 } 5250 5251 bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt) 5252 { 5253 return ctxt->d & PageTable; 5254 } 5255 5256 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt) 5257 { 5258 /* The second termination condition only applies for REPE 5259 * and REPNE. Test if the repeat string operation prefix is 5260 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the 5261 * corresponding termination condition according to: 5262 * - if REPE/REPZ and ZF = 0 then done 5263 * - if REPNE/REPNZ and ZF = 1 then done 5264 */ 5265 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) || 5266 (ctxt->b == 0xae) || (ctxt->b == 0xaf)) 5267 && (((ctxt->rep_prefix == REPE_PREFIX) && 5268 ((ctxt->eflags & X86_EFLAGS_ZF) == 0)) 5269 || ((ctxt->rep_prefix == REPNE_PREFIX) && 5270 ((ctxt->eflags & X86_EFLAGS_ZF) == X86_EFLAGS_ZF)))) 5271 return true; 5272 5273 return false; 5274 } 5275 5276 static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt) 5277 { 5278 int rc; 5279 5280 ctxt->ops->get_fpu(ctxt); 5281 rc = asm_safe("fwait"); 5282 ctxt->ops->put_fpu(ctxt); 5283 5284 if (unlikely(rc != X86EMUL_CONTINUE)) 5285 return emulate_exception(ctxt, MF_VECTOR, 0, false); 5286 5287 return X86EMUL_CONTINUE; 5288 } 5289 5290 static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt, 5291 struct operand *op) 5292 { 5293 if (op->type == OP_MM) 5294 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm); 5295 } 5296 5297 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *)) 5298 { 5299 register void *__sp asm(_ASM_SP); 5300 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF; 5301 5302 if (!(ctxt->d & ByteOp)) 5303 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE; 5304 5305 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n" 5306 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags), 5307 [fastop]"+S"(fop), "+r"(__sp) 5308 : "c"(ctxt->src2.val)); 5309 5310 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK); 5311 if (!fop) /* exception is returned in fop variable */ 5312 return emulate_de(ctxt); 5313 return X86EMUL_CONTINUE; 5314 } 5315 5316 void init_decode_cache(struct x86_emulate_ctxt *ctxt) 5317 { 5318 memset(&ctxt->rip_relative, 0, 5319 (void *)&ctxt->modrm - (void *)&ctxt->rip_relative); 5320 5321 ctxt->io_read.pos = 0; 5322 ctxt->io_read.end = 0; 5323 ctxt->mem_read.end = 0; 5324 } 5325 5326 int x86_emulate_insn(struct x86_emulate_ctxt *ctxt) 5327 { 5328 const struct x86_emulate_ops *ops = ctxt->ops; 5329 int rc = X86EMUL_CONTINUE; 5330 int saved_dst_type = ctxt->dst.type; 5331 unsigned emul_flags; 5332 5333 ctxt->mem_read.pos = 0; 5334 5335 /* LOCK prefix is allowed only with some instructions */ 5336 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) { 5337 rc = emulate_ud(ctxt); 5338 goto done; 5339 } 5340 5341 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) { 5342 rc = emulate_ud(ctxt); 5343 goto done; 5344 } 5345 5346 emul_flags = ctxt->ops->get_hflags(ctxt); 5347 if (unlikely(ctxt->d & 5348 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) { 5349 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) || 5350 (ctxt->d & Undefined)) { 5351 rc = emulate_ud(ctxt); 5352 goto done; 5353 } 5354 5355 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM))) 5356 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) { 5357 rc = emulate_ud(ctxt); 5358 goto done; 5359 } 5360 5361 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) { 5362 rc = emulate_nm(ctxt); 5363 goto done; 5364 } 5365 5366 if (ctxt->d & Mmx) { 5367 rc = flush_pending_x87_faults(ctxt); 5368 if (rc != X86EMUL_CONTINUE) 5369 goto done; 5370 /* 5371 * Now that we know the fpu is exception safe, we can fetch 5372 * operands from it. 5373 */ 5374 fetch_possible_mmx_operand(ctxt, &ctxt->src); 5375 fetch_possible_mmx_operand(ctxt, &ctxt->src2); 5376 if (!(ctxt->d & Mov)) 5377 fetch_possible_mmx_operand(ctxt, &ctxt->dst); 5378 } 5379 5380 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && ctxt->intercept) { 5381 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5382 X86_ICPT_PRE_EXCEPT); 5383 if (rc != X86EMUL_CONTINUE) 5384 goto done; 5385 } 5386 5387 /* Instruction can only be executed in protected mode */ 5388 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) { 5389 rc = emulate_ud(ctxt); 5390 goto done; 5391 } 5392 5393 /* Privileged instruction can be executed only in CPL=0 */ 5394 if ((ctxt->d & Priv) && ops->cpl(ctxt)) { 5395 if (ctxt->d & PrivUD) 5396 rc = emulate_ud(ctxt); 5397 else 5398 rc = emulate_gp(ctxt, 0); 5399 goto done; 5400 } 5401 5402 /* Do instruction specific permission checks */ 5403 if (ctxt->d & CheckPerm) { 5404 rc = ctxt->check_perm(ctxt); 5405 if (rc != X86EMUL_CONTINUE) 5406 goto done; 5407 } 5408 5409 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) { 5410 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5411 X86_ICPT_POST_EXCEPT); 5412 if (rc != X86EMUL_CONTINUE) 5413 goto done; 5414 } 5415 5416 if (ctxt->rep_prefix && (ctxt->d & String)) { 5417 /* All REP prefixes have the same first termination condition */ 5418 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) { 5419 string_registers_quirk(ctxt); 5420 ctxt->eip = ctxt->_eip; 5421 ctxt->eflags &= ~X86_EFLAGS_RF; 5422 goto done; 5423 } 5424 } 5425 } 5426 5427 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) { 5428 rc = segmented_read(ctxt, ctxt->src.addr.mem, 5429 ctxt->src.valptr, ctxt->src.bytes); 5430 if (rc != X86EMUL_CONTINUE) 5431 goto done; 5432 ctxt->src.orig_val64 = ctxt->src.val64; 5433 } 5434 5435 if (ctxt->src2.type == OP_MEM) { 5436 rc = segmented_read(ctxt, ctxt->src2.addr.mem, 5437 &ctxt->src2.val, ctxt->src2.bytes); 5438 if (rc != X86EMUL_CONTINUE) 5439 goto done; 5440 } 5441 5442 if ((ctxt->d & DstMask) == ImplicitOps) 5443 goto special_insn; 5444 5445 5446 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) { 5447 /* optimisation - avoid slow emulated read if Mov */ 5448 rc = segmented_read(ctxt, ctxt->dst.addr.mem, 5449 &ctxt->dst.val, ctxt->dst.bytes); 5450 if (rc != X86EMUL_CONTINUE) { 5451 if (!(ctxt->d & NoWrite) && 5452 rc == X86EMUL_PROPAGATE_FAULT && 5453 ctxt->exception.vector == PF_VECTOR) 5454 ctxt->exception.error_code |= PFERR_WRITE_MASK; 5455 goto done; 5456 } 5457 } 5458 /* Copy full 64-bit value for CMPXCHG8B. */ 5459 ctxt->dst.orig_val64 = ctxt->dst.val64; 5460 5461 special_insn: 5462 5463 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) { 5464 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5465 X86_ICPT_POST_MEMACCESS); 5466 if (rc != X86EMUL_CONTINUE) 5467 goto done; 5468 } 5469 5470 if (ctxt->rep_prefix && (ctxt->d & String)) 5471 ctxt->eflags |= X86_EFLAGS_RF; 5472 else 5473 ctxt->eflags &= ~X86_EFLAGS_RF; 5474 5475 if (ctxt->execute) { 5476 if (ctxt->d & Fastop) { 5477 void (*fop)(struct fastop *) = (void *)ctxt->execute; 5478 rc = fastop(ctxt, fop); 5479 if (rc != X86EMUL_CONTINUE) 5480 goto done; 5481 goto writeback; 5482 } 5483 rc = ctxt->execute(ctxt); 5484 if (rc != X86EMUL_CONTINUE) 5485 goto done; 5486 goto writeback; 5487 } 5488 5489 if (ctxt->opcode_len == 2) 5490 goto twobyte_insn; 5491 else if (ctxt->opcode_len == 3) 5492 goto threebyte_insn; 5493 5494 switch (ctxt->b) { 5495 case 0x70 ... 0x7f: /* jcc (short) */ 5496 if (test_cc(ctxt->b, ctxt->eflags)) 5497 rc = jmp_rel(ctxt, ctxt->src.val); 5498 break; 5499 case 0x8d: /* lea r16/r32, m */ 5500 ctxt->dst.val = ctxt->src.addr.mem.ea; 5501 break; 5502 case 0x90 ... 0x97: /* nop / xchg reg, rax */ 5503 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX)) 5504 ctxt->dst.type = OP_NONE; 5505 else 5506 rc = em_xchg(ctxt); 5507 break; 5508 case 0x98: /* cbw/cwde/cdqe */ 5509 switch (ctxt->op_bytes) { 5510 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break; 5511 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break; 5512 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break; 5513 } 5514 break; 5515 case 0xcc: /* int3 */ 5516 rc = emulate_int(ctxt, 3); 5517 break; 5518 case 0xcd: /* int n */ 5519 rc = emulate_int(ctxt, ctxt->src.val); 5520 break; 5521 case 0xce: /* into */ 5522 if (ctxt->eflags & X86_EFLAGS_OF) 5523 rc = emulate_int(ctxt, 4); 5524 break; 5525 case 0xe9: /* jmp rel */ 5526 case 0xeb: /* jmp rel short */ 5527 rc = jmp_rel(ctxt, ctxt->src.val); 5528 ctxt->dst.type = OP_NONE; /* Disable writeback. */ 5529 break; 5530 case 0xf4: /* hlt */ 5531 ctxt->ops->halt(ctxt); 5532 break; 5533 case 0xf5: /* cmc */ 5534 /* complement carry flag from eflags reg */ 5535 ctxt->eflags ^= X86_EFLAGS_CF; 5536 break; 5537 case 0xf8: /* clc */ 5538 ctxt->eflags &= ~X86_EFLAGS_CF; 5539 break; 5540 case 0xf9: /* stc */ 5541 ctxt->eflags |= X86_EFLAGS_CF; 5542 break; 5543 case 0xfc: /* cld */ 5544 ctxt->eflags &= ~X86_EFLAGS_DF; 5545 break; 5546 case 0xfd: /* std */ 5547 ctxt->eflags |= X86_EFLAGS_DF; 5548 break; 5549 default: 5550 goto cannot_emulate; 5551 } 5552 5553 if (rc != X86EMUL_CONTINUE) 5554 goto done; 5555 5556 writeback: 5557 if (ctxt->d & SrcWrite) { 5558 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR); 5559 rc = writeback(ctxt, &ctxt->src); 5560 if (rc != X86EMUL_CONTINUE) 5561 goto done; 5562 } 5563 if (!(ctxt->d & NoWrite)) { 5564 rc = writeback(ctxt, &ctxt->dst); 5565 if (rc != X86EMUL_CONTINUE) 5566 goto done; 5567 } 5568 5569 /* 5570 * restore dst type in case the decoding will be reused 5571 * (happens for string instruction ) 5572 */ 5573 ctxt->dst.type = saved_dst_type; 5574 5575 if ((ctxt->d & SrcMask) == SrcSI) 5576 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src); 5577 5578 if ((ctxt->d & DstMask) == DstDI) 5579 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst); 5580 5581 if (ctxt->rep_prefix && (ctxt->d & String)) { 5582 unsigned int count; 5583 struct read_cache *r = &ctxt->io_read; 5584 if ((ctxt->d & SrcMask) == SrcSI) 5585 count = ctxt->src.count; 5586 else 5587 count = ctxt->dst.count; 5588 register_address_increment(ctxt, VCPU_REGS_RCX, -count); 5589 5590 if (!string_insn_completed(ctxt)) { 5591 /* 5592 * Re-enter guest when pio read ahead buffer is empty 5593 * or, if it is not used, after each 1024 iteration. 5594 */ 5595 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) && 5596 (r->end == 0 || r->end != r->pos)) { 5597 /* 5598 * Reset read cache. Usually happens before 5599 * decode, but since instruction is restarted 5600 * we have to do it here. 5601 */ 5602 ctxt->mem_read.end = 0; 5603 writeback_registers(ctxt); 5604 return EMULATION_RESTART; 5605 } 5606 goto done; /* skip rip writeback */ 5607 } 5608 ctxt->eflags &= ~X86_EFLAGS_RF; 5609 } 5610 5611 ctxt->eip = ctxt->_eip; 5612 5613 done: 5614 if (rc == X86EMUL_PROPAGATE_FAULT) { 5615 WARN_ON(ctxt->exception.vector > 0x1f); 5616 ctxt->have_exception = true; 5617 } 5618 if (rc == X86EMUL_INTERCEPTED) 5619 return EMULATION_INTERCEPTED; 5620 5621 if (rc == X86EMUL_CONTINUE) 5622 writeback_registers(ctxt); 5623 5624 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 5625 5626 twobyte_insn: 5627 switch (ctxt->b) { 5628 case 0x09: /* wbinvd */ 5629 (ctxt->ops->wbinvd)(ctxt); 5630 break; 5631 case 0x08: /* invd */ 5632 case 0x0d: /* GrpP (prefetch) */ 5633 case 0x18: /* Grp16 (prefetch/nop) */ 5634 case 0x1f: /* nop */ 5635 break; 5636 case 0x20: /* mov cr, reg */ 5637 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg); 5638 break; 5639 case 0x21: /* mov from dr to reg */ 5640 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val); 5641 break; 5642 case 0x40 ... 0x4f: /* cmov */ 5643 if (test_cc(ctxt->b, ctxt->eflags)) 5644 ctxt->dst.val = ctxt->src.val; 5645 else if (ctxt->op_bytes != 4) 5646 ctxt->dst.type = OP_NONE; /* no writeback */ 5647 break; 5648 case 0x80 ... 0x8f: /* jnz rel, etc*/ 5649 if (test_cc(ctxt->b, ctxt->eflags)) 5650 rc = jmp_rel(ctxt, ctxt->src.val); 5651 break; 5652 case 0x90 ... 0x9f: /* setcc r/m8 */ 5653 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags); 5654 break; 5655 case 0xb6 ... 0xb7: /* movzx */ 5656 ctxt->dst.bytes = ctxt->op_bytes; 5657 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val 5658 : (u16) ctxt->src.val; 5659 break; 5660 case 0xbe ... 0xbf: /* movsx */ 5661 ctxt->dst.bytes = ctxt->op_bytes; 5662 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val : 5663 (s16) ctxt->src.val; 5664 break; 5665 default: 5666 goto cannot_emulate; 5667 } 5668 5669 threebyte_insn: 5670 5671 if (rc != X86EMUL_CONTINUE) 5672 goto done; 5673 5674 goto writeback; 5675 5676 cannot_emulate: 5677 return EMULATION_FAILED; 5678 } 5679 5680 void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt) 5681 { 5682 invalidate_registers(ctxt); 5683 } 5684 5685 void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt) 5686 { 5687 writeback_registers(ctxt); 5688 } 5689 5690 bool emulator_can_use_gpa(struct x86_emulate_ctxt *ctxt) 5691 { 5692 if (ctxt->rep_prefix && (ctxt->d & String)) 5693 return false; 5694 5695 if (ctxt->d & TwoMemOp) 5696 return false; 5697 5698 return true; 5699 } 5700