1 /****************************************************************************** 2 * emulate.c 3 * 4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. 5 * 6 * Copyright (c) 2005 Keir Fraser 7 * 8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode 9 * privileged instructions: 10 * 11 * Copyright (C) 2006 Qumranet 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 13 * 14 * Avi Kivity <avi@qumranet.com> 15 * Yaniv Kamay <yaniv@qumranet.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 21 */ 22 23 #include <linux/kvm_host.h> 24 #include "kvm_cache_regs.h" 25 #include <linux/module.h> 26 #include <asm/kvm_emulate.h> 27 #include <linux/stringify.h> 28 29 #include "x86.h" 30 #include "tss.h" 31 32 /* 33 * Operand types 34 */ 35 #define OpNone 0ull 36 #define OpImplicit 1ull /* No generic decode */ 37 #define OpReg 2ull /* Register */ 38 #define OpMem 3ull /* Memory */ 39 #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */ 40 #define OpDI 5ull /* ES:DI/EDI/RDI */ 41 #define OpMem64 6ull /* Memory, 64-bit */ 42 #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */ 43 #define OpDX 8ull /* DX register */ 44 #define OpCL 9ull /* CL register (for shifts) */ 45 #define OpImmByte 10ull /* 8-bit sign extended immediate */ 46 #define OpOne 11ull /* Implied 1 */ 47 #define OpImm 12ull /* Sign extended up to 32-bit immediate */ 48 #define OpMem16 13ull /* Memory operand (16-bit). */ 49 #define OpMem32 14ull /* Memory operand (32-bit). */ 50 #define OpImmU 15ull /* Immediate operand, zero extended */ 51 #define OpSI 16ull /* SI/ESI/RSI */ 52 #define OpImmFAddr 17ull /* Immediate far address */ 53 #define OpMemFAddr 18ull /* Far address in memory */ 54 #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */ 55 #define OpES 20ull /* ES */ 56 #define OpCS 21ull /* CS */ 57 #define OpSS 22ull /* SS */ 58 #define OpDS 23ull /* DS */ 59 #define OpFS 24ull /* FS */ 60 #define OpGS 25ull /* GS */ 61 #define OpMem8 26ull /* 8-bit zero extended memory operand */ 62 #define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */ 63 #define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */ 64 65 #define OpBits 5 /* Width of operand field */ 66 #define OpMask ((1ull << OpBits) - 1) 67 68 /* 69 * Opcode effective-address decode tables. 70 * Note that we only emulate instructions that have at least one memory 71 * operand (excluding implicit stack references). We assume that stack 72 * references and instruction fetches will never occur in special memory 73 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need 74 * not be handled. 75 */ 76 77 /* Operand sizes: 8-bit operands or specified/overridden size. */ 78 #define ByteOp (1<<0) /* 8-bit operands. */ 79 /* Destination operand type. */ 80 #define DstShift 1 81 #define ImplicitOps (OpImplicit << DstShift) 82 #define DstReg (OpReg << DstShift) 83 #define DstMem (OpMem << DstShift) 84 #define DstAcc (OpAcc << DstShift) 85 #define DstDI (OpDI << DstShift) 86 #define DstMem64 (OpMem64 << DstShift) 87 #define DstImmUByte (OpImmUByte << DstShift) 88 #define DstDX (OpDX << DstShift) 89 #define DstMask (OpMask << DstShift) 90 /* Source operand type. */ 91 #define SrcShift 6 92 #define SrcNone (OpNone << SrcShift) 93 #define SrcReg (OpReg << SrcShift) 94 #define SrcMem (OpMem << SrcShift) 95 #define SrcMem16 (OpMem16 << SrcShift) 96 #define SrcMem32 (OpMem32 << SrcShift) 97 #define SrcImm (OpImm << SrcShift) 98 #define SrcImmByte (OpImmByte << SrcShift) 99 #define SrcOne (OpOne << SrcShift) 100 #define SrcImmUByte (OpImmUByte << SrcShift) 101 #define SrcImmU (OpImmU << SrcShift) 102 #define SrcSI (OpSI << SrcShift) 103 #define SrcXLat (OpXLat << SrcShift) 104 #define SrcImmFAddr (OpImmFAddr << SrcShift) 105 #define SrcMemFAddr (OpMemFAddr << SrcShift) 106 #define SrcAcc (OpAcc << SrcShift) 107 #define SrcImmU16 (OpImmU16 << SrcShift) 108 #define SrcImm64 (OpImm64 << SrcShift) 109 #define SrcDX (OpDX << SrcShift) 110 #define SrcMem8 (OpMem8 << SrcShift) 111 #define SrcMask (OpMask << SrcShift) 112 #define BitOp (1<<11) 113 #define MemAbs (1<<12) /* Memory operand is absolute displacement */ 114 #define String (1<<13) /* String instruction (rep capable) */ 115 #define Stack (1<<14) /* Stack instruction (push/pop) */ 116 #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */ 117 #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */ 118 #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */ 119 #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */ 120 #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */ 121 #define Escape (5<<15) /* Escape to coprocessor instruction */ 122 #define Sse (1<<18) /* SSE Vector instruction */ 123 /* Generic ModRM decode. */ 124 #define ModRM (1<<19) 125 /* Destination is only written; never read. */ 126 #define Mov (1<<20) 127 /* Misc flags */ 128 #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */ 129 #define VendorSpecific (1<<22) /* Vendor specific instruction */ 130 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ 131 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ 132 #define Undefined (1<<25) /* No Such Instruction */ 133 #define Lock (1<<26) /* lock prefix is allowed for the instruction */ 134 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ 135 #define No64 (1<<28) 136 #define PageTable (1 << 29) /* instruction used to write page table */ 137 #define NotImpl (1 << 30) /* instruction is not implemented */ 138 /* Source 2 operand type */ 139 #define Src2Shift (31) 140 #define Src2None (OpNone << Src2Shift) 141 #define Src2CL (OpCL << Src2Shift) 142 #define Src2ImmByte (OpImmByte << Src2Shift) 143 #define Src2One (OpOne << Src2Shift) 144 #define Src2Imm (OpImm << Src2Shift) 145 #define Src2ES (OpES << Src2Shift) 146 #define Src2CS (OpCS << Src2Shift) 147 #define Src2SS (OpSS << Src2Shift) 148 #define Src2DS (OpDS << Src2Shift) 149 #define Src2FS (OpFS << Src2Shift) 150 #define Src2GS (OpGS << Src2Shift) 151 #define Src2Mask (OpMask << Src2Shift) 152 #define Mmx ((u64)1 << 40) /* MMX Vector instruction */ 153 #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */ 154 #define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */ 155 #define Avx ((u64)1 << 43) /* Advanced Vector Extensions */ 156 #define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */ 157 #define NoWrite ((u64)1 << 45) /* No writeback */ 158 159 #define X2(x...) x, x 160 #define X3(x...) X2(x), x 161 #define X4(x...) X2(x), X2(x) 162 #define X5(x...) X4(x), x 163 #define X6(x...) X4(x), X2(x) 164 #define X7(x...) X4(x), X3(x) 165 #define X8(x...) X4(x), X4(x) 166 #define X16(x...) X8(x), X8(x) 167 168 #define NR_FASTOP (ilog2(sizeof(ulong)) + 1) 169 #define FASTOP_SIZE 8 170 171 /* 172 * fastop functions have a special calling convention: 173 * 174 * dst: [rdx]:rax (in/out) 175 * src: rbx (in/out) 176 * src2: rcx (in) 177 * flags: rflags (in/out) 178 * 179 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for 180 * different operand sizes can be reached by calculation, rather than a jump 181 * table (which would be bigger than the code). 182 * 183 * fastop functions are declared as taking a never-defined fastop parameter, 184 * so they can't be called from C directly. 185 */ 186 187 struct fastop; 188 189 struct opcode { 190 u64 flags : 56; 191 u64 intercept : 8; 192 union { 193 int (*execute)(struct x86_emulate_ctxt *ctxt); 194 const struct opcode *group; 195 const struct group_dual *gdual; 196 const struct gprefix *gprefix; 197 const struct escape *esc; 198 void (*fastop)(struct fastop *fake); 199 } u; 200 int (*check_perm)(struct x86_emulate_ctxt *ctxt); 201 }; 202 203 struct group_dual { 204 struct opcode mod012[8]; 205 struct opcode mod3[8]; 206 }; 207 208 struct gprefix { 209 struct opcode pfx_no; 210 struct opcode pfx_66; 211 struct opcode pfx_f2; 212 struct opcode pfx_f3; 213 }; 214 215 struct escape { 216 struct opcode op[8]; 217 struct opcode high[64]; 218 }; 219 220 /* EFLAGS bit definitions. */ 221 #define EFLG_ID (1<<21) 222 #define EFLG_VIP (1<<20) 223 #define EFLG_VIF (1<<19) 224 #define EFLG_AC (1<<18) 225 #define EFLG_VM (1<<17) 226 #define EFLG_RF (1<<16) 227 #define EFLG_IOPL (3<<12) 228 #define EFLG_NT (1<<14) 229 #define EFLG_OF (1<<11) 230 #define EFLG_DF (1<<10) 231 #define EFLG_IF (1<<9) 232 #define EFLG_TF (1<<8) 233 #define EFLG_SF (1<<7) 234 #define EFLG_ZF (1<<6) 235 #define EFLG_AF (1<<4) 236 #define EFLG_PF (1<<2) 237 #define EFLG_CF (1<<0) 238 239 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a 240 #define EFLG_RESERVED_ONE_MASK 2 241 242 static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr) 243 { 244 if (!(ctxt->regs_valid & (1 << nr))) { 245 ctxt->regs_valid |= 1 << nr; 246 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr); 247 } 248 return ctxt->_regs[nr]; 249 } 250 251 static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr) 252 { 253 ctxt->regs_valid |= 1 << nr; 254 ctxt->regs_dirty |= 1 << nr; 255 return &ctxt->_regs[nr]; 256 } 257 258 static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr) 259 { 260 reg_read(ctxt, nr); 261 return reg_write(ctxt, nr); 262 } 263 264 static void writeback_registers(struct x86_emulate_ctxt *ctxt) 265 { 266 unsigned reg; 267 268 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16) 269 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]); 270 } 271 272 static void invalidate_registers(struct x86_emulate_ctxt *ctxt) 273 { 274 ctxt->regs_dirty = 0; 275 ctxt->regs_valid = 0; 276 } 277 278 /* 279 * Instruction emulation: 280 * Most instructions are emulated directly via a fragment of inline assembly 281 * code. This allows us to save/restore EFLAGS and thus very easily pick up 282 * any modified flags. 283 */ 284 285 #if defined(CONFIG_X86_64) 286 #define _LO32 "k" /* force 32-bit operand */ 287 #define _STK "%%rsp" /* stack pointer */ 288 #elif defined(__i386__) 289 #define _LO32 "" /* force 32-bit operand */ 290 #define _STK "%%esp" /* stack pointer */ 291 #endif 292 293 /* 294 * These EFLAGS bits are restored from saved value during emulation, and 295 * any changes are written back to the saved value after emulation. 296 */ 297 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) 298 299 /* Before executing instruction: restore necessary bits in EFLAGS. */ 300 #define _PRE_EFLAGS(_sav, _msk, _tmp) \ 301 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \ 302 "movl %"_sav",%"_LO32 _tmp"; " \ 303 "push %"_tmp"; " \ 304 "push %"_tmp"; " \ 305 "movl %"_msk",%"_LO32 _tmp"; " \ 306 "andl %"_LO32 _tmp",("_STK"); " \ 307 "pushf; " \ 308 "notl %"_LO32 _tmp"; " \ 309 "andl %"_LO32 _tmp",("_STK"); " \ 310 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \ 311 "pop %"_tmp"; " \ 312 "orl %"_LO32 _tmp",("_STK"); " \ 313 "popf; " \ 314 "pop %"_sav"; " 315 316 /* After executing instruction: write-back necessary bits in EFLAGS. */ 317 #define _POST_EFLAGS(_sav, _msk, _tmp) \ 318 /* _sav |= EFLAGS & _msk; */ \ 319 "pushf; " \ 320 "pop %"_tmp"; " \ 321 "andl %"_msk",%"_LO32 _tmp"; " \ 322 "orl %"_LO32 _tmp",%"_sav"; " 323 324 #ifdef CONFIG_X86_64 325 #define ON64(x) x 326 #else 327 #define ON64(x) 328 #endif 329 330 #define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \ 331 do { \ 332 __asm__ __volatile__ ( \ 333 _PRE_EFLAGS("0", "4", "2") \ 334 _op _suffix " %"_x"3,%1; " \ 335 _POST_EFLAGS("0", "4", "2") \ 336 : "=m" ((ctxt)->eflags), \ 337 "+q" (*(_dsttype*)&(ctxt)->dst.val), \ 338 "=&r" (_tmp) \ 339 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \ 340 } while (0) 341 342 343 /* Raw emulation: instruction has two explicit operands. */ 344 #define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \ 345 do { \ 346 unsigned long _tmp; \ 347 \ 348 switch ((ctxt)->dst.bytes) { \ 349 case 2: \ 350 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \ 351 break; \ 352 case 4: \ 353 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \ 354 break; \ 355 case 8: \ 356 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \ 357 break; \ 358 } \ 359 } while (0) 360 361 #define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \ 362 do { \ 363 unsigned long _tmp; \ 364 switch ((ctxt)->dst.bytes) { \ 365 case 1: \ 366 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \ 367 break; \ 368 default: \ 369 __emulate_2op_nobyte(ctxt, _op, \ 370 _wx, _wy, _lx, _ly, _qx, _qy); \ 371 break; \ 372 } \ 373 } while (0) 374 375 /* Source operand is byte-sized and may be restricted to just %cl. */ 376 #define emulate_2op_SrcB(ctxt, _op) \ 377 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c") 378 379 /* Source operand is byte, word, long or quad sized. */ 380 #define emulate_2op_SrcV(ctxt, _op) \ 381 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r") 382 383 /* Source operand is word, long or quad sized. */ 384 #define emulate_2op_SrcV_nobyte(ctxt, _op) \ 385 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r") 386 387 /* Instruction has three operands and one operand is stored in ECX register */ 388 #define __emulate_2op_cl(ctxt, _op, _suffix, _type) \ 389 do { \ 390 unsigned long _tmp; \ 391 _type _clv = (ctxt)->src2.val; \ 392 _type _srcv = (ctxt)->src.val; \ 393 _type _dstv = (ctxt)->dst.val; \ 394 \ 395 __asm__ __volatile__ ( \ 396 _PRE_EFLAGS("0", "5", "2") \ 397 _op _suffix " %4,%1 \n" \ 398 _POST_EFLAGS("0", "5", "2") \ 399 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \ 400 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \ 401 ); \ 402 \ 403 (ctxt)->src2.val = (unsigned long) _clv; \ 404 (ctxt)->src2.val = (unsigned long) _srcv; \ 405 (ctxt)->dst.val = (unsigned long) _dstv; \ 406 } while (0) 407 408 #define emulate_2op_cl(ctxt, _op) \ 409 do { \ 410 switch ((ctxt)->dst.bytes) { \ 411 case 2: \ 412 __emulate_2op_cl(ctxt, _op, "w", u16); \ 413 break; \ 414 case 4: \ 415 __emulate_2op_cl(ctxt, _op, "l", u32); \ 416 break; \ 417 case 8: \ 418 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \ 419 break; \ 420 } \ 421 } while (0) 422 423 #define __emulate_1op(ctxt, _op, _suffix) \ 424 do { \ 425 unsigned long _tmp; \ 426 \ 427 __asm__ __volatile__ ( \ 428 _PRE_EFLAGS("0", "3", "2") \ 429 _op _suffix " %1; " \ 430 _POST_EFLAGS("0", "3", "2") \ 431 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \ 432 "=&r" (_tmp) \ 433 : "i" (EFLAGS_MASK)); \ 434 } while (0) 435 436 /* Instruction has only one explicit operand (no source operand). */ 437 #define emulate_1op(ctxt, _op) \ 438 do { \ 439 switch ((ctxt)->dst.bytes) { \ 440 case 1: __emulate_1op(ctxt, _op, "b"); break; \ 441 case 2: __emulate_1op(ctxt, _op, "w"); break; \ 442 case 4: __emulate_1op(ctxt, _op, "l"); break; \ 443 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \ 444 } \ 445 } while (0) 446 447 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *)); 448 449 #define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t" 450 #define FOP_RET "ret \n\t" 451 452 #define FOP_START(op) \ 453 extern void em_##op(struct fastop *fake); \ 454 asm(".pushsection .text, \"ax\" \n\t" \ 455 ".global em_" #op " \n\t" \ 456 FOP_ALIGN \ 457 "em_" #op ": \n\t" 458 459 #define FOP_END \ 460 ".popsection") 461 462 #define FOPNOP() FOP_ALIGN FOP_RET 463 464 #define FOP1E(op, dst) \ 465 FOP_ALIGN #op " %" #dst " \n\t" FOP_RET 466 467 #define FASTOP1(op) \ 468 FOP_START(op) \ 469 FOP1E(op##b, al) \ 470 FOP1E(op##w, ax) \ 471 FOP1E(op##l, eax) \ 472 ON64(FOP1E(op##q, rax)) \ 473 FOP_END 474 475 #define FOP2E(op, dst, src) \ 476 FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET 477 478 #define FASTOP2(op) \ 479 FOP_START(op) \ 480 FOP2E(op##b, al, bl) \ 481 FOP2E(op##w, ax, bx) \ 482 FOP2E(op##l, eax, ebx) \ 483 ON64(FOP2E(op##q, rax, rbx)) \ 484 FOP_END 485 486 /* 2 operand, word only */ 487 #define FASTOP2W(op) \ 488 FOP_START(op) \ 489 FOPNOP() \ 490 FOP2E(op##w, ax, bx) \ 491 FOP2E(op##l, eax, ebx) \ 492 ON64(FOP2E(op##q, rax, rbx)) \ 493 FOP_END 494 495 /* 2 operand, src is CL */ 496 #define FASTOP2CL(op) \ 497 FOP_START(op) \ 498 FOP2E(op##b, al, cl) \ 499 FOP2E(op##w, ax, cl) \ 500 FOP2E(op##l, eax, cl) \ 501 ON64(FOP2E(op##q, rax, cl)) \ 502 FOP_END 503 504 #define FOP3E(op, dst, src, src2) \ 505 FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET 506 507 /* 3-operand, word-only, src2=cl */ 508 #define FASTOP3WCL(op) \ 509 FOP_START(op) \ 510 FOPNOP() \ 511 FOP3E(op##w, ax, bx, cl) \ 512 FOP3E(op##l, eax, ebx, cl) \ 513 ON64(FOP3E(op##q, rax, rbx, cl)) \ 514 FOP_END 515 516 /* Special case for SETcc - 1 instruction per cc */ 517 #define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t" 518 519 FOP_START(setcc) 520 FOP_SETCC(seto) 521 FOP_SETCC(setno) 522 FOP_SETCC(setc) 523 FOP_SETCC(setnc) 524 FOP_SETCC(setz) 525 FOP_SETCC(setnz) 526 FOP_SETCC(setbe) 527 FOP_SETCC(setnbe) 528 FOP_SETCC(sets) 529 FOP_SETCC(setns) 530 FOP_SETCC(setp) 531 FOP_SETCC(setnp) 532 FOP_SETCC(setl) 533 FOP_SETCC(setnl) 534 FOP_SETCC(setle) 535 FOP_SETCC(setnle) 536 FOP_END; 537 538 FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET 539 FOP_END; 540 541 #define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \ 542 do { \ 543 unsigned long _tmp; \ 544 ulong *rax = reg_rmw((ctxt), VCPU_REGS_RAX); \ 545 ulong *rdx = reg_rmw((ctxt), VCPU_REGS_RDX); \ 546 \ 547 __asm__ __volatile__ ( \ 548 _PRE_EFLAGS("0", "5", "1") \ 549 "1: \n\t" \ 550 _op _suffix " %6; " \ 551 "2: \n\t" \ 552 _POST_EFLAGS("0", "5", "1") \ 553 ".pushsection .fixup,\"ax\" \n\t" \ 554 "3: movb $1, %4 \n\t" \ 555 "jmp 2b \n\t" \ 556 ".popsection \n\t" \ 557 _ASM_EXTABLE(1b, 3b) \ 558 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \ 559 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \ 560 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val)); \ 561 } while (0) 562 563 /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */ 564 #define emulate_1op_rax_rdx(ctxt, _op, _ex) \ 565 do { \ 566 switch((ctxt)->src.bytes) { \ 567 case 1: \ 568 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \ 569 break; \ 570 case 2: \ 571 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \ 572 break; \ 573 case 4: \ 574 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \ 575 break; \ 576 case 8: ON64( \ 577 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \ 578 break; \ 579 } \ 580 } while (0) 581 582 static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt, 583 enum x86_intercept intercept, 584 enum x86_intercept_stage stage) 585 { 586 struct x86_instruction_info info = { 587 .intercept = intercept, 588 .rep_prefix = ctxt->rep_prefix, 589 .modrm_mod = ctxt->modrm_mod, 590 .modrm_reg = ctxt->modrm_reg, 591 .modrm_rm = ctxt->modrm_rm, 592 .src_val = ctxt->src.val64, 593 .src_bytes = ctxt->src.bytes, 594 .dst_bytes = ctxt->dst.bytes, 595 .ad_bytes = ctxt->ad_bytes, 596 .next_rip = ctxt->eip, 597 }; 598 599 return ctxt->ops->intercept(ctxt, &info, stage); 600 } 601 602 static void assign_masked(ulong *dest, ulong src, ulong mask) 603 { 604 *dest = (*dest & ~mask) | (src & mask); 605 } 606 607 static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt) 608 { 609 return (1UL << (ctxt->ad_bytes << 3)) - 1; 610 } 611 612 static ulong stack_mask(struct x86_emulate_ctxt *ctxt) 613 { 614 u16 sel; 615 struct desc_struct ss; 616 617 if (ctxt->mode == X86EMUL_MODE_PROT64) 618 return ~0UL; 619 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS); 620 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */ 621 } 622 623 static int stack_size(struct x86_emulate_ctxt *ctxt) 624 { 625 return (__fls(stack_mask(ctxt)) + 1) >> 3; 626 } 627 628 /* Access/update address held in a register, based on addressing mode. */ 629 static inline unsigned long 630 address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg) 631 { 632 if (ctxt->ad_bytes == sizeof(unsigned long)) 633 return reg; 634 else 635 return reg & ad_mask(ctxt); 636 } 637 638 static inline unsigned long 639 register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg) 640 { 641 return address_mask(ctxt, reg); 642 } 643 644 static void masked_increment(ulong *reg, ulong mask, int inc) 645 { 646 assign_masked(reg, *reg + inc, mask); 647 } 648 649 static inline void 650 register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc) 651 { 652 ulong mask; 653 654 if (ctxt->ad_bytes == sizeof(unsigned long)) 655 mask = ~0UL; 656 else 657 mask = ad_mask(ctxt); 658 masked_increment(reg, mask, inc); 659 } 660 661 static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc) 662 { 663 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc); 664 } 665 666 static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel) 667 { 668 register_address_increment(ctxt, &ctxt->_eip, rel); 669 } 670 671 static u32 desc_limit_scaled(struct desc_struct *desc) 672 { 673 u32 limit = get_desc_limit(desc); 674 675 return desc->g ? (limit << 12) | 0xfff : limit; 676 } 677 678 static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg) 679 { 680 ctxt->has_seg_override = true; 681 ctxt->seg_override = seg; 682 } 683 684 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) 685 { 686 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) 687 return 0; 688 689 return ctxt->ops->get_cached_segment_base(ctxt, seg); 690 } 691 692 static unsigned seg_override(struct x86_emulate_ctxt *ctxt) 693 { 694 if (!ctxt->has_seg_override) 695 return 0; 696 697 return ctxt->seg_override; 698 } 699 700 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, 701 u32 error, bool valid) 702 { 703 ctxt->exception.vector = vec; 704 ctxt->exception.error_code = error; 705 ctxt->exception.error_code_valid = valid; 706 return X86EMUL_PROPAGATE_FAULT; 707 } 708 709 static int emulate_db(struct x86_emulate_ctxt *ctxt) 710 { 711 return emulate_exception(ctxt, DB_VECTOR, 0, false); 712 } 713 714 static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err) 715 { 716 return emulate_exception(ctxt, GP_VECTOR, err, true); 717 } 718 719 static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err) 720 { 721 return emulate_exception(ctxt, SS_VECTOR, err, true); 722 } 723 724 static int emulate_ud(struct x86_emulate_ctxt *ctxt) 725 { 726 return emulate_exception(ctxt, UD_VECTOR, 0, false); 727 } 728 729 static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err) 730 { 731 return emulate_exception(ctxt, TS_VECTOR, err, true); 732 } 733 734 static int emulate_de(struct x86_emulate_ctxt *ctxt) 735 { 736 return emulate_exception(ctxt, DE_VECTOR, 0, false); 737 } 738 739 static int emulate_nm(struct x86_emulate_ctxt *ctxt) 740 { 741 return emulate_exception(ctxt, NM_VECTOR, 0, false); 742 } 743 744 static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg) 745 { 746 u16 selector; 747 struct desc_struct desc; 748 749 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg); 750 return selector; 751 } 752 753 static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector, 754 unsigned seg) 755 { 756 u16 dummy; 757 u32 base3; 758 struct desc_struct desc; 759 760 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg); 761 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg); 762 } 763 764 /* 765 * x86 defines three classes of vector instructions: explicitly 766 * aligned, explicitly unaligned, and the rest, which change behaviour 767 * depending on whether they're AVX encoded or not. 768 * 769 * Also included is CMPXCHG16B which is not a vector instruction, yet it is 770 * subject to the same check. 771 */ 772 static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size) 773 { 774 if (likely(size < 16)) 775 return false; 776 777 if (ctxt->d & Aligned) 778 return true; 779 else if (ctxt->d & Unaligned) 780 return false; 781 else if (ctxt->d & Avx) 782 return false; 783 else 784 return true; 785 } 786 787 static int __linearize(struct x86_emulate_ctxt *ctxt, 788 struct segmented_address addr, 789 unsigned size, bool write, bool fetch, 790 ulong *linear) 791 { 792 struct desc_struct desc; 793 bool usable; 794 ulong la; 795 u32 lim; 796 u16 sel; 797 unsigned cpl; 798 799 la = seg_base(ctxt, addr.seg) + addr.ea; 800 switch (ctxt->mode) { 801 case X86EMUL_MODE_PROT64: 802 if (((signed long)la << 16) >> 16 != la) 803 return emulate_gp(ctxt, 0); 804 break; 805 default: 806 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL, 807 addr.seg); 808 if (!usable) 809 goto bad; 810 /* code segment in protected mode or read-only data segment */ 811 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8)) 812 || !(desc.type & 2)) && write) 813 goto bad; 814 /* unreadable code segment */ 815 if (!fetch && (desc.type & 8) && !(desc.type & 2)) 816 goto bad; 817 lim = desc_limit_scaled(&desc); 818 if ((desc.type & 8) || !(desc.type & 4)) { 819 /* expand-up segment */ 820 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim) 821 goto bad; 822 } else { 823 /* expand-down segment */ 824 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim) 825 goto bad; 826 lim = desc.d ? 0xffffffff : 0xffff; 827 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim) 828 goto bad; 829 } 830 cpl = ctxt->ops->cpl(ctxt); 831 if (!(desc.type & 8)) { 832 /* data segment */ 833 if (cpl > desc.dpl) 834 goto bad; 835 } else if ((desc.type & 8) && !(desc.type & 4)) { 836 /* nonconforming code segment */ 837 if (cpl != desc.dpl) 838 goto bad; 839 } else if ((desc.type & 8) && (desc.type & 4)) { 840 /* conforming code segment */ 841 if (cpl < desc.dpl) 842 goto bad; 843 } 844 break; 845 } 846 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8) 847 la &= (u32)-1; 848 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0)) 849 return emulate_gp(ctxt, 0); 850 *linear = la; 851 return X86EMUL_CONTINUE; 852 bad: 853 if (addr.seg == VCPU_SREG_SS) 854 return emulate_ss(ctxt, sel); 855 else 856 return emulate_gp(ctxt, sel); 857 } 858 859 static int linearize(struct x86_emulate_ctxt *ctxt, 860 struct segmented_address addr, 861 unsigned size, bool write, 862 ulong *linear) 863 { 864 return __linearize(ctxt, addr, size, write, false, linear); 865 } 866 867 868 static int segmented_read_std(struct x86_emulate_ctxt *ctxt, 869 struct segmented_address addr, 870 void *data, 871 unsigned size) 872 { 873 int rc; 874 ulong linear; 875 876 rc = linearize(ctxt, addr, size, false, &linear); 877 if (rc != X86EMUL_CONTINUE) 878 return rc; 879 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception); 880 } 881 882 /* 883 * Fetch the next byte of the instruction being emulated which is pointed to 884 * by ctxt->_eip, then increment ctxt->_eip. 885 * 886 * Also prefetch the remaining bytes of the instruction without crossing page 887 * boundary if they are not in fetch_cache yet. 888 */ 889 static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest) 890 { 891 struct fetch_cache *fc = &ctxt->fetch; 892 int rc; 893 int size, cur_size; 894 895 if (ctxt->_eip == fc->end) { 896 unsigned long linear; 897 struct segmented_address addr = { .seg = VCPU_SREG_CS, 898 .ea = ctxt->_eip }; 899 cur_size = fc->end - fc->start; 900 size = min(15UL - cur_size, 901 PAGE_SIZE - offset_in_page(ctxt->_eip)); 902 rc = __linearize(ctxt, addr, size, false, true, &linear); 903 if (unlikely(rc != X86EMUL_CONTINUE)) 904 return rc; 905 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size, 906 size, &ctxt->exception); 907 if (unlikely(rc != X86EMUL_CONTINUE)) 908 return rc; 909 fc->end += size; 910 } 911 *dest = fc->data[ctxt->_eip - fc->start]; 912 ctxt->_eip++; 913 return X86EMUL_CONTINUE; 914 } 915 916 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt, 917 void *dest, unsigned size) 918 { 919 int rc; 920 921 /* x86 instructions are limited to 15 bytes. */ 922 if (unlikely(ctxt->_eip + size - ctxt->eip > 15)) 923 return X86EMUL_UNHANDLEABLE; 924 while (size--) { 925 rc = do_insn_fetch_byte(ctxt, dest++); 926 if (rc != X86EMUL_CONTINUE) 927 return rc; 928 } 929 return X86EMUL_CONTINUE; 930 } 931 932 /* Fetch next part of the instruction being emulated. */ 933 #define insn_fetch(_type, _ctxt) \ 934 ({ unsigned long _x; \ 935 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \ 936 if (rc != X86EMUL_CONTINUE) \ 937 goto done; \ 938 (_type)_x; \ 939 }) 940 941 #define insn_fetch_arr(_arr, _size, _ctxt) \ 942 ({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \ 943 if (rc != X86EMUL_CONTINUE) \ 944 goto done; \ 945 }) 946 947 /* 948 * Given the 'reg' portion of a ModRM byte, and a register block, return a 949 * pointer into the block that addresses the relevant register. 950 * @highbyte_regs specifies whether to decode AH,CH,DH,BH. 951 */ 952 static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg, 953 int highbyte_regs) 954 { 955 void *p; 956 957 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) 958 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1; 959 else 960 p = reg_rmw(ctxt, modrm_reg); 961 return p; 962 } 963 964 static int read_descriptor(struct x86_emulate_ctxt *ctxt, 965 struct segmented_address addr, 966 u16 *size, unsigned long *address, int op_bytes) 967 { 968 int rc; 969 970 if (op_bytes == 2) 971 op_bytes = 3; 972 *address = 0; 973 rc = segmented_read_std(ctxt, addr, size, 2); 974 if (rc != X86EMUL_CONTINUE) 975 return rc; 976 addr.ea += 2; 977 rc = segmented_read_std(ctxt, addr, address, op_bytes); 978 return rc; 979 } 980 981 FASTOP2(add); 982 FASTOP2(or); 983 FASTOP2(adc); 984 FASTOP2(sbb); 985 FASTOP2(and); 986 FASTOP2(sub); 987 FASTOP2(xor); 988 FASTOP2(cmp); 989 FASTOP2(test); 990 991 FASTOP3WCL(shld); 992 FASTOP3WCL(shrd); 993 994 FASTOP2W(imul); 995 996 FASTOP1(not); 997 FASTOP1(neg); 998 FASTOP1(inc); 999 FASTOP1(dec); 1000 1001 FASTOP2CL(rol); 1002 FASTOP2CL(ror); 1003 FASTOP2CL(rcl); 1004 FASTOP2CL(rcr); 1005 FASTOP2CL(shl); 1006 FASTOP2CL(shr); 1007 FASTOP2CL(sar); 1008 1009 FASTOP2W(bsf); 1010 FASTOP2W(bsr); 1011 FASTOP2W(bt); 1012 FASTOP2W(bts); 1013 FASTOP2W(btr); 1014 FASTOP2W(btc); 1015 1016 static u8 test_cc(unsigned int condition, unsigned long flags) 1017 { 1018 u8 rc; 1019 void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf); 1020 1021 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF; 1022 asm("push %[flags]; popf; call *%[fastop]" 1023 : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags)); 1024 return rc; 1025 } 1026 1027 static void fetch_register_operand(struct operand *op) 1028 { 1029 switch (op->bytes) { 1030 case 1: 1031 op->val = *(u8 *)op->addr.reg; 1032 break; 1033 case 2: 1034 op->val = *(u16 *)op->addr.reg; 1035 break; 1036 case 4: 1037 op->val = *(u32 *)op->addr.reg; 1038 break; 1039 case 8: 1040 op->val = *(u64 *)op->addr.reg; 1041 break; 1042 } 1043 } 1044 1045 static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg) 1046 { 1047 ctxt->ops->get_fpu(ctxt); 1048 switch (reg) { 1049 case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break; 1050 case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break; 1051 case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break; 1052 case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break; 1053 case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break; 1054 case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break; 1055 case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break; 1056 case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break; 1057 #ifdef CONFIG_X86_64 1058 case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break; 1059 case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break; 1060 case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break; 1061 case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break; 1062 case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break; 1063 case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break; 1064 case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break; 1065 case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break; 1066 #endif 1067 default: BUG(); 1068 } 1069 ctxt->ops->put_fpu(ctxt); 1070 } 1071 1072 static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, 1073 int reg) 1074 { 1075 ctxt->ops->get_fpu(ctxt); 1076 switch (reg) { 1077 case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break; 1078 case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break; 1079 case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break; 1080 case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break; 1081 case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break; 1082 case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break; 1083 case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break; 1084 case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break; 1085 #ifdef CONFIG_X86_64 1086 case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break; 1087 case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break; 1088 case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break; 1089 case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break; 1090 case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break; 1091 case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break; 1092 case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break; 1093 case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break; 1094 #endif 1095 default: BUG(); 1096 } 1097 ctxt->ops->put_fpu(ctxt); 1098 } 1099 1100 static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) 1101 { 1102 ctxt->ops->get_fpu(ctxt); 1103 switch (reg) { 1104 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break; 1105 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break; 1106 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break; 1107 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break; 1108 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break; 1109 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break; 1110 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break; 1111 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break; 1112 default: BUG(); 1113 } 1114 ctxt->ops->put_fpu(ctxt); 1115 } 1116 1117 static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) 1118 { 1119 ctxt->ops->get_fpu(ctxt); 1120 switch (reg) { 1121 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break; 1122 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break; 1123 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break; 1124 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break; 1125 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break; 1126 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break; 1127 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break; 1128 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break; 1129 default: BUG(); 1130 } 1131 ctxt->ops->put_fpu(ctxt); 1132 } 1133 1134 static int em_fninit(struct x86_emulate_ctxt *ctxt) 1135 { 1136 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1137 return emulate_nm(ctxt); 1138 1139 ctxt->ops->get_fpu(ctxt); 1140 asm volatile("fninit"); 1141 ctxt->ops->put_fpu(ctxt); 1142 return X86EMUL_CONTINUE; 1143 } 1144 1145 static int em_fnstcw(struct x86_emulate_ctxt *ctxt) 1146 { 1147 u16 fcw; 1148 1149 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1150 return emulate_nm(ctxt); 1151 1152 ctxt->ops->get_fpu(ctxt); 1153 asm volatile("fnstcw %0": "+m"(fcw)); 1154 ctxt->ops->put_fpu(ctxt); 1155 1156 /* force 2 byte destination */ 1157 ctxt->dst.bytes = 2; 1158 ctxt->dst.val = fcw; 1159 1160 return X86EMUL_CONTINUE; 1161 } 1162 1163 static int em_fnstsw(struct x86_emulate_ctxt *ctxt) 1164 { 1165 u16 fsw; 1166 1167 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1168 return emulate_nm(ctxt); 1169 1170 ctxt->ops->get_fpu(ctxt); 1171 asm volatile("fnstsw %0": "+m"(fsw)); 1172 ctxt->ops->put_fpu(ctxt); 1173 1174 /* force 2 byte destination */ 1175 ctxt->dst.bytes = 2; 1176 ctxt->dst.val = fsw; 1177 1178 return X86EMUL_CONTINUE; 1179 } 1180 1181 static void decode_register_operand(struct x86_emulate_ctxt *ctxt, 1182 struct operand *op) 1183 { 1184 unsigned reg = ctxt->modrm_reg; 1185 int highbyte_regs = ctxt->rex_prefix == 0; 1186 1187 if (!(ctxt->d & ModRM)) 1188 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3); 1189 1190 if (ctxt->d & Sse) { 1191 op->type = OP_XMM; 1192 op->bytes = 16; 1193 op->addr.xmm = reg; 1194 read_sse_reg(ctxt, &op->vec_val, reg); 1195 return; 1196 } 1197 if (ctxt->d & Mmx) { 1198 reg &= 7; 1199 op->type = OP_MM; 1200 op->bytes = 8; 1201 op->addr.mm = reg; 1202 return; 1203 } 1204 1205 op->type = OP_REG; 1206 if (ctxt->d & ByteOp) { 1207 op->addr.reg = decode_register(ctxt, reg, highbyte_regs); 1208 op->bytes = 1; 1209 } else { 1210 op->addr.reg = decode_register(ctxt, reg, 0); 1211 op->bytes = ctxt->op_bytes; 1212 } 1213 fetch_register_operand(op); 1214 op->orig_val = op->val; 1215 } 1216 1217 static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg) 1218 { 1219 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP) 1220 ctxt->modrm_seg = VCPU_SREG_SS; 1221 } 1222 1223 static int decode_modrm(struct x86_emulate_ctxt *ctxt, 1224 struct operand *op) 1225 { 1226 u8 sib; 1227 int index_reg = 0, base_reg = 0, scale; 1228 int rc = X86EMUL_CONTINUE; 1229 ulong modrm_ea = 0; 1230 1231 if (ctxt->rex_prefix) { 1232 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */ 1233 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */ 1234 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */ 1235 } 1236 1237 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6; 1238 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3; 1239 ctxt->modrm_rm |= (ctxt->modrm & 0x07); 1240 ctxt->modrm_seg = VCPU_SREG_DS; 1241 1242 if (ctxt->modrm_mod == 3) { 1243 op->type = OP_REG; 1244 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 1245 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, ctxt->d & ByteOp); 1246 if (ctxt->d & Sse) { 1247 op->type = OP_XMM; 1248 op->bytes = 16; 1249 op->addr.xmm = ctxt->modrm_rm; 1250 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm); 1251 return rc; 1252 } 1253 if (ctxt->d & Mmx) { 1254 op->type = OP_MM; 1255 op->bytes = 8; 1256 op->addr.xmm = ctxt->modrm_rm & 7; 1257 return rc; 1258 } 1259 fetch_register_operand(op); 1260 return rc; 1261 } 1262 1263 op->type = OP_MEM; 1264 1265 if (ctxt->ad_bytes == 2) { 1266 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX); 1267 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP); 1268 unsigned si = reg_read(ctxt, VCPU_REGS_RSI); 1269 unsigned di = reg_read(ctxt, VCPU_REGS_RDI); 1270 1271 /* 16-bit ModR/M decode. */ 1272 switch (ctxt->modrm_mod) { 1273 case 0: 1274 if (ctxt->modrm_rm == 6) 1275 modrm_ea += insn_fetch(u16, ctxt); 1276 break; 1277 case 1: 1278 modrm_ea += insn_fetch(s8, ctxt); 1279 break; 1280 case 2: 1281 modrm_ea += insn_fetch(u16, ctxt); 1282 break; 1283 } 1284 switch (ctxt->modrm_rm) { 1285 case 0: 1286 modrm_ea += bx + si; 1287 break; 1288 case 1: 1289 modrm_ea += bx + di; 1290 break; 1291 case 2: 1292 modrm_ea += bp + si; 1293 break; 1294 case 3: 1295 modrm_ea += bp + di; 1296 break; 1297 case 4: 1298 modrm_ea += si; 1299 break; 1300 case 5: 1301 modrm_ea += di; 1302 break; 1303 case 6: 1304 if (ctxt->modrm_mod != 0) 1305 modrm_ea += bp; 1306 break; 1307 case 7: 1308 modrm_ea += bx; 1309 break; 1310 } 1311 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 || 1312 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0)) 1313 ctxt->modrm_seg = VCPU_SREG_SS; 1314 modrm_ea = (u16)modrm_ea; 1315 } else { 1316 /* 32/64-bit ModR/M decode. */ 1317 if ((ctxt->modrm_rm & 7) == 4) { 1318 sib = insn_fetch(u8, ctxt); 1319 index_reg |= (sib >> 3) & 7; 1320 base_reg |= sib & 7; 1321 scale = sib >> 6; 1322 1323 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0) 1324 modrm_ea += insn_fetch(s32, ctxt); 1325 else { 1326 modrm_ea += reg_read(ctxt, base_reg); 1327 adjust_modrm_seg(ctxt, base_reg); 1328 } 1329 if (index_reg != 4) 1330 modrm_ea += reg_read(ctxt, index_reg) << scale; 1331 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) { 1332 if (ctxt->mode == X86EMUL_MODE_PROT64) 1333 ctxt->rip_relative = 1; 1334 } else { 1335 base_reg = ctxt->modrm_rm; 1336 modrm_ea += reg_read(ctxt, base_reg); 1337 adjust_modrm_seg(ctxt, base_reg); 1338 } 1339 switch (ctxt->modrm_mod) { 1340 case 0: 1341 if (ctxt->modrm_rm == 5) 1342 modrm_ea += insn_fetch(s32, ctxt); 1343 break; 1344 case 1: 1345 modrm_ea += insn_fetch(s8, ctxt); 1346 break; 1347 case 2: 1348 modrm_ea += insn_fetch(s32, ctxt); 1349 break; 1350 } 1351 } 1352 op->addr.mem.ea = modrm_ea; 1353 done: 1354 return rc; 1355 } 1356 1357 static int decode_abs(struct x86_emulate_ctxt *ctxt, 1358 struct operand *op) 1359 { 1360 int rc = X86EMUL_CONTINUE; 1361 1362 op->type = OP_MEM; 1363 switch (ctxt->ad_bytes) { 1364 case 2: 1365 op->addr.mem.ea = insn_fetch(u16, ctxt); 1366 break; 1367 case 4: 1368 op->addr.mem.ea = insn_fetch(u32, ctxt); 1369 break; 1370 case 8: 1371 op->addr.mem.ea = insn_fetch(u64, ctxt); 1372 break; 1373 } 1374 done: 1375 return rc; 1376 } 1377 1378 static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt) 1379 { 1380 long sv = 0, mask; 1381 1382 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) { 1383 mask = ~(ctxt->dst.bytes * 8 - 1); 1384 1385 if (ctxt->src.bytes == 2) 1386 sv = (s16)ctxt->src.val & (s16)mask; 1387 else if (ctxt->src.bytes == 4) 1388 sv = (s32)ctxt->src.val & (s32)mask; 1389 1390 ctxt->dst.addr.mem.ea += (sv >> 3); 1391 } 1392 1393 /* only subword offset */ 1394 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; 1395 } 1396 1397 static int read_emulated(struct x86_emulate_ctxt *ctxt, 1398 unsigned long addr, void *dest, unsigned size) 1399 { 1400 int rc; 1401 struct read_cache *mc = &ctxt->mem_read; 1402 1403 if (mc->pos < mc->end) 1404 goto read_cached; 1405 1406 WARN_ON((mc->end + size) >= sizeof(mc->data)); 1407 1408 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size, 1409 &ctxt->exception); 1410 if (rc != X86EMUL_CONTINUE) 1411 return rc; 1412 1413 mc->end += size; 1414 1415 read_cached: 1416 memcpy(dest, mc->data + mc->pos, size); 1417 mc->pos += size; 1418 return X86EMUL_CONTINUE; 1419 } 1420 1421 static int segmented_read(struct x86_emulate_ctxt *ctxt, 1422 struct segmented_address addr, 1423 void *data, 1424 unsigned size) 1425 { 1426 int rc; 1427 ulong linear; 1428 1429 rc = linearize(ctxt, addr, size, false, &linear); 1430 if (rc != X86EMUL_CONTINUE) 1431 return rc; 1432 return read_emulated(ctxt, linear, data, size); 1433 } 1434 1435 static int segmented_write(struct x86_emulate_ctxt *ctxt, 1436 struct segmented_address addr, 1437 const void *data, 1438 unsigned size) 1439 { 1440 int rc; 1441 ulong linear; 1442 1443 rc = linearize(ctxt, addr, size, true, &linear); 1444 if (rc != X86EMUL_CONTINUE) 1445 return rc; 1446 return ctxt->ops->write_emulated(ctxt, linear, data, size, 1447 &ctxt->exception); 1448 } 1449 1450 static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt, 1451 struct segmented_address addr, 1452 const void *orig_data, const void *data, 1453 unsigned size) 1454 { 1455 int rc; 1456 ulong linear; 1457 1458 rc = linearize(ctxt, addr, size, true, &linear); 1459 if (rc != X86EMUL_CONTINUE) 1460 return rc; 1461 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data, 1462 size, &ctxt->exception); 1463 } 1464 1465 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, 1466 unsigned int size, unsigned short port, 1467 void *dest) 1468 { 1469 struct read_cache *rc = &ctxt->io_read; 1470 1471 if (rc->pos == rc->end) { /* refill pio read ahead */ 1472 unsigned int in_page, n; 1473 unsigned int count = ctxt->rep_prefix ? 1474 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1; 1475 in_page = (ctxt->eflags & EFLG_DF) ? 1476 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) : 1477 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)); 1478 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size, 1479 count); 1480 if (n == 0) 1481 n = 1; 1482 rc->pos = rc->end = 0; 1483 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n)) 1484 return 0; 1485 rc->end = n * size; 1486 } 1487 1488 if (ctxt->rep_prefix && !(ctxt->eflags & EFLG_DF)) { 1489 ctxt->dst.data = rc->data + rc->pos; 1490 ctxt->dst.type = OP_MEM_STR; 1491 ctxt->dst.count = (rc->end - rc->pos) / size; 1492 rc->pos = rc->end; 1493 } else { 1494 memcpy(dest, rc->data + rc->pos, size); 1495 rc->pos += size; 1496 } 1497 return 1; 1498 } 1499 1500 static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt, 1501 u16 index, struct desc_struct *desc) 1502 { 1503 struct desc_ptr dt; 1504 ulong addr; 1505 1506 ctxt->ops->get_idt(ctxt, &dt); 1507 1508 if (dt.size < index * 8 + 7) 1509 return emulate_gp(ctxt, index << 3 | 0x2); 1510 1511 addr = dt.address + index * 8; 1512 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc, 1513 &ctxt->exception); 1514 } 1515 1516 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, 1517 u16 selector, struct desc_ptr *dt) 1518 { 1519 const struct x86_emulate_ops *ops = ctxt->ops; 1520 1521 if (selector & 1 << 2) { 1522 struct desc_struct desc; 1523 u16 sel; 1524 1525 memset (dt, 0, sizeof *dt); 1526 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR)) 1527 return; 1528 1529 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ 1530 dt->address = get_desc_base(&desc); 1531 } else 1532 ops->get_gdt(ctxt, dt); 1533 } 1534 1535 /* allowed just for 8 bytes segments */ 1536 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1537 u16 selector, struct desc_struct *desc, 1538 ulong *desc_addr_p) 1539 { 1540 struct desc_ptr dt; 1541 u16 index = selector >> 3; 1542 ulong addr; 1543 1544 get_descriptor_table_ptr(ctxt, selector, &dt); 1545 1546 if (dt.size < index * 8 + 7) 1547 return emulate_gp(ctxt, selector & 0xfffc); 1548 1549 *desc_addr_p = addr = dt.address + index * 8; 1550 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc, 1551 &ctxt->exception); 1552 } 1553 1554 /* allowed just for 8 bytes segments */ 1555 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1556 u16 selector, struct desc_struct *desc) 1557 { 1558 struct desc_ptr dt; 1559 u16 index = selector >> 3; 1560 ulong addr; 1561 1562 get_descriptor_table_ptr(ctxt, selector, &dt); 1563 1564 if (dt.size < index * 8 + 7) 1565 return emulate_gp(ctxt, selector & 0xfffc); 1566 1567 addr = dt.address + index * 8; 1568 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc, 1569 &ctxt->exception); 1570 } 1571 1572 /* Does not support long mode */ 1573 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1574 u16 selector, int seg) 1575 { 1576 struct desc_struct seg_desc, old_desc; 1577 u8 dpl, rpl, cpl; 1578 unsigned err_vec = GP_VECTOR; 1579 u32 err_code = 0; 1580 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ 1581 ulong desc_addr; 1582 int ret; 1583 u16 dummy; 1584 1585 memset(&seg_desc, 0, sizeof seg_desc); 1586 1587 if (ctxt->mode == X86EMUL_MODE_REAL) { 1588 /* set real mode segment descriptor (keep limit etc. for 1589 * unreal mode) */ 1590 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg); 1591 set_desc_base(&seg_desc, selector << 4); 1592 goto load; 1593 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) { 1594 /* VM86 needs a clean new segment descriptor */ 1595 set_desc_base(&seg_desc, selector << 4); 1596 set_desc_limit(&seg_desc, 0xffff); 1597 seg_desc.type = 3; 1598 seg_desc.p = 1; 1599 seg_desc.s = 1; 1600 seg_desc.dpl = 3; 1601 goto load; 1602 } 1603 1604 rpl = selector & 3; 1605 cpl = ctxt->ops->cpl(ctxt); 1606 1607 /* NULL selector is not valid for TR, CS and SS (except for long mode) */ 1608 if ((seg == VCPU_SREG_CS 1609 || (seg == VCPU_SREG_SS 1610 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl)) 1611 || seg == VCPU_SREG_TR) 1612 && null_selector) 1613 goto exception; 1614 1615 /* TR should be in GDT only */ 1616 if (seg == VCPU_SREG_TR && (selector & (1 << 2))) 1617 goto exception; 1618 1619 if (null_selector) /* for NULL selector skip all following checks */ 1620 goto load; 1621 1622 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr); 1623 if (ret != X86EMUL_CONTINUE) 1624 return ret; 1625 1626 err_code = selector & 0xfffc; 1627 err_vec = GP_VECTOR; 1628 1629 /* can't load system descriptor into segment selector */ 1630 if (seg <= VCPU_SREG_GS && !seg_desc.s) 1631 goto exception; 1632 1633 if (!seg_desc.p) { 1634 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; 1635 goto exception; 1636 } 1637 1638 dpl = seg_desc.dpl; 1639 1640 switch (seg) { 1641 case VCPU_SREG_SS: 1642 /* 1643 * segment is not a writable data segment or segment 1644 * selector's RPL != CPL or segment selector's RPL != CPL 1645 */ 1646 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) 1647 goto exception; 1648 break; 1649 case VCPU_SREG_CS: 1650 if (!(seg_desc.type & 8)) 1651 goto exception; 1652 1653 if (seg_desc.type & 4) { 1654 /* conforming */ 1655 if (dpl > cpl) 1656 goto exception; 1657 } else { 1658 /* nonconforming */ 1659 if (rpl > cpl || dpl != cpl) 1660 goto exception; 1661 } 1662 /* CS(RPL) <- CPL */ 1663 selector = (selector & 0xfffc) | cpl; 1664 break; 1665 case VCPU_SREG_TR: 1666 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) 1667 goto exception; 1668 old_desc = seg_desc; 1669 seg_desc.type |= 2; /* busy */ 1670 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc, 1671 sizeof(seg_desc), &ctxt->exception); 1672 if (ret != X86EMUL_CONTINUE) 1673 return ret; 1674 break; 1675 case VCPU_SREG_LDTR: 1676 if (seg_desc.s || seg_desc.type != 2) 1677 goto exception; 1678 break; 1679 default: /* DS, ES, FS, or GS */ 1680 /* 1681 * segment is not a data or readable code segment or 1682 * ((segment is a data or nonconforming code segment) 1683 * and (both RPL and CPL > DPL)) 1684 */ 1685 if ((seg_desc.type & 0xa) == 0x8 || 1686 (((seg_desc.type & 0xc) != 0xc) && 1687 (rpl > dpl && cpl > dpl))) 1688 goto exception; 1689 break; 1690 } 1691 1692 if (seg_desc.s) { 1693 /* mark segment as accessed */ 1694 seg_desc.type |= 1; 1695 ret = write_segment_descriptor(ctxt, selector, &seg_desc); 1696 if (ret != X86EMUL_CONTINUE) 1697 return ret; 1698 } 1699 load: 1700 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg); 1701 return X86EMUL_CONTINUE; 1702 exception: 1703 emulate_exception(ctxt, err_vec, err_code, true); 1704 return X86EMUL_PROPAGATE_FAULT; 1705 } 1706 1707 static void write_register_operand(struct operand *op) 1708 { 1709 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ 1710 switch (op->bytes) { 1711 case 1: 1712 *(u8 *)op->addr.reg = (u8)op->val; 1713 break; 1714 case 2: 1715 *(u16 *)op->addr.reg = (u16)op->val; 1716 break; 1717 case 4: 1718 *op->addr.reg = (u32)op->val; 1719 break; /* 64b: zero-extend */ 1720 case 8: 1721 *op->addr.reg = op->val; 1722 break; 1723 } 1724 } 1725 1726 static int writeback(struct x86_emulate_ctxt *ctxt) 1727 { 1728 int rc; 1729 1730 if (ctxt->d & NoWrite) 1731 return X86EMUL_CONTINUE; 1732 1733 switch (ctxt->dst.type) { 1734 case OP_REG: 1735 write_register_operand(&ctxt->dst); 1736 break; 1737 case OP_MEM: 1738 if (ctxt->lock_prefix) 1739 rc = segmented_cmpxchg(ctxt, 1740 ctxt->dst.addr.mem, 1741 &ctxt->dst.orig_val, 1742 &ctxt->dst.val, 1743 ctxt->dst.bytes); 1744 else 1745 rc = segmented_write(ctxt, 1746 ctxt->dst.addr.mem, 1747 &ctxt->dst.val, 1748 ctxt->dst.bytes); 1749 if (rc != X86EMUL_CONTINUE) 1750 return rc; 1751 break; 1752 case OP_MEM_STR: 1753 rc = segmented_write(ctxt, 1754 ctxt->dst.addr.mem, 1755 ctxt->dst.data, 1756 ctxt->dst.bytes * ctxt->dst.count); 1757 if (rc != X86EMUL_CONTINUE) 1758 return rc; 1759 break; 1760 case OP_XMM: 1761 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm); 1762 break; 1763 case OP_MM: 1764 write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm); 1765 break; 1766 case OP_NONE: 1767 /* no writeback */ 1768 break; 1769 default: 1770 break; 1771 } 1772 return X86EMUL_CONTINUE; 1773 } 1774 1775 static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes) 1776 { 1777 struct segmented_address addr; 1778 1779 rsp_increment(ctxt, -bytes); 1780 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); 1781 addr.seg = VCPU_SREG_SS; 1782 1783 return segmented_write(ctxt, addr, data, bytes); 1784 } 1785 1786 static int em_push(struct x86_emulate_ctxt *ctxt) 1787 { 1788 /* Disable writeback. */ 1789 ctxt->dst.type = OP_NONE; 1790 return push(ctxt, &ctxt->src.val, ctxt->op_bytes); 1791 } 1792 1793 static int emulate_pop(struct x86_emulate_ctxt *ctxt, 1794 void *dest, int len) 1795 { 1796 int rc; 1797 struct segmented_address addr; 1798 1799 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); 1800 addr.seg = VCPU_SREG_SS; 1801 rc = segmented_read(ctxt, addr, dest, len); 1802 if (rc != X86EMUL_CONTINUE) 1803 return rc; 1804 1805 rsp_increment(ctxt, len); 1806 return rc; 1807 } 1808 1809 static int em_pop(struct x86_emulate_ctxt *ctxt) 1810 { 1811 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1812 } 1813 1814 static int emulate_popf(struct x86_emulate_ctxt *ctxt, 1815 void *dest, int len) 1816 { 1817 int rc; 1818 unsigned long val, change_mask; 1819 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; 1820 int cpl = ctxt->ops->cpl(ctxt); 1821 1822 rc = emulate_pop(ctxt, &val, len); 1823 if (rc != X86EMUL_CONTINUE) 1824 return rc; 1825 1826 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF 1827 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID; 1828 1829 switch(ctxt->mode) { 1830 case X86EMUL_MODE_PROT64: 1831 case X86EMUL_MODE_PROT32: 1832 case X86EMUL_MODE_PROT16: 1833 if (cpl == 0) 1834 change_mask |= EFLG_IOPL; 1835 if (cpl <= iopl) 1836 change_mask |= EFLG_IF; 1837 break; 1838 case X86EMUL_MODE_VM86: 1839 if (iopl < 3) 1840 return emulate_gp(ctxt, 0); 1841 change_mask |= EFLG_IF; 1842 break; 1843 default: /* real mode */ 1844 change_mask |= (EFLG_IOPL | EFLG_IF); 1845 break; 1846 } 1847 1848 *(unsigned long *)dest = 1849 (ctxt->eflags & ~change_mask) | (val & change_mask); 1850 1851 return rc; 1852 } 1853 1854 static int em_popf(struct x86_emulate_ctxt *ctxt) 1855 { 1856 ctxt->dst.type = OP_REG; 1857 ctxt->dst.addr.reg = &ctxt->eflags; 1858 ctxt->dst.bytes = ctxt->op_bytes; 1859 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1860 } 1861 1862 static int em_enter(struct x86_emulate_ctxt *ctxt) 1863 { 1864 int rc; 1865 unsigned frame_size = ctxt->src.val; 1866 unsigned nesting_level = ctxt->src2.val & 31; 1867 ulong rbp; 1868 1869 if (nesting_level) 1870 return X86EMUL_UNHANDLEABLE; 1871 1872 rbp = reg_read(ctxt, VCPU_REGS_RBP); 1873 rc = push(ctxt, &rbp, stack_size(ctxt)); 1874 if (rc != X86EMUL_CONTINUE) 1875 return rc; 1876 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP), 1877 stack_mask(ctxt)); 1878 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), 1879 reg_read(ctxt, VCPU_REGS_RSP) - frame_size, 1880 stack_mask(ctxt)); 1881 return X86EMUL_CONTINUE; 1882 } 1883 1884 static int em_leave(struct x86_emulate_ctxt *ctxt) 1885 { 1886 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP), 1887 stack_mask(ctxt)); 1888 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes); 1889 } 1890 1891 static int em_push_sreg(struct x86_emulate_ctxt *ctxt) 1892 { 1893 int seg = ctxt->src2.val; 1894 1895 ctxt->src.val = get_segment_selector(ctxt, seg); 1896 1897 return em_push(ctxt); 1898 } 1899 1900 static int em_pop_sreg(struct x86_emulate_ctxt *ctxt) 1901 { 1902 int seg = ctxt->src2.val; 1903 unsigned long selector; 1904 int rc; 1905 1906 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes); 1907 if (rc != X86EMUL_CONTINUE) 1908 return rc; 1909 1910 rc = load_segment_descriptor(ctxt, (u16)selector, seg); 1911 return rc; 1912 } 1913 1914 static int em_pusha(struct x86_emulate_ctxt *ctxt) 1915 { 1916 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP); 1917 int rc = X86EMUL_CONTINUE; 1918 int reg = VCPU_REGS_RAX; 1919 1920 while (reg <= VCPU_REGS_RDI) { 1921 (reg == VCPU_REGS_RSP) ? 1922 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg)); 1923 1924 rc = em_push(ctxt); 1925 if (rc != X86EMUL_CONTINUE) 1926 return rc; 1927 1928 ++reg; 1929 } 1930 1931 return rc; 1932 } 1933 1934 static int em_pushf(struct x86_emulate_ctxt *ctxt) 1935 { 1936 ctxt->src.val = (unsigned long)ctxt->eflags; 1937 return em_push(ctxt); 1938 } 1939 1940 static int em_popa(struct x86_emulate_ctxt *ctxt) 1941 { 1942 int rc = X86EMUL_CONTINUE; 1943 int reg = VCPU_REGS_RDI; 1944 1945 while (reg >= VCPU_REGS_RAX) { 1946 if (reg == VCPU_REGS_RSP) { 1947 rsp_increment(ctxt, ctxt->op_bytes); 1948 --reg; 1949 } 1950 1951 rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes); 1952 if (rc != X86EMUL_CONTINUE) 1953 break; 1954 --reg; 1955 } 1956 return rc; 1957 } 1958 1959 static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) 1960 { 1961 const struct x86_emulate_ops *ops = ctxt->ops; 1962 int rc; 1963 struct desc_ptr dt; 1964 gva_t cs_addr; 1965 gva_t eip_addr; 1966 u16 cs, eip; 1967 1968 /* TODO: Add limit checks */ 1969 ctxt->src.val = ctxt->eflags; 1970 rc = em_push(ctxt); 1971 if (rc != X86EMUL_CONTINUE) 1972 return rc; 1973 1974 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC); 1975 1976 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS); 1977 rc = em_push(ctxt); 1978 if (rc != X86EMUL_CONTINUE) 1979 return rc; 1980 1981 ctxt->src.val = ctxt->_eip; 1982 rc = em_push(ctxt); 1983 if (rc != X86EMUL_CONTINUE) 1984 return rc; 1985 1986 ops->get_idt(ctxt, &dt); 1987 1988 eip_addr = dt.address + (irq << 2); 1989 cs_addr = dt.address + (irq << 2) + 2; 1990 1991 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception); 1992 if (rc != X86EMUL_CONTINUE) 1993 return rc; 1994 1995 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception); 1996 if (rc != X86EMUL_CONTINUE) 1997 return rc; 1998 1999 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS); 2000 if (rc != X86EMUL_CONTINUE) 2001 return rc; 2002 2003 ctxt->_eip = eip; 2004 2005 return rc; 2006 } 2007 2008 int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) 2009 { 2010 int rc; 2011 2012 invalidate_registers(ctxt); 2013 rc = __emulate_int_real(ctxt, irq); 2014 if (rc == X86EMUL_CONTINUE) 2015 writeback_registers(ctxt); 2016 return rc; 2017 } 2018 2019 static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq) 2020 { 2021 switch(ctxt->mode) { 2022 case X86EMUL_MODE_REAL: 2023 return __emulate_int_real(ctxt, irq); 2024 case X86EMUL_MODE_VM86: 2025 case X86EMUL_MODE_PROT16: 2026 case X86EMUL_MODE_PROT32: 2027 case X86EMUL_MODE_PROT64: 2028 default: 2029 /* Protected mode interrupts unimplemented yet */ 2030 return X86EMUL_UNHANDLEABLE; 2031 } 2032 } 2033 2034 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt) 2035 { 2036 int rc = X86EMUL_CONTINUE; 2037 unsigned long temp_eip = 0; 2038 unsigned long temp_eflags = 0; 2039 unsigned long cs = 0; 2040 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF | 2041 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF | 2042 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */ 2043 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP; 2044 2045 /* TODO: Add stack limit check */ 2046 2047 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes); 2048 2049 if (rc != X86EMUL_CONTINUE) 2050 return rc; 2051 2052 if (temp_eip & ~0xffff) 2053 return emulate_gp(ctxt, 0); 2054 2055 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 2056 2057 if (rc != X86EMUL_CONTINUE) 2058 return rc; 2059 2060 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes); 2061 2062 if (rc != X86EMUL_CONTINUE) 2063 return rc; 2064 2065 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); 2066 2067 if (rc != X86EMUL_CONTINUE) 2068 return rc; 2069 2070 ctxt->_eip = temp_eip; 2071 2072 2073 if (ctxt->op_bytes == 4) 2074 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); 2075 else if (ctxt->op_bytes == 2) { 2076 ctxt->eflags &= ~0xffff; 2077 ctxt->eflags |= temp_eflags; 2078 } 2079 2080 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ 2081 ctxt->eflags |= EFLG_RESERVED_ONE_MASK; 2082 2083 return rc; 2084 } 2085 2086 static int em_iret(struct x86_emulate_ctxt *ctxt) 2087 { 2088 switch(ctxt->mode) { 2089 case X86EMUL_MODE_REAL: 2090 return emulate_iret_real(ctxt); 2091 case X86EMUL_MODE_VM86: 2092 case X86EMUL_MODE_PROT16: 2093 case X86EMUL_MODE_PROT32: 2094 case X86EMUL_MODE_PROT64: 2095 default: 2096 /* iret from protected mode unimplemented yet */ 2097 return X86EMUL_UNHANDLEABLE; 2098 } 2099 } 2100 2101 static int em_jmp_far(struct x86_emulate_ctxt *ctxt) 2102 { 2103 int rc; 2104 unsigned short sel; 2105 2106 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2107 2108 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS); 2109 if (rc != X86EMUL_CONTINUE) 2110 return rc; 2111 2112 ctxt->_eip = 0; 2113 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes); 2114 return X86EMUL_CONTINUE; 2115 } 2116 2117 static int em_mul_ex(struct x86_emulate_ctxt *ctxt) 2118 { 2119 u8 ex = 0; 2120 2121 emulate_1op_rax_rdx(ctxt, "mul", ex); 2122 return X86EMUL_CONTINUE; 2123 } 2124 2125 static int em_imul_ex(struct x86_emulate_ctxt *ctxt) 2126 { 2127 u8 ex = 0; 2128 2129 emulate_1op_rax_rdx(ctxt, "imul", ex); 2130 return X86EMUL_CONTINUE; 2131 } 2132 2133 static int em_div_ex(struct x86_emulate_ctxt *ctxt) 2134 { 2135 u8 de = 0; 2136 2137 emulate_1op_rax_rdx(ctxt, "div", de); 2138 if (de) 2139 return emulate_de(ctxt); 2140 return X86EMUL_CONTINUE; 2141 } 2142 2143 static int em_idiv_ex(struct x86_emulate_ctxt *ctxt) 2144 { 2145 u8 de = 0; 2146 2147 emulate_1op_rax_rdx(ctxt, "idiv", de); 2148 if (de) 2149 return emulate_de(ctxt); 2150 return X86EMUL_CONTINUE; 2151 } 2152 2153 static int em_grp45(struct x86_emulate_ctxt *ctxt) 2154 { 2155 int rc = X86EMUL_CONTINUE; 2156 2157 switch (ctxt->modrm_reg) { 2158 case 2: /* call near abs */ { 2159 long int old_eip; 2160 old_eip = ctxt->_eip; 2161 ctxt->_eip = ctxt->src.val; 2162 ctxt->src.val = old_eip; 2163 rc = em_push(ctxt); 2164 break; 2165 } 2166 case 4: /* jmp abs */ 2167 ctxt->_eip = ctxt->src.val; 2168 break; 2169 case 5: /* jmp far */ 2170 rc = em_jmp_far(ctxt); 2171 break; 2172 case 6: /* push */ 2173 rc = em_push(ctxt); 2174 break; 2175 } 2176 return rc; 2177 } 2178 2179 static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt) 2180 { 2181 u64 old = ctxt->dst.orig_val64; 2182 2183 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) || 2184 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) { 2185 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0); 2186 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32); 2187 ctxt->eflags &= ~EFLG_ZF; 2188 } else { 2189 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) | 2190 (u32) reg_read(ctxt, VCPU_REGS_RBX); 2191 2192 ctxt->eflags |= EFLG_ZF; 2193 } 2194 return X86EMUL_CONTINUE; 2195 } 2196 2197 static int em_ret(struct x86_emulate_ctxt *ctxt) 2198 { 2199 ctxt->dst.type = OP_REG; 2200 ctxt->dst.addr.reg = &ctxt->_eip; 2201 ctxt->dst.bytes = ctxt->op_bytes; 2202 return em_pop(ctxt); 2203 } 2204 2205 static int em_ret_far(struct x86_emulate_ctxt *ctxt) 2206 { 2207 int rc; 2208 unsigned long cs; 2209 2210 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes); 2211 if (rc != X86EMUL_CONTINUE) 2212 return rc; 2213 if (ctxt->op_bytes == 4) 2214 ctxt->_eip = (u32)ctxt->_eip; 2215 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 2216 if (rc != X86EMUL_CONTINUE) 2217 return rc; 2218 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); 2219 return rc; 2220 } 2221 2222 static int em_cmpxchg(struct x86_emulate_ctxt *ctxt) 2223 { 2224 /* Save real source value, then compare EAX against destination. */ 2225 ctxt->src.orig_val = ctxt->src.val; 2226 ctxt->src.val = reg_read(ctxt, VCPU_REGS_RAX); 2227 fastop(ctxt, em_cmp); 2228 2229 if (ctxt->eflags & EFLG_ZF) { 2230 /* Success: write back to memory. */ 2231 ctxt->dst.val = ctxt->src.orig_val; 2232 } else { 2233 /* Failure: write the value we saw to EAX. */ 2234 ctxt->dst.type = OP_REG; 2235 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 2236 } 2237 return X86EMUL_CONTINUE; 2238 } 2239 2240 static int em_lseg(struct x86_emulate_ctxt *ctxt) 2241 { 2242 int seg = ctxt->src2.val; 2243 unsigned short sel; 2244 int rc; 2245 2246 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2247 2248 rc = load_segment_descriptor(ctxt, sel, seg); 2249 if (rc != X86EMUL_CONTINUE) 2250 return rc; 2251 2252 ctxt->dst.val = ctxt->src.val; 2253 return rc; 2254 } 2255 2256 static void 2257 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, 2258 struct desc_struct *cs, struct desc_struct *ss) 2259 { 2260 cs->l = 0; /* will be adjusted later */ 2261 set_desc_base(cs, 0); /* flat segment */ 2262 cs->g = 1; /* 4kb granularity */ 2263 set_desc_limit(cs, 0xfffff); /* 4GB limit */ 2264 cs->type = 0x0b; /* Read, Execute, Accessed */ 2265 cs->s = 1; 2266 cs->dpl = 0; /* will be adjusted later */ 2267 cs->p = 1; 2268 cs->d = 1; 2269 cs->avl = 0; 2270 2271 set_desc_base(ss, 0); /* flat segment */ 2272 set_desc_limit(ss, 0xfffff); /* 4GB limit */ 2273 ss->g = 1; /* 4kb granularity */ 2274 ss->s = 1; 2275 ss->type = 0x03; /* Read/Write, Accessed */ 2276 ss->d = 1; /* 32bit stack segment */ 2277 ss->dpl = 0; 2278 ss->p = 1; 2279 ss->l = 0; 2280 ss->avl = 0; 2281 } 2282 2283 static bool vendor_intel(struct x86_emulate_ctxt *ctxt) 2284 { 2285 u32 eax, ebx, ecx, edx; 2286 2287 eax = ecx = 0; 2288 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); 2289 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx 2290 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx 2291 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx; 2292 } 2293 2294 static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt) 2295 { 2296 const struct x86_emulate_ops *ops = ctxt->ops; 2297 u32 eax, ebx, ecx, edx; 2298 2299 /* 2300 * syscall should always be enabled in longmode - so only become 2301 * vendor specific (cpuid) if other modes are active... 2302 */ 2303 if (ctxt->mode == X86EMUL_MODE_PROT64) 2304 return true; 2305 2306 eax = 0x00000000; 2307 ecx = 0x00000000; 2308 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); 2309 /* 2310 * Intel ("GenuineIntel") 2311 * remark: Intel CPUs only support "syscall" in 64bit 2312 * longmode. Also an 64bit guest with a 2313 * 32bit compat-app running will #UD !! While this 2314 * behaviour can be fixed (by emulating) into AMD 2315 * response - CPUs of AMD can't behave like Intel. 2316 */ 2317 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx && 2318 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx && 2319 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx) 2320 return false; 2321 2322 /* AMD ("AuthenticAMD") */ 2323 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx && 2324 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx && 2325 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx) 2326 return true; 2327 2328 /* AMD ("AMDisbetter!") */ 2329 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx && 2330 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx && 2331 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx) 2332 return true; 2333 2334 /* default: (not Intel, not AMD), apply Intel's stricter rules... */ 2335 return false; 2336 } 2337 2338 static int em_syscall(struct x86_emulate_ctxt *ctxt) 2339 { 2340 const struct x86_emulate_ops *ops = ctxt->ops; 2341 struct desc_struct cs, ss; 2342 u64 msr_data; 2343 u16 cs_sel, ss_sel; 2344 u64 efer = 0; 2345 2346 /* syscall is not available in real mode */ 2347 if (ctxt->mode == X86EMUL_MODE_REAL || 2348 ctxt->mode == X86EMUL_MODE_VM86) 2349 return emulate_ud(ctxt); 2350 2351 if (!(em_syscall_is_enabled(ctxt))) 2352 return emulate_ud(ctxt); 2353 2354 ops->get_msr(ctxt, MSR_EFER, &efer); 2355 setup_syscalls_segments(ctxt, &cs, &ss); 2356 2357 if (!(efer & EFER_SCE)) 2358 return emulate_ud(ctxt); 2359 2360 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2361 msr_data >>= 32; 2362 cs_sel = (u16)(msr_data & 0xfffc); 2363 ss_sel = (u16)(msr_data + 8); 2364 2365 if (efer & EFER_LMA) { 2366 cs.d = 0; 2367 cs.l = 1; 2368 } 2369 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2370 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2371 2372 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip; 2373 if (efer & EFER_LMA) { 2374 #ifdef CONFIG_X86_64 2375 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF; 2376 2377 ops->get_msr(ctxt, 2378 ctxt->mode == X86EMUL_MODE_PROT64 ? 2379 MSR_LSTAR : MSR_CSTAR, &msr_data); 2380 ctxt->_eip = msr_data; 2381 2382 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data); 2383 ctxt->eflags &= ~(msr_data | EFLG_RF); 2384 #endif 2385 } else { 2386 /* legacy mode */ 2387 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2388 ctxt->_eip = (u32)msr_data; 2389 2390 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); 2391 } 2392 2393 return X86EMUL_CONTINUE; 2394 } 2395 2396 static int em_sysenter(struct x86_emulate_ctxt *ctxt) 2397 { 2398 const struct x86_emulate_ops *ops = ctxt->ops; 2399 struct desc_struct cs, ss; 2400 u64 msr_data; 2401 u16 cs_sel, ss_sel; 2402 u64 efer = 0; 2403 2404 ops->get_msr(ctxt, MSR_EFER, &efer); 2405 /* inject #GP if in real mode */ 2406 if (ctxt->mode == X86EMUL_MODE_REAL) 2407 return emulate_gp(ctxt, 0); 2408 2409 /* 2410 * Not recognized on AMD in compat mode (but is recognized in legacy 2411 * mode). 2412 */ 2413 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA) 2414 && !vendor_intel(ctxt)) 2415 return emulate_ud(ctxt); 2416 2417 /* XXX sysenter/sysexit have not been tested in 64bit mode. 2418 * Therefore, we inject an #UD. 2419 */ 2420 if (ctxt->mode == X86EMUL_MODE_PROT64) 2421 return emulate_ud(ctxt); 2422 2423 setup_syscalls_segments(ctxt, &cs, &ss); 2424 2425 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2426 switch (ctxt->mode) { 2427 case X86EMUL_MODE_PROT32: 2428 if ((msr_data & 0xfffc) == 0x0) 2429 return emulate_gp(ctxt, 0); 2430 break; 2431 case X86EMUL_MODE_PROT64: 2432 if (msr_data == 0x0) 2433 return emulate_gp(ctxt, 0); 2434 break; 2435 default: 2436 break; 2437 } 2438 2439 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); 2440 cs_sel = (u16)msr_data; 2441 cs_sel &= ~SELECTOR_RPL_MASK; 2442 ss_sel = cs_sel + 8; 2443 ss_sel &= ~SELECTOR_RPL_MASK; 2444 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) { 2445 cs.d = 0; 2446 cs.l = 1; 2447 } 2448 2449 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2450 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2451 2452 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data); 2453 ctxt->_eip = msr_data; 2454 2455 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data); 2456 *reg_write(ctxt, VCPU_REGS_RSP) = msr_data; 2457 2458 return X86EMUL_CONTINUE; 2459 } 2460 2461 static int em_sysexit(struct x86_emulate_ctxt *ctxt) 2462 { 2463 const struct x86_emulate_ops *ops = ctxt->ops; 2464 struct desc_struct cs, ss; 2465 u64 msr_data; 2466 int usermode; 2467 u16 cs_sel = 0, ss_sel = 0; 2468 2469 /* inject #GP if in real mode or Virtual 8086 mode */ 2470 if (ctxt->mode == X86EMUL_MODE_REAL || 2471 ctxt->mode == X86EMUL_MODE_VM86) 2472 return emulate_gp(ctxt, 0); 2473 2474 setup_syscalls_segments(ctxt, &cs, &ss); 2475 2476 if ((ctxt->rex_prefix & 0x8) != 0x0) 2477 usermode = X86EMUL_MODE_PROT64; 2478 else 2479 usermode = X86EMUL_MODE_PROT32; 2480 2481 cs.dpl = 3; 2482 ss.dpl = 3; 2483 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2484 switch (usermode) { 2485 case X86EMUL_MODE_PROT32: 2486 cs_sel = (u16)(msr_data + 16); 2487 if ((msr_data & 0xfffc) == 0x0) 2488 return emulate_gp(ctxt, 0); 2489 ss_sel = (u16)(msr_data + 24); 2490 break; 2491 case X86EMUL_MODE_PROT64: 2492 cs_sel = (u16)(msr_data + 32); 2493 if (msr_data == 0x0) 2494 return emulate_gp(ctxt, 0); 2495 ss_sel = cs_sel + 8; 2496 cs.d = 0; 2497 cs.l = 1; 2498 break; 2499 } 2500 cs_sel |= SELECTOR_RPL_MASK; 2501 ss_sel |= SELECTOR_RPL_MASK; 2502 2503 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2504 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2505 2506 ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX); 2507 *reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX); 2508 2509 return X86EMUL_CONTINUE; 2510 } 2511 2512 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt) 2513 { 2514 int iopl; 2515 if (ctxt->mode == X86EMUL_MODE_REAL) 2516 return false; 2517 if (ctxt->mode == X86EMUL_MODE_VM86) 2518 return true; 2519 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; 2520 return ctxt->ops->cpl(ctxt) > iopl; 2521 } 2522 2523 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, 2524 u16 port, u16 len) 2525 { 2526 const struct x86_emulate_ops *ops = ctxt->ops; 2527 struct desc_struct tr_seg; 2528 u32 base3; 2529 int r; 2530 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7; 2531 unsigned mask = (1 << len) - 1; 2532 unsigned long base; 2533 2534 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR); 2535 if (!tr_seg.p) 2536 return false; 2537 if (desc_limit_scaled(&tr_seg) < 103) 2538 return false; 2539 base = get_desc_base(&tr_seg); 2540 #ifdef CONFIG_X86_64 2541 base |= ((u64)base3) << 32; 2542 #endif 2543 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL); 2544 if (r != X86EMUL_CONTINUE) 2545 return false; 2546 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) 2547 return false; 2548 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL); 2549 if (r != X86EMUL_CONTINUE) 2550 return false; 2551 if ((perm >> bit_idx) & mask) 2552 return false; 2553 return true; 2554 } 2555 2556 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, 2557 u16 port, u16 len) 2558 { 2559 if (ctxt->perm_ok) 2560 return true; 2561 2562 if (emulator_bad_iopl(ctxt)) 2563 if (!emulator_io_port_access_allowed(ctxt, port, len)) 2564 return false; 2565 2566 ctxt->perm_ok = true; 2567 2568 return true; 2569 } 2570 2571 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, 2572 struct tss_segment_16 *tss) 2573 { 2574 tss->ip = ctxt->_eip; 2575 tss->flag = ctxt->eflags; 2576 tss->ax = reg_read(ctxt, VCPU_REGS_RAX); 2577 tss->cx = reg_read(ctxt, VCPU_REGS_RCX); 2578 tss->dx = reg_read(ctxt, VCPU_REGS_RDX); 2579 tss->bx = reg_read(ctxt, VCPU_REGS_RBX); 2580 tss->sp = reg_read(ctxt, VCPU_REGS_RSP); 2581 tss->bp = reg_read(ctxt, VCPU_REGS_RBP); 2582 tss->si = reg_read(ctxt, VCPU_REGS_RSI); 2583 tss->di = reg_read(ctxt, VCPU_REGS_RDI); 2584 2585 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 2586 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 2587 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 2588 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 2589 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR); 2590 } 2591 2592 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, 2593 struct tss_segment_16 *tss) 2594 { 2595 int ret; 2596 2597 ctxt->_eip = tss->ip; 2598 ctxt->eflags = tss->flag | 2; 2599 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax; 2600 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx; 2601 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx; 2602 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx; 2603 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp; 2604 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp; 2605 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si; 2606 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di; 2607 2608 /* 2609 * SDM says that segment selectors are loaded before segment 2610 * descriptors 2611 */ 2612 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR); 2613 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 2614 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 2615 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 2616 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 2617 2618 /* 2619 * Now load segment descriptors. If fault happens at this stage 2620 * it is handled in a context of new task 2621 */ 2622 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR); 2623 if (ret != X86EMUL_CONTINUE) 2624 return ret; 2625 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES); 2626 if (ret != X86EMUL_CONTINUE) 2627 return ret; 2628 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS); 2629 if (ret != X86EMUL_CONTINUE) 2630 return ret; 2631 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS); 2632 if (ret != X86EMUL_CONTINUE) 2633 return ret; 2634 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS); 2635 if (ret != X86EMUL_CONTINUE) 2636 return ret; 2637 2638 return X86EMUL_CONTINUE; 2639 } 2640 2641 static int task_switch_16(struct x86_emulate_ctxt *ctxt, 2642 u16 tss_selector, u16 old_tss_sel, 2643 ulong old_tss_base, struct desc_struct *new_desc) 2644 { 2645 const struct x86_emulate_ops *ops = ctxt->ops; 2646 struct tss_segment_16 tss_seg; 2647 int ret; 2648 u32 new_tss_base = get_desc_base(new_desc); 2649 2650 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, 2651 &ctxt->exception); 2652 if (ret != X86EMUL_CONTINUE) 2653 /* FIXME: need to provide precise fault address */ 2654 return ret; 2655 2656 save_state_to_tss16(ctxt, &tss_seg); 2657 2658 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, 2659 &ctxt->exception); 2660 if (ret != X86EMUL_CONTINUE) 2661 /* FIXME: need to provide precise fault address */ 2662 return ret; 2663 2664 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, 2665 &ctxt->exception); 2666 if (ret != X86EMUL_CONTINUE) 2667 /* FIXME: need to provide precise fault address */ 2668 return ret; 2669 2670 if (old_tss_sel != 0xffff) { 2671 tss_seg.prev_task_link = old_tss_sel; 2672 2673 ret = ops->write_std(ctxt, new_tss_base, 2674 &tss_seg.prev_task_link, 2675 sizeof tss_seg.prev_task_link, 2676 &ctxt->exception); 2677 if (ret != X86EMUL_CONTINUE) 2678 /* FIXME: need to provide precise fault address */ 2679 return ret; 2680 } 2681 2682 return load_state_from_tss16(ctxt, &tss_seg); 2683 } 2684 2685 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, 2686 struct tss_segment_32 *tss) 2687 { 2688 tss->cr3 = ctxt->ops->get_cr(ctxt, 3); 2689 tss->eip = ctxt->_eip; 2690 tss->eflags = ctxt->eflags; 2691 tss->eax = reg_read(ctxt, VCPU_REGS_RAX); 2692 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX); 2693 tss->edx = reg_read(ctxt, VCPU_REGS_RDX); 2694 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX); 2695 tss->esp = reg_read(ctxt, VCPU_REGS_RSP); 2696 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP); 2697 tss->esi = reg_read(ctxt, VCPU_REGS_RSI); 2698 tss->edi = reg_read(ctxt, VCPU_REGS_RDI); 2699 2700 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 2701 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 2702 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 2703 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 2704 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS); 2705 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS); 2706 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR); 2707 } 2708 2709 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, 2710 struct tss_segment_32 *tss) 2711 { 2712 int ret; 2713 2714 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3)) 2715 return emulate_gp(ctxt, 0); 2716 ctxt->_eip = tss->eip; 2717 ctxt->eflags = tss->eflags | 2; 2718 2719 /* General purpose registers */ 2720 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax; 2721 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx; 2722 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx; 2723 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx; 2724 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp; 2725 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp; 2726 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi; 2727 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi; 2728 2729 /* 2730 * SDM says that segment selectors are loaded before segment 2731 * descriptors 2732 */ 2733 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); 2734 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 2735 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 2736 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 2737 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 2738 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS); 2739 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS); 2740 2741 /* 2742 * If we're switching between Protected Mode and VM86, we need to make 2743 * sure to update the mode before loading the segment descriptors so 2744 * that the selectors are interpreted correctly. 2745 * 2746 * Need to get rflags to the vcpu struct immediately because it 2747 * influences the CPL which is checked at least when loading the segment 2748 * descriptors and when pushing an error code to the new kernel stack. 2749 * 2750 * TODO Introduce a separate ctxt->ops->set_cpl callback 2751 */ 2752 if (ctxt->eflags & X86_EFLAGS_VM) 2753 ctxt->mode = X86EMUL_MODE_VM86; 2754 else 2755 ctxt->mode = X86EMUL_MODE_PROT32; 2756 2757 ctxt->ops->set_rflags(ctxt, ctxt->eflags); 2758 2759 /* 2760 * Now load segment descriptors. If fault happenes at this stage 2761 * it is handled in a context of new task 2762 */ 2763 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); 2764 if (ret != X86EMUL_CONTINUE) 2765 return ret; 2766 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES); 2767 if (ret != X86EMUL_CONTINUE) 2768 return ret; 2769 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS); 2770 if (ret != X86EMUL_CONTINUE) 2771 return ret; 2772 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS); 2773 if (ret != X86EMUL_CONTINUE) 2774 return ret; 2775 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS); 2776 if (ret != X86EMUL_CONTINUE) 2777 return ret; 2778 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS); 2779 if (ret != X86EMUL_CONTINUE) 2780 return ret; 2781 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS); 2782 if (ret != X86EMUL_CONTINUE) 2783 return ret; 2784 2785 return X86EMUL_CONTINUE; 2786 } 2787 2788 static int task_switch_32(struct x86_emulate_ctxt *ctxt, 2789 u16 tss_selector, u16 old_tss_sel, 2790 ulong old_tss_base, struct desc_struct *new_desc) 2791 { 2792 const struct x86_emulate_ops *ops = ctxt->ops; 2793 struct tss_segment_32 tss_seg; 2794 int ret; 2795 u32 new_tss_base = get_desc_base(new_desc); 2796 2797 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, 2798 &ctxt->exception); 2799 if (ret != X86EMUL_CONTINUE) 2800 /* FIXME: need to provide precise fault address */ 2801 return ret; 2802 2803 save_state_to_tss32(ctxt, &tss_seg); 2804 2805 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, 2806 &ctxt->exception); 2807 if (ret != X86EMUL_CONTINUE) 2808 /* FIXME: need to provide precise fault address */ 2809 return ret; 2810 2811 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, 2812 &ctxt->exception); 2813 if (ret != X86EMUL_CONTINUE) 2814 /* FIXME: need to provide precise fault address */ 2815 return ret; 2816 2817 if (old_tss_sel != 0xffff) { 2818 tss_seg.prev_task_link = old_tss_sel; 2819 2820 ret = ops->write_std(ctxt, new_tss_base, 2821 &tss_seg.prev_task_link, 2822 sizeof tss_seg.prev_task_link, 2823 &ctxt->exception); 2824 if (ret != X86EMUL_CONTINUE) 2825 /* FIXME: need to provide precise fault address */ 2826 return ret; 2827 } 2828 2829 return load_state_from_tss32(ctxt, &tss_seg); 2830 } 2831 2832 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, 2833 u16 tss_selector, int idt_index, int reason, 2834 bool has_error_code, u32 error_code) 2835 { 2836 const struct x86_emulate_ops *ops = ctxt->ops; 2837 struct desc_struct curr_tss_desc, next_tss_desc; 2838 int ret; 2839 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR); 2840 ulong old_tss_base = 2841 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR); 2842 u32 desc_limit; 2843 ulong desc_addr; 2844 2845 /* FIXME: old_tss_base == ~0 ? */ 2846 2847 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr); 2848 if (ret != X86EMUL_CONTINUE) 2849 return ret; 2850 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr); 2851 if (ret != X86EMUL_CONTINUE) 2852 return ret; 2853 2854 /* FIXME: check that next_tss_desc is tss */ 2855 2856 /* 2857 * Check privileges. The three cases are task switch caused by... 2858 * 2859 * 1. jmp/call/int to task gate: Check against DPL of the task gate 2860 * 2. Exception/IRQ/iret: No check is performed 2861 * 3. jmp/call to TSS: Check against DPL of the TSS 2862 */ 2863 if (reason == TASK_SWITCH_GATE) { 2864 if (idt_index != -1) { 2865 /* Software interrupts */ 2866 struct desc_struct task_gate_desc; 2867 int dpl; 2868 2869 ret = read_interrupt_descriptor(ctxt, idt_index, 2870 &task_gate_desc); 2871 if (ret != X86EMUL_CONTINUE) 2872 return ret; 2873 2874 dpl = task_gate_desc.dpl; 2875 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) 2876 return emulate_gp(ctxt, (idt_index << 3) | 0x2); 2877 } 2878 } else if (reason != TASK_SWITCH_IRET) { 2879 int dpl = next_tss_desc.dpl; 2880 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) 2881 return emulate_gp(ctxt, tss_selector); 2882 } 2883 2884 2885 desc_limit = desc_limit_scaled(&next_tss_desc); 2886 if (!next_tss_desc.p || 2887 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || 2888 desc_limit < 0x2b)) { 2889 emulate_ts(ctxt, tss_selector & 0xfffc); 2890 return X86EMUL_PROPAGATE_FAULT; 2891 } 2892 2893 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { 2894 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ 2895 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); 2896 } 2897 2898 if (reason == TASK_SWITCH_IRET) 2899 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; 2900 2901 /* set back link to prev task only if NT bit is set in eflags 2902 note that old_tss_sel is not used after this point */ 2903 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) 2904 old_tss_sel = 0xffff; 2905 2906 if (next_tss_desc.type & 8) 2907 ret = task_switch_32(ctxt, tss_selector, old_tss_sel, 2908 old_tss_base, &next_tss_desc); 2909 else 2910 ret = task_switch_16(ctxt, tss_selector, old_tss_sel, 2911 old_tss_base, &next_tss_desc); 2912 if (ret != X86EMUL_CONTINUE) 2913 return ret; 2914 2915 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) 2916 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; 2917 2918 if (reason != TASK_SWITCH_IRET) { 2919 next_tss_desc.type |= (1 << 1); /* set busy flag */ 2920 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc); 2921 } 2922 2923 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS); 2924 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR); 2925 2926 if (has_error_code) { 2927 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; 2928 ctxt->lock_prefix = 0; 2929 ctxt->src.val = (unsigned long) error_code; 2930 ret = em_push(ctxt); 2931 } 2932 2933 return ret; 2934 } 2935 2936 int emulator_task_switch(struct x86_emulate_ctxt *ctxt, 2937 u16 tss_selector, int idt_index, int reason, 2938 bool has_error_code, u32 error_code) 2939 { 2940 int rc; 2941 2942 invalidate_registers(ctxt); 2943 ctxt->_eip = ctxt->eip; 2944 ctxt->dst.type = OP_NONE; 2945 2946 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason, 2947 has_error_code, error_code); 2948 2949 if (rc == X86EMUL_CONTINUE) { 2950 ctxt->eip = ctxt->_eip; 2951 writeback_registers(ctxt); 2952 } 2953 2954 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 2955 } 2956 2957 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg, 2958 struct operand *op) 2959 { 2960 int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count; 2961 2962 register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes); 2963 op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg)); 2964 } 2965 2966 static int em_das(struct x86_emulate_ctxt *ctxt) 2967 { 2968 u8 al, old_al; 2969 bool af, cf, old_cf; 2970 2971 cf = ctxt->eflags & X86_EFLAGS_CF; 2972 al = ctxt->dst.val; 2973 2974 old_al = al; 2975 old_cf = cf; 2976 cf = false; 2977 af = ctxt->eflags & X86_EFLAGS_AF; 2978 if ((al & 0x0f) > 9 || af) { 2979 al -= 6; 2980 cf = old_cf | (al >= 250); 2981 af = true; 2982 } else { 2983 af = false; 2984 } 2985 if (old_al > 0x99 || old_cf) { 2986 al -= 0x60; 2987 cf = true; 2988 } 2989 2990 ctxt->dst.val = al; 2991 /* Set PF, ZF, SF */ 2992 ctxt->src.type = OP_IMM; 2993 ctxt->src.val = 0; 2994 ctxt->src.bytes = 1; 2995 fastop(ctxt, em_or); 2996 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); 2997 if (cf) 2998 ctxt->eflags |= X86_EFLAGS_CF; 2999 if (af) 3000 ctxt->eflags |= X86_EFLAGS_AF; 3001 return X86EMUL_CONTINUE; 3002 } 3003 3004 static int em_aam(struct x86_emulate_ctxt *ctxt) 3005 { 3006 u8 al, ah; 3007 3008 if (ctxt->src.val == 0) 3009 return emulate_de(ctxt); 3010 3011 al = ctxt->dst.val & 0xff; 3012 ah = al / ctxt->src.val; 3013 al %= ctxt->src.val; 3014 3015 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8); 3016 3017 /* Set PF, ZF, SF */ 3018 ctxt->src.type = OP_IMM; 3019 ctxt->src.val = 0; 3020 ctxt->src.bytes = 1; 3021 fastop(ctxt, em_or); 3022 3023 return X86EMUL_CONTINUE; 3024 } 3025 3026 static int em_aad(struct x86_emulate_ctxt *ctxt) 3027 { 3028 u8 al = ctxt->dst.val & 0xff; 3029 u8 ah = (ctxt->dst.val >> 8) & 0xff; 3030 3031 al = (al + (ah * ctxt->src.val)) & 0xff; 3032 3033 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al; 3034 3035 /* Set PF, ZF, SF */ 3036 ctxt->src.type = OP_IMM; 3037 ctxt->src.val = 0; 3038 ctxt->src.bytes = 1; 3039 fastop(ctxt, em_or); 3040 3041 return X86EMUL_CONTINUE; 3042 } 3043 3044 static int em_call(struct x86_emulate_ctxt *ctxt) 3045 { 3046 long rel = ctxt->src.val; 3047 3048 ctxt->src.val = (unsigned long)ctxt->_eip; 3049 jmp_rel(ctxt, rel); 3050 return em_push(ctxt); 3051 } 3052 3053 static int em_call_far(struct x86_emulate_ctxt *ctxt) 3054 { 3055 u16 sel, old_cs; 3056 ulong old_eip; 3057 int rc; 3058 3059 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS); 3060 old_eip = ctxt->_eip; 3061 3062 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 3063 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS)) 3064 return X86EMUL_CONTINUE; 3065 3066 ctxt->_eip = 0; 3067 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes); 3068 3069 ctxt->src.val = old_cs; 3070 rc = em_push(ctxt); 3071 if (rc != X86EMUL_CONTINUE) 3072 return rc; 3073 3074 ctxt->src.val = old_eip; 3075 return em_push(ctxt); 3076 } 3077 3078 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) 3079 { 3080 int rc; 3081 3082 ctxt->dst.type = OP_REG; 3083 ctxt->dst.addr.reg = &ctxt->_eip; 3084 ctxt->dst.bytes = ctxt->op_bytes; 3085 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); 3086 if (rc != X86EMUL_CONTINUE) 3087 return rc; 3088 rsp_increment(ctxt, ctxt->src.val); 3089 return X86EMUL_CONTINUE; 3090 } 3091 3092 static int em_xchg(struct x86_emulate_ctxt *ctxt) 3093 { 3094 /* Write back the register source. */ 3095 ctxt->src.val = ctxt->dst.val; 3096 write_register_operand(&ctxt->src); 3097 3098 /* Write back the memory destination with implicit LOCK prefix. */ 3099 ctxt->dst.val = ctxt->src.orig_val; 3100 ctxt->lock_prefix = 1; 3101 return X86EMUL_CONTINUE; 3102 } 3103 3104 static int em_imul_3op(struct x86_emulate_ctxt *ctxt) 3105 { 3106 ctxt->dst.val = ctxt->src2.val; 3107 return fastop(ctxt, em_imul); 3108 } 3109 3110 static int em_cwd(struct x86_emulate_ctxt *ctxt) 3111 { 3112 ctxt->dst.type = OP_REG; 3113 ctxt->dst.bytes = ctxt->src.bytes; 3114 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 3115 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1); 3116 3117 return X86EMUL_CONTINUE; 3118 } 3119 3120 static int em_rdtsc(struct x86_emulate_ctxt *ctxt) 3121 { 3122 u64 tsc = 0; 3123 3124 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc); 3125 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc; 3126 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32; 3127 return X86EMUL_CONTINUE; 3128 } 3129 3130 static int em_rdpmc(struct x86_emulate_ctxt *ctxt) 3131 { 3132 u64 pmc; 3133 3134 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc)) 3135 return emulate_gp(ctxt, 0); 3136 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc; 3137 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32; 3138 return X86EMUL_CONTINUE; 3139 } 3140 3141 static int em_mov(struct x86_emulate_ctxt *ctxt) 3142 { 3143 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes); 3144 return X86EMUL_CONTINUE; 3145 } 3146 3147 static int em_cr_write(struct x86_emulate_ctxt *ctxt) 3148 { 3149 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) 3150 return emulate_gp(ctxt, 0); 3151 3152 /* Disable writeback. */ 3153 ctxt->dst.type = OP_NONE; 3154 return X86EMUL_CONTINUE; 3155 } 3156 3157 static int em_dr_write(struct x86_emulate_ctxt *ctxt) 3158 { 3159 unsigned long val; 3160 3161 if (ctxt->mode == X86EMUL_MODE_PROT64) 3162 val = ctxt->src.val & ~0ULL; 3163 else 3164 val = ctxt->src.val & ~0U; 3165 3166 /* #UD condition is already handled. */ 3167 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0) 3168 return emulate_gp(ctxt, 0); 3169 3170 /* Disable writeback. */ 3171 ctxt->dst.type = OP_NONE; 3172 return X86EMUL_CONTINUE; 3173 } 3174 3175 static int em_wrmsr(struct x86_emulate_ctxt *ctxt) 3176 { 3177 u64 msr_data; 3178 3179 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX) 3180 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32); 3181 if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data)) 3182 return emulate_gp(ctxt, 0); 3183 3184 return X86EMUL_CONTINUE; 3185 } 3186 3187 static int em_rdmsr(struct x86_emulate_ctxt *ctxt) 3188 { 3189 u64 msr_data; 3190 3191 if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data)) 3192 return emulate_gp(ctxt, 0); 3193 3194 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data; 3195 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32; 3196 return X86EMUL_CONTINUE; 3197 } 3198 3199 static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt) 3200 { 3201 if (ctxt->modrm_reg > VCPU_SREG_GS) 3202 return emulate_ud(ctxt); 3203 3204 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg); 3205 return X86EMUL_CONTINUE; 3206 } 3207 3208 static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt) 3209 { 3210 u16 sel = ctxt->src.val; 3211 3212 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS) 3213 return emulate_ud(ctxt); 3214 3215 if (ctxt->modrm_reg == VCPU_SREG_SS) 3216 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; 3217 3218 /* Disable writeback. */ 3219 ctxt->dst.type = OP_NONE; 3220 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg); 3221 } 3222 3223 static int em_lldt(struct x86_emulate_ctxt *ctxt) 3224 { 3225 u16 sel = ctxt->src.val; 3226 3227 /* Disable writeback. */ 3228 ctxt->dst.type = OP_NONE; 3229 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR); 3230 } 3231 3232 static int em_ltr(struct x86_emulate_ctxt *ctxt) 3233 { 3234 u16 sel = ctxt->src.val; 3235 3236 /* Disable writeback. */ 3237 ctxt->dst.type = OP_NONE; 3238 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR); 3239 } 3240 3241 static int em_invlpg(struct x86_emulate_ctxt *ctxt) 3242 { 3243 int rc; 3244 ulong linear; 3245 3246 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear); 3247 if (rc == X86EMUL_CONTINUE) 3248 ctxt->ops->invlpg(ctxt, linear); 3249 /* Disable writeback. */ 3250 ctxt->dst.type = OP_NONE; 3251 return X86EMUL_CONTINUE; 3252 } 3253 3254 static int em_clts(struct x86_emulate_ctxt *ctxt) 3255 { 3256 ulong cr0; 3257 3258 cr0 = ctxt->ops->get_cr(ctxt, 0); 3259 cr0 &= ~X86_CR0_TS; 3260 ctxt->ops->set_cr(ctxt, 0, cr0); 3261 return X86EMUL_CONTINUE; 3262 } 3263 3264 static int em_vmcall(struct x86_emulate_ctxt *ctxt) 3265 { 3266 int rc; 3267 3268 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1) 3269 return X86EMUL_UNHANDLEABLE; 3270 3271 rc = ctxt->ops->fix_hypercall(ctxt); 3272 if (rc != X86EMUL_CONTINUE) 3273 return rc; 3274 3275 /* Let the processor re-execute the fixed hypercall */ 3276 ctxt->_eip = ctxt->eip; 3277 /* Disable writeback. */ 3278 ctxt->dst.type = OP_NONE; 3279 return X86EMUL_CONTINUE; 3280 } 3281 3282 static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt, 3283 void (*get)(struct x86_emulate_ctxt *ctxt, 3284 struct desc_ptr *ptr)) 3285 { 3286 struct desc_ptr desc_ptr; 3287 3288 if (ctxt->mode == X86EMUL_MODE_PROT64) 3289 ctxt->op_bytes = 8; 3290 get(ctxt, &desc_ptr); 3291 if (ctxt->op_bytes == 2) { 3292 ctxt->op_bytes = 4; 3293 desc_ptr.address &= 0x00ffffff; 3294 } 3295 /* Disable writeback. */ 3296 ctxt->dst.type = OP_NONE; 3297 return segmented_write(ctxt, ctxt->dst.addr.mem, 3298 &desc_ptr, 2 + ctxt->op_bytes); 3299 } 3300 3301 static int em_sgdt(struct x86_emulate_ctxt *ctxt) 3302 { 3303 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt); 3304 } 3305 3306 static int em_sidt(struct x86_emulate_ctxt *ctxt) 3307 { 3308 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt); 3309 } 3310 3311 static int em_lgdt(struct x86_emulate_ctxt *ctxt) 3312 { 3313 struct desc_ptr desc_ptr; 3314 int rc; 3315 3316 if (ctxt->mode == X86EMUL_MODE_PROT64) 3317 ctxt->op_bytes = 8; 3318 rc = read_descriptor(ctxt, ctxt->src.addr.mem, 3319 &desc_ptr.size, &desc_ptr.address, 3320 ctxt->op_bytes); 3321 if (rc != X86EMUL_CONTINUE) 3322 return rc; 3323 ctxt->ops->set_gdt(ctxt, &desc_ptr); 3324 /* Disable writeback. */ 3325 ctxt->dst.type = OP_NONE; 3326 return X86EMUL_CONTINUE; 3327 } 3328 3329 static int em_vmmcall(struct x86_emulate_ctxt *ctxt) 3330 { 3331 int rc; 3332 3333 rc = ctxt->ops->fix_hypercall(ctxt); 3334 3335 /* Disable writeback. */ 3336 ctxt->dst.type = OP_NONE; 3337 return rc; 3338 } 3339 3340 static int em_lidt(struct x86_emulate_ctxt *ctxt) 3341 { 3342 struct desc_ptr desc_ptr; 3343 int rc; 3344 3345 if (ctxt->mode == X86EMUL_MODE_PROT64) 3346 ctxt->op_bytes = 8; 3347 rc = read_descriptor(ctxt, ctxt->src.addr.mem, 3348 &desc_ptr.size, &desc_ptr.address, 3349 ctxt->op_bytes); 3350 if (rc != X86EMUL_CONTINUE) 3351 return rc; 3352 ctxt->ops->set_idt(ctxt, &desc_ptr); 3353 /* Disable writeback. */ 3354 ctxt->dst.type = OP_NONE; 3355 return X86EMUL_CONTINUE; 3356 } 3357 3358 static int em_smsw(struct x86_emulate_ctxt *ctxt) 3359 { 3360 ctxt->dst.bytes = 2; 3361 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0); 3362 return X86EMUL_CONTINUE; 3363 } 3364 3365 static int em_lmsw(struct x86_emulate_ctxt *ctxt) 3366 { 3367 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul) 3368 | (ctxt->src.val & 0x0f)); 3369 ctxt->dst.type = OP_NONE; 3370 return X86EMUL_CONTINUE; 3371 } 3372 3373 static int em_loop(struct x86_emulate_ctxt *ctxt) 3374 { 3375 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1); 3376 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) && 3377 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags))) 3378 jmp_rel(ctxt, ctxt->src.val); 3379 3380 return X86EMUL_CONTINUE; 3381 } 3382 3383 static int em_jcxz(struct x86_emulate_ctxt *ctxt) 3384 { 3385 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) 3386 jmp_rel(ctxt, ctxt->src.val); 3387 3388 return X86EMUL_CONTINUE; 3389 } 3390 3391 static int em_in(struct x86_emulate_ctxt *ctxt) 3392 { 3393 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val, 3394 &ctxt->dst.val)) 3395 return X86EMUL_IO_NEEDED; 3396 3397 return X86EMUL_CONTINUE; 3398 } 3399 3400 static int em_out(struct x86_emulate_ctxt *ctxt) 3401 { 3402 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val, 3403 &ctxt->src.val, 1); 3404 /* Disable writeback. */ 3405 ctxt->dst.type = OP_NONE; 3406 return X86EMUL_CONTINUE; 3407 } 3408 3409 static int em_cli(struct x86_emulate_ctxt *ctxt) 3410 { 3411 if (emulator_bad_iopl(ctxt)) 3412 return emulate_gp(ctxt, 0); 3413 3414 ctxt->eflags &= ~X86_EFLAGS_IF; 3415 return X86EMUL_CONTINUE; 3416 } 3417 3418 static int em_sti(struct x86_emulate_ctxt *ctxt) 3419 { 3420 if (emulator_bad_iopl(ctxt)) 3421 return emulate_gp(ctxt, 0); 3422 3423 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; 3424 ctxt->eflags |= X86_EFLAGS_IF; 3425 return X86EMUL_CONTINUE; 3426 } 3427 3428 static int em_cpuid(struct x86_emulate_ctxt *ctxt) 3429 { 3430 u32 eax, ebx, ecx, edx; 3431 3432 eax = reg_read(ctxt, VCPU_REGS_RAX); 3433 ecx = reg_read(ctxt, VCPU_REGS_RCX); 3434 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx); 3435 *reg_write(ctxt, VCPU_REGS_RAX) = eax; 3436 *reg_write(ctxt, VCPU_REGS_RBX) = ebx; 3437 *reg_write(ctxt, VCPU_REGS_RCX) = ecx; 3438 *reg_write(ctxt, VCPU_REGS_RDX) = edx; 3439 return X86EMUL_CONTINUE; 3440 } 3441 3442 static int em_lahf(struct x86_emulate_ctxt *ctxt) 3443 { 3444 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL; 3445 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8; 3446 return X86EMUL_CONTINUE; 3447 } 3448 3449 static int em_bswap(struct x86_emulate_ctxt *ctxt) 3450 { 3451 switch (ctxt->op_bytes) { 3452 #ifdef CONFIG_X86_64 3453 case 8: 3454 asm("bswap %0" : "+r"(ctxt->dst.val)); 3455 break; 3456 #endif 3457 default: 3458 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val)); 3459 break; 3460 } 3461 return X86EMUL_CONTINUE; 3462 } 3463 3464 static bool valid_cr(int nr) 3465 { 3466 switch (nr) { 3467 case 0: 3468 case 2 ... 4: 3469 case 8: 3470 return true; 3471 default: 3472 return false; 3473 } 3474 } 3475 3476 static int check_cr_read(struct x86_emulate_ctxt *ctxt) 3477 { 3478 if (!valid_cr(ctxt->modrm_reg)) 3479 return emulate_ud(ctxt); 3480 3481 return X86EMUL_CONTINUE; 3482 } 3483 3484 static int check_cr_write(struct x86_emulate_ctxt *ctxt) 3485 { 3486 u64 new_val = ctxt->src.val64; 3487 int cr = ctxt->modrm_reg; 3488 u64 efer = 0; 3489 3490 static u64 cr_reserved_bits[] = { 3491 0xffffffff00000000ULL, 3492 0, 0, 0, /* CR3 checked later */ 3493 CR4_RESERVED_BITS, 3494 0, 0, 0, 3495 CR8_RESERVED_BITS, 3496 }; 3497 3498 if (!valid_cr(cr)) 3499 return emulate_ud(ctxt); 3500 3501 if (new_val & cr_reserved_bits[cr]) 3502 return emulate_gp(ctxt, 0); 3503 3504 switch (cr) { 3505 case 0: { 3506 u64 cr4; 3507 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) || 3508 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD))) 3509 return emulate_gp(ctxt, 0); 3510 3511 cr4 = ctxt->ops->get_cr(ctxt, 4); 3512 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 3513 3514 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) && 3515 !(cr4 & X86_CR4_PAE)) 3516 return emulate_gp(ctxt, 0); 3517 3518 break; 3519 } 3520 case 3: { 3521 u64 rsvd = 0; 3522 3523 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 3524 if (efer & EFER_LMA) 3525 rsvd = CR3_L_MODE_RESERVED_BITS; 3526 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE) 3527 rsvd = CR3_PAE_RESERVED_BITS; 3528 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG) 3529 rsvd = CR3_NONPAE_RESERVED_BITS; 3530 3531 if (new_val & rsvd) 3532 return emulate_gp(ctxt, 0); 3533 3534 break; 3535 } 3536 case 4: { 3537 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 3538 3539 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE)) 3540 return emulate_gp(ctxt, 0); 3541 3542 break; 3543 } 3544 } 3545 3546 return X86EMUL_CONTINUE; 3547 } 3548 3549 static int check_dr7_gd(struct x86_emulate_ctxt *ctxt) 3550 { 3551 unsigned long dr7; 3552 3553 ctxt->ops->get_dr(ctxt, 7, &dr7); 3554 3555 /* Check if DR7.Global_Enable is set */ 3556 return dr7 & (1 << 13); 3557 } 3558 3559 static int check_dr_read(struct x86_emulate_ctxt *ctxt) 3560 { 3561 int dr = ctxt->modrm_reg; 3562 u64 cr4; 3563 3564 if (dr > 7) 3565 return emulate_ud(ctxt); 3566 3567 cr4 = ctxt->ops->get_cr(ctxt, 4); 3568 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5)) 3569 return emulate_ud(ctxt); 3570 3571 if (check_dr7_gd(ctxt)) 3572 return emulate_db(ctxt); 3573 3574 return X86EMUL_CONTINUE; 3575 } 3576 3577 static int check_dr_write(struct x86_emulate_ctxt *ctxt) 3578 { 3579 u64 new_val = ctxt->src.val64; 3580 int dr = ctxt->modrm_reg; 3581 3582 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL)) 3583 return emulate_gp(ctxt, 0); 3584 3585 return check_dr_read(ctxt); 3586 } 3587 3588 static int check_svme(struct x86_emulate_ctxt *ctxt) 3589 { 3590 u64 efer; 3591 3592 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 3593 3594 if (!(efer & EFER_SVME)) 3595 return emulate_ud(ctxt); 3596 3597 return X86EMUL_CONTINUE; 3598 } 3599 3600 static int check_svme_pa(struct x86_emulate_ctxt *ctxt) 3601 { 3602 u64 rax = reg_read(ctxt, VCPU_REGS_RAX); 3603 3604 /* Valid physical address? */ 3605 if (rax & 0xffff000000000000ULL) 3606 return emulate_gp(ctxt, 0); 3607 3608 return check_svme(ctxt); 3609 } 3610 3611 static int check_rdtsc(struct x86_emulate_ctxt *ctxt) 3612 { 3613 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 3614 3615 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt)) 3616 return emulate_ud(ctxt); 3617 3618 return X86EMUL_CONTINUE; 3619 } 3620 3621 static int check_rdpmc(struct x86_emulate_ctxt *ctxt) 3622 { 3623 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 3624 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX); 3625 3626 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) || 3627 (rcx > 3)) 3628 return emulate_gp(ctxt, 0); 3629 3630 return X86EMUL_CONTINUE; 3631 } 3632 3633 static int check_perm_in(struct x86_emulate_ctxt *ctxt) 3634 { 3635 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u); 3636 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes)) 3637 return emulate_gp(ctxt, 0); 3638 3639 return X86EMUL_CONTINUE; 3640 } 3641 3642 static int check_perm_out(struct x86_emulate_ctxt *ctxt) 3643 { 3644 ctxt->src.bytes = min(ctxt->src.bytes, 4u); 3645 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes)) 3646 return emulate_gp(ctxt, 0); 3647 3648 return X86EMUL_CONTINUE; 3649 } 3650 3651 #define D(_y) { .flags = (_y) } 3652 #define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i } 3653 #define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \ 3654 .check_perm = (_p) } 3655 #define N D(NotImpl) 3656 #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) } 3657 #define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) } 3658 #define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) } 3659 #define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) } 3660 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } 3661 #define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) } 3662 #define II(_f, _e, _i) \ 3663 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i } 3664 #define IIP(_f, _e, _i, _p) \ 3665 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \ 3666 .check_perm = (_p) } 3667 #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) } 3668 3669 #define D2bv(_f) D((_f) | ByteOp), D(_f) 3670 #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p) 3671 #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) 3672 #define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e) 3673 #define I2bvIP(_f, _e, _i, _p) \ 3674 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p) 3675 3676 #define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \ 3677 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \ 3678 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e) 3679 3680 static const struct opcode group7_rm1[] = { 3681 DI(SrcNone | Priv, monitor), 3682 DI(SrcNone | Priv, mwait), 3683 N, N, N, N, N, N, 3684 }; 3685 3686 static const struct opcode group7_rm3[] = { 3687 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa), 3688 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall), 3689 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa), 3690 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa), 3691 DIP(SrcNone | Prot | Priv, stgi, check_svme), 3692 DIP(SrcNone | Prot | Priv, clgi, check_svme), 3693 DIP(SrcNone | Prot | Priv, skinit, check_svme), 3694 DIP(SrcNone | Prot | Priv, invlpga, check_svme), 3695 }; 3696 3697 static const struct opcode group7_rm7[] = { 3698 N, 3699 DIP(SrcNone, rdtscp, check_rdtsc), 3700 N, N, N, N, N, N, 3701 }; 3702 3703 static const struct opcode group1[] = { 3704 F(Lock, em_add), 3705 F(Lock | PageTable, em_or), 3706 F(Lock, em_adc), 3707 F(Lock, em_sbb), 3708 F(Lock | PageTable, em_and), 3709 F(Lock, em_sub), 3710 F(Lock, em_xor), 3711 F(NoWrite, em_cmp), 3712 }; 3713 3714 static const struct opcode group1A[] = { 3715 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N, 3716 }; 3717 3718 static const struct opcode group2[] = { 3719 F(DstMem | ModRM, em_rol), 3720 F(DstMem | ModRM, em_ror), 3721 F(DstMem | ModRM, em_rcl), 3722 F(DstMem | ModRM, em_rcr), 3723 F(DstMem | ModRM, em_shl), 3724 F(DstMem | ModRM, em_shr), 3725 F(DstMem | ModRM, em_shl), 3726 F(DstMem | ModRM, em_sar), 3727 }; 3728 3729 static const struct opcode group3[] = { 3730 F(DstMem | SrcImm | NoWrite, em_test), 3731 F(DstMem | SrcImm | NoWrite, em_test), 3732 F(DstMem | SrcNone | Lock, em_not), 3733 F(DstMem | SrcNone | Lock, em_neg), 3734 I(SrcMem, em_mul_ex), 3735 I(SrcMem, em_imul_ex), 3736 I(SrcMem, em_div_ex), 3737 I(SrcMem, em_idiv_ex), 3738 }; 3739 3740 static const struct opcode group4[] = { 3741 F(ByteOp | DstMem | SrcNone | Lock, em_inc), 3742 F(ByteOp | DstMem | SrcNone | Lock, em_dec), 3743 N, N, N, N, N, N, 3744 }; 3745 3746 static const struct opcode group5[] = { 3747 F(DstMem | SrcNone | Lock, em_inc), 3748 F(DstMem | SrcNone | Lock, em_dec), 3749 I(SrcMem | Stack, em_grp45), 3750 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far), 3751 I(SrcMem | Stack, em_grp45), 3752 I(SrcMemFAddr | ImplicitOps, em_grp45), 3753 I(SrcMem | Stack, em_grp45), D(Undefined), 3754 }; 3755 3756 static const struct opcode group6[] = { 3757 DI(Prot, sldt), 3758 DI(Prot, str), 3759 II(Prot | Priv | SrcMem16, em_lldt, lldt), 3760 II(Prot | Priv | SrcMem16, em_ltr, ltr), 3761 N, N, N, N, 3762 }; 3763 3764 static const struct group_dual group7 = { { 3765 II(Mov | DstMem | Priv, em_sgdt, sgdt), 3766 II(Mov | DstMem | Priv, em_sidt, sidt), 3767 II(SrcMem | Priv, em_lgdt, lgdt), 3768 II(SrcMem | Priv, em_lidt, lidt), 3769 II(SrcNone | DstMem | Mov, em_smsw, smsw), N, 3770 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), 3771 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg), 3772 }, { 3773 I(SrcNone | Priv | VendorSpecific, em_vmcall), 3774 EXT(0, group7_rm1), 3775 N, EXT(0, group7_rm3), 3776 II(SrcNone | DstMem | Mov, em_smsw, smsw), N, 3777 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), 3778 EXT(0, group7_rm7), 3779 } }; 3780 3781 static const struct opcode group8[] = { 3782 N, N, N, N, 3783 F(DstMem | SrcImmByte | NoWrite, em_bt), 3784 F(DstMem | SrcImmByte | Lock | PageTable, em_bts), 3785 F(DstMem | SrcImmByte | Lock, em_btr), 3786 F(DstMem | SrcImmByte | Lock | PageTable, em_btc), 3787 }; 3788 3789 static const struct group_dual group9 = { { 3790 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N, 3791 }, { 3792 N, N, N, N, N, N, N, N, 3793 } }; 3794 3795 static const struct opcode group11[] = { 3796 I(DstMem | SrcImm | Mov | PageTable, em_mov), 3797 X7(D(Undefined)), 3798 }; 3799 3800 static const struct gprefix pfx_0f_6f_0f_7f = { 3801 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov), 3802 }; 3803 3804 static const struct gprefix pfx_vmovntpx = { 3805 I(0, em_mov), N, N, N, 3806 }; 3807 3808 static const struct escape escape_d9 = { { 3809 N, N, N, N, N, N, N, I(DstMem, em_fnstcw), 3810 }, { 3811 /* 0xC0 - 0xC7 */ 3812 N, N, N, N, N, N, N, N, 3813 /* 0xC8 - 0xCF */ 3814 N, N, N, N, N, N, N, N, 3815 /* 0xD0 - 0xC7 */ 3816 N, N, N, N, N, N, N, N, 3817 /* 0xD8 - 0xDF */ 3818 N, N, N, N, N, N, N, N, 3819 /* 0xE0 - 0xE7 */ 3820 N, N, N, N, N, N, N, N, 3821 /* 0xE8 - 0xEF */ 3822 N, N, N, N, N, N, N, N, 3823 /* 0xF0 - 0xF7 */ 3824 N, N, N, N, N, N, N, N, 3825 /* 0xF8 - 0xFF */ 3826 N, N, N, N, N, N, N, N, 3827 } }; 3828 3829 static const struct escape escape_db = { { 3830 N, N, N, N, N, N, N, N, 3831 }, { 3832 /* 0xC0 - 0xC7 */ 3833 N, N, N, N, N, N, N, N, 3834 /* 0xC8 - 0xCF */ 3835 N, N, N, N, N, N, N, N, 3836 /* 0xD0 - 0xC7 */ 3837 N, N, N, N, N, N, N, N, 3838 /* 0xD8 - 0xDF */ 3839 N, N, N, N, N, N, N, N, 3840 /* 0xE0 - 0xE7 */ 3841 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N, 3842 /* 0xE8 - 0xEF */ 3843 N, N, N, N, N, N, N, N, 3844 /* 0xF0 - 0xF7 */ 3845 N, N, N, N, N, N, N, N, 3846 /* 0xF8 - 0xFF */ 3847 N, N, N, N, N, N, N, N, 3848 } }; 3849 3850 static const struct escape escape_dd = { { 3851 N, N, N, N, N, N, N, I(DstMem, em_fnstsw), 3852 }, { 3853 /* 0xC0 - 0xC7 */ 3854 N, N, N, N, N, N, N, N, 3855 /* 0xC8 - 0xCF */ 3856 N, N, N, N, N, N, N, N, 3857 /* 0xD0 - 0xC7 */ 3858 N, N, N, N, N, N, N, N, 3859 /* 0xD8 - 0xDF */ 3860 N, N, N, N, N, N, N, N, 3861 /* 0xE0 - 0xE7 */ 3862 N, N, N, N, N, N, N, N, 3863 /* 0xE8 - 0xEF */ 3864 N, N, N, N, N, N, N, N, 3865 /* 0xF0 - 0xF7 */ 3866 N, N, N, N, N, N, N, N, 3867 /* 0xF8 - 0xFF */ 3868 N, N, N, N, N, N, N, N, 3869 } }; 3870 3871 static const struct opcode opcode_table[256] = { 3872 /* 0x00 - 0x07 */ 3873 F6ALU(Lock, em_add), 3874 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg), 3875 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg), 3876 /* 0x08 - 0x0F */ 3877 F6ALU(Lock | PageTable, em_or), 3878 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg), 3879 N, 3880 /* 0x10 - 0x17 */ 3881 F6ALU(Lock, em_adc), 3882 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg), 3883 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg), 3884 /* 0x18 - 0x1F */ 3885 F6ALU(Lock, em_sbb), 3886 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg), 3887 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg), 3888 /* 0x20 - 0x27 */ 3889 F6ALU(Lock | PageTable, em_and), N, N, 3890 /* 0x28 - 0x2F */ 3891 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das), 3892 /* 0x30 - 0x37 */ 3893 F6ALU(Lock, em_xor), N, N, 3894 /* 0x38 - 0x3F */ 3895 F6ALU(NoWrite, em_cmp), N, N, 3896 /* 0x40 - 0x4F */ 3897 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)), 3898 /* 0x50 - 0x57 */ 3899 X8(I(SrcReg | Stack, em_push)), 3900 /* 0x58 - 0x5F */ 3901 X8(I(DstReg | Stack, em_pop)), 3902 /* 0x60 - 0x67 */ 3903 I(ImplicitOps | Stack | No64, em_pusha), 3904 I(ImplicitOps | Stack | No64, em_popa), 3905 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ , 3906 N, N, N, N, 3907 /* 0x68 - 0x6F */ 3908 I(SrcImm | Mov | Stack, em_push), 3909 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), 3910 I(SrcImmByte | Mov | Stack, em_push), 3911 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), 3912 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */ 3913 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */ 3914 /* 0x70 - 0x7F */ 3915 X16(D(SrcImmByte)), 3916 /* 0x80 - 0x87 */ 3917 G(ByteOp | DstMem | SrcImm, group1), 3918 G(DstMem | SrcImm, group1), 3919 G(ByteOp | DstMem | SrcImm | No64, group1), 3920 G(DstMem | SrcImmByte, group1), 3921 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test), 3922 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg), 3923 /* 0x88 - 0x8F */ 3924 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov), 3925 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov), 3926 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg), 3927 D(ModRM | SrcMem | NoAccess | DstReg), 3928 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm), 3929 G(0, group1A), 3930 /* 0x90 - 0x97 */ 3931 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)), 3932 /* 0x98 - 0x9F */ 3933 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), 3934 I(SrcImmFAddr | No64, em_call_far), N, 3935 II(ImplicitOps | Stack, em_pushf, pushf), 3936 II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf), 3937 /* 0xA0 - 0xA7 */ 3938 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), 3939 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov), 3940 I2bv(SrcSI | DstDI | Mov | String, em_mov), 3941 F2bv(SrcSI | DstDI | String | NoWrite, em_cmp), 3942 /* 0xA8 - 0xAF */ 3943 F2bv(DstAcc | SrcImm | NoWrite, em_test), 3944 I2bv(SrcAcc | DstDI | Mov | String, em_mov), 3945 I2bv(SrcSI | DstAcc | Mov | String, em_mov), 3946 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp), 3947 /* 0xB0 - 0xB7 */ 3948 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), 3949 /* 0xB8 - 0xBF */ 3950 X8(I(DstReg | SrcImm64 | Mov, em_mov)), 3951 /* 0xC0 - 0xC7 */ 3952 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2), 3953 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm), 3954 I(ImplicitOps | Stack, em_ret), 3955 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg), 3956 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg), 3957 G(ByteOp, group11), G(0, group11), 3958 /* 0xC8 - 0xCF */ 3959 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave), 3960 N, I(ImplicitOps | Stack, em_ret_far), 3961 D(ImplicitOps), DI(SrcImmByte, intn), 3962 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret), 3963 /* 0xD0 - 0xD7 */ 3964 G(Src2One | ByteOp, group2), G(Src2One, group2), 3965 G(Src2CL | ByteOp, group2), G(Src2CL, group2), 3966 I(DstAcc | SrcImmUByte | No64, em_aam), 3967 I(DstAcc | SrcImmUByte | No64, em_aad), 3968 F(DstAcc | ByteOp | No64, em_salc), 3969 I(DstAcc | SrcXLat | ByteOp, em_mov), 3970 /* 0xD8 - 0xDF */ 3971 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N, 3972 /* 0xE0 - 0xE7 */ 3973 X3(I(SrcImmByte, em_loop)), 3974 I(SrcImmByte, em_jcxz), 3975 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in), 3976 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out), 3977 /* 0xE8 - 0xEF */ 3978 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps), 3979 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps), 3980 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in), 3981 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out), 3982 /* 0xF0 - 0xF7 */ 3983 N, DI(ImplicitOps, icebp), N, N, 3984 DI(ImplicitOps | Priv, hlt), D(ImplicitOps), 3985 G(ByteOp, group3), G(0, group3), 3986 /* 0xF8 - 0xFF */ 3987 D(ImplicitOps), D(ImplicitOps), 3988 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti), 3989 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), 3990 }; 3991 3992 static const struct opcode twobyte_table[256] = { 3993 /* 0x00 - 0x0F */ 3994 G(0, group6), GD(0, &group7), N, N, 3995 N, I(ImplicitOps | VendorSpecific, em_syscall), 3996 II(ImplicitOps | Priv, em_clts, clts), N, 3997 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, 3998 N, D(ImplicitOps | ModRM), N, N, 3999 /* 0x10 - 0x1F */ 4000 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N, 4001 /* 0x20 - 0x2F */ 4002 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read), 4003 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read), 4004 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write), 4005 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write), 4006 N, N, N, N, 4007 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx), 4008 N, N, N, N, 4009 /* 0x30 - 0x3F */ 4010 II(ImplicitOps | Priv, em_wrmsr, wrmsr), 4011 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc), 4012 II(ImplicitOps | Priv, em_rdmsr, rdmsr), 4013 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc), 4014 I(ImplicitOps | VendorSpecific, em_sysenter), 4015 I(ImplicitOps | Priv | VendorSpecific, em_sysexit), 4016 N, N, 4017 N, N, N, N, N, N, N, N, 4018 /* 0x40 - 0x4F */ 4019 X16(D(DstReg | SrcMem | ModRM | Mov)), 4020 /* 0x50 - 0x5F */ 4021 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 4022 /* 0x60 - 0x6F */ 4023 N, N, N, N, 4024 N, N, N, N, 4025 N, N, N, N, 4026 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f), 4027 /* 0x70 - 0x7F */ 4028 N, N, N, N, 4029 N, N, N, N, 4030 N, N, N, N, 4031 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f), 4032 /* 0x80 - 0x8F */ 4033 X16(D(SrcImm)), 4034 /* 0x90 - 0x9F */ 4035 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), 4036 /* 0xA0 - 0xA7 */ 4037 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg), 4038 II(ImplicitOps, em_cpuid, cpuid), 4039 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt), 4040 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld), 4041 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N, 4042 /* 0xA8 - 0xAF */ 4043 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg), 4044 DI(ImplicitOps, rsm), 4045 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts), 4046 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd), 4047 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd), 4048 D(ModRM), F(DstReg | SrcMem | ModRM, em_imul), 4049 /* 0xB0 - 0xB7 */ 4050 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg), 4051 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg), 4052 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr), 4053 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg), 4054 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg), 4055 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 4056 /* 0xB8 - 0xBF */ 4057 N, N, 4058 G(BitOp, group8), 4059 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc), 4060 F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr), 4061 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 4062 /* 0xC0 - 0xC7 */ 4063 D2bv(DstMem | SrcReg | ModRM | Lock), 4064 N, D(DstMem | SrcReg | ModRM | Mov), 4065 N, N, N, GD(0, &group9), 4066 /* 0xC8 - 0xCF */ 4067 X8(I(DstReg, em_bswap)), 4068 /* 0xD0 - 0xDF */ 4069 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 4070 /* 0xE0 - 0xEF */ 4071 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 4072 /* 0xF0 - 0xFF */ 4073 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N 4074 }; 4075 4076 #undef D 4077 #undef N 4078 #undef G 4079 #undef GD 4080 #undef I 4081 #undef GP 4082 #undef EXT 4083 4084 #undef D2bv 4085 #undef D2bvIP 4086 #undef I2bv 4087 #undef I2bvIP 4088 #undef I6ALU 4089 4090 static unsigned imm_size(struct x86_emulate_ctxt *ctxt) 4091 { 4092 unsigned size; 4093 4094 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4095 if (size == 8) 4096 size = 4; 4097 return size; 4098 } 4099 4100 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, 4101 unsigned size, bool sign_extension) 4102 { 4103 int rc = X86EMUL_CONTINUE; 4104 4105 op->type = OP_IMM; 4106 op->bytes = size; 4107 op->addr.mem.ea = ctxt->_eip; 4108 /* NB. Immediates are sign-extended as necessary. */ 4109 switch (op->bytes) { 4110 case 1: 4111 op->val = insn_fetch(s8, ctxt); 4112 break; 4113 case 2: 4114 op->val = insn_fetch(s16, ctxt); 4115 break; 4116 case 4: 4117 op->val = insn_fetch(s32, ctxt); 4118 break; 4119 case 8: 4120 op->val = insn_fetch(s64, ctxt); 4121 break; 4122 } 4123 if (!sign_extension) { 4124 switch (op->bytes) { 4125 case 1: 4126 op->val &= 0xff; 4127 break; 4128 case 2: 4129 op->val &= 0xffff; 4130 break; 4131 case 4: 4132 op->val &= 0xffffffff; 4133 break; 4134 } 4135 } 4136 done: 4137 return rc; 4138 } 4139 4140 static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op, 4141 unsigned d) 4142 { 4143 int rc = X86EMUL_CONTINUE; 4144 4145 switch (d) { 4146 case OpReg: 4147 decode_register_operand(ctxt, op); 4148 break; 4149 case OpImmUByte: 4150 rc = decode_imm(ctxt, op, 1, false); 4151 break; 4152 case OpMem: 4153 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4154 mem_common: 4155 *op = ctxt->memop; 4156 ctxt->memopp = op; 4157 if ((ctxt->d & BitOp) && op == &ctxt->dst) 4158 fetch_bit_operand(ctxt); 4159 op->orig_val = op->val; 4160 break; 4161 case OpMem64: 4162 ctxt->memop.bytes = 8; 4163 goto mem_common; 4164 case OpAcc: 4165 op->type = OP_REG; 4166 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4167 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 4168 fetch_register_operand(op); 4169 op->orig_val = op->val; 4170 break; 4171 case OpDI: 4172 op->type = OP_MEM; 4173 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4174 op->addr.mem.ea = 4175 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI)); 4176 op->addr.mem.seg = VCPU_SREG_ES; 4177 op->val = 0; 4178 op->count = 1; 4179 break; 4180 case OpDX: 4181 op->type = OP_REG; 4182 op->bytes = 2; 4183 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 4184 fetch_register_operand(op); 4185 break; 4186 case OpCL: 4187 op->bytes = 1; 4188 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff; 4189 break; 4190 case OpImmByte: 4191 rc = decode_imm(ctxt, op, 1, true); 4192 break; 4193 case OpOne: 4194 op->bytes = 1; 4195 op->val = 1; 4196 break; 4197 case OpImm: 4198 rc = decode_imm(ctxt, op, imm_size(ctxt), true); 4199 break; 4200 case OpImm64: 4201 rc = decode_imm(ctxt, op, ctxt->op_bytes, true); 4202 break; 4203 case OpMem8: 4204 ctxt->memop.bytes = 1; 4205 if (ctxt->memop.type == OP_REG) { 4206 ctxt->memop.addr.reg = decode_register(ctxt, ctxt->modrm_rm, 1); 4207 fetch_register_operand(&ctxt->memop); 4208 } 4209 goto mem_common; 4210 case OpMem16: 4211 ctxt->memop.bytes = 2; 4212 goto mem_common; 4213 case OpMem32: 4214 ctxt->memop.bytes = 4; 4215 goto mem_common; 4216 case OpImmU16: 4217 rc = decode_imm(ctxt, op, 2, false); 4218 break; 4219 case OpImmU: 4220 rc = decode_imm(ctxt, op, imm_size(ctxt), false); 4221 break; 4222 case OpSI: 4223 op->type = OP_MEM; 4224 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4225 op->addr.mem.ea = 4226 register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI)); 4227 op->addr.mem.seg = seg_override(ctxt); 4228 op->val = 0; 4229 op->count = 1; 4230 break; 4231 case OpXLat: 4232 op->type = OP_MEM; 4233 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4234 op->addr.mem.ea = 4235 register_address(ctxt, 4236 reg_read(ctxt, VCPU_REGS_RBX) + 4237 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff)); 4238 op->addr.mem.seg = seg_override(ctxt); 4239 op->val = 0; 4240 break; 4241 case OpImmFAddr: 4242 op->type = OP_IMM; 4243 op->addr.mem.ea = ctxt->_eip; 4244 op->bytes = ctxt->op_bytes + 2; 4245 insn_fetch_arr(op->valptr, op->bytes, ctxt); 4246 break; 4247 case OpMemFAddr: 4248 ctxt->memop.bytes = ctxt->op_bytes + 2; 4249 goto mem_common; 4250 case OpES: 4251 op->val = VCPU_SREG_ES; 4252 break; 4253 case OpCS: 4254 op->val = VCPU_SREG_CS; 4255 break; 4256 case OpSS: 4257 op->val = VCPU_SREG_SS; 4258 break; 4259 case OpDS: 4260 op->val = VCPU_SREG_DS; 4261 break; 4262 case OpFS: 4263 op->val = VCPU_SREG_FS; 4264 break; 4265 case OpGS: 4266 op->val = VCPU_SREG_GS; 4267 break; 4268 case OpImplicit: 4269 /* Special instructions do their own operand decoding. */ 4270 default: 4271 op->type = OP_NONE; /* Disable writeback. */ 4272 break; 4273 } 4274 4275 done: 4276 return rc; 4277 } 4278 4279 int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len) 4280 { 4281 int rc = X86EMUL_CONTINUE; 4282 int mode = ctxt->mode; 4283 int def_op_bytes, def_ad_bytes, goffset, simd_prefix; 4284 bool op_prefix = false; 4285 struct opcode opcode; 4286 4287 ctxt->memop.type = OP_NONE; 4288 ctxt->memopp = NULL; 4289 ctxt->_eip = ctxt->eip; 4290 ctxt->fetch.start = ctxt->_eip; 4291 ctxt->fetch.end = ctxt->fetch.start + insn_len; 4292 if (insn_len > 0) 4293 memcpy(ctxt->fetch.data, insn, insn_len); 4294 4295 switch (mode) { 4296 case X86EMUL_MODE_REAL: 4297 case X86EMUL_MODE_VM86: 4298 case X86EMUL_MODE_PROT16: 4299 def_op_bytes = def_ad_bytes = 2; 4300 break; 4301 case X86EMUL_MODE_PROT32: 4302 def_op_bytes = def_ad_bytes = 4; 4303 break; 4304 #ifdef CONFIG_X86_64 4305 case X86EMUL_MODE_PROT64: 4306 def_op_bytes = 4; 4307 def_ad_bytes = 8; 4308 break; 4309 #endif 4310 default: 4311 return EMULATION_FAILED; 4312 } 4313 4314 ctxt->op_bytes = def_op_bytes; 4315 ctxt->ad_bytes = def_ad_bytes; 4316 4317 /* Legacy prefixes. */ 4318 for (;;) { 4319 switch (ctxt->b = insn_fetch(u8, ctxt)) { 4320 case 0x66: /* operand-size override */ 4321 op_prefix = true; 4322 /* switch between 2/4 bytes */ 4323 ctxt->op_bytes = def_op_bytes ^ 6; 4324 break; 4325 case 0x67: /* address-size override */ 4326 if (mode == X86EMUL_MODE_PROT64) 4327 /* switch between 4/8 bytes */ 4328 ctxt->ad_bytes = def_ad_bytes ^ 12; 4329 else 4330 /* switch between 2/4 bytes */ 4331 ctxt->ad_bytes = def_ad_bytes ^ 6; 4332 break; 4333 case 0x26: /* ES override */ 4334 case 0x2e: /* CS override */ 4335 case 0x36: /* SS override */ 4336 case 0x3e: /* DS override */ 4337 set_seg_override(ctxt, (ctxt->b >> 3) & 3); 4338 break; 4339 case 0x64: /* FS override */ 4340 case 0x65: /* GS override */ 4341 set_seg_override(ctxt, ctxt->b & 7); 4342 break; 4343 case 0x40 ... 0x4f: /* REX */ 4344 if (mode != X86EMUL_MODE_PROT64) 4345 goto done_prefixes; 4346 ctxt->rex_prefix = ctxt->b; 4347 continue; 4348 case 0xf0: /* LOCK */ 4349 ctxt->lock_prefix = 1; 4350 break; 4351 case 0xf2: /* REPNE/REPNZ */ 4352 case 0xf3: /* REP/REPE/REPZ */ 4353 ctxt->rep_prefix = ctxt->b; 4354 break; 4355 default: 4356 goto done_prefixes; 4357 } 4358 4359 /* Any legacy prefix after a REX prefix nullifies its effect. */ 4360 4361 ctxt->rex_prefix = 0; 4362 } 4363 4364 done_prefixes: 4365 4366 /* REX prefix. */ 4367 if (ctxt->rex_prefix & 8) 4368 ctxt->op_bytes = 8; /* REX.W */ 4369 4370 /* Opcode byte(s). */ 4371 opcode = opcode_table[ctxt->b]; 4372 /* Two-byte opcode? */ 4373 if (ctxt->b == 0x0f) { 4374 ctxt->twobyte = 1; 4375 ctxt->b = insn_fetch(u8, ctxt); 4376 opcode = twobyte_table[ctxt->b]; 4377 } 4378 ctxt->d = opcode.flags; 4379 4380 if (ctxt->d & ModRM) 4381 ctxt->modrm = insn_fetch(u8, ctxt); 4382 4383 while (ctxt->d & GroupMask) { 4384 switch (ctxt->d & GroupMask) { 4385 case Group: 4386 goffset = (ctxt->modrm >> 3) & 7; 4387 opcode = opcode.u.group[goffset]; 4388 break; 4389 case GroupDual: 4390 goffset = (ctxt->modrm >> 3) & 7; 4391 if ((ctxt->modrm >> 6) == 3) 4392 opcode = opcode.u.gdual->mod3[goffset]; 4393 else 4394 opcode = opcode.u.gdual->mod012[goffset]; 4395 break; 4396 case RMExt: 4397 goffset = ctxt->modrm & 7; 4398 opcode = opcode.u.group[goffset]; 4399 break; 4400 case Prefix: 4401 if (ctxt->rep_prefix && op_prefix) 4402 return EMULATION_FAILED; 4403 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix; 4404 switch (simd_prefix) { 4405 case 0x00: opcode = opcode.u.gprefix->pfx_no; break; 4406 case 0x66: opcode = opcode.u.gprefix->pfx_66; break; 4407 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break; 4408 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break; 4409 } 4410 break; 4411 case Escape: 4412 if (ctxt->modrm > 0xbf) 4413 opcode = opcode.u.esc->high[ctxt->modrm - 0xc0]; 4414 else 4415 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7]; 4416 break; 4417 default: 4418 return EMULATION_FAILED; 4419 } 4420 4421 ctxt->d &= ~(u64)GroupMask; 4422 ctxt->d |= opcode.flags; 4423 } 4424 4425 ctxt->execute = opcode.u.execute; 4426 ctxt->check_perm = opcode.check_perm; 4427 ctxt->intercept = opcode.intercept; 4428 4429 /* Unrecognised? */ 4430 if (ctxt->d == 0 || (ctxt->d & NotImpl)) 4431 return EMULATION_FAILED; 4432 4433 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn) 4434 return EMULATION_FAILED; 4435 4436 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack)) 4437 ctxt->op_bytes = 8; 4438 4439 if (ctxt->d & Op3264) { 4440 if (mode == X86EMUL_MODE_PROT64) 4441 ctxt->op_bytes = 8; 4442 else 4443 ctxt->op_bytes = 4; 4444 } 4445 4446 if (ctxt->d & Sse) 4447 ctxt->op_bytes = 16; 4448 else if (ctxt->d & Mmx) 4449 ctxt->op_bytes = 8; 4450 4451 /* ModRM and SIB bytes. */ 4452 if (ctxt->d & ModRM) { 4453 rc = decode_modrm(ctxt, &ctxt->memop); 4454 if (!ctxt->has_seg_override) 4455 set_seg_override(ctxt, ctxt->modrm_seg); 4456 } else if (ctxt->d & MemAbs) 4457 rc = decode_abs(ctxt, &ctxt->memop); 4458 if (rc != X86EMUL_CONTINUE) 4459 goto done; 4460 4461 if (!ctxt->has_seg_override) 4462 set_seg_override(ctxt, VCPU_SREG_DS); 4463 4464 ctxt->memop.addr.mem.seg = seg_override(ctxt); 4465 4466 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8) 4467 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea; 4468 4469 /* 4470 * Decode and fetch the source operand: register, memory 4471 * or immediate. 4472 */ 4473 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask); 4474 if (rc != X86EMUL_CONTINUE) 4475 goto done; 4476 4477 /* 4478 * Decode and fetch the second source operand: register, memory 4479 * or immediate. 4480 */ 4481 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask); 4482 if (rc != X86EMUL_CONTINUE) 4483 goto done; 4484 4485 /* Decode and fetch the destination operand: register or memory. */ 4486 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask); 4487 4488 done: 4489 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative) 4490 ctxt->memopp->addr.mem.ea += ctxt->_eip; 4491 4492 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK; 4493 } 4494 4495 bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt) 4496 { 4497 return ctxt->d & PageTable; 4498 } 4499 4500 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt) 4501 { 4502 /* The second termination condition only applies for REPE 4503 * and REPNE. Test if the repeat string operation prefix is 4504 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the 4505 * corresponding termination condition according to: 4506 * - if REPE/REPZ and ZF = 0 then done 4507 * - if REPNE/REPNZ and ZF = 1 then done 4508 */ 4509 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) || 4510 (ctxt->b == 0xae) || (ctxt->b == 0xaf)) 4511 && (((ctxt->rep_prefix == REPE_PREFIX) && 4512 ((ctxt->eflags & EFLG_ZF) == 0)) 4513 || ((ctxt->rep_prefix == REPNE_PREFIX) && 4514 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)))) 4515 return true; 4516 4517 return false; 4518 } 4519 4520 static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt) 4521 { 4522 bool fault = false; 4523 4524 ctxt->ops->get_fpu(ctxt); 4525 asm volatile("1: fwait \n\t" 4526 "2: \n\t" 4527 ".pushsection .fixup,\"ax\" \n\t" 4528 "3: \n\t" 4529 "movb $1, %[fault] \n\t" 4530 "jmp 2b \n\t" 4531 ".popsection \n\t" 4532 _ASM_EXTABLE(1b, 3b) 4533 : [fault]"+qm"(fault)); 4534 ctxt->ops->put_fpu(ctxt); 4535 4536 if (unlikely(fault)) 4537 return emulate_exception(ctxt, MF_VECTOR, 0, false); 4538 4539 return X86EMUL_CONTINUE; 4540 } 4541 4542 static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt, 4543 struct operand *op) 4544 { 4545 if (op->type == OP_MM) 4546 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm); 4547 } 4548 4549 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *)) 4550 { 4551 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF; 4552 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE; 4553 asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n" 4554 : "+a"(ctxt->dst.val), "+b"(ctxt->src.val), [flags]"+D"(flags) 4555 : "c"(ctxt->src2.val), [fastop]"S"(fop)); 4556 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK); 4557 return X86EMUL_CONTINUE; 4558 } 4559 4560 int x86_emulate_insn(struct x86_emulate_ctxt *ctxt) 4561 { 4562 const struct x86_emulate_ops *ops = ctxt->ops; 4563 int rc = X86EMUL_CONTINUE; 4564 int saved_dst_type = ctxt->dst.type; 4565 4566 ctxt->mem_read.pos = 0; 4567 4568 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) || 4569 (ctxt->d & Undefined)) { 4570 rc = emulate_ud(ctxt); 4571 goto done; 4572 } 4573 4574 /* LOCK prefix is allowed only with some instructions */ 4575 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) { 4576 rc = emulate_ud(ctxt); 4577 goto done; 4578 } 4579 4580 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) { 4581 rc = emulate_ud(ctxt); 4582 goto done; 4583 } 4584 4585 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM))) 4586 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) { 4587 rc = emulate_ud(ctxt); 4588 goto done; 4589 } 4590 4591 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) { 4592 rc = emulate_nm(ctxt); 4593 goto done; 4594 } 4595 4596 if (ctxt->d & Mmx) { 4597 rc = flush_pending_x87_faults(ctxt); 4598 if (rc != X86EMUL_CONTINUE) 4599 goto done; 4600 /* 4601 * Now that we know the fpu is exception safe, we can fetch 4602 * operands from it. 4603 */ 4604 fetch_possible_mmx_operand(ctxt, &ctxt->src); 4605 fetch_possible_mmx_operand(ctxt, &ctxt->src2); 4606 if (!(ctxt->d & Mov)) 4607 fetch_possible_mmx_operand(ctxt, &ctxt->dst); 4608 } 4609 4610 if (unlikely(ctxt->guest_mode) && ctxt->intercept) { 4611 rc = emulator_check_intercept(ctxt, ctxt->intercept, 4612 X86_ICPT_PRE_EXCEPT); 4613 if (rc != X86EMUL_CONTINUE) 4614 goto done; 4615 } 4616 4617 /* Privileged instruction can be executed only in CPL=0 */ 4618 if ((ctxt->d & Priv) && ops->cpl(ctxt)) { 4619 rc = emulate_gp(ctxt, 0); 4620 goto done; 4621 } 4622 4623 /* Instruction can only be executed in protected mode */ 4624 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) { 4625 rc = emulate_ud(ctxt); 4626 goto done; 4627 } 4628 4629 /* Do instruction specific permission checks */ 4630 if (ctxt->check_perm) { 4631 rc = ctxt->check_perm(ctxt); 4632 if (rc != X86EMUL_CONTINUE) 4633 goto done; 4634 } 4635 4636 if (unlikely(ctxt->guest_mode) && ctxt->intercept) { 4637 rc = emulator_check_intercept(ctxt, ctxt->intercept, 4638 X86_ICPT_POST_EXCEPT); 4639 if (rc != X86EMUL_CONTINUE) 4640 goto done; 4641 } 4642 4643 if (ctxt->rep_prefix && (ctxt->d & String)) { 4644 /* All REP prefixes have the same first termination condition */ 4645 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) { 4646 ctxt->eip = ctxt->_eip; 4647 goto done; 4648 } 4649 } 4650 4651 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) { 4652 rc = segmented_read(ctxt, ctxt->src.addr.mem, 4653 ctxt->src.valptr, ctxt->src.bytes); 4654 if (rc != X86EMUL_CONTINUE) 4655 goto done; 4656 ctxt->src.orig_val64 = ctxt->src.val64; 4657 } 4658 4659 if (ctxt->src2.type == OP_MEM) { 4660 rc = segmented_read(ctxt, ctxt->src2.addr.mem, 4661 &ctxt->src2.val, ctxt->src2.bytes); 4662 if (rc != X86EMUL_CONTINUE) 4663 goto done; 4664 } 4665 4666 if ((ctxt->d & DstMask) == ImplicitOps) 4667 goto special_insn; 4668 4669 4670 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) { 4671 /* optimisation - avoid slow emulated read if Mov */ 4672 rc = segmented_read(ctxt, ctxt->dst.addr.mem, 4673 &ctxt->dst.val, ctxt->dst.bytes); 4674 if (rc != X86EMUL_CONTINUE) 4675 goto done; 4676 } 4677 ctxt->dst.orig_val = ctxt->dst.val; 4678 4679 special_insn: 4680 4681 if (unlikely(ctxt->guest_mode) && ctxt->intercept) { 4682 rc = emulator_check_intercept(ctxt, ctxt->intercept, 4683 X86_ICPT_POST_MEMACCESS); 4684 if (rc != X86EMUL_CONTINUE) 4685 goto done; 4686 } 4687 4688 if (ctxt->execute) { 4689 if (ctxt->d & Fastop) { 4690 void (*fop)(struct fastop *) = (void *)ctxt->execute; 4691 rc = fastop(ctxt, fop); 4692 if (rc != X86EMUL_CONTINUE) 4693 goto done; 4694 goto writeback; 4695 } 4696 rc = ctxt->execute(ctxt); 4697 if (rc != X86EMUL_CONTINUE) 4698 goto done; 4699 goto writeback; 4700 } 4701 4702 if (ctxt->twobyte) 4703 goto twobyte_insn; 4704 4705 switch (ctxt->b) { 4706 case 0x63: /* movsxd */ 4707 if (ctxt->mode != X86EMUL_MODE_PROT64) 4708 goto cannot_emulate; 4709 ctxt->dst.val = (s32) ctxt->src.val; 4710 break; 4711 case 0x70 ... 0x7f: /* jcc (short) */ 4712 if (test_cc(ctxt->b, ctxt->eflags)) 4713 jmp_rel(ctxt, ctxt->src.val); 4714 break; 4715 case 0x8d: /* lea r16/r32, m */ 4716 ctxt->dst.val = ctxt->src.addr.mem.ea; 4717 break; 4718 case 0x90 ... 0x97: /* nop / xchg reg, rax */ 4719 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX)) 4720 break; 4721 rc = em_xchg(ctxt); 4722 break; 4723 case 0x98: /* cbw/cwde/cdqe */ 4724 switch (ctxt->op_bytes) { 4725 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break; 4726 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break; 4727 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break; 4728 } 4729 break; 4730 case 0xcc: /* int3 */ 4731 rc = emulate_int(ctxt, 3); 4732 break; 4733 case 0xcd: /* int n */ 4734 rc = emulate_int(ctxt, ctxt->src.val); 4735 break; 4736 case 0xce: /* into */ 4737 if (ctxt->eflags & EFLG_OF) 4738 rc = emulate_int(ctxt, 4); 4739 break; 4740 case 0xe9: /* jmp rel */ 4741 case 0xeb: /* jmp rel short */ 4742 jmp_rel(ctxt, ctxt->src.val); 4743 ctxt->dst.type = OP_NONE; /* Disable writeback. */ 4744 break; 4745 case 0xf4: /* hlt */ 4746 ctxt->ops->halt(ctxt); 4747 break; 4748 case 0xf5: /* cmc */ 4749 /* complement carry flag from eflags reg */ 4750 ctxt->eflags ^= EFLG_CF; 4751 break; 4752 case 0xf8: /* clc */ 4753 ctxt->eflags &= ~EFLG_CF; 4754 break; 4755 case 0xf9: /* stc */ 4756 ctxt->eflags |= EFLG_CF; 4757 break; 4758 case 0xfc: /* cld */ 4759 ctxt->eflags &= ~EFLG_DF; 4760 break; 4761 case 0xfd: /* std */ 4762 ctxt->eflags |= EFLG_DF; 4763 break; 4764 default: 4765 goto cannot_emulate; 4766 } 4767 4768 if (rc != X86EMUL_CONTINUE) 4769 goto done; 4770 4771 writeback: 4772 rc = writeback(ctxt); 4773 if (rc != X86EMUL_CONTINUE) 4774 goto done; 4775 4776 /* 4777 * restore dst type in case the decoding will be reused 4778 * (happens for string instruction ) 4779 */ 4780 ctxt->dst.type = saved_dst_type; 4781 4782 if ((ctxt->d & SrcMask) == SrcSI) 4783 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src); 4784 4785 if ((ctxt->d & DstMask) == DstDI) 4786 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst); 4787 4788 if (ctxt->rep_prefix && (ctxt->d & String)) { 4789 unsigned int count; 4790 struct read_cache *r = &ctxt->io_read; 4791 if ((ctxt->d & SrcMask) == SrcSI) 4792 count = ctxt->src.count; 4793 else 4794 count = ctxt->dst.count; 4795 register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), 4796 -count); 4797 4798 if (!string_insn_completed(ctxt)) { 4799 /* 4800 * Re-enter guest when pio read ahead buffer is empty 4801 * or, if it is not used, after each 1024 iteration. 4802 */ 4803 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) && 4804 (r->end == 0 || r->end != r->pos)) { 4805 /* 4806 * Reset read cache. Usually happens before 4807 * decode, but since instruction is restarted 4808 * we have to do it here. 4809 */ 4810 ctxt->mem_read.end = 0; 4811 writeback_registers(ctxt); 4812 return EMULATION_RESTART; 4813 } 4814 goto done; /* skip rip writeback */ 4815 } 4816 } 4817 4818 ctxt->eip = ctxt->_eip; 4819 4820 done: 4821 if (rc == X86EMUL_PROPAGATE_FAULT) 4822 ctxt->have_exception = true; 4823 if (rc == X86EMUL_INTERCEPTED) 4824 return EMULATION_INTERCEPTED; 4825 4826 if (rc == X86EMUL_CONTINUE) 4827 writeback_registers(ctxt); 4828 4829 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 4830 4831 twobyte_insn: 4832 switch (ctxt->b) { 4833 case 0x09: /* wbinvd */ 4834 (ctxt->ops->wbinvd)(ctxt); 4835 break; 4836 case 0x08: /* invd */ 4837 case 0x0d: /* GrpP (prefetch) */ 4838 case 0x18: /* Grp16 (prefetch/nop) */ 4839 break; 4840 case 0x20: /* mov cr, reg */ 4841 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg); 4842 break; 4843 case 0x21: /* mov from dr to reg */ 4844 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val); 4845 break; 4846 case 0x40 ... 0x4f: /* cmov */ 4847 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val; 4848 if (!test_cc(ctxt->b, ctxt->eflags)) 4849 ctxt->dst.type = OP_NONE; /* no writeback */ 4850 break; 4851 case 0x80 ... 0x8f: /* jnz rel, etc*/ 4852 if (test_cc(ctxt->b, ctxt->eflags)) 4853 jmp_rel(ctxt, ctxt->src.val); 4854 break; 4855 case 0x90 ... 0x9f: /* setcc r/m8 */ 4856 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags); 4857 break; 4858 case 0xae: /* clflush */ 4859 break; 4860 case 0xb6 ... 0xb7: /* movzx */ 4861 ctxt->dst.bytes = ctxt->op_bytes; 4862 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val 4863 : (u16) ctxt->src.val; 4864 break; 4865 case 0xbe ... 0xbf: /* movsx */ 4866 ctxt->dst.bytes = ctxt->op_bytes; 4867 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val : 4868 (s16) ctxt->src.val; 4869 break; 4870 case 0xc0 ... 0xc1: /* xadd */ 4871 fastop(ctxt, em_add); 4872 /* Write back the register source. */ 4873 ctxt->src.val = ctxt->dst.orig_val; 4874 write_register_operand(&ctxt->src); 4875 break; 4876 case 0xc3: /* movnti */ 4877 ctxt->dst.bytes = ctxt->op_bytes; 4878 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val : 4879 (u64) ctxt->src.val; 4880 break; 4881 default: 4882 goto cannot_emulate; 4883 } 4884 4885 if (rc != X86EMUL_CONTINUE) 4886 goto done; 4887 4888 goto writeback; 4889 4890 cannot_emulate: 4891 return EMULATION_FAILED; 4892 } 4893 4894 void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt) 4895 { 4896 invalidate_registers(ctxt); 4897 } 4898 4899 void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt) 4900 { 4901 writeback_registers(ctxt); 4902 } 4903