1 // SPDX-License-Identifier: GPL-2.0-only 2 /****************************************************************************** 3 * emulate.c 4 * 5 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. 6 * 7 * Copyright (c) 2005 Keir Fraser 8 * 9 * Linux coding style, mod r/m decoder, segment base fixes, real-mode 10 * privileged instructions: 11 * 12 * Copyright (C) 2006 Qumranet 13 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 14 * 15 * Avi Kivity <avi@qumranet.com> 16 * Yaniv Kamay <yaniv@qumranet.com> 17 * 18 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 19 */ 20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 21 22 #include <linux/kvm_host.h> 23 #include "regs.h" 24 #include "kvm_emulate.h" 25 #include <linux/stringify.h> 26 #include <asm/debugreg.h> 27 #include <asm/insn-eval.h> 28 #include <asm/nospec-branch.h> 29 #include <asm/ibt.h> 30 #include <asm/text-patching.h> 31 32 #include "x86.h" 33 #include "tss.h" 34 #include "mmu.h" 35 #include "pmu.h" 36 37 /* 38 * Operand types 39 */ 40 #define OpNone 0ull 41 #define OpImplicit 1ull /* No generic decode */ 42 #define OpReg 2ull /* Register */ 43 #define OpMem 3ull /* Memory */ 44 #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */ 45 #define OpDI 5ull /* ES:DI/EDI/RDI */ 46 #define OpMem64 6ull /* Memory, 64-bit */ 47 #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */ 48 #define OpDX 8ull /* DX register */ 49 #define OpCL 9ull /* CL register (for shifts) */ 50 #define OpImmByte 10ull /* 8-bit sign extended immediate */ 51 #define OpOne 11ull /* Implied 1 */ 52 #define OpImm 12ull /* Sign extended up to 32-bit immediate */ 53 #define OpMem16 13ull /* Memory operand (16-bit). */ 54 #define OpMem32 14ull /* Memory operand (32-bit). */ 55 #define OpImmU 15ull /* Immediate operand, zero extended */ 56 #define OpSI 16ull /* SI/ESI/RSI */ 57 #define OpImmFAddr 17ull /* Immediate far address */ 58 #define OpMemFAddr 18ull /* Far address in memory */ 59 #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */ 60 #define OpES 20ull /* ES */ 61 #define OpCS 21ull /* CS */ 62 #define OpSS 22ull /* SS */ 63 #define OpDS 23ull /* DS */ 64 #define OpFS 24ull /* FS */ 65 #define OpGS 25ull /* GS */ 66 #define OpMem8 26ull /* 8-bit zero extended memory operand */ 67 #define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */ 68 #define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */ 69 #define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */ 70 #define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */ 71 72 #define OpBits 5 /* Width of operand field */ 73 #define OpMask ((1ull << OpBits) - 1) 74 75 /* 76 * Opcode effective-address decode tables. 77 * Note that we only emulate instructions that have at least one memory 78 * operand (excluding implicit stack references). We assume that stack 79 * references and instruction fetches will never occur in special memory 80 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need 81 * not be handled. 82 */ 83 84 /* Operand sizes: 8-bit operands or specified/overridden size. */ 85 #define ByteOp (1<<0) /* 8-bit operands. */ 86 #define DstShift 1 /* Destination operand type at bits 1-5 */ 87 #define ImplicitOps (OpImplicit << DstShift) 88 #define DstReg (OpReg << DstShift) 89 #define DstMem (OpMem << DstShift) 90 #define DstAcc (OpAcc << DstShift) 91 #define DstDI (OpDI << DstShift) 92 #define DstMem64 (OpMem64 << DstShift) 93 #define DstMem16 (OpMem16 << DstShift) 94 #define DstImmUByte (OpImmUByte << DstShift) 95 #define DstDX (OpDX << DstShift) 96 #define DstAccLo (OpAccLo << DstShift) 97 #define DstMask (OpMask << DstShift) 98 #define SrcShift 6 /* Source operand type at bits 6-10 */ 99 #define SrcNone (OpNone << SrcShift) 100 #define SrcReg (OpReg << SrcShift) 101 #define SrcMem (OpMem << SrcShift) 102 #define SrcMem16 (OpMem16 << SrcShift) 103 #define SrcMem32 (OpMem32 << SrcShift) 104 #define SrcImm (OpImm << SrcShift) 105 #define SrcImmByte (OpImmByte << SrcShift) 106 #define SrcOne (OpOne << SrcShift) 107 #define SrcImmUByte (OpImmUByte << SrcShift) 108 #define SrcImmU (OpImmU << SrcShift) 109 #define SrcSI (OpSI << SrcShift) 110 #define SrcXLat (OpXLat << SrcShift) 111 #define SrcImmFAddr (OpImmFAddr << SrcShift) 112 #define SrcMemFAddr (OpMemFAddr << SrcShift) 113 #define SrcAcc (OpAcc << SrcShift) 114 #define SrcImmU16 (OpImmU16 << SrcShift) 115 #define SrcImm64 (OpImm64 << SrcShift) 116 #define SrcDX (OpDX << SrcShift) 117 #define SrcMem8 (OpMem8 << SrcShift) 118 #define SrcAccHi (OpAccHi << SrcShift) 119 #define SrcMask (OpMask << SrcShift) 120 #define BitOp (1<<11) 121 #define MemAbs (1<<12) /* Memory operand is absolute displacement */ 122 #define String (1<<13) /* String instruction (rep capable) */ 123 #define Stack (1<<14) /* Stack instruction (push/pop) */ 124 #define GroupMask (7<<15) /* Group mechanisms, at bits 15-17 */ 125 #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */ 126 #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */ 127 #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */ 128 #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */ 129 #define Escape (5<<15) /* Escape to coprocessor instruction */ 130 #define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */ 131 #define ModeDual (7<<15) /* Different instruction for 32/64 bit */ 132 #define Sse (1<<18) /* SSE Vector instruction */ 133 #define ModRM (1<<19) /* Generic ModRM decode. */ 134 #define Mov (1<<20) /* Destination is only written; never read. */ 135 #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */ 136 #define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */ 137 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ 138 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ 139 #define Undefined (1<<25) /* No Such Instruction */ 140 #define Lock (1<<26) /* lock prefix is allowed for the instruction */ 141 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ 142 #define No64 (1<<28) /* Instruction generates #UD in 64-bit mode */ 143 #define PageTable (1 << 29) /* instruction used to write page table */ 144 #define NotImpl (1 << 30) /* instruction is not implemented */ 145 #define Avx ((u64)1 << 31) /* Instruction uses VEX prefix */ 146 #define Src2Shift (32) /* Source 2 operand type at bits 32-36 */ 147 #define Src2None (OpNone << Src2Shift) 148 #define Src2Mem (OpMem << Src2Shift) 149 #define Src2CL (OpCL << Src2Shift) 150 #define Src2ImmByte (OpImmByte << Src2Shift) 151 #define Src2One (OpOne << Src2Shift) 152 #define Src2Imm (OpImm << Src2Shift) 153 #define Src2ES (OpES << Src2Shift) 154 #define Src2CS (OpCS << Src2Shift) 155 #define Src2SS (OpSS << Src2Shift) 156 #define Src2DS (OpDS << Src2Shift) 157 #define Src2FS (OpFS << Src2Shift) 158 #define Src2GS (OpGS << Src2Shift) 159 #define Src2Mask (OpMask << Src2Shift) 160 /* free: 37-39 */ 161 #define Mmx ((u64)1 << 40) /* MMX Vector instruction */ 162 #define AlignMask ((u64)3 << 41) /* Memory alignment requirement at bits 41-42 */ 163 #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */ 164 #define Unaligned ((u64)2 << 41) /* Explicitly unaligned (e.g. MOVDQU) */ 165 #define Aligned16 ((u64)3 << 41) /* Aligned to 16 byte boundary (e.g. FXSAVE) */ 166 /* free: 43-44 */ 167 #define NoWrite ((u64)1 << 45) /* No writeback */ 168 #define SrcWrite ((u64)1 << 46) /* Write back src operand */ 169 #define NoMod ((u64)1 << 47) /* Mod field is ignored */ 170 #define Intercept ((u64)1 << 48) /* Has valid intercept field */ 171 #define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */ 172 #define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */ 173 #define NearBranch ((u64)1 << 52) /* Near branches */ 174 #define No16 ((u64)1 << 53) /* No 16 bit operand */ 175 #define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */ 176 #define TwoMemOp ((u64)1 << 55) /* Instruction has two memory operand */ 177 #define IsBranch ((u64)1 << 56) /* Instruction is considered a branch. */ 178 #define ShadowStack ((u64)1 << 57) /* Instruction affects Shadow Stacks. */ 179 180 #define DstXacc (DstAccLo | SrcAccHi | SrcWrite) 181 182 #define X2(x...) x, x 183 #define X3(x...) X2(x), x 184 #define X4(x...) X2(x), X2(x) 185 #define X5(x...) X4(x), x 186 #define X6(x...) X4(x), X2(x) 187 #define X7(x...) X4(x), X3(x) 188 #define X8(x...) X4(x), X4(x) 189 #define X16(x...) X8(x), X8(x) 190 191 struct opcode { 192 u64 flags; 193 u8 intercept; 194 u8 pad[7]; 195 union { 196 int (*execute)(struct x86_emulate_ctxt *ctxt); 197 const struct opcode *group; 198 const struct group_dual *gdual; 199 const struct gprefix *gprefix; 200 const struct escape *esc; 201 const struct instr_dual *idual; 202 const struct mode_dual *mdual; 203 } u; 204 int (*check_perm)(struct x86_emulate_ctxt *ctxt); 205 }; 206 207 struct group_dual { 208 struct opcode mod012[8]; 209 struct opcode mod3[8]; 210 }; 211 212 struct gprefix { 213 struct opcode pfx_no; 214 struct opcode pfx_66; 215 struct opcode pfx_f2; 216 struct opcode pfx_f3; 217 }; 218 219 struct escape { 220 struct opcode op[8]; 221 struct opcode high[64]; 222 }; 223 224 struct instr_dual { 225 struct opcode mod012; 226 struct opcode mod3; 227 }; 228 229 struct mode_dual { 230 struct opcode mode32; 231 struct opcode mode64; 232 }; 233 234 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a 235 236 enum x86_transfer_type { 237 X86_TRANSFER_NONE, 238 X86_TRANSFER_CALL_JMP, 239 X86_TRANSFER_RET, 240 X86_TRANSFER_TASK_SWITCH, 241 }; 242 243 enum rex_bits { 244 REX_B = 1, 245 REX_X = 2, 246 REX_R = 4, 247 REX_W = 8, 248 }; 249 250 static void writeback_registers(struct x86_emulate_ctxt *ctxt) 251 { 252 unsigned long dirty = ctxt->regs_dirty; 253 unsigned reg; 254 255 for_each_set_bit(reg, &dirty, NR_EMULATOR_GPRS) 256 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]); 257 } 258 259 static void invalidate_registers(struct x86_emulate_ctxt *ctxt) 260 { 261 ctxt->regs_dirty = 0; 262 ctxt->regs_valid = 0; 263 } 264 265 /* 266 * These EFLAGS bits are restored from saved value during emulation, and 267 * any changes are written back to the saved value after emulation. 268 */ 269 #define EFLAGS_MASK (X86_EFLAGS_OF|X86_EFLAGS_SF|X86_EFLAGS_ZF|X86_EFLAGS_AF|\ 270 X86_EFLAGS_PF|X86_EFLAGS_CF) 271 272 #ifdef CONFIG_X86_64 273 #define ON64(x...) x 274 #else 275 #define ON64(x...) 276 #endif 277 278 #define EM_ASM_START(op) \ 279 static int em_##op(struct x86_emulate_ctxt *ctxt) \ 280 { \ 281 unsigned long flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF; \ 282 int bytes = 1, ok = 1; \ 283 if (!(ctxt->d & ByteOp)) \ 284 bytes = ctxt->dst.bytes; \ 285 switch (bytes) { 286 287 #define __EM_ASM(str) \ 288 asm("push %[flags]; popf \n\t" \ 289 "10: " str \ 290 "pushf; pop %[flags] \n\t" \ 291 "11: \n\t" \ 292 : "+a" (ctxt->dst.val), \ 293 "+d" (ctxt->src.val), \ 294 [flags] "+D" (flags), \ 295 "+S" (ok) \ 296 : "c" (ctxt->src2.val)) 297 298 #define __EM_ASM_1(op, dst) \ 299 __EM_ASM(#op " %%" #dst " \n\t") 300 301 #define __EM_ASM_1_EX(op, dst) \ 302 __EM_ASM(#op " %%" #dst " \n\t" \ 303 _ASM_EXTABLE_TYPE_REG(10b, 11f, EX_TYPE_ZERO_REG, %%esi)) 304 305 #define __EM_ASM_2(op, dst, src) \ 306 __EM_ASM(#op " %%" #src ", %%" #dst " \n\t") 307 308 #define __EM_ASM_3(op, dst, src, src2) \ 309 __EM_ASM(#op " %%" #src2 ", %%" #src ", %%" #dst " \n\t") 310 311 #define EM_ASM_END \ 312 } \ 313 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK); \ 314 return !ok ? emulate_de(ctxt) : X86EMUL_CONTINUE; \ 315 } 316 317 /* 1-operand, using "a" (dst) */ 318 #define EM_ASM_1(op) \ 319 EM_ASM_START(op) \ 320 case 1: __EM_ASM_1(op##b, al); break; \ 321 case 2: __EM_ASM_1(op##w, ax); break; \ 322 case 4: __EM_ASM_1(op##l, eax); break; \ 323 ON64(case 8: __EM_ASM_1(op##q, rax); break;) \ 324 EM_ASM_END 325 326 /* 1-operand, using "c" (src2) */ 327 #define EM_ASM_1SRC2(op, name) \ 328 EM_ASM_START(name) \ 329 case 1: __EM_ASM_1(op##b, cl); break; \ 330 case 2: __EM_ASM_1(op##w, cx); break; \ 331 case 4: __EM_ASM_1(op##l, ecx); break; \ 332 ON64(case 8: __EM_ASM_1(op##q, rcx); break;) \ 333 EM_ASM_END 334 335 /* 1-operand, using "c" (src2) with exception */ 336 #define EM_ASM_1SRC2EX(op, name) \ 337 EM_ASM_START(name) \ 338 case 1: __EM_ASM_1_EX(op##b, cl); break; \ 339 case 2: __EM_ASM_1_EX(op##w, cx); break; \ 340 case 4: __EM_ASM_1_EX(op##l, ecx); break; \ 341 ON64(case 8: __EM_ASM_1_EX(op##q, rcx); break;) \ 342 EM_ASM_END 343 344 /* 2-operand, using "a" (dst), "d" (src) */ 345 #define EM_ASM_2(op) \ 346 EM_ASM_START(op) \ 347 case 1: __EM_ASM_2(op##b, al, dl); break; \ 348 case 2: __EM_ASM_2(op##w, ax, dx); break; \ 349 case 4: __EM_ASM_2(op##l, eax, edx); break; \ 350 ON64(case 8: __EM_ASM_2(op##q, rax, rdx); break;) \ 351 EM_ASM_END 352 353 /* 2-operand, reversed */ 354 #define EM_ASM_2R(op, name) \ 355 EM_ASM_START(name) \ 356 case 1: __EM_ASM_2(op##b, dl, al); break; \ 357 case 2: __EM_ASM_2(op##w, dx, ax); break; \ 358 case 4: __EM_ASM_2(op##l, edx, eax); break; \ 359 ON64(case 8: __EM_ASM_2(op##q, rdx, rax); break;) \ 360 EM_ASM_END 361 362 /* 2-operand, word only (no byte op) */ 363 #define EM_ASM_2W(op) \ 364 EM_ASM_START(op) \ 365 case 1: break; \ 366 case 2: __EM_ASM_2(op##w, ax, dx); break; \ 367 case 4: __EM_ASM_2(op##l, eax, edx); break; \ 368 ON64(case 8: __EM_ASM_2(op##q, rax, rdx); break;) \ 369 EM_ASM_END 370 371 /* 2-operand, using "a" (dst) and CL (src2) */ 372 #define EM_ASM_2CL(op) \ 373 EM_ASM_START(op) \ 374 case 1: __EM_ASM_2(op##b, al, cl); break; \ 375 case 2: __EM_ASM_2(op##w, ax, cl); break; \ 376 case 4: __EM_ASM_2(op##l, eax, cl); break; \ 377 ON64(case 8: __EM_ASM_2(op##q, rax, cl); break;) \ 378 EM_ASM_END 379 380 /* 3-operand, using "a" (dst), "d" (src) and CL (src2) */ 381 #define EM_ASM_3WCL(op) \ 382 EM_ASM_START(op) \ 383 case 1: break; \ 384 case 2: __EM_ASM_3(op##w, ax, dx, cl); break; \ 385 case 4: __EM_ASM_3(op##l, eax, edx, cl); break; \ 386 ON64(case 8: __EM_ASM_3(op##q, rax, rdx, cl); break;) \ 387 EM_ASM_END 388 389 static int em_salc(struct x86_emulate_ctxt *ctxt) 390 { 391 /* 392 * Set AL 0xFF if CF is set, or 0x00 when clear. 393 */ 394 ctxt->dst.val = 0xFF * !!(ctxt->eflags & X86_EFLAGS_CF); 395 return X86EMUL_CONTINUE; 396 } 397 398 /* 399 * XXX: inoutclob user must know where the argument is being expanded. 400 * Using asm goto would allow us to remove _fault. 401 */ 402 #define asm_safe(insn, inoutclob...) \ 403 ({ \ 404 int _fault = 0; \ 405 \ 406 asm volatile("1:" insn "\n" \ 407 "2:\n" \ 408 _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_ONE_REG, %[_fault]) \ 409 : [_fault] "+r"(_fault) inoutclob ); \ 410 \ 411 _fault ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; \ 412 }) 413 414 static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt, 415 enum x86_intercept intercept, 416 enum x86_intercept_stage stage) 417 { 418 struct x86_instruction_info info = { 419 .intercept = intercept, 420 .rep_prefix = ctxt->rep_prefix, 421 .modrm_mod = ctxt->modrm_mod, 422 .modrm_reg = ctxt->modrm_reg, 423 .modrm_rm = ctxt->modrm_rm, 424 .src_val = ctxt->src.val64, 425 .dst_val = ctxt->dst.val64, 426 .src_bytes = ctxt->src.bytes, 427 .dst_bytes = ctxt->dst.bytes, 428 .src_type = ctxt->src.type, 429 .dst_type = ctxt->dst.type, 430 .ad_bytes = ctxt->ad_bytes, 431 .rip = ctxt->eip, 432 .next_rip = ctxt->_eip, 433 }; 434 435 return ctxt->ops->intercept(ctxt, &info, stage); 436 } 437 438 static void assign_masked(ulong *dest, ulong src, ulong mask) 439 { 440 *dest = (*dest & ~mask) | (src & mask); 441 } 442 443 static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt) 444 { 445 return (1UL << (ctxt->ad_bytes << 3)) - 1; 446 } 447 448 static ulong stack_mask(struct x86_emulate_ctxt *ctxt) 449 { 450 u16 sel; 451 struct desc_struct ss; 452 453 if (ctxt->mode == X86EMUL_MODE_PROT64) 454 return ~0UL; 455 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS); 456 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */ 457 } 458 459 static int stack_size(struct x86_emulate_ctxt *ctxt) 460 { 461 return (__fls(stack_mask(ctxt)) + 1) >> 3; 462 } 463 464 /* Access/update address held in a register, based on addressing mode. */ 465 static inline unsigned long 466 address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg) 467 { 468 if (ctxt->ad_bytes == sizeof(unsigned long)) 469 return reg; 470 else 471 return reg & ad_mask(ctxt); 472 } 473 474 static inline unsigned long 475 register_address(struct x86_emulate_ctxt *ctxt, int reg) 476 { 477 return address_mask(ctxt, reg_read(ctxt, reg)); 478 } 479 480 static void masked_increment(ulong *reg, ulong mask, int inc) 481 { 482 assign_masked(reg, *reg + inc, mask); 483 } 484 485 static inline void 486 register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc) 487 { 488 ulong *preg = reg_rmw(ctxt, reg); 489 490 insn_assign_reg(preg, *preg + inc, ctxt->ad_bytes); 491 } 492 493 static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc) 494 { 495 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc); 496 } 497 498 static u32 desc_limit_scaled(struct desc_struct *desc) 499 { 500 u32 limit = get_desc_limit(desc); 501 502 return desc->g ? (limit << 12) | 0xfff : limit; 503 } 504 505 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) 506 { 507 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) 508 return 0; 509 510 return ctxt->ops->get_cached_segment_base(ctxt, seg); 511 } 512 513 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, 514 u32 error, bool valid) 515 { 516 if (KVM_EMULATOR_BUG_ON(vec > 0x1f, ctxt)) 517 return X86EMUL_UNHANDLEABLE; 518 519 ctxt->exception.vector = vec; 520 ctxt->exception.error_code = error; 521 ctxt->exception.error_code_valid = valid; 522 return X86EMUL_PROPAGATE_FAULT; 523 } 524 525 static int emulate_db(struct x86_emulate_ctxt *ctxt, unsigned long dr6) 526 { 527 ctxt->exception.dr6 = dr6; 528 return emulate_exception(ctxt, DB_VECTOR, 0, false); 529 } 530 531 static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err) 532 { 533 return emulate_exception(ctxt, GP_VECTOR, err, true); 534 } 535 536 static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err) 537 { 538 return emulate_exception(ctxt, SS_VECTOR, err, true); 539 } 540 541 static int emulate_ud(struct x86_emulate_ctxt *ctxt) 542 { 543 return emulate_exception(ctxt, UD_VECTOR, 0, false); 544 } 545 546 static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err) 547 { 548 return emulate_exception(ctxt, TS_VECTOR, err, true); 549 } 550 551 static int emulate_de(struct x86_emulate_ctxt *ctxt) 552 { 553 return emulate_exception(ctxt, DE_VECTOR, 0, false); 554 } 555 556 static int emulate_nm(struct x86_emulate_ctxt *ctxt) 557 { 558 return emulate_exception(ctxt, NM_VECTOR, 0, false); 559 } 560 561 static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg) 562 { 563 u16 selector; 564 struct desc_struct desc; 565 566 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg); 567 return selector; 568 } 569 570 static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector, 571 unsigned seg) 572 { 573 u16 dummy; 574 u32 base3; 575 struct desc_struct desc; 576 577 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg); 578 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg); 579 } 580 581 static inline u8 ctxt_virt_addr_bits(struct x86_emulate_ctxt *ctxt) 582 { 583 return (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_LA57) ? 57 : 48; 584 } 585 586 static inline bool emul_is_noncanonical_address(u64 la, 587 struct x86_emulate_ctxt *ctxt, 588 unsigned int flags) 589 { 590 return !ctxt->ops->is_canonical_addr(ctxt, la, flags); 591 } 592 593 /* 594 * x86 defines three classes of vector instructions: explicitly 595 * aligned, explicitly unaligned, and the rest, which change behaviour 596 * depending on whether they're AVX encoded or not. 597 * 598 * Also included is CMPXCHG16B which is not a vector instruction, yet it is 599 * subject to the same check. FXSAVE and FXRSTOR are checked here too as their 600 * 512 bytes of data must be aligned to a 16 byte boundary. 601 */ 602 static unsigned insn_alignment(struct x86_emulate_ctxt *ctxt, unsigned size) 603 { 604 u64 alignment = ctxt->d & AlignMask; 605 606 if (likely(size < 16)) 607 return 1; 608 609 switch (alignment) { 610 case Unaligned: 611 return 1; 612 case Aligned16: 613 return 16; 614 case Aligned: 615 default: 616 return size; 617 } 618 } 619 620 static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt, 621 struct segmented_address addr, 622 unsigned *max_size, unsigned size, 623 enum x86emul_mode mode, ulong *linear, 624 unsigned int flags) 625 { 626 struct desc_struct desc; 627 bool usable; 628 ulong la; 629 u32 lim; 630 u16 sel; 631 u8 va_bits; 632 633 la = seg_base(ctxt, addr.seg) + addr.ea; 634 *max_size = 0; 635 switch (mode) { 636 case X86EMUL_MODE_PROT64: 637 *linear = la = ctxt->ops->get_untagged_addr(ctxt, la, flags); 638 va_bits = ctxt_virt_addr_bits(ctxt); 639 if (!__is_canonical_address(la, va_bits)) 640 goto bad; 641 642 *max_size = min_t(u64, ~0u, (1ull << va_bits) - la); 643 if (size > *max_size) 644 goto bad; 645 break; 646 default: 647 *linear = la = (u32)la; 648 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL, 649 addr.seg); 650 if (!usable) 651 goto bad; 652 /* code segment in protected mode or read-only data segment */ 653 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8)) || !(desc.type & 2)) && 654 (flags & X86EMUL_F_WRITE)) 655 goto bad; 656 /* unreadable code segment */ 657 if (!(flags & X86EMUL_F_FETCH) && (desc.type & 8) && !(desc.type & 2)) 658 goto bad; 659 lim = desc_limit_scaled(&desc); 660 if (!(desc.type & 8) && (desc.type & 4)) { 661 /* expand-down segment */ 662 if (addr.ea <= lim) 663 goto bad; 664 lim = desc.d ? 0xffffffff : 0xffff; 665 } 666 if (addr.ea > lim) 667 goto bad; 668 if (lim == 0xffffffff) 669 *max_size = ~0u; 670 else { 671 *max_size = (u64)lim + 1 - addr.ea; 672 if (size > *max_size) 673 goto bad; 674 } 675 break; 676 } 677 if (la & (insn_alignment(ctxt, size) - 1)) 678 return emulate_gp(ctxt, 0); 679 return X86EMUL_CONTINUE; 680 bad: 681 if (addr.seg == VCPU_SREG_SS) 682 return emulate_ss(ctxt, 0); 683 else 684 return emulate_gp(ctxt, 0); 685 } 686 687 static int linearize(struct x86_emulate_ctxt *ctxt, 688 struct segmented_address addr, 689 unsigned size, bool write, 690 ulong *linear) 691 { 692 unsigned max_size; 693 return __linearize(ctxt, addr, &max_size, size, ctxt->mode, linear, 694 write ? X86EMUL_F_WRITE : 0); 695 } 696 697 static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst) 698 { 699 ulong linear; 700 int rc; 701 unsigned max_size; 702 struct segmented_address addr = { .seg = VCPU_SREG_CS, 703 .ea = dst }; 704 705 if (ctxt->op_bytes != sizeof(unsigned long)) 706 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1); 707 rc = __linearize(ctxt, addr, &max_size, 1, ctxt->mode, &linear, 708 X86EMUL_F_FETCH); 709 if (rc == X86EMUL_CONTINUE) 710 ctxt->_eip = addr.ea; 711 return rc; 712 } 713 714 static inline int emulator_recalc_and_set_mode(struct x86_emulate_ctxt *ctxt) 715 { 716 u64 efer; 717 struct desc_struct cs; 718 u16 selector; 719 u32 base3; 720 721 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 722 723 if (!(ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PE)) { 724 /* Real mode. cpu must not have long mode active */ 725 if (efer & EFER_LMA) 726 return X86EMUL_UNHANDLEABLE; 727 ctxt->mode = X86EMUL_MODE_REAL; 728 return X86EMUL_CONTINUE; 729 } 730 731 if (ctxt->eflags & X86_EFLAGS_VM) { 732 /* Protected/VM86 mode. cpu must not have long mode active */ 733 if (efer & EFER_LMA) 734 return X86EMUL_UNHANDLEABLE; 735 ctxt->mode = X86EMUL_MODE_VM86; 736 return X86EMUL_CONTINUE; 737 } 738 739 if (!ctxt->ops->get_segment(ctxt, &selector, &cs, &base3, VCPU_SREG_CS)) 740 return X86EMUL_UNHANDLEABLE; 741 742 if (efer & EFER_LMA) { 743 if (cs.l) { 744 /* Proper long mode */ 745 ctxt->mode = X86EMUL_MODE_PROT64; 746 } else if (cs.d) { 747 /* 32 bit compatibility mode*/ 748 ctxt->mode = X86EMUL_MODE_PROT32; 749 } else { 750 ctxt->mode = X86EMUL_MODE_PROT16; 751 } 752 } else { 753 /* Legacy 32 bit / 16 bit mode */ 754 ctxt->mode = cs.d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; 755 } 756 757 return X86EMUL_CONTINUE; 758 } 759 760 static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst) 761 { 762 return assign_eip(ctxt, dst); 763 } 764 765 static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst) 766 { 767 int rc = emulator_recalc_and_set_mode(ctxt); 768 769 if (rc != X86EMUL_CONTINUE) 770 return rc; 771 772 return assign_eip(ctxt, dst); 773 } 774 775 static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel) 776 { 777 return assign_eip_near(ctxt, ctxt->_eip + rel); 778 } 779 780 static int linear_read_system(struct x86_emulate_ctxt *ctxt, ulong linear, 781 void *data, unsigned size) 782 { 783 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception, true); 784 } 785 786 static int linear_write_system(struct x86_emulate_ctxt *ctxt, 787 ulong linear, void *data, 788 unsigned int size) 789 { 790 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception, true); 791 } 792 793 static int segmented_read_std(struct x86_emulate_ctxt *ctxt, 794 struct segmented_address addr, 795 void *data, 796 unsigned size) 797 { 798 int rc; 799 ulong linear; 800 801 rc = linearize(ctxt, addr, size, false, &linear); 802 if (rc != X86EMUL_CONTINUE) 803 return rc; 804 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception, false); 805 } 806 807 static int segmented_write_std(struct x86_emulate_ctxt *ctxt, 808 struct segmented_address addr, 809 void *data, 810 unsigned int size) 811 { 812 int rc; 813 ulong linear; 814 815 rc = linearize(ctxt, addr, size, true, &linear); 816 if (rc != X86EMUL_CONTINUE) 817 return rc; 818 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception, false); 819 } 820 821 /* 822 * Prefetch the remaining bytes of the instruction without crossing page 823 * boundary if they are not in fetch_cache yet. 824 */ 825 static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size) 826 { 827 int rc; 828 unsigned size, max_size; 829 unsigned long linear; 830 int cur_size = ctxt->fetch.end - ctxt->fetch.data; 831 struct segmented_address addr = { .seg = VCPU_SREG_CS, 832 .ea = ctxt->eip + cur_size }; 833 834 /* 835 * We do not know exactly how many bytes will be needed, and 836 * __linearize is expensive, so fetch as much as possible. We 837 * just have to avoid going beyond the 15 byte limit, the end 838 * of the segment, or the end of the page. 839 * 840 * __linearize is called with size 0 so that it does not do any 841 * boundary check itself. Instead, we use max_size to check 842 * against op_size. 843 */ 844 rc = __linearize(ctxt, addr, &max_size, 0, ctxt->mode, &linear, 845 X86EMUL_F_FETCH); 846 if (unlikely(rc != X86EMUL_CONTINUE)) 847 return rc; 848 849 size = min_t(unsigned, 15UL ^ cur_size, max_size); 850 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear)); 851 852 /* 853 * One instruction can only straddle two pages, 854 * and one has been loaded at the beginning of 855 * x86_decode_insn. So, if not enough bytes 856 * still, we must have hit the 15-byte boundary. 857 */ 858 if (unlikely(size < op_size)) 859 return emulate_gp(ctxt, 0); 860 861 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end, 862 size, &ctxt->exception); 863 if (unlikely(rc != X86EMUL_CONTINUE)) 864 return rc; 865 ctxt->fetch.end += size; 866 return X86EMUL_CONTINUE; 867 } 868 869 static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, 870 unsigned size) 871 { 872 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr; 873 874 if (unlikely(done_size < size)) 875 return __do_insn_fetch_bytes(ctxt, size - done_size); 876 else 877 return X86EMUL_CONTINUE; 878 } 879 880 /* Fetch next part of the instruction being emulated. */ 881 #define insn_fetch(_type, _ctxt) \ 882 ({ _type _x; \ 883 \ 884 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \ 885 if (rc != X86EMUL_CONTINUE) \ 886 goto done; \ 887 ctxt->_eip += sizeof(_type); \ 888 memcpy(&_x, ctxt->fetch.ptr, sizeof(_type)); \ 889 ctxt->fetch.ptr += sizeof(_type); \ 890 _x; \ 891 }) 892 893 #define insn_fetch_arr(_arr, _size, _ctxt) \ 894 ({ \ 895 rc = do_insn_fetch_bytes(_ctxt, _size); \ 896 if (rc != X86EMUL_CONTINUE) \ 897 goto done; \ 898 ctxt->_eip += (_size); \ 899 memcpy(_arr, ctxt->fetch.ptr, _size); \ 900 ctxt->fetch.ptr += (_size); \ 901 }) 902 903 /* 904 * Given the 'reg' portion of a ModRM byte, and a register block, return a 905 * pointer into the block that addresses the relevant register. 906 * @highbyte_regs specifies whether to decode AH,CH,DH,BH. 907 */ 908 static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg, 909 int byteop) 910 { 911 void *p; 912 int highbyte_regs = (ctxt->rex_prefix == REX_NONE) && byteop; 913 914 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) 915 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1; 916 else 917 p = reg_rmw(ctxt, modrm_reg); 918 return p; 919 } 920 921 static int read_descriptor(struct x86_emulate_ctxt *ctxt, 922 struct segmented_address addr, 923 u16 *size, unsigned long *address, int op_bytes) 924 { 925 int rc; 926 927 if (op_bytes == 2) 928 op_bytes = 3; 929 *address = 0; 930 rc = segmented_read_std(ctxt, addr, size, 2); 931 if (rc != X86EMUL_CONTINUE) 932 return rc; 933 addr.ea += 2; 934 rc = segmented_read_std(ctxt, addr, address, op_bytes); 935 return rc; 936 } 937 938 EM_ASM_2(add); 939 EM_ASM_2(or); 940 EM_ASM_2(adc); 941 EM_ASM_2(sbb); 942 EM_ASM_2(and); 943 EM_ASM_2(sub); 944 EM_ASM_2(xor); 945 EM_ASM_2(cmp); 946 EM_ASM_2(test); 947 EM_ASM_2(xadd); 948 949 EM_ASM_1SRC2(mul, mul_ex); 950 EM_ASM_1SRC2(imul, imul_ex); 951 EM_ASM_1SRC2EX(div, div_ex); 952 EM_ASM_1SRC2EX(idiv, idiv_ex); 953 954 EM_ASM_3WCL(shld); 955 EM_ASM_3WCL(shrd); 956 957 EM_ASM_2W(imul); 958 959 EM_ASM_1(not); 960 EM_ASM_1(neg); 961 EM_ASM_1(inc); 962 EM_ASM_1(dec); 963 964 EM_ASM_2CL(rol); 965 EM_ASM_2CL(ror); 966 EM_ASM_2CL(rcl); 967 EM_ASM_2CL(rcr); 968 EM_ASM_2CL(shl); 969 EM_ASM_2CL(shr); 970 EM_ASM_2CL(sar); 971 972 EM_ASM_2W(bsf); 973 EM_ASM_2W(bsr); 974 EM_ASM_2W(bt); 975 EM_ASM_2W(bts); 976 EM_ASM_2W(btr); 977 EM_ASM_2W(btc); 978 979 EM_ASM_2R(cmp, cmp_r); 980 981 static int em_bsf_c(struct x86_emulate_ctxt *ctxt) 982 { 983 /* If src is zero, do not writeback, but update flags */ 984 if (ctxt->src.val == 0) 985 ctxt->dst.type = OP_NONE; 986 return em_bsf(ctxt); 987 } 988 989 static int em_bsr_c(struct x86_emulate_ctxt *ctxt) 990 { 991 /* If src is zero, do not writeback, but update flags */ 992 if (ctxt->src.val == 0) 993 ctxt->dst.type = OP_NONE; 994 return em_bsr(ctxt); 995 } 996 997 static __always_inline u8 test_cc(unsigned int condition, unsigned long flags) 998 { 999 return __emulate_cc(flags, condition & 0xf); 1000 } 1001 1002 static void fetch_register_operand(struct operand *op) 1003 { 1004 switch (op->bytes) { 1005 case 1: 1006 op->val = *(u8 *)op->addr.reg; 1007 break; 1008 case 2: 1009 op->val = *(u16 *)op->addr.reg; 1010 break; 1011 case 4: 1012 op->val = *(u32 *)op->addr.reg; 1013 break; 1014 case 8: 1015 op->val = *(u64 *)op->addr.reg; 1016 break; 1017 } 1018 op->orig_val = op->val; 1019 } 1020 1021 static int em_fninit(struct x86_emulate_ctxt *ctxt) 1022 { 1023 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1024 return emulate_nm(ctxt); 1025 1026 kvm_fpu_get(); 1027 asm volatile("fninit"); 1028 kvm_fpu_put(); 1029 return X86EMUL_CONTINUE; 1030 } 1031 1032 static int em_fnstcw(struct x86_emulate_ctxt *ctxt) 1033 { 1034 u16 fcw; 1035 1036 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1037 return emulate_nm(ctxt); 1038 1039 kvm_fpu_get(); 1040 asm volatile("fnstcw %0": "+m"(fcw)); 1041 kvm_fpu_put(); 1042 1043 ctxt->dst.val = fcw; 1044 1045 return X86EMUL_CONTINUE; 1046 } 1047 1048 static int em_fnstsw(struct x86_emulate_ctxt *ctxt) 1049 { 1050 u16 fsw; 1051 1052 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1053 return emulate_nm(ctxt); 1054 1055 kvm_fpu_get(); 1056 asm volatile("fnstsw %0": "+m"(fsw)); 1057 kvm_fpu_put(); 1058 1059 ctxt->dst.val = fsw; 1060 1061 return X86EMUL_CONTINUE; 1062 } 1063 1064 static void __decode_register_operand(struct x86_emulate_ctxt *ctxt, 1065 struct operand *op, int reg) 1066 { 1067 if ((ctxt->d & Avx) && ctxt->op_bytes == 32) { 1068 op->type = OP_YMM; 1069 op->bytes = 32; 1070 op->addr.xmm = reg; 1071 kvm_read_avx_reg(reg, &op->vec_val2); 1072 return; 1073 } 1074 if (ctxt->d & (Avx|Sse)) { 1075 op->type = OP_XMM; 1076 op->bytes = 16; 1077 op->addr.xmm = reg; 1078 kvm_read_sse_reg(reg, &op->vec_val); 1079 return; 1080 } 1081 if (ctxt->d & Mmx) { 1082 reg &= 7; 1083 op->type = OP_MM; 1084 op->bytes = 8; 1085 op->addr.mm = reg; 1086 return; 1087 } 1088 1089 op->type = OP_REG; 1090 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 1091 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp); 1092 fetch_register_operand(op); 1093 } 1094 1095 static void decode_register_operand(struct x86_emulate_ctxt *ctxt, 1096 struct operand *op) 1097 { 1098 unsigned int reg; 1099 1100 if (ctxt->d & ModRM) 1101 reg = ctxt->modrm_reg; 1102 else 1103 reg = (ctxt->b & 7) | (ctxt->rex_bits & REX_B ? 8 : 0); 1104 1105 __decode_register_operand(ctxt, op, reg); 1106 } 1107 1108 static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg) 1109 { 1110 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP) 1111 ctxt->modrm_seg = VCPU_SREG_SS; 1112 } 1113 1114 static int decode_modrm(struct x86_emulate_ctxt *ctxt, 1115 struct operand *op) 1116 { 1117 u8 sib; 1118 int index_reg, base_reg, scale; 1119 int rc = X86EMUL_CONTINUE; 1120 ulong modrm_ea = 0; 1121 1122 ctxt->modrm_reg = (ctxt->rex_bits & REX_R ? 8 : 0); 1123 index_reg = (ctxt->rex_bits & REX_X ? 8 : 0); 1124 base_reg = (ctxt->rex_bits & REX_B ? 8 : 0); 1125 1126 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6; 1127 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3; 1128 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07); 1129 ctxt->modrm_seg = VCPU_SREG_DS; 1130 1131 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) { 1132 __decode_register_operand(ctxt, op, ctxt->modrm_rm); 1133 return rc; 1134 } 1135 1136 op->type = OP_MEM; 1137 1138 if (ctxt->ad_bytes == 2) { 1139 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX); 1140 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP); 1141 unsigned si = reg_read(ctxt, VCPU_REGS_RSI); 1142 unsigned di = reg_read(ctxt, VCPU_REGS_RDI); 1143 1144 /* 16-bit ModR/M decode. */ 1145 switch (ctxt->modrm_mod) { 1146 case 0: 1147 if (ctxt->modrm_rm == 6) 1148 modrm_ea += insn_fetch(u16, ctxt); 1149 break; 1150 case 1: 1151 modrm_ea += insn_fetch(s8, ctxt); 1152 break; 1153 case 2: 1154 modrm_ea += insn_fetch(u16, ctxt); 1155 break; 1156 } 1157 switch (ctxt->modrm_rm) { 1158 case 0: 1159 modrm_ea += bx + si; 1160 break; 1161 case 1: 1162 modrm_ea += bx + di; 1163 break; 1164 case 2: 1165 modrm_ea += bp + si; 1166 break; 1167 case 3: 1168 modrm_ea += bp + di; 1169 break; 1170 case 4: 1171 modrm_ea += si; 1172 break; 1173 case 5: 1174 modrm_ea += di; 1175 break; 1176 case 6: 1177 if (ctxt->modrm_mod != 0) 1178 modrm_ea += bp; 1179 break; 1180 case 7: 1181 modrm_ea += bx; 1182 break; 1183 } 1184 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 || 1185 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0)) 1186 ctxt->modrm_seg = VCPU_SREG_SS; 1187 modrm_ea = (u16)modrm_ea; 1188 } else { 1189 /* 32/64-bit ModR/M decode. */ 1190 if ((ctxt->modrm_rm & 7) == 4) { 1191 sib = insn_fetch(u8, ctxt); 1192 index_reg |= (sib >> 3) & 7; 1193 base_reg |= sib & 7; 1194 scale = sib >> 6; 1195 1196 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0) 1197 modrm_ea += insn_fetch(s32, ctxt); 1198 else { 1199 modrm_ea += reg_read(ctxt, base_reg); 1200 adjust_modrm_seg(ctxt, base_reg); 1201 /* Increment ESP on POP [ESP] */ 1202 if ((ctxt->d & IncSP) && 1203 base_reg == VCPU_REGS_RSP) 1204 modrm_ea += ctxt->op_bytes; 1205 } 1206 if (index_reg != 4) 1207 modrm_ea += reg_read(ctxt, index_reg) << scale; 1208 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) { 1209 modrm_ea += insn_fetch(s32, ctxt); 1210 if (ctxt->mode == X86EMUL_MODE_PROT64) 1211 ctxt->rip_relative = 1; 1212 } else { 1213 base_reg = ctxt->modrm_rm; 1214 modrm_ea += reg_read(ctxt, base_reg); 1215 adjust_modrm_seg(ctxt, base_reg); 1216 } 1217 switch (ctxt->modrm_mod) { 1218 case 1: 1219 modrm_ea += insn_fetch(s8, ctxt); 1220 break; 1221 case 2: 1222 modrm_ea += insn_fetch(s32, ctxt); 1223 break; 1224 } 1225 } 1226 op->addr.mem.ea = modrm_ea; 1227 if (ctxt->ad_bytes != 8) 1228 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea; 1229 1230 done: 1231 return rc; 1232 } 1233 1234 static int decode_abs(struct x86_emulate_ctxt *ctxt, 1235 struct operand *op) 1236 { 1237 int rc = X86EMUL_CONTINUE; 1238 1239 op->type = OP_MEM; 1240 switch (ctxt->ad_bytes) { 1241 case 2: 1242 op->addr.mem.ea = insn_fetch(u16, ctxt); 1243 break; 1244 case 4: 1245 op->addr.mem.ea = insn_fetch(u32, ctxt); 1246 break; 1247 case 8: 1248 op->addr.mem.ea = insn_fetch(u64, ctxt); 1249 break; 1250 } 1251 done: 1252 return rc; 1253 } 1254 1255 static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt) 1256 { 1257 long sv = 0, mask; 1258 1259 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) { 1260 mask = ~((long)ctxt->dst.bytes * 8 - 1); 1261 1262 if (ctxt->src.bytes == 2) 1263 sv = (s16)ctxt->src.val & (s16)mask; 1264 else if (ctxt->src.bytes == 4) 1265 sv = (s32)ctxt->src.val & (s32)mask; 1266 else 1267 sv = (s64)ctxt->src.val & (s64)mask; 1268 1269 ctxt->dst.addr.mem.ea = address_mask(ctxt, 1270 ctxt->dst.addr.mem.ea + (sv >> 3)); 1271 } 1272 1273 /* only subword offset */ 1274 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; 1275 } 1276 1277 static int read_emulated(struct x86_emulate_ctxt *ctxt, 1278 unsigned long addr, void *dest, unsigned size) 1279 { 1280 int rc; 1281 struct read_cache *mc = &ctxt->mem_read; 1282 1283 /* 1284 * If the read gets a cache hit, simply copy the value from the cache. 1285 * A "hit" here means that there is unused data in the cache, i.e. when 1286 * re-emulating an instruction to complete a userspace exit, KVM relies 1287 * on "no decode" to ensure the instruction is re-emulated in the same 1288 * sequence, so that multiple reads are fulfilled in the correct order. 1289 */ 1290 if (mc->pos < mc->end) 1291 goto read_cached; 1292 1293 if (KVM_EMULATOR_BUG_ON((mc->end + size) >= sizeof(mc->data), ctxt)) 1294 return X86EMUL_UNHANDLEABLE; 1295 1296 /* 1297 * Route all reads to the cache. This allows @dest to be an on-stack 1298 * variable without triggering use-after-free if KVM needs to exit to 1299 * userspace to handle an MMIO read (the MMIO fragment will point at 1300 * the current location in the cache). 1301 */ 1302 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size, 1303 &ctxt->exception); 1304 if (rc != X86EMUL_CONTINUE) 1305 return rc; 1306 1307 mc->end += size; 1308 1309 read_cached: 1310 memcpy(dest, mc->data + mc->pos, size); 1311 mc->pos += size; 1312 return X86EMUL_CONTINUE; 1313 } 1314 1315 static int segmented_read(struct x86_emulate_ctxt *ctxt, 1316 struct segmented_address addr, 1317 void *data, 1318 unsigned size) 1319 { 1320 int rc; 1321 ulong linear; 1322 1323 rc = linearize(ctxt, addr, size, false, &linear); 1324 if (rc != X86EMUL_CONTINUE) 1325 return rc; 1326 return read_emulated(ctxt, linear, data, size); 1327 } 1328 1329 static int segmented_write(struct x86_emulate_ctxt *ctxt, 1330 struct segmented_address addr, 1331 const void *data, 1332 unsigned size) 1333 { 1334 int rc; 1335 ulong linear; 1336 1337 rc = linearize(ctxt, addr, size, true, &linear); 1338 if (rc != X86EMUL_CONTINUE) 1339 return rc; 1340 return ctxt->ops->write_emulated(ctxt, linear, data, size, 1341 &ctxt->exception); 1342 } 1343 1344 static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt, 1345 struct segmented_address addr, 1346 const void *orig_data, const void *data, 1347 unsigned size) 1348 { 1349 int rc; 1350 ulong linear; 1351 1352 rc = linearize(ctxt, addr, size, true, &linear); 1353 if (rc != X86EMUL_CONTINUE) 1354 return rc; 1355 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data, 1356 size, &ctxt->exception); 1357 } 1358 1359 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, 1360 unsigned int size, unsigned short port, 1361 void *dest) 1362 { 1363 struct read_cache *rc = &ctxt->io_read; 1364 1365 if (rc->pos == rc->end) { /* refill pio read ahead */ 1366 unsigned int in_page, n; 1367 unsigned int count = ctxt->rep_prefix ? 1368 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1; 1369 in_page = (ctxt->eflags & X86_EFLAGS_DF) ? 1370 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) : 1371 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)); 1372 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count); 1373 if (n == 0) 1374 n = 1; 1375 rc->pos = rc->end = 0; 1376 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n)) 1377 return 0; 1378 rc->end = n * size; 1379 } 1380 1381 if (ctxt->rep_prefix && (ctxt->d & String) && 1382 !(ctxt->eflags & X86_EFLAGS_DF)) { 1383 ctxt->dst.data = rc->data + rc->pos; 1384 ctxt->dst.type = OP_MEM_STR; 1385 ctxt->dst.count = (rc->end - rc->pos) / size; 1386 rc->pos = rc->end; 1387 } else { 1388 memcpy(dest, rc->data + rc->pos, size); 1389 rc->pos += size; 1390 } 1391 return 1; 1392 } 1393 1394 static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt, 1395 u16 index, struct desc_struct *desc) 1396 { 1397 struct desc_ptr dt; 1398 ulong addr; 1399 1400 ctxt->ops->get_idt(ctxt, &dt); 1401 1402 if (dt.size < index * 8 + 7) 1403 return emulate_gp(ctxt, index << 3 | 0x2); 1404 1405 addr = dt.address + index * 8; 1406 return linear_read_system(ctxt, addr, desc, sizeof(*desc)); 1407 } 1408 1409 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, 1410 u16 selector, struct desc_ptr *dt) 1411 { 1412 const struct x86_emulate_ops *ops = ctxt->ops; 1413 u32 base3 = 0; 1414 1415 if (selector & 1 << 2) { 1416 struct desc_struct desc; 1417 u16 sel; 1418 1419 memset(dt, 0, sizeof(*dt)); 1420 if (!ops->get_segment(ctxt, &sel, &desc, &base3, 1421 VCPU_SREG_LDTR)) 1422 return; 1423 1424 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ 1425 dt->address = get_desc_base(&desc) | ((u64)base3 << 32); 1426 } else 1427 ops->get_gdt(ctxt, dt); 1428 } 1429 1430 static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt, 1431 u16 selector, ulong *desc_addr_p) 1432 { 1433 struct desc_ptr dt; 1434 u16 index = selector >> 3; 1435 ulong addr; 1436 1437 get_descriptor_table_ptr(ctxt, selector, &dt); 1438 1439 if (dt.size < index * 8 + 7) 1440 return emulate_gp(ctxt, selector & 0xfffc); 1441 1442 addr = dt.address + index * 8; 1443 1444 #ifdef CONFIG_X86_64 1445 if (addr >> 32 != 0) { 1446 u64 efer = 0; 1447 1448 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 1449 if (!(efer & EFER_LMA)) 1450 addr &= (u32)-1; 1451 } 1452 #endif 1453 1454 *desc_addr_p = addr; 1455 return X86EMUL_CONTINUE; 1456 } 1457 1458 /* allowed just for 8 bytes segments */ 1459 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1460 u16 selector, struct desc_struct *desc, 1461 ulong *desc_addr_p) 1462 { 1463 int rc; 1464 1465 rc = get_descriptor_ptr(ctxt, selector, desc_addr_p); 1466 if (rc != X86EMUL_CONTINUE) 1467 return rc; 1468 1469 return linear_read_system(ctxt, *desc_addr_p, desc, sizeof(*desc)); 1470 } 1471 1472 /* allowed just for 8 bytes segments */ 1473 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1474 u16 selector, struct desc_struct *desc) 1475 { 1476 int rc; 1477 ulong addr; 1478 1479 rc = get_descriptor_ptr(ctxt, selector, &addr); 1480 if (rc != X86EMUL_CONTINUE) 1481 return rc; 1482 1483 return linear_write_system(ctxt, addr, desc, sizeof(*desc)); 1484 } 1485 1486 static bool emulator_is_ssp_invalid(struct x86_emulate_ctxt *ctxt, u8 cpl) 1487 { 1488 const u32 MSR_IA32_X_CET = cpl == 3 ? MSR_IA32_U_CET : MSR_IA32_S_CET; 1489 u64 efer = 0, cet = 0, ssp = 0; 1490 1491 if (!(ctxt->ops->get_cr(ctxt, 4) & X86_CR4_CET)) 1492 return false; 1493 1494 if (ctxt->ops->get_msr(ctxt, MSR_EFER, &efer)) 1495 return true; 1496 1497 /* SSP is guaranteed to be valid if the vCPU was already in 32-bit mode. */ 1498 if (!(efer & EFER_LMA)) 1499 return false; 1500 1501 if (ctxt->ops->get_msr(ctxt, MSR_IA32_X_CET, &cet)) 1502 return true; 1503 1504 if (!(cet & CET_SHSTK_EN)) 1505 return false; 1506 1507 if (ctxt->ops->get_msr(ctxt, MSR_KVM_INTERNAL_GUEST_SSP, &ssp)) 1508 return true; 1509 1510 /* 1511 * On transfer from 64-bit mode to compatibility mode, SSP[63:32] must 1512 * be 0, i.e. SSP must be a 32-bit value outside of 64-bit mode. 1513 */ 1514 return ssp >> 32; 1515 } 1516 1517 static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1518 u16 selector, int seg, u8 cpl, 1519 enum x86_transfer_type transfer, 1520 struct desc_struct *desc) 1521 { 1522 struct desc_struct seg_desc, old_desc; 1523 u8 dpl, rpl; 1524 unsigned err_vec = GP_VECTOR; 1525 u32 err_code = 0; 1526 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ 1527 ulong desc_addr; 1528 int ret; 1529 u16 dummy; 1530 u32 base3 = 0; 1531 1532 memset(&seg_desc, 0, sizeof(seg_desc)); 1533 1534 if (ctxt->mode == X86EMUL_MODE_REAL) { 1535 /* set real mode segment descriptor (keep limit etc. for 1536 * unreal mode) */ 1537 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg); 1538 set_desc_base(&seg_desc, selector << 4); 1539 goto load; 1540 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) { 1541 /* VM86 needs a clean new segment descriptor */ 1542 set_desc_base(&seg_desc, selector << 4); 1543 set_desc_limit(&seg_desc, 0xffff); 1544 seg_desc.type = 3; 1545 seg_desc.p = 1; 1546 seg_desc.s = 1; 1547 seg_desc.dpl = 3; 1548 goto load; 1549 } 1550 1551 rpl = selector & 3; 1552 1553 /* TR should be in GDT only */ 1554 if (seg == VCPU_SREG_TR && (selector & (1 << 2))) 1555 goto exception; 1556 1557 /* NULL selector is not valid for TR, CS and (except for long mode) SS */ 1558 if (null_selector) { 1559 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_TR) 1560 goto exception; 1561 1562 if (seg == VCPU_SREG_SS) { 1563 if (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl) 1564 goto exception; 1565 1566 /* 1567 * ctxt->ops->set_segment expects the CPL to be in 1568 * SS.DPL, so fake an expand-up 32-bit data segment. 1569 */ 1570 seg_desc.type = 3; 1571 seg_desc.p = 1; 1572 seg_desc.s = 1; 1573 seg_desc.dpl = cpl; 1574 seg_desc.d = 1; 1575 seg_desc.g = 1; 1576 } 1577 1578 /* Skip all following checks */ 1579 goto load; 1580 } 1581 1582 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr); 1583 if (ret != X86EMUL_CONTINUE) 1584 return ret; 1585 1586 err_code = selector & 0xfffc; 1587 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR : 1588 GP_VECTOR; 1589 1590 /* can't load system descriptor into segment selector */ 1591 if (seg <= VCPU_SREG_GS && !seg_desc.s) { 1592 if (transfer == X86_TRANSFER_CALL_JMP) 1593 return X86EMUL_UNHANDLEABLE; 1594 goto exception; 1595 } 1596 1597 dpl = seg_desc.dpl; 1598 1599 switch (seg) { 1600 case VCPU_SREG_SS: 1601 /* 1602 * segment is not a writable data segment or segment 1603 * selector's RPL != CPL or DPL != CPL 1604 */ 1605 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) 1606 goto exception; 1607 break; 1608 case VCPU_SREG_CS: 1609 /* 1610 * KVM uses "none" when loading CS as part of emulating Real 1611 * Mode exceptions and IRET (handled above). In all other 1612 * cases, loading CS without a control transfer is a KVM bug. 1613 */ 1614 if (WARN_ON_ONCE(transfer == X86_TRANSFER_NONE)) 1615 goto exception; 1616 1617 if (!(seg_desc.type & 8)) 1618 goto exception; 1619 1620 if (transfer == X86_TRANSFER_RET) { 1621 /* RET can never return to an inner privilege level. */ 1622 if (rpl < cpl) 1623 goto exception; 1624 /* Outer-privilege level return is not implemented */ 1625 if (rpl > cpl) 1626 return X86EMUL_UNHANDLEABLE; 1627 } 1628 if (transfer == X86_TRANSFER_RET || transfer == X86_TRANSFER_TASK_SWITCH) { 1629 if (seg_desc.type & 4) { 1630 /* conforming */ 1631 if (dpl > rpl) 1632 goto exception; 1633 } else { 1634 /* nonconforming */ 1635 if (dpl != rpl) 1636 goto exception; 1637 } 1638 } else { /* X86_TRANSFER_CALL_JMP */ 1639 if (seg_desc.type & 4) { 1640 /* conforming */ 1641 if (dpl > cpl) 1642 goto exception; 1643 } else { 1644 /* nonconforming */ 1645 if (rpl > cpl || dpl != cpl) 1646 goto exception; 1647 } 1648 } 1649 /* in long-mode d/b must be clear if l is set */ 1650 if (seg_desc.d && seg_desc.l) { 1651 u64 efer = 0; 1652 1653 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 1654 if (efer & EFER_LMA) 1655 goto exception; 1656 } 1657 if (!seg_desc.l && emulator_is_ssp_invalid(ctxt, cpl)) { 1658 err_code = 0; 1659 goto exception; 1660 } 1661 1662 /* CS(RPL) <- CPL */ 1663 selector = (selector & 0xfffc) | cpl; 1664 break; 1665 case VCPU_SREG_TR: 1666 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) 1667 goto exception; 1668 break; 1669 case VCPU_SREG_LDTR: 1670 if (seg_desc.s || seg_desc.type != 2) 1671 goto exception; 1672 break; 1673 default: /* DS, ES, FS, or GS */ 1674 /* 1675 * segment is not a data or readable code segment or 1676 * ((segment is a data or nonconforming code segment) 1677 * and ((RPL > DPL) or (CPL > DPL))) 1678 */ 1679 if ((seg_desc.type & 0xa) == 0x8 || 1680 (((seg_desc.type & 0xc) != 0xc) && 1681 (rpl > dpl || cpl > dpl))) 1682 goto exception; 1683 break; 1684 } 1685 1686 if (!seg_desc.p) { 1687 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; 1688 goto exception; 1689 } 1690 1691 if (seg_desc.s) { 1692 /* mark segment as accessed */ 1693 if (!(seg_desc.type & 1)) { 1694 seg_desc.type |= 1; 1695 ret = write_segment_descriptor(ctxt, selector, 1696 &seg_desc); 1697 if (ret != X86EMUL_CONTINUE) 1698 return ret; 1699 } 1700 } else if (ctxt->mode == X86EMUL_MODE_PROT64) { 1701 ret = linear_read_system(ctxt, desc_addr+8, &base3, sizeof(base3)); 1702 if (ret != X86EMUL_CONTINUE) 1703 return ret; 1704 if (emul_is_noncanonical_address(get_desc_base(&seg_desc) | 1705 ((u64)base3 << 32), ctxt, 1706 X86EMUL_F_DT_LOAD)) 1707 return emulate_gp(ctxt, err_code); 1708 } 1709 1710 if (seg == VCPU_SREG_TR) { 1711 old_desc = seg_desc; 1712 seg_desc.type |= 2; /* busy */ 1713 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc, 1714 sizeof(seg_desc), &ctxt->exception); 1715 if (ret != X86EMUL_CONTINUE) 1716 return ret; 1717 } 1718 load: 1719 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg); 1720 if (desc) 1721 *desc = seg_desc; 1722 return X86EMUL_CONTINUE; 1723 exception: 1724 return emulate_exception(ctxt, err_vec, err_code, true); 1725 } 1726 1727 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1728 u16 selector, int seg) 1729 { 1730 u8 cpl = ctxt->ops->cpl(ctxt); 1731 1732 /* 1733 * None of MOV, POP and LSS can load a NULL selector in CPL=3, but 1734 * they can load it at CPL<3 (Intel's manual says only LSS can, 1735 * but it's wrong). 1736 * 1737 * However, the Intel manual says that putting IST=1/DPL=3 in 1738 * an interrupt gate will result in SS=3 (the AMD manual instead 1739 * says it doesn't), so allow SS=3 in __load_segment_descriptor 1740 * and only forbid it here. 1741 */ 1742 if (seg == VCPU_SREG_SS && selector == 3 && 1743 ctxt->mode == X86EMUL_MODE_PROT64) 1744 return emulate_exception(ctxt, GP_VECTOR, 0, true); 1745 1746 return __load_segment_descriptor(ctxt, selector, seg, cpl, 1747 X86_TRANSFER_NONE, NULL); 1748 } 1749 1750 static void write_register_operand(struct operand *op) 1751 { 1752 return insn_assign_reg(op->addr.reg, op->val, op->bytes); 1753 } 1754 1755 static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op) 1756 { 1757 switch (op->type) { 1758 case OP_REG: 1759 write_register_operand(op); 1760 break; 1761 case OP_MEM: 1762 if (ctxt->lock_prefix) 1763 return segmented_cmpxchg(ctxt, 1764 op->addr.mem, 1765 &op->orig_val, 1766 &op->val, 1767 op->bytes); 1768 else 1769 return segmented_write(ctxt, 1770 op->addr.mem, 1771 &op->val, 1772 op->bytes); 1773 case OP_MEM_STR: 1774 return segmented_write(ctxt, 1775 op->addr.mem, 1776 op->data, 1777 op->bytes * op->count); 1778 case OP_XMM: 1779 if (!(ctxt->d & Avx)) { 1780 kvm_write_sse_reg(op->addr.xmm, &op->vec_val); 1781 break; 1782 } 1783 /* full YMM write but with high bytes cleared */ 1784 memset(op->valptr + 16, 0, 16); 1785 fallthrough; 1786 case OP_YMM: 1787 kvm_write_avx_reg(op->addr.xmm, &op->vec_val2); 1788 break; 1789 case OP_MM: 1790 kvm_write_mmx_reg(op->addr.mm, &op->mm_val); 1791 break; 1792 case OP_NONE: 1793 /* no writeback */ 1794 break; 1795 default: 1796 break; 1797 } 1798 return X86EMUL_CONTINUE; 1799 } 1800 1801 static int emulate_push(struct x86_emulate_ctxt *ctxt, const void *data, int len) 1802 { 1803 struct segmented_address addr; 1804 1805 rsp_increment(ctxt, -len); 1806 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); 1807 addr.seg = VCPU_SREG_SS; 1808 1809 return segmented_write(ctxt, addr, data, len); 1810 } 1811 1812 static int em_push(struct x86_emulate_ctxt *ctxt) 1813 { 1814 /* Disable writeback. */ 1815 ctxt->dst.type = OP_NONE; 1816 return emulate_push(ctxt, &ctxt->src.val, ctxt->op_bytes); 1817 } 1818 1819 static int emulate_pop(struct x86_emulate_ctxt *ctxt, 1820 void *dest, int len) 1821 { 1822 int rc; 1823 struct segmented_address addr; 1824 1825 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); 1826 addr.seg = VCPU_SREG_SS; 1827 rc = segmented_read(ctxt, addr, dest, len); 1828 if (rc != X86EMUL_CONTINUE) 1829 return rc; 1830 1831 rsp_increment(ctxt, len); 1832 return rc; 1833 } 1834 1835 static int em_pop(struct x86_emulate_ctxt *ctxt) 1836 { 1837 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1838 } 1839 1840 static int emulate_popf(struct x86_emulate_ctxt *ctxt, 1841 void *dest, int len) 1842 { 1843 int rc; 1844 unsigned long val = 0; 1845 unsigned long change_mask; 1846 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT; 1847 int cpl = ctxt->ops->cpl(ctxt); 1848 1849 rc = emulate_pop(ctxt, &val, len); 1850 if (rc != X86EMUL_CONTINUE) 1851 return rc; 1852 1853 change_mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | 1854 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF | 1855 X86_EFLAGS_TF | X86_EFLAGS_DF | X86_EFLAGS_NT | 1856 X86_EFLAGS_AC | X86_EFLAGS_ID; 1857 1858 switch(ctxt->mode) { 1859 case X86EMUL_MODE_PROT64: 1860 case X86EMUL_MODE_PROT32: 1861 case X86EMUL_MODE_PROT16: 1862 if (cpl == 0) 1863 change_mask |= X86_EFLAGS_IOPL; 1864 if (cpl <= iopl) 1865 change_mask |= X86_EFLAGS_IF; 1866 break; 1867 case X86EMUL_MODE_VM86: 1868 if (iopl < 3) 1869 return emulate_gp(ctxt, 0); 1870 change_mask |= X86_EFLAGS_IF; 1871 break; 1872 default: /* real mode */ 1873 change_mask |= (X86_EFLAGS_IOPL | X86_EFLAGS_IF); 1874 break; 1875 } 1876 1877 *(unsigned long *)dest = 1878 (ctxt->eflags & ~change_mask) | (val & change_mask); 1879 1880 return rc; 1881 } 1882 1883 static int em_popf(struct x86_emulate_ctxt *ctxt) 1884 { 1885 ctxt->dst.type = OP_REG; 1886 ctxt->dst.addr.reg = &ctxt->eflags; 1887 ctxt->dst.bytes = ctxt->op_bytes; 1888 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1889 } 1890 1891 static int em_enter(struct x86_emulate_ctxt *ctxt) 1892 { 1893 int rc; 1894 unsigned frame_size = ctxt->src.val; 1895 unsigned nesting_level = ctxt->src2.val & 31; 1896 ulong rbp; 1897 1898 if (nesting_level) 1899 return X86EMUL_UNHANDLEABLE; 1900 1901 rbp = reg_read(ctxt, VCPU_REGS_RBP); 1902 rc = emulate_push(ctxt, &rbp, stack_size(ctxt)); 1903 if (rc != X86EMUL_CONTINUE) 1904 return rc; 1905 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP), 1906 stack_mask(ctxt)); 1907 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), 1908 reg_read(ctxt, VCPU_REGS_RSP) - frame_size, 1909 stack_mask(ctxt)); 1910 return X86EMUL_CONTINUE; 1911 } 1912 1913 static int em_leave(struct x86_emulate_ctxt *ctxt) 1914 { 1915 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP), 1916 stack_mask(ctxt)); 1917 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes); 1918 } 1919 1920 static int em_push_sreg(struct x86_emulate_ctxt *ctxt) 1921 { 1922 int seg = ctxt->src2.val; 1923 1924 ctxt->src.val = get_segment_selector(ctxt, seg); 1925 if (ctxt->op_bytes == 4) { 1926 rsp_increment(ctxt, -2); 1927 ctxt->op_bytes = 2; 1928 } 1929 1930 return em_push(ctxt); 1931 } 1932 1933 static int em_pop_sreg(struct x86_emulate_ctxt *ctxt) 1934 { 1935 int seg = ctxt->src2.val; 1936 unsigned long selector = 0; 1937 int rc; 1938 1939 rc = emulate_pop(ctxt, &selector, 2); 1940 if (rc != X86EMUL_CONTINUE) 1941 return rc; 1942 1943 if (seg == VCPU_SREG_SS) 1944 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; 1945 if (ctxt->op_bytes > 2) 1946 rsp_increment(ctxt, ctxt->op_bytes - 2); 1947 1948 rc = load_segment_descriptor(ctxt, (u16)selector, seg); 1949 return rc; 1950 } 1951 1952 static int em_pusha(struct x86_emulate_ctxt *ctxt) 1953 { 1954 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP); 1955 int rc = X86EMUL_CONTINUE; 1956 int reg = VCPU_REGS_RAX; 1957 1958 while (reg <= VCPU_REGS_RDI) { 1959 (reg == VCPU_REGS_RSP) ? 1960 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg)); 1961 1962 rc = em_push(ctxt); 1963 if (rc != X86EMUL_CONTINUE) 1964 return rc; 1965 1966 ++reg; 1967 } 1968 1969 return rc; 1970 } 1971 1972 static int em_pushf(struct x86_emulate_ctxt *ctxt) 1973 { 1974 ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM; 1975 return em_push(ctxt); 1976 } 1977 1978 static int em_popa(struct x86_emulate_ctxt *ctxt) 1979 { 1980 int rc = X86EMUL_CONTINUE; 1981 int reg = VCPU_REGS_RDI; 1982 u32 val = 0; 1983 1984 while (reg >= VCPU_REGS_RAX) { 1985 if (reg == VCPU_REGS_RSP) { 1986 rsp_increment(ctxt, ctxt->op_bytes); 1987 --reg; 1988 } 1989 1990 rc = emulate_pop(ctxt, &val, ctxt->op_bytes); 1991 if (rc != X86EMUL_CONTINUE) 1992 break; 1993 insn_assign_reg(reg_rmw(ctxt, reg), val, ctxt->op_bytes); 1994 --reg; 1995 } 1996 return rc; 1997 } 1998 1999 static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) 2000 { 2001 const struct x86_emulate_ops *ops = ctxt->ops; 2002 int rc; 2003 struct desc_ptr dt; 2004 gva_t cs_addr; 2005 gva_t eip_addr; 2006 u16 cs, eip; 2007 2008 /* TODO: Add limit checks */ 2009 ctxt->src.val = ctxt->eflags; 2010 rc = em_push(ctxt); 2011 if (rc != X86EMUL_CONTINUE) 2012 return rc; 2013 2014 ctxt->eflags &= ~(X86_EFLAGS_IF | X86_EFLAGS_TF | X86_EFLAGS_AC); 2015 2016 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS); 2017 rc = em_push(ctxt); 2018 if (rc != X86EMUL_CONTINUE) 2019 return rc; 2020 2021 ctxt->src.val = ctxt->_eip; 2022 rc = em_push(ctxt); 2023 if (rc != X86EMUL_CONTINUE) 2024 return rc; 2025 2026 ops->get_idt(ctxt, &dt); 2027 2028 eip_addr = dt.address + (irq << 2); 2029 cs_addr = dt.address + (irq << 2) + 2; 2030 2031 rc = linear_read_system(ctxt, cs_addr, &cs, 2); 2032 if (rc != X86EMUL_CONTINUE) 2033 return rc; 2034 2035 rc = linear_read_system(ctxt, eip_addr, &eip, 2); 2036 if (rc != X86EMUL_CONTINUE) 2037 return rc; 2038 2039 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS); 2040 if (rc != X86EMUL_CONTINUE) 2041 return rc; 2042 2043 ctxt->_eip = eip; 2044 2045 return rc; 2046 } 2047 2048 int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) 2049 { 2050 int rc; 2051 2052 invalidate_registers(ctxt); 2053 rc = __emulate_int_real(ctxt, irq); 2054 if (rc == X86EMUL_CONTINUE) 2055 writeback_registers(ctxt); 2056 return rc; 2057 } 2058 2059 static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq) 2060 { 2061 switch(ctxt->mode) { 2062 case X86EMUL_MODE_REAL: 2063 return __emulate_int_real(ctxt, irq); 2064 case X86EMUL_MODE_VM86: 2065 case X86EMUL_MODE_PROT16: 2066 case X86EMUL_MODE_PROT32: 2067 case X86EMUL_MODE_PROT64: 2068 default: 2069 /* Protected mode interrupts unimplemented yet */ 2070 return X86EMUL_UNHANDLEABLE; 2071 } 2072 } 2073 2074 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt) 2075 { 2076 int rc = X86EMUL_CONTINUE; 2077 unsigned long temp_eip = 0; 2078 unsigned long temp_eflags = 0; 2079 unsigned long cs = 0; 2080 unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | 2081 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_TF | 2082 X86_EFLAGS_IF | X86_EFLAGS_DF | X86_EFLAGS_OF | 2083 X86_EFLAGS_IOPL | X86_EFLAGS_NT | X86_EFLAGS_RF | 2084 X86_EFLAGS_AC | X86_EFLAGS_ID | 2085 X86_EFLAGS_FIXED; 2086 unsigned long vm86_mask = X86_EFLAGS_VM | X86_EFLAGS_VIF | 2087 X86_EFLAGS_VIP; 2088 2089 /* TODO: Add stack limit check */ 2090 2091 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes); 2092 2093 if (rc != X86EMUL_CONTINUE) 2094 return rc; 2095 2096 if (temp_eip & ~0xffff) 2097 return emulate_gp(ctxt, 0); 2098 2099 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 2100 2101 if (rc != X86EMUL_CONTINUE) 2102 return rc; 2103 2104 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes); 2105 2106 if (rc != X86EMUL_CONTINUE) 2107 return rc; 2108 2109 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); 2110 2111 if (rc != X86EMUL_CONTINUE) 2112 return rc; 2113 2114 ctxt->_eip = temp_eip; 2115 2116 if (ctxt->op_bytes == 4) 2117 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); 2118 else if (ctxt->op_bytes == 2) { 2119 ctxt->eflags &= ~0xffff; 2120 ctxt->eflags |= temp_eflags; 2121 } 2122 2123 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ 2124 ctxt->eflags |= X86_EFLAGS_FIXED; 2125 ctxt->ops->set_nmi_mask(ctxt, false); 2126 2127 return rc; 2128 } 2129 2130 static int em_iret(struct x86_emulate_ctxt *ctxt) 2131 { 2132 switch(ctxt->mode) { 2133 case X86EMUL_MODE_REAL: 2134 return emulate_iret_real(ctxt); 2135 case X86EMUL_MODE_VM86: 2136 case X86EMUL_MODE_PROT16: 2137 case X86EMUL_MODE_PROT32: 2138 case X86EMUL_MODE_PROT64: 2139 default: 2140 /* iret from protected mode unimplemented yet */ 2141 return X86EMUL_UNHANDLEABLE; 2142 } 2143 } 2144 2145 static int em_jmp_far(struct x86_emulate_ctxt *ctxt) 2146 { 2147 int rc; 2148 unsigned short sel; 2149 struct desc_struct new_desc; 2150 u8 cpl = ctxt->ops->cpl(ctxt); 2151 2152 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2153 2154 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, 2155 X86_TRANSFER_CALL_JMP, 2156 &new_desc); 2157 if (rc != X86EMUL_CONTINUE) 2158 return rc; 2159 2160 rc = assign_eip_far(ctxt, ctxt->src.val); 2161 /* Error handling is not implemented. */ 2162 if (rc != X86EMUL_CONTINUE) 2163 return X86EMUL_UNHANDLEABLE; 2164 2165 return rc; 2166 } 2167 2168 static int em_jmp_abs(struct x86_emulate_ctxt *ctxt) 2169 { 2170 return assign_eip_near(ctxt, ctxt->src.val); 2171 } 2172 2173 static int em_call_near_abs(struct x86_emulate_ctxt *ctxt) 2174 { 2175 int rc; 2176 long int old_eip; 2177 2178 old_eip = ctxt->_eip; 2179 rc = assign_eip_near(ctxt, ctxt->src.val); 2180 if (rc != X86EMUL_CONTINUE) 2181 return rc; 2182 ctxt->src.val = old_eip; 2183 rc = em_push(ctxt); 2184 return rc; 2185 } 2186 2187 static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt) 2188 { 2189 u64 old = ctxt->dst.orig_val64; 2190 2191 if (ctxt->dst.bytes == 16) 2192 return X86EMUL_UNHANDLEABLE; 2193 2194 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) || 2195 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) { 2196 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0); 2197 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32); 2198 ctxt->eflags &= ~X86_EFLAGS_ZF; 2199 } else { 2200 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) | 2201 (u32) reg_read(ctxt, VCPU_REGS_RBX); 2202 2203 ctxt->eflags |= X86_EFLAGS_ZF; 2204 } 2205 return X86EMUL_CONTINUE; 2206 } 2207 2208 static int em_ret(struct x86_emulate_ctxt *ctxt) 2209 { 2210 int rc; 2211 unsigned long eip = 0; 2212 2213 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 2214 if (rc != X86EMUL_CONTINUE) 2215 return rc; 2216 2217 return assign_eip_near(ctxt, eip); 2218 } 2219 2220 static int em_ret_far(struct x86_emulate_ctxt *ctxt) 2221 { 2222 int rc; 2223 unsigned long eip = 0; 2224 unsigned long cs = 0; 2225 int cpl = ctxt->ops->cpl(ctxt); 2226 struct desc_struct new_desc; 2227 2228 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 2229 if (rc != X86EMUL_CONTINUE) 2230 return rc; 2231 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 2232 if (rc != X86EMUL_CONTINUE) 2233 return rc; 2234 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl, 2235 X86_TRANSFER_RET, 2236 &new_desc); 2237 if (rc != X86EMUL_CONTINUE) 2238 return rc; 2239 rc = assign_eip_far(ctxt, eip); 2240 /* Error handling is not implemented. */ 2241 if (rc != X86EMUL_CONTINUE) 2242 return X86EMUL_UNHANDLEABLE; 2243 2244 return rc; 2245 } 2246 2247 static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt) 2248 { 2249 int rc; 2250 2251 rc = em_ret_far(ctxt); 2252 if (rc != X86EMUL_CONTINUE) 2253 return rc; 2254 rsp_increment(ctxt, ctxt->src.val); 2255 return X86EMUL_CONTINUE; 2256 } 2257 2258 static int em_cmpxchg(struct x86_emulate_ctxt *ctxt) 2259 { 2260 /* Save real source value, then compare EAX against destination. */ 2261 ctxt->dst.orig_val = ctxt->dst.val; 2262 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX); 2263 ctxt->src.orig_val = ctxt->src.val; 2264 ctxt->src.val = ctxt->dst.orig_val; 2265 em_cmp(ctxt); 2266 2267 if (ctxt->eflags & X86_EFLAGS_ZF) { 2268 /* Success: write back to memory; no update of EAX */ 2269 ctxt->src.type = OP_NONE; 2270 ctxt->dst.val = ctxt->src.orig_val; 2271 } else { 2272 /* Failure: write the value we saw to EAX. */ 2273 ctxt->src.type = OP_REG; 2274 ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 2275 ctxt->src.val = ctxt->dst.orig_val; 2276 /* Create write-cycle to dest by writing the same value */ 2277 ctxt->dst.val = ctxt->dst.orig_val; 2278 } 2279 return X86EMUL_CONTINUE; 2280 } 2281 2282 static int em_lseg(struct x86_emulate_ctxt *ctxt) 2283 { 2284 int seg = ctxt->src2.val; 2285 unsigned short sel; 2286 int rc; 2287 2288 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2289 2290 rc = load_segment_descriptor(ctxt, sel, seg); 2291 if (rc != X86EMUL_CONTINUE) 2292 return rc; 2293 2294 ctxt->dst.val = ctxt->src.val; 2295 return rc; 2296 } 2297 2298 static int em_rsm(struct x86_emulate_ctxt *ctxt) 2299 { 2300 if (!ctxt->ops->is_smm(ctxt)) 2301 return emulate_ud(ctxt); 2302 2303 if (ctxt->ops->leave_smm(ctxt)) 2304 ctxt->ops->triple_fault(ctxt); 2305 2306 return emulator_recalc_and_set_mode(ctxt); 2307 } 2308 2309 static void 2310 setup_syscalls_segments(struct desc_struct *cs, struct desc_struct *ss) 2311 { 2312 cs->l = 0; /* will be adjusted later */ 2313 set_desc_base(cs, 0); /* flat segment */ 2314 cs->g = 1; /* 4kb granularity */ 2315 set_desc_limit(cs, 0xfffff); /* 4GB limit */ 2316 cs->type = 0x0b; /* Read, Execute, Accessed */ 2317 cs->s = 1; 2318 cs->dpl = 0; /* will be adjusted later */ 2319 cs->p = 1; 2320 cs->d = 1; 2321 cs->avl = 0; 2322 2323 set_desc_base(ss, 0); /* flat segment */ 2324 set_desc_limit(ss, 0xfffff); /* 4GB limit */ 2325 ss->g = 1; /* 4kb granularity */ 2326 ss->s = 1; 2327 ss->type = 0x03; /* Read/Write, Accessed */ 2328 ss->d = 1; /* 32bit stack segment */ 2329 ss->dpl = 0; 2330 ss->p = 1; 2331 ss->l = 0; 2332 ss->avl = 0; 2333 } 2334 2335 static int em_syscall(struct x86_emulate_ctxt *ctxt) 2336 { 2337 const struct x86_emulate_ops *ops = ctxt->ops; 2338 struct desc_struct cs, ss; 2339 u64 msr_data; 2340 u16 cs_sel, ss_sel; 2341 u64 efer = 0; 2342 2343 /* syscall is not available in real mode */ 2344 if (ctxt->mode == X86EMUL_MODE_REAL || 2345 ctxt->mode == X86EMUL_MODE_VM86) 2346 return emulate_ud(ctxt); 2347 2348 /* 2349 * Intel compatible CPUs only support SYSCALL in 64-bit mode, whereas 2350 * AMD allows SYSCALL in any flavor of protected mode. Note, it's 2351 * infeasible to emulate Intel behavior when running on AMD hardware, 2352 * as SYSCALL won't fault in the "wrong" mode, i.e. there is no #UD 2353 * for KVM to trap-and-emulate, unlike emulating AMD on Intel. 2354 */ 2355 if (ctxt->mode != X86EMUL_MODE_PROT64 && 2356 ctxt->ops->guest_cpuid_is_intel_compatible(ctxt)) 2357 return emulate_ud(ctxt); 2358 2359 ops->get_msr(ctxt, MSR_EFER, &efer); 2360 if (!(efer & EFER_SCE)) 2361 return emulate_ud(ctxt); 2362 2363 setup_syscalls_segments(&cs, &ss); 2364 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2365 msr_data >>= 32; 2366 cs_sel = (u16)(msr_data & 0xfffc); 2367 ss_sel = (u16)(msr_data + 8); 2368 2369 if (efer & EFER_LMA) { 2370 cs.d = 0; 2371 cs.l = 1; 2372 } 2373 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2374 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2375 2376 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip; 2377 if (efer & EFER_LMA) { 2378 #ifdef CONFIG_X86_64 2379 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags; 2380 2381 ops->get_msr(ctxt, 2382 ctxt->mode == X86EMUL_MODE_PROT64 ? 2383 MSR_LSTAR : MSR_CSTAR, &msr_data); 2384 ctxt->_eip = msr_data; 2385 2386 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data); 2387 ctxt->eflags &= ~msr_data; 2388 ctxt->eflags |= X86_EFLAGS_FIXED; 2389 #endif 2390 } else { 2391 /* legacy mode */ 2392 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2393 ctxt->_eip = (u32)msr_data; 2394 2395 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF); 2396 } 2397 2398 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 2399 return X86EMUL_CONTINUE; 2400 } 2401 2402 static int em_sysenter(struct x86_emulate_ctxt *ctxt) 2403 { 2404 const struct x86_emulate_ops *ops = ctxt->ops; 2405 struct desc_struct cs, ss; 2406 u64 msr_data; 2407 u16 cs_sel, ss_sel; 2408 u64 efer = 0; 2409 2410 ops->get_msr(ctxt, MSR_EFER, &efer); 2411 /* inject #GP if in real mode */ 2412 if (ctxt->mode == X86EMUL_MODE_REAL) 2413 return emulate_gp(ctxt, 0); 2414 2415 /* 2416 * Intel's architecture allows SYSENTER in compatibility mode, but AMD 2417 * does not. Note, AMD does allow SYSENTER in legacy protected mode. 2418 */ 2419 if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA) && 2420 !ctxt->ops->guest_cpuid_is_intel_compatible(ctxt)) 2421 return emulate_ud(ctxt); 2422 2423 /* sysenter/sysexit have not been tested in 64bit mode. */ 2424 if (ctxt->mode == X86EMUL_MODE_PROT64) 2425 return X86EMUL_UNHANDLEABLE; 2426 2427 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2428 if ((msr_data & 0xfffc) == 0x0) 2429 return emulate_gp(ctxt, 0); 2430 2431 setup_syscalls_segments(&cs, &ss); 2432 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF); 2433 cs_sel = (u16)msr_data & ~SEGMENT_RPL_MASK; 2434 ss_sel = cs_sel + 8; 2435 if (efer & EFER_LMA) { 2436 cs.d = 0; 2437 cs.l = 1; 2438 } 2439 2440 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2441 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2442 2443 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data); 2444 ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data; 2445 2446 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data); 2447 *reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data : 2448 (u32)msr_data; 2449 if (efer & EFER_LMA) 2450 ctxt->mode = X86EMUL_MODE_PROT64; 2451 2452 return X86EMUL_CONTINUE; 2453 } 2454 2455 static int em_sysexit(struct x86_emulate_ctxt *ctxt) 2456 { 2457 const struct x86_emulate_ops *ops = ctxt->ops; 2458 struct desc_struct cs, ss; 2459 u64 msr_data, rcx, rdx; 2460 int usermode; 2461 u16 cs_sel = 0, ss_sel = 0; 2462 2463 /* inject #GP if in real mode or Virtual 8086 mode */ 2464 if (ctxt->mode == X86EMUL_MODE_REAL || 2465 ctxt->mode == X86EMUL_MODE_VM86) 2466 return emulate_gp(ctxt, 0); 2467 2468 setup_syscalls_segments(&cs, &ss); 2469 2470 if (ctxt->rex_bits & REX_W) 2471 usermode = X86EMUL_MODE_PROT64; 2472 else 2473 usermode = X86EMUL_MODE_PROT32; 2474 2475 rcx = reg_read(ctxt, VCPU_REGS_RCX); 2476 rdx = reg_read(ctxt, VCPU_REGS_RDX); 2477 2478 cs.dpl = 3; 2479 ss.dpl = 3; 2480 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2481 switch (usermode) { 2482 case X86EMUL_MODE_PROT32: 2483 cs_sel = (u16)(msr_data + 16); 2484 if ((msr_data & 0xfffc) == 0x0) 2485 return emulate_gp(ctxt, 0); 2486 ss_sel = (u16)(msr_data + 24); 2487 rcx = (u32)rcx; 2488 rdx = (u32)rdx; 2489 break; 2490 case X86EMUL_MODE_PROT64: 2491 cs_sel = (u16)(msr_data + 32); 2492 if (msr_data == 0x0) 2493 return emulate_gp(ctxt, 0); 2494 ss_sel = cs_sel + 8; 2495 cs.d = 0; 2496 cs.l = 1; 2497 if (emul_is_noncanonical_address(rcx, ctxt, 0) || 2498 emul_is_noncanonical_address(rdx, ctxt, 0)) 2499 return emulate_gp(ctxt, 0); 2500 break; 2501 } 2502 cs_sel |= SEGMENT_RPL_MASK; 2503 ss_sel |= SEGMENT_RPL_MASK; 2504 2505 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2506 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2507 2508 ctxt->_eip = rdx; 2509 ctxt->mode = usermode; 2510 *reg_write(ctxt, VCPU_REGS_RSP) = rcx; 2511 2512 return X86EMUL_CONTINUE; 2513 } 2514 2515 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt) 2516 { 2517 int iopl; 2518 if (ctxt->mode == X86EMUL_MODE_REAL) 2519 return false; 2520 if (ctxt->mode == X86EMUL_MODE_VM86) 2521 return true; 2522 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT; 2523 return ctxt->ops->cpl(ctxt) > iopl; 2524 } 2525 2526 #define VMWARE_PORT_VMPORT (0x5658) 2527 #define VMWARE_PORT_VMRPC (0x5659) 2528 2529 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, 2530 u16 port, u16 len) 2531 { 2532 const struct x86_emulate_ops *ops = ctxt->ops; 2533 struct desc_struct tr_seg; 2534 u32 base3; 2535 int r; 2536 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7; 2537 unsigned mask = (1 << len) - 1; 2538 unsigned long base; 2539 2540 /* 2541 * VMware allows access to these ports even if denied 2542 * by TSS I/O permission bitmap. Mimic behavior. 2543 */ 2544 if (enable_vmware_backdoor && 2545 ((port == VMWARE_PORT_VMPORT) || (port == VMWARE_PORT_VMRPC))) 2546 return true; 2547 2548 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR); 2549 if (!tr_seg.p) 2550 return false; 2551 if (desc_limit_scaled(&tr_seg) < 103) 2552 return false; 2553 base = get_desc_base(&tr_seg); 2554 #ifdef CONFIG_X86_64 2555 base |= ((u64)base3) << 32; 2556 #endif 2557 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL, true); 2558 if (r != X86EMUL_CONTINUE) 2559 return false; 2560 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) 2561 return false; 2562 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL, true); 2563 if (r != X86EMUL_CONTINUE) 2564 return false; 2565 if ((perm >> bit_idx) & mask) 2566 return false; 2567 return true; 2568 } 2569 2570 static bool emulator_io_permitted(struct x86_emulate_ctxt *ctxt, 2571 u16 port, u16 len) 2572 { 2573 if (ctxt->perm_ok) 2574 return true; 2575 2576 if (emulator_bad_iopl(ctxt)) 2577 if (!emulator_io_port_access_allowed(ctxt, port, len)) 2578 return false; 2579 2580 ctxt->perm_ok = true; 2581 2582 return true; 2583 } 2584 2585 static void string_registers_quirk(struct x86_emulate_ctxt *ctxt) 2586 { 2587 /* 2588 * Intel CPUs mask the counter and pointers in quite strange 2589 * manner when ECX is zero due to REP-string optimizations. 2590 */ 2591 #ifdef CONFIG_X86_64 2592 u32 eax, ebx, ecx, edx; 2593 2594 if (ctxt->ad_bytes != 4) 2595 return; 2596 2597 eax = ecx = 0; 2598 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, true); 2599 if (!is_guest_vendor_intel(ebx, ecx, edx)) 2600 return; 2601 2602 *reg_write(ctxt, VCPU_REGS_RCX) = 0; 2603 2604 switch (ctxt->b) { 2605 case 0xa4: /* movsb */ 2606 case 0xa5: /* movsd/w */ 2607 *reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1; 2608 fallthrough; 2609 case 0xaa: /* stosb */ 2610 case 0xab: /* stosd/w */ 2611 *reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1; 2612 } 2613 #endif 2614 } 2615 2616 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, 2617 struct tss_segment_16 *tss) 2618 { 2619 tss->ip = ctxt->_eip; 2620 tss->flag = ctxt->eflags; 2621 tss->ax = reg_read(ctxt, VCPU_REGS_RAX); 2622 tss->cx = reg_read(ctxt, VCPU_REGS_RCX); 2623 tss->dx = reg_read(ctxt, VCPU_REGS_RDX); 2624 tss->bx = reg_read(ctxt, VCPU_REGS_RBX); 2625 tss->sp = reg_read(ctxt, VCPU_REGS_RSP); 2626 tss->bp = reg_read(ctxt, VCPU_REGS_RBP); 2627 tss->si = reg_read(ctxt, VCPU_REGS_RSI); 2628 tss->di = reg_read(ctxt, VCPU_REGS_RDI); 2629 2630 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 2631 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 2632 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 2633 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 2634 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR); 2635 } 2636 2637 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, 2638 struct tss_segment_16 *tss) 2639 { 2640 int ret; 2641 u8 cpl; 2642 2643 ctxt->_eip = tss->ip; 2644 ctxt->eflags = tss->flag | 2; 2645 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax; 2646 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx; 2647 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx; 2648 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx; 2649 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp; 2650 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp; 2651 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si; 2652 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di; 2653 2654 /* 2655 * SDM says that segment selectors are loaded before segment 2656 * descriptors 2657 */ 2658 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR); 2659 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 2660 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 2661 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 2662 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 2663 2664 cpl = tss->cs & 3; 2665 2666 /* 2667 * Now load segment descriptors. If fault happens at this stage 2668 * it is handled in a context of new task 2669 */ 2670 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, 2671 X86_TRANSFER_TASK_SWITCH, NULL); 2672 if (ret != X86EMUL_CONTINUE) 2673 return ret; 2674 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, 2675 X86_TRANSFER_TASK_SWITCH, NULL); 2676 if (ret != X86EMUL_CONTINUE) 2677 return ret; 2678 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, 2679 X86_TRANSFER_TASK_SWITCH, NULL); 2680 if (ret != X86EMUL_CONTINUE) 2681 return ret; 2682 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, 2683 X86_TRANSFER_TASK_SWITCH, NULL); 2684 if (ret != X86EMUL_CONTINUE) 2685 return ret; 2686 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, 2687 X86_TRANSFER_TASK_SWITCH, NULL); 2688 if (ret != X86EMUL_CONTINUE) 2689 return ret; 2690 2691 return X86EMUL_CONTINUE; 2692 } 2693 2694 static int task_switch_16(struct x86_emulate_ctxt *ctxt, u16 old_tss_sel, 2695 ulong old_tss_base, struct desc_struct *new_desc) 2696 { 2697 struct tss_segment_16 tss_seg; 2698 int ret; 2699 u32 new_tss_base = get_desc_base(new_desc); 2700 2701 ret = linear_read_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg)); 2702 if (ret != X86EMUL_CONTINUE) 2703 return ret; 2704 2705 save_state_to_tss16(ctxt, &tss_seg); 2706 2707 ret = linear_write_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg)); 2708 if (ret != X86EMUL_CONTINUE) 2709 return ret; 2710 2711 ret = linear_read_system(ctxt, new_tss_base, &tss_seg, sizeof(tss_seg)); 2712 if (ret != X86EMUL_CONTINUE) 2713 return ret; 2714 2715 if (old_tss_sel != 0xffff) { 2716 tss_seg.prev_task_link = old_tss_sel; 2717 2718 ret = linear_write_system(ctxt, new_tss_base, 2719 &tss_seg.prev_task_link, 2720 sizeof(tss_seg.prev_task_link)); 2721 if (ret != X86EMUL_CONTINUE) 2722 return ret; 2723 } 2724 2725 return load_state_from_tss16(ctxt, &tss_seg); 2726 } 2727 2728 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, 2729 struct tss_segment_32 *tss) 2730 { 2731 /* CR3 and ldt selector are not saved intentionally */ 2732 tss->eip = ctxt->_eip; 2733 tss->eflags = ctxt->eflags; 2734 tss->eax = reg_read(ctxt, VCPU_REGS_RAX); 2735 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX); 2736 tss->edx = reg_read(ctxt, VCPU_REGS_RDX); 2737 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX); 2738 tss->esp = reg_read(ctxt, VCPU_REGS_RSP); 2739 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP); 2740 tss->esi = reg_read(ctxt, VCPU_REGS_RSI); 2741 tss->edi = reg_read(ctxt, VCPU_REGS_RDI); 2742 2743 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 2744 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 2745 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 2746 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 2747 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS); 2748 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS); 2749 } 2750 2751 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, 2752 struct tss_segment_32 *tss) 2753 { 2754 int ret; 2755 u8 cpl; 2756 2757 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3)) 2758 return emulate_gp(ctxt, 0); 2759 ctxt->_eip = tss->eip; 2760 ctxt->eflags = tss->eflags | 2; 2761 2762 /* General purpose registers */ 2763 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax; 2764 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx; 2765 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx; 2766 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx; 2767 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp; 2768 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp; 2769 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi; 2770 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi; 2771 2772 /* 2773 * SDM says that segment selectors are loaded before segment 2774 * descriptors. This is important because CPL checks will 2775 * use CS.RPL. 2776 */ 2777 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); 2778 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 2779 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 2780 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 2781 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 2782 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS); 2783 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS); 2784 2785 /* 2786 * If we're switching between Protected Mode and VM86, we need to make 2787 * sure to update the mode before loading the segment descriptors so 2788 * that the selectors are interpreted correctly. 2789 */ 2790 if (ctxt->eflags & X86_EFLAGS_VM) { 2791 ctxt->mode = X86EMUL_MODE_VM86; 2792 cpl = 3; 2793 } else { 2794 ctxt->mode = X86EMUL_MODE_PROT32; 2795 cpl = tss->cs & 3; 2796 } 2797 2798 /* 2799 * Now load segment descriptors. If fault happens at this stage 2800 * it is handled in a context of new task 2801 */ 2802 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, 2803 cpl, X86_TRANSFER_TASK_SWITCH, NULL); 2804 if (ret != X86EMUL_CONTINUE) 2805 return ret; 2806 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, 2807 X86_TRANSFER_TASK_SWITCH, NULL); 2808 if (ret != X86EMUL_CONTINUE) 2809 return ret; 2810 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, 2811 X86_TRANSFER_TASK_SWITCH, NULL); 2812 if (ret != X86EMUL_CONTINUE) 2813 return ret; 2814 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, 2815 X86_TRANSFER_TASK_SWITCH, NULL); 2816 if (ret != X86EMUL_CONTINUE) 2817 return ret; 2818 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, 2819 X86_TRANSFER_TASK_SWITCH, NULL); 2820 if (ret != X86EMUL_CONTINUE) 2821 return ret; 2822 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, 2823 X86_TRANSFER_TASK_SWITCH, NULL); 2824 if (ret != X86EMUL_CONTINUE) 2825 return ret; 2826 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, 2827 X86_TRANSFER_TASK_SWITCH, NULL); 2828 2829 return ret; 2830 } 2831 2832 static int task_switch_32(struct x86_emulate_ctxt *ctxt, u16 old_tss_sel, 2833 ulong old_tss_base, struct desc_struct *new_desc) 2834 { 2835 struct tss_segment_32 tss_seg; 2836 int ret; 2837 u32 new_tss_base = get_desc_base(new_desc); 2838 u32 eip_offset = offsetof(struct tss_segment_32, eip); 2839 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector); 2840 2841 ret = linear_read_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg)); 2842 if (ret != X86EMUL_CONTINUE) 2843 return ret; 2844 2845 save_state_to_tss32(ctxt, &tss_seg); 2846 2847 /* Only GP registers and segment selectors are saved */ 2848 ret = linear_write_system(ctxt, old_tss_base + eip_offset, &tss_seg.eip, 2849 ldt_sel_offset - eip_offset); 2850 if (ret != X86EMUL_CONTINUE) 2851 return ret; 2852 2853 ret = linear_read_system(ctxt, new_tss_base, &tss_seg, sizeof(tss_seg)); 2854 if (ret != X86EMUL_CONTINUE) 2855 return ret; 2856 2857 if (old_tss_sel != 0xffff) { 2858 tss_seg.prev_task_link = old_tss_sel; 2859 2860 ret = linear_write_system(ctxt, new_tss_base, 2861 &tss_seg.prev_task_link, 2862 sizeof(tss_seg.prev_task_link)); 2863 if (ret != X86EMUL_CONTINUE) 2864 return ret; 2865 } 2866 2867 return load_state_from_tss32(ctxt, &tss_seg); 2868 } 2869 2870 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, 2871 u16 tss_selector, int idt_index, int reason, 2872 bool has_error_code, u32 error_code) 2873 { 2874 const struct x86_emulate_ops *ops = ctxt->ops; 2875 struct desc_struct curr_tss_desc, next_tss_desc; 2876 int ret; 2877 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR); 2878 ulong old_tss_base = 2879 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR); 2880 u32 desc_limit; 2881 ulong desc_addr, dr7; 2882 2883 /* FIXME: old_tss_base == ~0 ? */ 2884 2885 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr); 2886 if (ret != X86EMUL_CONTINUE) 2887 return ret; 2888 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr); 2889 if (ret != X86EMUL_CONTINUE) 2890 return ret; 2891 2892 /* FIXME: check that next_tss_desc is tss */ 2893 2894 /* 2895 * Check privileges. The three cases are task switch caused by... 2896 * 2897 * 1. jmp/call/int to task gate: Check against DPL of the task gate 2898 * 2. Exception/IRQ/iret: No check is performed 2899 * 3. jmp/call to TSS/task-gate: No check is performed since the 2900 * hardware checks it before exiting. 2901 */ 2902 if (reason == TASK_SWITCH_GATE) { 2903 if (idt_index != -1) { 2904 /* Software interrupts */ 2905 struct desc_struct task_gate_desc; 2906 int dpl; 2907 2908 ret = read_interrupt_descriptor(ctxt, idt_index, 2909 &task_gate_desc); 2910 if (ret != X86EMUL_CONTINUE) 2911 return ret; 2912 2913 dpl = task_gate_desc.dpl; 2914 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) 2915 return emulate_gp(ctxt, (idt_index << 3) | 0x2); 2916 } 2917 } 2918 2919 desc_limit = desc_limit_scaled(&next_tss_desc); 2920 if (!next_tss_desc.p || 2921 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || 2922 desc_limit < 0x2b)) { 2923 return emulate_ts(ctxt, tss_selector & 0xfffc); 2924 } 2925 2926 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { 2927 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ 2928 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); 2929 } 2930 2931 if (reason == TASK_SWITCH_IRET) 2932 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; 2933 2934 /* set back link to prev task only if NT bit is set in eflags 2935 note that old_tss_sel is not used after this point */ 2936 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) 2937 old_tss_sel = 0xffff; 2938 2939 if (next_tss_desc.type & 8) 2940 ret = task_switch_32(ctxt, old_tss_sel, old_tss_base, &next_tss_desc); 2941 else 2942 ret = task_switch_16(ctxt, old_tss_sel, 2943 old_tss_base, &next_tss_desc); 2944 if (ret != X86EMUL_CONTINUE) 2945 return ret; 2946 2947 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) 2948 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; 2949 2950 if (reason != TASK_SWITCH_IRET) { 2951 next_tss_desc.type |= (1 << 1); /* set busy flag */ 2952 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc); 2953 } 2954 2955 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS); 2956 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR); 2957 2958 if (has_error_code) { 2959 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; 2960 ctxt->lock_prefix = 0; 2961 ctxt->src.val = (unsigned long) error_code; 2962 ret = em_push(ctxt); 2963 } 2964 2965 dr7 = ops->get_dr(ctxt, 7); 2966 ops->set_dr(ctxt, 7, dr7 & ~(DR_LOCAL_ENABLE_MASK | DR_LOCAL_SLOWDOWN)); 2967 2968 return ret; 2969 } 2970 2971 int emulator_task_switch(struct x86_emulate_ctxt *ctxt, 2972 u16 tss_selector, int idt_index, int reason, 2973 bool has_error_code, u32 error_code) 2974 { 2975 int rc; 2976 2977 invalidate_registers(ctxt); 2978 ctxt->_eip = ctxt->eip; 2979 ctxt->dst.type = OP_NONE; 2980 2981 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason, 2982 has_error_code, error_code); 2983 2984 if (rc == X86EMUL_CONTINUE) { 2985 ctxt->eip = ctxt->_eip; 2986 writeback_registers(ctxt); 2987 } 2988 2989 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 2990 } 2991 2992 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg, 2993 struct operand *op) 2994 { 2995 int df = (ctxt->eflags & X86_EFLAGS_DF) ? -op->count : op->count; 2996 2997 register_address_increment(ctxt, reg, df * op->bytes); 2998 op->addr.mem.ea = register_address(ctxt, reg); 2999 } 3000 3001 static int em_das(struct x86_emulate_ctxt *ctxt) 3002 { 3003 u8 al, old_al; 3004 bool af, cf, old_cf; 3005 3006 cf = ctxt->eflags & X86_EFLAGS_CF; 3007 al = ctxt->dst.val; 3008 3009 old_al = al; 3010 old_cf = cf; 3011 cf = false; 3012 af = ctxt->eflags & X86_EFLAGS_AF; 3013 if ((al & 0x0f) > 9 || af) { 3014 al -= 6; 3015 cf = old_cf | (al >= 250); 3016 af = true; 3017 } else { 3018 af = false; 3019 } 3020 if (old_al > 0x99 || old_cf) { 3021 al -= 0x60; 3022 cf = true; 3023 } 3024 3025 ctxt->dst.val = al; 3026 /* Set PF, ZF, SF */ 3027 ctxt->src.type = OP_IMM; 3028 ctxt->src.val = 0; 3029 ctxt->src.bytes = 1; 3030 em_or(ctxt); 3031 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); 3032 if (cf) 3033 ctxt->eflags |= X86_EFLAGS_CF; 3034 if (af) 3035 ctxt->eflags |= X86_EFLAGS_AF; 3036 return X86EMUL_CONTINUE; 3037 } 3038 3039 static int em_aam(struct x86_emulate_ctxt *ctxt) 3040 { 3041 u8 al, ah; 3042 3043 if (ctxt->src.val == 0) 3044 return emulate_de(ctxt); 3045 3046 al = ctxt->dst.val & 0xff; 3047 ah = al / ctxt->src.val; 3048 al %= ctxt->src.val; 3049 3050 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8); 3051 3052 /* Set PF, ZF, SF */ 3053 ctxt->src.type = OP_IMM; 3054 ctxt->src.val = 0; 3055 ctxt->src.bytes = 1; 3056 em_or(ctxt); 3057 3058 return X86EMUL_CONTINUE; 3059 } 3060 3061 static int em_aad(struct x86_emulate_ctxt *ctxt) 3062 { 3063 u8 al = ctxt->dst.val & 0xff; 3064 u8 ah = (ctxt->dst.val >> 8) & 0xff; 3065 3066 al = (al + (ah * ctxt->src.val)) & 0xff; 3067 3068 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al; 3069 3070 /* Set PF, ZF, SF */ 3071 ctxt->src.type = OP_IMM; 3072 ctxt->src.val = 0; 3073 ctxt->src.bytes = 1; 3074 em_or(ctxt); 3075 3076 return X86EMUL_CONTINUE; 3077 } 3078 3079 static int em_call(struct x86_emulate_ctxt *ctxt) 3080 { 3081 int rc; 3082 long rel = ctxt->src.val; 3083 3084 ctxt->src.val = (unsigned long)ctxt->_eip; 3085 rc = jmp_rel(ctxt, rel); 3086 if (rc != X86EMUL_CONTINUE) 3087 return rc; 3088 return em_push(ctxt); 3089 } 3090 3091 static int em_call_far(struct x86_emulate_ctxt *ctxt) 3092 { 3093 u16 sel, old_cs; 3094 ulong old_eip; 3095 int rc; 3096 struct desc_struct old_desc, new_desc; 3097 const struct x86_emulate_ops *ops = ctxt->ops; 3098 int cpl = ctxt->ops->cpl(ctxt); 3099 enum x86emul_mode prev_mode = ctxt->mode; 3100 3101 old_eip = ctxt->_eip; 3102 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS); 3103 3104 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 3105 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, 3106 X86_TRANSFER_CALL_JMP, &new_desc); 3107 if (rc != X86EMUL_CONTINUE) 3108 return rc; 3109 3110 rc = assign_eip_far(ctxt, ctxt->src.val); 3111 if (rc != X86EMUL_CONTINUE) 3112 goto fail; 3113 3114 ctxt->src.val = old_cs; 3115 rc = em_push(ctxt); 3116 if (rc != X86EMUL_CONTINUE) 3117 goto fail; 3118 3119 ctxt->src.val = old_eip; 3120 rc = em_push(ctxt); 3121 /* If we failed, we tainted the memory, but the very least we should 3122 restore cs */ 3123 if (rc != X86EMUL_CONTINUE) { 3124 pr_warn_once("faulting far call emulation tainted memory\n"); 3125 goto fail; 3126 } 3127 return rc; 3128 fail: 3129 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS); 3130 ctxt->mode = prev_mode; 3131 return rc; 3132 3133 } 3134 3135 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) 3136 { 3137 int rc; 3138 unsigned long eip = 0; 3139 3140 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 3141 if (rc != X86EMUL_CONTINUE) 3142 return rc; 3143 rc = assign_eip_near(ctxt, eip); 3144 if (rc != X86EMUL_CONTINUE) 3145 return rc; 3146 rsp_increment(ctxt, ctxt->src.val); 3147 return X86EMUL_CONTINUE; 3148 } 3149 3150 static int em_xchg(struct x86_emulate_ctxt *ctxt) 3151 { 3152 /* Write back the register source. */ 3153 ctxt->src.val = ctxt->dst.val; 3154 write_register_operand(&ctxt->src); 3155 3156 /* Write back the memory destination with implicit LOCK prefix. */ 3157 ctxt->dst.val = ctxt->src.orig_val; 3158 ctxt->lock_prefix = 1; 3159 return X86EMUL_CONTINUE; 3160 } 3161 3162 static int em_imul_3op(struct x86_emulate_ctxt *ctxt) 3163 { 3164 ctxt->dst.val = ctxt->src2.val; 3165 return em_imul(ctxt); 3166 } 3167 3168 static int em_cwd(struct x86_emulate_ctxt *ctxt) 3169 { 3170 ctxt->dst.type = OP_REG; 3171 ctxt->dst.bytes = ctxt->src.bytes; 3172 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 3173 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1); 3174 3175 return X86EMUL_CONTINUE; 3176 } 3177 3178 static int em_rdpid(struct x86_emulate_ctxt *ctxt) 3179 { 3180 u64 tsc_aux = 0; 3181 3182 if (!ctxt->ops->guest_has_rdpid(ctxt)) 3183 return emulate_ud(ctxt); 3184 3185 ctxt->ops->get_msr(ctxt, MSR_TSC_AUX, &tsc_aux); 3186 ctxt->dst.val = tsc_aux; 3187 return X86EMUL_CONTINUE; 3188 } 3189 3190 static int em_rdtsc(struct x86_emulate_ctxt *ctxt) 3191 { 3192 u64 tsc = 0; 3193 3194 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc); 3195 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc; 3196 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32; 3197 return X86EMUL_CONTINUE; 3198 } 3199 3200 static int em_rdpmc(struct x86_emulate_ctxt *ctxt) 3201 { 3202 u64 pmc; 3203 3204 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc)) 3205 return emulate_gp(ctxt, 0); 3206 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc; 3207 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32; 3208 return X86EMUL_CONTINUE; 3209 } 3210 3211 static int em_mov(struct x86_emulate_ctxt *ctxt) 3212 { 3213 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr)); 3214 return X86EMUL_CONTINUE; 3215 } 3216 3217 static int em_movbe(struct x86_emulate_ctxt *ctxt) 3218 { 3219 u16 tmp; 3220 3221 if (!ctxt->ops->guest_has_movbe(ctxt)) 3222 return emulate_ud(ctxt); 3223 3224 switch (ctxt->op_bytes) { 3225 case 2: 3226 /* 3227 * From MOVBE definition: "...When the operand size is 16 bits, 3228 * the upper word of the destination register remains unchanged 3229 * ..." 3230 * 3231 * Both casting ->valptr and ->val to u16 breaks strict aliasing 3232 * rules so we have to do the operation almost per hand. 3233 */ 3234 tmp = (u16)ctxt->src.val; 3235 ctxt->dst.val &= ~0xffffUL; 3236 ctxt->dst.val |= (unsigned long)swab16(tmp); 3237 break; 3238 case 4: 3239 ctxt->dst.val = swab32((u32)ctxt->src.val); 3240 break; 3241 case 8: 3242 ctxt->dst.val = swab64(ctxt->src.val); 3243 break; 3244 default: 3245 BUG(); 3246 } 3247 return X86EMUL_CONTINUE; 3248 } 3249 3250 static int em_cr_write(struct x86_emulate_ctxt *ctxt) 3251 { 3252 int cr_num = ctxt->modrm_reg; 3253 int r; 3254 3255 if (ctxt->ops->set_cr(ctxt, cr_num, ctxt->src.val)) 3256 return emulate_gp(ctxt, 0); 3257 3258 /* Disable writeback. */ 3259 ctxt->dst.type = OP_NONE; 3260 3261 if (cr_num == 0) { 3262 /* 3263 * CR0 write might have updated CR0.PE and/or CR0.PG 3264 * which can affect the cpu's execution mode. 3265 */ 3266 r = emulator_recalc_and_set_mode(ctxt); 3267 if (r != X86EMUL_CONTINUE) 3268 return r; 3269 } 3270 3271 return X86EMUL_CONTINUE; 3272 } 3273 3274 static int em_dr_write(struct x86_emulate_ctxt *ctxt) 3275 { 3276 unsigned long val; 3277 3278 if (ctxt->mode == X86EMUL_MODE_PROT64) 3279 val = ctxt->src.val & ~0ULL; 3280 else 3281 val = ctxt->src.val & ~0U; 3282 3283 /* 3284 * A #GP due to an illegal value should be impossible at this point, as 3285 * such #GPs have priority over MOV DR intercepts on SVM, i.e. KVM must 3286 * manually check the value *before* emulating the write. 3287 */ 3288 if (WARN_ON_ONCE(ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val))) 3289 return emulate_gp(ctxt, 0); 3290 3291 /* Disable writeback. */ 3292 ctxt->dst.type = OP_NONE; 3293 return X86EMUL_CONTINUE; 3294 } 3295 3296 static int em_wrmsr(struct x86_emulate_ctxt *ctxt) 3297 { 3298 u64 msr_index = reg_read(ctxt, VCPU_REGS_RCX); 3299 u64 msr_data; 3300 int r; 3301 3302 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX) 3303 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32); 3304 r = ctxt->ops->set_msr_with_filter(ctxt, msr_index, msr_data); 3305 3306 if (r == X86EMUL_PROPAGATE_FAULT) 3307 return emulate_gp(ctxt, 0); 3308 3309 return r; 3310 } 3311 3312 static int em_rdmsr(struct x86_emulate_ctxt *ctxt) 3313 { 3314 u64 msr_index = reg_read(ctxt, VCPU_REGS_RCX); 3315 u64 msr_data; 3316 int r; 3317 3318 r = ctxt->ops->get_msr_with_filter(ctxt, msr_index, &msr_data); 3319 3320 if (r == X86EMUL_PROPAGATE_FAULT) 3321 return emulate_gp(ctxt, 0); 3322 3323 if (r == X86EMUL_CONTINUE) { 3324 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data; 3325 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32; 3326 } 3327 return r; 3328 } 3329 3330 static int em_store_sreg(struct x86_emulate_ctxt *ctxt, int segment) 3331 { 3332 if (segment > VCPU_SREG_GS && 3333 (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) && 3334 ctxt->ops->cpl(ctxt) > 0) 3335 return emulate_gp(ctxt, 0); 3336 3337 ctxt->dst.val = get_segment_selector(ctxt, segment); 3338 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM) 3339 ctxt->dst.bytes = 2; 3340 return X86EMUL_CONTINUE; 3341 } 3342 3343 static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt) 3344 { 3345 if (ctxt->modrm_reg > VCPU_SREG_GS) 3346 return emulate_ud(ctxt); 3347 3348 return em_store_sreg(ctxt, ctxt->modrm_reg); 3349 } 3350 3351 static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt) 3352 { 3353 u16 sel = ctxt->src.val; 3354 3355 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS) 3356 return emulate_ud(ctxt); 3357 3358 if (ctxt->modrm_reg == VCPU_SREG_SS) 3359 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; 3360 3361 /* Disable writeback. */ 3362 ctxt->dst.type = OP_NONE; 3363 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg); 3364 } 3365 3366 static int em_sldt(struct x86_emulate_ctxt *ctxt) 3367 { 3368 return em_store_sreg(ctxt, VCPU_SREG_LDTR); 3369 } 3370 3371 static int em_lldt(struct x86_emulate_ctxt *ctxt) 3372 { 3373 u16 sel = ctxt->src.val; 3374 3375 /* Disable writeback. */ 3376 ctxt->dst.type = OP_NONE; 3377 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR); 3378 } 3379 3380 static int em_str(struct x86_emulate_ctxt *ctxt) 3381 { 3382 return em_store_sreg(ctxt, VCPU_SREG_TR); 3383 } 3384 3385 static int em_ltr(struct x86_emulate_ctxt *ctxt) 3386 { 3387 u16 sel = ctxt->src.val; 3388 3389 /* Disable writeback. */ 3390 ctxt->dst.type = OP_NONE; 3391 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR); 3392 } 3393 3394 static int em_invlpg(struct x86_emulate_ctxt *ctxt) 3395 { 3396 int rc; 3397 ulong linear; 3398 unsigned int max_size; 3399 3400 rc = __linearize(ctxt, ctxt->src.addr.mem, &max_size, 1, ctxt->mode, 3401 &linear, X86EMUL_F_INVLPG); 3402 if (rc == X86EMUL_CONTINUE) 3403 ctxt->ops->invlpg(ctxt, linear); 3404 /* Disable writeback. */ 3405 ctxt->dst.type = OP_NONE; 3406 return X86EMUL_CONTINUE; 3407 } 3408 3409 static int em_clts(struct x86_emulate_ctxt *ctxt) 3410 { 3411 ulong cr0; 3412 3413 cr0 = ctxt->ops->get_cr(ctxt, 0); 3414 cr0 &= ~X86_CR0_TS; 3415 ctxt->ops->set_cr(ctxt, 0, cr0); 3416 return X86EMUL_CONTINUE; 3417 } 3418 3419 static int em_hypercall(struct x86_emulate_ctxt *ctxt) 3420 { 3421 int rc = ctxt->ops->fix_hypercall(ctxt); 3422 3423 if (rc != X86EMUL_CONTINUE) 3424 return rc; 3425 3426 /* Let the processor re-execute the fixed hypercall */ 3427 ctxt->_eip = ctxt->eip; 3428 /* Disable writeback. */ 3429 ctxt->dst.type = OP_NONE; 3430 return X86EMUL_CONTINUE; 3431 } 3432 3433 static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt, 3434 void (*get)(struct x86_emulate_ctxt *ctxt, 3435 struct desc_ptr *ptr)) 3436 { 3437 struct desc_ptr desc_ptr; 3438 3439 if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) && 3440 ctxt->ops->cpl(ctxt) > 0) 3441 return emulate_gp(ctxt, 0); 3442 3443 if (ctxt->mode == X86EMUL_MODE_PROT64) 3444 ctxt->op_bytes = 8; 3445 get(ctxt, &desc_ptr); 3446 if (ctxt->op_bytes == 2) { 3447 ctxt->op_bytes = 4; 3448 desc_ptr.address &= 0x00ffffff; 3449 } 3450 /* Disable writeback. */ 3451 ctxt->dst.type = OP_NONE; 3452 return segmented_write_std(ctxt, ctxt->dst.addr.mem, 3453 &desc_ptr, 2 + ctxt->op_bytes); 3454 } 3455 3456 static int em_sgdt(struct x86_emulate_ctxt *ctxt) 3457 { 3458 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt); 3459 } 3460 3461 static int em_sidt(struct x86_emulate_ctxt *ctxt) 3462 { 3463 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt); 3464 } 3465 3466 static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt) 3467 { 3468 struct desc_ptr desc_ptr; 3469 int rc; 3470 3471 if (ctxt->mode == X86EMUL_MODE_PROT64) 3472 ctxt->op_bytes = 8; 3473 rc = read_descriptor(ctxt, ctxt->src.addr.mem, 3474 &desc_ptr.size, &desc_ptr.address, 3475 ctxt->op_bytes); 3476 if (rc != X86EMUL_CONTINUE) 3477 return rc; 3478 if (ctxt->mode == X86EMUL_MODE_PROT64 && 3479 emul_is_noncanonical_address(desc_ptr.address, ctxt, 3480 X86EMUL_F_DT_LOAD)) 3481 return emulate_gp(ctxt, 0); 3482 if (lgdt) 3483 ctxt->ops->set_gdt(ctxt, &desc_ptr); 3484 else 3485 ctxt->ops->set_idt(ctxt, &desc_ptr); 3486 /* Disable writeback. */ 3487 ctxt->dst.type = OP_NONE; 3488 return X86EMUL_CONTINUE; 3489 } 3490 3491 static int em_lgdt(struct x86_emulate_ctxt *ctxt) 3492 { 3493 return em_lgdt_lidt(ctxt, true); 3494 } 3495 3496 static int em_lidt(struct x86_emulate_ctxt *ctxt) 3497 { 3498 return em_lgdt_lidt(ctxt, false); 3499 } 3500 3501 static int em_smsw(struct x86_emulate_ctxt *ctxt) 3502 { 3503 if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) && 3504 ctxt->ops->cpl(ctxt) > 0) 3505 return emulate_gp(ctxt, 0); 3506 3507 if (ctxt->dst.type == OP_MEM) 3508 ctxt->dst.bytes = 2; 3509 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0); 3510 return X86EMUL_CONTINUE; 3511 } 3512 3513 static int em_lmsw(struct x86_emulate_ctxt *ctxt) 3514 { 3515 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul) 3516 | (ctxt->src.val & 0x0f)); 3517 ctxt->dst.type = OP_NONE; 3518 return X86EMUL_CONTINUE; 3519 } 3520 3521 static int em_loop(struct x86_emulate_ctxt *ctxt) 3522 { 3523 int rc = X86EMUL_CONTINUE; 3524 3525 register_address_increment(ctxt, VCPU_REGS_RCX, -1); 3526 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) && 3527 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags))) 3528 rc = jmp_rel(ctxt, ctxt->src.val); 3529 3530 return rc; 3531 } 3532 3533 static int em_jcxz(struct x86_emulate_ctxt *ctxt) 3534 { 3535 int rc = X86EMUL_CONTINUE; 3536 3537 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) 3538 rc = jmp_rel(ctxt, ctxt->src.val); 3539 3540 return rc; 3541 } 3542 3543 static int em_in(struct x86_emulate_ctxt *ctxt) 3544 { 3545 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val, 3546 &ctxt->dst.val)) 3547 return X86EMUL_IO_NEEDED; 3548 3549 return X86EMUL_CONTINUE; 3550 } 3551 3552 static int em_out(struct x86_emulate_ctxt *ctxt) 3553 { 3554 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val, 3555 &ctxt->src.val, 1); 3556 /* Disable writeback. */ 3557 ctxt->dst.type = OP_NONE; 3558 return X86EMUL_CONTINUE; 3559 } 3560 3561 static int em_cli(struct x86_emulate_ctxt *ctxt) 3562 { 3563 if (emulator_bad_iopl(ctxt)) 3564 return emulate_gp(ctxt, 0); 3565 3566 ctxt->eflags &= ~X86_EFLAGS_IF; 3567 return X86EMUL_CONTINUE; 3568 } 3569 3570 static int em_sti(struct x86_emulate_ctxt *ctxt) 3571 { 3572 if (emulator_bad_iopl(ctxt)) 3573 return emulate_gp(ctxt, 0); 3574 3575 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; 3576 ctxt->eflags |= X86_EFLAGS_IF; 3577 return X86EMUL_CONTINUE; 3578 } 3579 3580 static int em_cpuid(struct x86_emulate_ctxt *ctxt) 3581 { 3582 u32 eax, ebx, ecx, edx; 3583 3584 if (!ctxt->ops->is_cpuid_allowed(ctxt)) 3585 return emulate_gp(ctxt, 0); 3586 3587 eax = reg_read(ctxt, VCPU_REGS_RAX); 3588 ecx = reg_read(ctxt, VCPU_REGS_RCX); 3589 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false); 3590 *reg_write(ctxt, VCPU_REGS_RAX) = eax; 3591 *reg_write(ctxt, VCPU_REGS_RBX) = ebx; 3592 *reg_write(ctxt, VCPU_REGS_RCX) = ecx; 3593 *reg_write(ctxt, VCPU_REGS_RDX) = edx; 3594 return X86EMUL_CONTINUE; 3595 } 3596 3597 static int em_sahf(struct x86_emulate_ctxt *ctxt) 3598 { 3599 u32 flags; 3600 3601 flags = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF | 3602 X86_EFLAGS_SF; 3603 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8; 3604 3605 ctxt->eflags &= ~0xffUL; 3606 ctxt->eflags |= flags | X86_EFLAGS_FIXED; 3607 return X86EMUL_CONTINUE; 3608 } 3609 3610 static int em_lahf(struct x86_emulate_ctxt *ctxt) 3611 { 3612 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL; 3613 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8; 3614 return X86EMUL_CONTINUE; 3615 } 3616 3617 static int em_bswap(struct x86_emulate_ctxt *ctxt) 3618 { 3619 switch (ctxt->op_bytes) { 3620 #ifdef CONFIG_X86_64 3621 case 8: 3622 asm("bswap %0" : "+r"(ctxt->dst.val)); 3623 break; 3624 #endif 3625 default: 3626 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val)); 3627 break; 3628 } 3629 return X86EMUL_CONTINUE; 3630 } 3631 3632 static int em_clflush(struct x86_emulate_ctxt *ctxt) 3633 { 3634 /* emulating clflush regardless of cpuid */ 3635 return X86EMUL_CONTINUE; 3636 } 3637 3638 static int em_clflushopt(struct x86_emulate_ctxt *ctxt) 3639 { 3640 /* emulating clflushopt regardless of cpuid */ 3641 return X86EMUL_CONTINUE; 3642 } 3643 3644 static int em_movsxd(struct x86_emulate_ctxt *ctxt) 3645 { 3646 ctxt->dst.val = (s32) ctxt->src.val; 3647 return X86EMUL_CONTINUE; 3648 } 3649 3650 static int check_fxsr(struct x86_emulate_ctxt *ctxt) 3651 { 3652 if (!ctxt->ops->guest_has_fxsr(ctxt)) 3653 return emulate_ud(ctxt); 3654 3655 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 3656 return emulate_nm(ctxt); 3657 3658 /* 3659 * Don't emulate a case that should never be hit, instead of working 3660 * around a lack of fxsave64/fxrstor64 on old compilers. 3661 */ 3662 if (ctxt->mode >= X86EMUL_MODE_PROT64) 3663 return X86EMUL_UNHANDLEABLE; 3664 3665 return X86EMUL_CONTINUE; 3666 } 3667 3668 /* 3669 * Hardware doesn't save and restore XMM 0-7 without CR4.OSFXSR, but does save 3670 * and restore MXCSR. 3671 */ 3672 static size_t __fxstate_size(int nregs) 3673 { 3674 return offsetof(struct fxregs_state, xmm_space[0]) + nregs * 16; 3675 } 3676 3677 static inline size_t fxstate_size(struct x86_emulate_ctxt *ctxt) 3678 { 3679 bool cr4_osfxsr; 3680 if (ctxt->mode == X86EMUL_MODE_PROT64) 3681 return __fxstate_size(16); 3682 3683 cr4_osfxsr = ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR; 3684 return __fxstate_size(cr4_osfxsr ? 8 : 0); 3685 } 3686 3687 /* 3688 * FXSAVE and FXRSTOR have 4 different formats depending on execution mode, 3689 * 1) 16 bit mode 3690 * 2) 32 bit mode 3691 * - like (1), but FIP and FDP (foo) are only 16 bit. At least Intel CPUs 3692 * preserve whole 32 bit values, though, so (1) and (2) are the same wrt. 3693 * save and restore 3694 * 3) 64-bit mode with REX.W prefix 3695 * - like (2), but XMM 8-15 are being saved and restored 3696 * 4) 64-bit mode without REX.W prefix 3697 * - like (3), but FIP and FDP are 64 bit 3698 * 3699 * Emulation uses (3) for (1) and (2) and preserves XMM 8-15 to reach the 3700 * desired result. (4) is not emulated. 3701 * 3702 * Note: Guest and host CPUID.(EAX=07H,ECX=0H):EBX[bit 13] (deprecate FPU CS 3703 * and FPU DS) should match. 3704 */ 3705 static int em_fxsave(struct x86_emulate_ctxt *ctxt) 3706 { 3707 struct fxregs_state fx_state = {}; 3708 int rc; 3709 3710 rc = check_fxsr(ctxt); 3711 if (rc != X86EMUL_CONTINUE) 3712 return rc; 3713 3714 kvm_fpu_get(); 3715 3716 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_state)); 3717 3718 kvm_fpu_put(); 3719 3720 if (rc != X86EMUL_CONTINUE) 3721 return rc; 3722 3723 return segmented_write_std(ctxt, ctxt->memop.addr.mem, &fx_state, 3724 fxstate_size(ctxt)); 3725 } 3726 3727 /* 3728 * FXRSTOR might restore XMM registers not provided by the guest. Fill 3729 * in the host registers (via FXSAVE) instead, so they won't be modified. 3730 * (preemption has to stay disabled until FXRSTOR). 3731 * 3732 * Use noinline to keep the stack for other functions called by callers small. 3733 */ 3734 static noinline int fxregs_fixup(struct fxregs_state *fx_state, 3735 const size_t used_size) 3736 { 3737 struct fxregs_state fx_tmp = {}; 3738 int rc; 3739 3740 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_tmp)); 3741 memcpy((void *)fx_state + used_size, (void *)&fx_tmp + used_size, 3742 __fxstate_size(16) - used_size); 3743 3744 return rc; 3745 } 3746 3747 static int em_fxrstor(struct x86_emulate_ctxt *ctxt) 3748 { 3749 struct fxregs_state fx_state; 3750 int rc; 3751 size_t size; 3752 3753 rc = check_fxsr(ctxt); 3754 if (rc != X86EMUL_CONTINUE) 3755 return rc; 3756 3757 size = fxstate_size(ctxt); 3758 rc = segmented_read_std(ctxt, ctxt->memop.addr.mem, &fx_state, size); 3759 if (rc != X86EMUL_CONTINUE) 3760 return rc; 3761 3762 kvm_fpu_get(); 3763 3764 if (size < __fxstate_size(16)) { 3765 rc = fxregs_fixup(&fx_state, size); 3766 if (rc != X86EMUL_CONTINUE) 3767 goto out; 3768 } 3769 3770 if (fx_state.mxcsr >> 16) { 3771 rc = emulate_gp(ctxt, 0); 3772 goto out; 3773 } 3774 3775 if (rc == X86EMUL_CONTINUE) 3776 rc = asm_safe("fxrstor %[fx]", : [fx] "m"(fx_state)); 3777 3778 out: 3779 kvm_fpu_put(); 3780 3781 return rc; 3782 } 3783 3784 static int em_xsetbv(struct x86_emulate_ctxt *ctxt) 3785 { 3786 u32 eax, ecx, edx; 3787 3788 if (!(ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSXSAVE)) 3789 return emulate_ud(ctxt); 3790 3791 eax = reg_read(ctxt, VCPU_REGS_RAX); 3792 edx = reg_read(ctxt, VCPU_REGS_RDX); 3793 ecx = reg_read(ctxt, VCPU_REGS_RCX); 3794 3795 if (ctxt->ops->set_xcr(ctxt, ecx, ((u64)edx << 32) | eax)) 3796 return emulate_gp(ctxt, 0); 3797 3798 return X86EMUL_CONTINUE; 3799 } 3800 3801 static bool valid_cr(int nr) 3802 { 3803 switch (nr) { 3804 case 0: 3805 case 2 ... 4: 3806 case 8: 3807 return true; 3808 default: 3809 return false; 3810 } 3811 } 3812 3813 static int check_cr_access(struct x86_emulate_ctxt *ctxt) 3814 { 3815 if (!valid_cr(ctxt->modrm_reg)) 3816 return emulate_ud(ctxt); 3817 3818 return X86EMUL_CONTINUE; 3819 } 3820 3821 static int check_dr_read(struct x86_emulate_ctxt *ctxt) 3822 { 3823 bool is_intel = ctxt->ops->guest_cpuid_is_intel_compatible(ctxt); 3824 int dr = ctxt->modrm_reg; 3825 3826 if (dr > 7) 3827 return emulate_ud(ctxt); 3828 3829 if ((dr == 4 || dr == 5) && (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_DE)) 3830 return emulate_ud(ctxt); 3831 3832 /* Intel CPUs prioritize the DR7.GD=1 #DB over the CPL>0 #GP. */ 3833 if (!is_intel && ctxt->ops->cpl(ctxt)) 3834 return emulate_gp(ctxt, 0); 3835 3836 if (ctxt->ops->get_effective_dr7(ctxt) & DR7_GD) 3837 return emulate_db(ctxt, DR6_BD); 3838 3839 if (is_intel && ctxt->ops->cpl(ctxt)) 3840 return emulate_gp(ctxt, 0); 3841 3842 return X86EMUL_CONTINUE; 3843 } 3844 3845 static int check_dr_write(struct x86_emulate_ctxt *ctxt) 3846 { 3847 u64 new_val = ctxt->src.val64; 3848 int rc; 3849 3850 rc = check_dr_read(ctxt); 3851 if (rc != X86EMUL_CONTINUE) 3852 return rc; 3853 3854 switch (ctxt->modrm_reg) { 3855 case 4: 3856 case 6: 3857 if (!kvm_dr6_valid(new_val)) 3858 return emulate_gp(ctxt, 0); 3859 break; 3860 case 5: 3861 case 7: 3862 if (!kvm_dr7_valid(new_val)) 3863 return emulate_gp(ctxt, 0); 3864 break; 3865 default: 3866 break; 3867 } 3868 3869 return X86EMUL_CONTINUE; 3870 } 3871 3872 static int check_svme(struct x86_emulate_ctxt *ctxt) 3873 { 3874 u64 efer = 0; 3875 3876 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 3877 3878 if (!(efer & EFER_SVME)) 3879 return emulate_ud(ctxt); 3880 3881 return X86EMUL_CONTINUE; 3882 } 3883 3884 static int check_svme_pa(struct x86_emulate_ctxt *ctxt) 3885 { 3886 u64 rax = reg_read(ctxt, VCPU_REGS_RAX); 3887 3888 if (!ctxt->ops->page_address_valid(ctxt, rax)) 3889 return emulate_gp(ctxt, 0); 3890 3891 return check_svme(ctxt); 3892 } 3893 3894 static int check_rdtsc(struct x86_emulate_ctxt *ctxt) 3895 { 3896 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 3897 3898 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt)) 3899 return emulate_gp(ctxt, 0); 3900 3901 return X86EMUL_CONTINUE; 3902 } 3903 3904 static int check_rdpmc(struct x86_emulate_ctxt *ctxt) 3905 { 3906 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 3907 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX); 3908 3909 /* 3910 * VMware allows access to these Pseduo-PMCs even when read via RDPMC 3911 * in Ring3 when CR4.PCE=0. 3912 */ 3913 if (enable_vmware_backdoor && is_vmware_backdoor_pmc(rcx)) 3914 return X86EMUL_CONTINUE; 3915 3916 /* 3917 * If CR4.PCE is set, the SDM requires CPL=0 or CR0.PE=0. The CR0.PE 3918 * check however is unnecessary because CPL is always 0 outside 3919 * protected mode. 3920 */ 3921 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) || 3922 ctxt->ops->check_rdpmc_early(ctxt, rcx)) 3923 return emulate_gp(ctxt, 0); 3924 3925 return X86EMUL_CONTINUE; 3926 } 3927 3928 static int check_perm_in(struct x86_emulate_ctxt *ctxt) 3929 { 3930 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u); 3931 if (!emulator_io_permitted(ctxt, ctxt->src.val, ctxt->dst.bytes)) 3932 return emulate_gp(ctxt, 0); 3933 3934 return X86EMUL_CONTINUE; 3935 } 3936 3937 static int check_perm_out(struct x86_emulate_ctxt *ctxt) 3938 { 3939 ctxt->src.bytes = min(ctxt->src.bytes, 4u); 3940 if (!emulator_io_permitted(ctxt, ctxt->dst.val, ctxt->src.bytes)) 3941 return emulate_gp(ctxt, 0); 3942 3943 return X86EMUL_CONTINUE; 3944 } 3945 3946 #define D(_y) { .flags = (_y) } 3947 #define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i } 3948 #define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \ 3949 .intercept = x86_intercept_##_i, .check_perm = (_p) } 3950 #define N D(NotImpl) 3951 #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) } 3952 #define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) } 3953 #define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) } 3954 #define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) } 3955 #define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) } 3956 #define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) } 3957 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } 3958 #define II(_f, _e, _i) \ 3959 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i } 3960 #define IIP(_f, _e, _i, _p) \ 3961 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \ 3962 .intercept = x86_intercept_##_i, .check_perm = (_p) } 3963 #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) } 3964 3965 #define D2bv(_f) D((_f) | ByteOp), D(_f) 3966 #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p) 3967 #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) 3968 #define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e) 3969 #define I2bvIP(_f, _e, _i, _p) \ 3970 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p) 3971 3972 #define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \ 3973 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \ 3974 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e) 3975 3976 static const struct opcode ud = I(SrcNone, emulate_ud); 3977 3978 static const struct opcode group7_rm0[] = { 3979 N, 3980 I(SrcNone | Priv | EmulateOnUD, em_hypercall), 3981 N, N, N, N, N, N, 3982 }; 3983 3984 static const struct opcode group7_rm1[] = { 3985 DI(SrcNone | Priv, monitor), 3986 DI(SrcNone | Priv, mwait), 3987 N, N, N, N, N, N, 3988 }; 3989 3990 static const struct opcode group7_rm2[] = { 3991 N, 3992 II(ImplicitOps | Priv, em_xsetbv, xsetbv), 3993 N, N, N, N, N, N, 3994 }; 3995 3996 static const struct opcode group7_rm3[] = { 3997 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa), 3998 II(SrcNone | Prot | EmulateOnUD, em_hypercall, vmmcall), 3999 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa), 4000 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa), 4001 DIP(SrcNone | Prot | Priv, stgi, check_svme), 4002 DIP(SrcNone | Prot | Priv, clgi, check_svme), 4003 DIP(SrcNone | Prot | Priv, skinit, check_svme), 4004 DIP(SrcNone | Prot | Priv, invlpga, check_svme), 4005 }; 4006 4007 static const struct opcode group7_rm7[] = { 4008 N, 4009 DIP(SrcNone, rdtscp, check_rdtsc), 4010 N, N, N, N, N, N, 4011 }; 4012 4013 static const struct opcode group1[] = { 4014 I(Lock, em_add), 4015 I(Lock | PageTable, em_or), 4016 I(Lock, em_adc), 4017 I(Lock, em_sbb), 4018 I(Lock | PageTable, em_and), 4019 I(Lock, em_sub), 4020 I(Lock, em_xor), 4021 I(NoWrite, em_cmp), 4022 }; 4023 4024 static const struct opcode group1A[] = { 4025 I(DstMem | SrcNone | Mov | Stack | IncSP | TwoMemOp, em_pop), N, N, N, N, N, N, N, 4026 }; 4027 4028 static const struct opcode group2[] = { 4029 I(DstMem | ModRM, em_rol), 4030 I(DstMem | ModRM, em_ror), 4031 I(DstMem | ModRM, em_rcl), 4032 I(DstMem | ModRM, em_rcr), 4033 I(DstMem | ModRM, em_shl), 4034 I(DstMem | ModRM, em_shr), 4035 I(DstMem | ModRM, em_shl), 4036 I(DstMem | ModRM, em_sar), 4037 }; 4038 4039 static const struct opcode group3[] = { 4040 I(DstMem | SrcImm | NoWrite, em_test), 4041 I(DstMem | SrcImm | NoWrite, em_test), 4042 I(DstMem | SrcNone | Lock, em_not), 4043 I(DstMem | SrcNone | Lock, em_neg), 4044 I(DstXacc | Src2Mem, em_mul_ex), 4045 I(DstXacc | Src2Mem, em_imul_ex), 4046 I(DstXacc | Src2Mem, em_div_ex), 4047 I(DstXacc | Src2Mem, em_idiv_ex), 4048 }; 4049 4050 static const struct opcode group4[] = { 4051 I(ByteOp | DstMem | SrcNone | Lock, em_inc), 4052 I(ByteOp | DstMem | SrcNone | Lock, em_dec), 4053 N, N, N, N, N, N, 4054 }; 4055 4056 static const struct opcode group5[] = { 4057 I(DstMem | SrcNone | Lock, em_inc), 4058 I(DstMem | SrcNone | Lock, em_dec), 4059 I(SrcMem | NearBranch | IsBranch | ShadowStack, em_call_near_abs), 4060 I(SrcMemFAddr | ImplicitOps | IsBranch | ShadowStack, em_call_far), 4061 I(SrcMem | NearBranch | IsBranch, em_jmp_abs), 4062 I(SrcMemFAddr | ImplicitOps | IsBranch, em_jmp_far), 4063 I(SrcMem | Stack | TwoMemOp, em_push), D(Undefined), 4064 }; 4065 4066 static const struct opcode group6[] = { 4067 II(Prot | DstMem, em_sldt, sldt), 4068 II(Prot | DstMem, em_str, str), 4069 II(Prot | Priv | SrcMem16, em_lldt, lldt), 4070 II(Prot | Priv | SrcMem16, em_ltr, ltr), 4071 N, N, N, N, 4072 }; 4073 4074 static const struct group_dual group7 = { { 4075 II(Mov | DstMem, em_sgdt, sgdt), 4076 II(Mov | DstMem, em_sidt, sidt), 4077 II(SrcMem | Priv, em_lgdt, lgdt), 4078 II(SrcMem | Priv, em_lidt, lidt), 4079 II(SrcNone | DstMem | Mov, em_smsw, smsw), N, 4080 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), 4081 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg), 4082 }, { 4083 EXT(0, group7_rm0), 4084 EXT(0, group7_rm1), 4085 EXT(0, group7_rm2), 4086 EXT(0, group7_rm3), 4087 II(SrcNone | DstMem | Mov, em_smsw, smsw), N, 4088 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), 4089 EXT(0, group7_rm7), 4090 } }; 4091 4092 static const struct opcode group8[] = { 4093 N, N, N, N, 4094 I(DstMem | SrcImmByte | NoWrite, em_bt), 4095 I(DstMem | SrcImmByte | Lock | PageTable, em_bts), 4096 I(DstMem | SrcImmByte | Lock, em_btr), 4097 I(DstMem | SrcImmByte | Lock | PageTable, em_btc), 4098 }; 4099 4100 /* 4101 * The "memory" destination is actually always a register, since we come 4102 * from the register case of group9. 4103 */ 4104 static const struct gprefix pfx_0f_c7_7 = { 4105 N, N, N, II(DstMem | ModRM | Op3264 | EmulateOnUD, em_rdpid, rdpid), 4106 }; 4107 4108 4109 static const struct group_dual group9 = { { 4110 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N, 4111 }, { 4112 N, N, N, N, N, N, N, 4113 GP(0, &pfx_0f_c7_7), 4114 } }; 4115 4116 static const struct opcode group11[] = { 4117 I(DstMem | SrcImm | Mov | PageTable, em_mov), 4118 X7(D(Undefined)), 4119 }; 4120 4121 static const struct gprefix pfx_0f_ae_7 = { 4122 I(SrcMem | ByteOp, em_clflush), I(SrcMem | ByteOp, em_clflushopt), N, N, 4123 }; 4124 4125 static const struct group_dual group15 = { { 4126 I(ModRM | Aligned16, em_fxsave), 4127 I(ModRM | Aligned16, em_fxrstor), 4128 N, N, N, N, N, GP(0, &pfx_0f_ae_7), 4129 }, { 4130 N, N, N, N, N, N, N, N, 4131 } }; 4132 4133 static const struct gprefix pfx_0f_6f_0f_7f = { 4134 I(Mmx, em_mov), I(Sse | Avx | Aligned, em_mov), N, I(Sse | Avx | Unaligned, em_mov), 4135 }; 4136 4137 static const struct instr_dual instr_dual_0f_2b = { 4138 I(0, em_mov), N 4139 }; 4140 4141 static const struct gprefix pfx_0f_2b = { 4142 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N, 4143 }; 4144 4145 static const struct gprefix pfx_0f_10_0f_11 = { 4146 I(Unaligned, em_mov), I(Unaligned, em_mov), N, N, 4147 }; 4148 4149 static const struct gprefix pfx_0f_28_0f_29 = { 4150 I(Aligned, em_mov), I(Aligned, em_mov), N, N, 4151 }; 4152 4153 static const struct gprefix pfx_0f_e7_0f_38_2a = { 4154 N, I(Sse | Avx, em_mov), N, N, 4155 }; 4156 4157 static const struct escape escape_d9 = { { 4158 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw), 4159 }, { 4160 /* 0xC0 - 0xC7 */ 4161 N, N, N, N, N, N, N, N, 4162 /* 0xC8 - 0xCF */ 4163 N, N, N, N, N, N, N, N, 4164 /* 0xD0 - 0xC7 */ 4165 N, N, N, N, N, N, N, N, 4166 /* 0xD8 - 0xDF */ 4167 N, N, N, N, N, N, N, N, 4168 /* 0xE0 - 0xE7 */ 4169 N, N, N, N, N, N, N, N, 4170 /* 0xE8 - 0xEF */ 4171 N, N, N, N, N, N, N, N, 4172 /* 0xF0 - 0xF7 */ 4173 N, N, N, N, N, N, N, N, 4174 /* 0xF8 - 0xFF */ 4175 N, N, N, N, N, N, N, N, 4176 } }; 4177 4178 static const struct escape escape_db = { { 4179 N, N, N, N, N, N, N, N, 4180 }, { 4181 /* 0xC0 - 0xC7 */ 4182 N, N, N, N, N, N, N, N, 4183 /* 0xC8 - 0xCF */ 4184 N, N, N, N, N, N, N, N, 4185 /* 0xD0 - 0xC7 */ 4186 N, N, N, N, N, N, N, N, 4187 /* 0xD8 - 0xDF */ 4188 N, N, N, N, N, N, N, N, 4189 /* 0xE0 - 0xE7 */ 4190 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N, 4191 /* 0xE8 - 0xEF */ 4192 N, N, N, N, N, N, N, N, 4193 /* 0xF0 - 0xF7 */ 4194 N, N, N, N, N, N, N, N, 4195 /* 0xF8 - 0xFF */ 4196 N, N, N, N, N, N, N, N, 4197 } }; 4198 4199 static const struct escape escape_dd = { { 4200 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw), 4201 }, { 4202 /* 0xC0 - 0xC7 */ 4203 N, N, N, N, N, N, N, N, 4204 /* 0xC8 - 0xCF */ 4205 N, N, N, N, N, N, N, N, 4206 /* 0xD0 - 0xC7 */ 4207 N, N, N, N, N, N, N, N, 4208 /* 0xD8 - 0xDF */ 4209 N, N, N, N, N, N, N, N, 4210 /* 0xE0 - 0xE7 */ 4211 N, N, N, N, N, N, N, N, 4212 /* 0xE8 - 0xEF */ 4213 N, N, N, N, N, N, N, N, 4214 /* 0xF0 - 0xF7 */ 4215 N, N, N, N, N, N, N, N, 4216 /* 0xF8 - 0xFF */ 4217 N, N, N, N, N, N, N, N, 4218 } }; 4219 4220 static const struct instr_dual instr_dual_0f_c3 = { 4221 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N 4222 }; 4223 4224 static const struct mode_dual mode_dual_63 = { 4225 N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd) 4226 }; 4227 4228 static const struct instr_dual instr_dual_8d = { 4229 D(DstReg | SrcMem | ModRM | NoAccess), N 4230 }; 4231 4232 static const struct opcode opcode_table[256] = { 4233 /* 0x00 - 0x07 */ 4234 I6ALU(Lock, em_add), 4235 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg), 4236 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg), 4237 /* 0x08 - 0x0F */ 4238 I6ALU(Lock | PageTable, em_or), 4239 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg), 4240 N, 4241 /* 0x10 - 0x17 */ 4242 I6ALU(Lock, em_adc), 4243 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg), 4244 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg), 4245 /* 0x18 - 0x1F */ 4246 I6ALU(Lock, em_sbb), 4247 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg), 4248 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg), 4249 /* 0x20 - 0x27 */ 4250 I6ALU(Lock | PageTable, em_and), N, N, 4251 /* 0x28 - 0x2F */ 4252 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das), 4253 /* 0x30 - 0x37 */ 4254 I6ALU(Lock, em_xor), N, N, 4255 /* 0x38 - 0x3F */ 4256 I6ALU(NoWrite, em_cmp), N, N, 4257 /* 0x40 - 0x4F */ 4258 X8(I(DstReg, em_inc)), X8(I(DstReg, em_dec)), 4259 /* 0x50 - 0x57 */ 4260 X8(I(SrcReg | Stack, em_push)), 4261 /* 0x58 - 0x5F */ 4262 X8(I(DstReg | Stack, em_pop)), 4263 /* 0x60 - 0x67 */ 4264 I(ImplicitOps | Stack | No64, em_pusha), 4265 I(ImplicitOps | Stack | No64, em_popa), 4266 N, MD(ModRM, &mode_dual_63), 4267 N, N, N, N, 4268 /* 0x68 - 0x6F */ 4269 I(SrcImm | Mov | Stack, em_push), 4270 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), 4271 I(SrcImmByte | Mov | Stack, em_push), 4272 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), 4273 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */ 4274 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */ 4275 /* 0x70 - 0x7F */ 4276 X16(D(SrcImmByte | NearBranch | IsBranch)), 4277 /* 0x80 - 0x87 */ 4278 G(ByteOp | DstMem | SrcImm, group1), 4279 G(DstMem | SrcImm, group1), 4280 G(ByteOp | DstMem | SrcImm | No64, group1), 4281 G(DstMem | SrcImmByte, group1), 4282 I2bv(DstMem | SrcReg | ModRM | NoWrite, em_test), 4283 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg), 4284 /* 0x88 - 0x8F */ 4285 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov), 4286 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov), 4287 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg), 4288 ID(0, &instr_dual_8d), 4289 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm), 4290 G(0, group1A), 4291 /* 0x90 - 0x97 */ 4292 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)), 4293 /* 0x98 - 0x9F */ 4294 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), 4295 I(SrcImmFAddr | No64 | IsBranch | ShadowStack, em_call_far), N, 4296 II(ImplicitOps | Stack, em_pushf, pushf), 4297 II(ImplicitOps | Stack, em_popf, popf), 4298 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf), 4299 /* 0xA0 - 0xA7 */ 4300 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), 4301 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov), 4302 I2bv(SrcSI | DstDI | Mov | String | TwoMemOp, em_mov), 4303 I2bv(SrcSI | DstDI | String | NoWrite | TwoMemOp, em_cmp_r), 4304 /* 0xA8 - 0xAF */ 4305 I2bv(DstAcc | SrcImm | NoWrite, em_test), 4306 I2bv(SrcAcc | DstDI | Mov | String, em_mov), 4307 I2bv(SrcSI | DstAcc | Mov | String, em_mov), 4308 I2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r), 4309 /* 0xB0 - 0xB7 */ 4310 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), 4311 /* 0xB8 - 0xBF */ 4312 X8(I(DstReg | SrcImm64 | Mov, em_mov)), 4313 /* 0xC0 - 0xC7 */ 4314 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2), 4315 I(ImplicitOps | NearBranch | SrcImmU16 | IsBranch | ShadowStack, em_ret_near_imm), 4316 I(ImplicitOps | NearBranch | IsBranch | ShadowStack, em_ret), 4317 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg), 4318 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg), 4319 G(ByteOp, group11), G(0, group11), 4320 /* 0xC8 - 0xCF */ 4321 I(Stack | SrcImmU16 | Src2ImmByte, em_enter), 4322 I(Stack, em_leave), 4323 I(ImplicitOps | SrcImmU16 | IsBranch | ShadowStack, em_ret_far_imm), 4324 I(ImplicitOps | IsBranch | ShadowStack, em_ret_far), 4325 D(ImplicitOps | IsBranch), DI(SrcImmByte | IsBranch | ShadowStack, intn), 4326 D(ImplicitOps | No64 | IsBranch), 4327 II(ImplicitOps | IsBranch | ShadowStack, em_iret, iret), 4328 /* 0xD0 - 0xD7 */ 4329 G(Src2One | ByteOp, group2), G(Src2One, group2), 4330 G(Src2CL | ByteOp, group2), G(Src2CL, group2), 4331 I(DstAcc | SrcImmUByte | No64, em_aam), 4332 I(DstAcc | SrcImmUByte | No64, em_aad), 4333 I(DstAcc | ByteOp | No64, em_salc), 4334 I(DstAcc | SrcXLat | ByteOp, em_mov), 4335 /* 0xD8 - 0xDF */ 4336 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N, 4337 /* 0xE0 - 0xE7 */ 4338 X3(I(SrcImmByte | NearBranch | IsBranch, em_loop)), 4339 I(SrcImmByte | NearBranch | IsBranch, em_jcxz), 4340 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in), 4341 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out), 4342 /* 0xE8 - 0xEF */ 4343 I(SrcImm | NearBranch | IsBranch | ShadowStack, em_call), 4344 D(SrcImm | ImplicitOps | NearBranch | IsBranch), 4345 I(SrcImmFAddr | No64 | IsBranch, em_jmp_far), 4346 D(SrcImmByte | ImplicitOps | NearBranch | IsBranch), 4347 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in), 4348 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out), 4349 /* 0xF0 - 0xF7 */ 4350 N, DI(ImplicitOps, icebp), N, N, 4351 DI(ImplicitOps | Priv, hlt), D(ImplicitOps), 4352 G(ByteOp, group3), G(0, group3), 4353 /* 0xF8 - 0xFF */ 4354 D(ImplicitOps), D(ImplicitOps), 4355 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti), 4356 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), 4357 }; 4358 4359 static const struct opcode twobyte_table[256] = { 4360 /* 0x00 - 0x0F */ 4361 G(0, group6), GD(0, &group7), N, N, 4362 N, I(ImplicitOps | EmulateOnUD | IsBranch | ShadowStack, em_syscall), 4363 II(ImplicitOps | Priv, em_clts, clts), N, 4364 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, 4365 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N, 4366 /* 0x10 - 0x1F */ 4367 GP(ModRM | DstReg | SrcMem | Mov | Sse | Avx, &pfx_0f_10_0f_11), 4368 GP(ModRM | DstMem | SrcReg | Mov | Sse | Avx, &pfx_0f_10_0f_11), 4369 N, N, N, N, N, N, 4370 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 4 * prefetch + 4 * reserved NOP */ 4371 D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N, 4372 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */ 4373 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */ 4374 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */ 4375 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* NOP + 7 * reserved NOP */ 4376 /* 0x20 - 0x2F */ 4377 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_access), 4378 DIP(ModRM | DstMem | Op3264 | NoMod, dr_read, check_dr_read), 4379 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write, 4380 check_cr_access), 4381 IIP(ModRM | SrcMem | Op3264 | NoMod, em_dr_write, dr_write, check_dr_write), 4382 N, N, N, N, 4383 GP(ModRM | DstReg | SrcMem | Mov | Sse | Avx, &pfx_0f_28_0f_29), 4384 GP(ModRM | DstMem | SrcReg | Mov | Sse | Avx, &pfx_0f_28_0f_29), 4385 N, GP(ModRM | DstMem | SrcReg | Mov | Sse | Avx, &pfx_0f_2b), 4386 N, N, N, N, 4387 /* 0x30 - 0x3F */ 4388 II(ImplicitOps | Priv, em_wrmsr, wrmsr), 4389 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc), 4390 II(ImplicitOps | Priv, em_rdmsr, rdmsr), 4391 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc), 4392 I(ImplicitOps | EmulateOnUD | IsBranch | ShadowStack, em_sysenter), 4393 I(ImplicitOps | Priv | EmulateOnUD | IsBranch | ShadowStack, em_sysexit), 4394 N, N, 4395 N, N, N, N, N, N, N, N, 4396 /* 0x40 - 0x4F */ 4397 X16(D(DstReg | SrcMem | ModRM)), 4398 /* 0x50 - 0x5F */ 4399 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 4400 /* 0x60 - 0x6F */ 4401 N, N, N, N, 4402 N, N, N, N, 4403 N, N, N, N, 4404 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f), 4405 /* 0x70 - 0x7F */ 4406 N, N, N, N, 4407 N, N, N, N, 4408 N, N, N, N, 4409 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f), 4410 /* 0x80 - 0x8F */ 4411 X16(D(SrcImm | NearBranch | IsBranch)), 4412 /* 0x90 - 0x9F */ 4413 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), 4414 /* 0xA0 - 0xA7 */ 4415 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg), 4416 II(ImplicitOps, em_cpuid, cpuid), 4417 I(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt), 4418 I(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld), 4419 I(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N, 4420 /* 0xA8 - 0xAF */ 4421 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg), 4422 II(EmulateOnUD | ImplicitOps, em_rsm, rsm), 4423 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts), 4424 I(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd), 4425 I(DstMem | SrcReg | Src2CL | ModRM, em_shrd), 4426 GD(0, &group15), I(DstReg | SrcMem | ModRM, em_imul), 4427 /* 0xB0 - 0xB7 */ 4428 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg), 4429 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg), 4430 I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr), 4431 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg), 4432 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg), 4433 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 4434 /* 0xB8 - 0xBF */ 4435 N, N, 4436 G(BitOp, group8), 4437 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc), 4438 I(DstReg | SrcMem | ModRM, em_bsf_c), 4439 I(DstReg | SrcMem | ModRM, em_bsr_c), 4440 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 4441 /* 0xC0 - 0xC7 */ 4442 I2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd), 4443 N, ID(0, &instr_dual_0f_c3), 4444 N, N, N, GD(0, &group9), 4445 /* 0xC8 - 0xCF */ 4446 X8(I(DstReg, em_bswap)), 4447 /* 0xD0 - 0xDF */ 4448 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 4449 /* 0xE0 - 0xEF */ 4450 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7_0f_38_2a), 4451 N, N, N, N, N, N, N, N, 4452 /* 0xF0 - 0xFF */ 4453 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N 4454 }; 4455 4456 static const struct instr_dual instr_dual_0f_38_f0 = { 4457 I(DstReg | SrcMem | Mov, em_movbe), N 4458 }; 4459 4460 static const struct instr_dual instr_dual_0f_38_f1 = { 4461 I(DstMem | SrcReg | Mov, em_movbe), N 4462 }; 4463 4464 static const struct gprefix three_byte_0f_38_f0 = { 4465 ID(0, &instr_dual_0f_38_f0), ID(0, &instr_dual_0f_38_f0), N, N 4466 }; 4467 4468 static const struct gprefix three_byte_0f_38_f1 = { 4469 ID(0, &instr_dual_0f_38_f1), ID(0, &instr_dual_0f_38_f1), N, N 4470 }; 4471 4472 /* 4473 * Insns below are selected by the prefix which indexed by the third opcode 4474 * byte. 4475 */ 4476 static const struct opcode opcode_map_0f_38[256] = { 4477 /* 0x00 - 0x1f */ 4478 X16(N), X16(N), 4479 /* 0x20 - 0x2f */ 4480 X8(N), 4481 X2(N), GP(SrcMem | DstReg | ModRM | Mov | Aligned, &pfx_0f_e7_0f_38_2a), N, N, N, N, N, 4482 /* 0x30 - 0x7f */ 4483 X16(N), X16(N), X16(N), X16(N), X16(N), 4484 /* 0x80 - 0xef */ 4485 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), 4486 /* 0xf0 - 0xf1 */ 4487 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0), 4488 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1), 4489 /* 0xf2 - 0xff */ 4490 N, N, X4(N), X8(N) 4491 }; 4492 4493 #undef D 4494 #undef N 4495 #undef G 4496 #undef GD 4497 #undef I 4498 #undef GP 4499 #undef EXT 4500 #undef MD 4501 #undef ID 4502 4503 #undef D2bv 4504 #undef D2bvIP 4505 #undef I2bv 4506 #undef I2bvIP 4507 #undef I6ALU 4508 4509 static bool is_shstk_instruction(struct x86_emulate_ctxt *ctxt) 4510 { 4511 return ctxt->d & ShadowStack; 4512 } 4513 4514 static bool is_ibt_instruction(struct x86_emulate_ctxt *ctxt) 4515 { 4516 u64 flags = ctxt->d; 4517 4518 if (!(flags & IsBranch)) 4519 return false; 4520 4521 /* 4522 * All far JMPs and CALLs (including SYSCALL, SYSENTER, and INTn) are 4523 * indirect and thus affect IBT state. All far RETs (including SYSEXIT 4524 * and IRET) are protected via Shadow Stacks and thus don't affect IBT 4525 * state. IRET #GPs when returning to virtual-8086 and IBT or SHSTK is 4526 * enabled, but that should be handled by IRET emulation (in the very 4527 * unlikely scenario that KVM adds support for fully emulating IRET). 4528 */ 4529 if (!(flags & NearBranch)) 4530 return ctxt->execute != em_iret && 4531 ctxt->execute != em_ret_far && 4532 ctxt->execute != em_ret_far_imm && 4533 ctxt->execute != em_sysexit; 4534 4535 switch (flags & SrcMask) { 4536 case SrcReg: 4537 case SrcMem: 4538 case SrcMem16: 4539 case SrcMem32: 4540 return true; 4541 case SrcMemFAddr: 4542 case SrcImmFAddr: 4543 /* Far branches should be handled above. */ 4544 WARN_ON_ONCE(1); 4545 return true; 4546 case SrcNone: 4547 case SrcImm: 4548 case SrcImmByte: 4549 /* 4550 * Note, ImmU16 is used only for the stack adjustment operand on ENTER 4551 * and RET instructions. ENTER isn't a branch and RET FAR is handled 4552 * by the NearBranch check above. RET itself isn't an indirect branch. 4553 */ 4554 case SrcImmU16: 4555 return false; 4556 default: 4557 WARN_ONCE(1, "Unexpected Src operand '%llx' on branch", 4558 flags & SrcMask); 4559 return false; 4560 } 4561 } 4562 4563 static unsigned imm_size(struct x86_emulate_ctxt *ctxt) 4564 { 4565 unsigned size; 4566 4567 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4568 if (size == 8) 4569 size = 4; 4570 return size; 4571 } 4572 4573 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, 4574 unsigned size, bool sign_extension) 4575 { 4576 int rc = X86EMUL_CONTINUE; 4577 4578 op->type = OP_IMM; 4579 op->bytes = size; 4580 op->addr.mem.ea = ctxt->_eip; 4581 /* NB. Immediates are sign-extended as necessary. */ 4582 switch (op->bytes) { 4583 case 1: 4584 op->val = insn_fetch(s8, ctxt); 4585 break; 4586 case 2: 4587 op->val = insn_fetch(s16, ctxt); 4588 break; 4589 case 4: 4590 op->val = insn_fetch(s32, ctxt); 4591 break; 4592 case 8: 4593 op->val = insn_fetch(s64, ctxt); 4594 break; 4595 } 4596 if (!sign_extension) { 4597 switch (op->bytes) { 4598 case 1: 4599 op->val &= 0xff; 4600 break; 4601 case 2: 4602 op->val &= 0xffff; 4603 break; 4604 case 4: 4605 op->val &= 0xffffffff; 4606 break; 4607 } 4608 } 4609 done: 4610 return rc; 4611 } 4612 4613 static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op, 4614 unsigned d) 4615 { 4616 int rc = X86EMUL_CONTINUE; 4617 4618 switch (d) { 4619 case OpReg: 4620 decode_register_operand(ctxt, op); 4621 break; 4622 case OpImmUByte: 4623 rc = decode_imm(ctxt, op, 1, false); 4624 break; 4625 case OpMem: 4626 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4627 mem_common: 4628 *op = ctxt->memop; 4629 ctxt->memopp = op; 4630 if (ctxt->d & BitOp) 4631 fetch_bit_operand(ctxt); 4632 op->orig_val = op->val; 4633 break; 4634 case OpMem64: 4635 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8; 4636 goto mem_common; 4637 case OpAcc: 4638 op->type = OP_REG; 4639 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4640 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 4641 fetch_register_operand(op); 4642 break; 4643 case OpAccLo: 4644 op->type = OP_REG; 4645 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes; 4646 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 4647 fetch_register_operand(op); 4648 break; 4649 case OpAccHi: 4650 if (ctxt->d & ByteOp) { 4651 op->type = OP_NONE; 4652 break; 4653 } 4654 op->type = OP_REG; 4655 op->bytes = ctxt->op_bytes; 4656 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 4657 fetch_register_operand(op); 4658 break; 4659 case OpDI: 4660 op->type = OP_MEM; 4661 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4662 op->addr.mem.ea = 4663 register_address(ctxt, VCPU_REGS_RDI); 4664 op->addr.mem.seg = VCPU_SREG_ES; 4665 op->val = 0; 4666 op->count = 1; 4667 break; 4668 case OpDX: 4669 op->type = OP_REG; 4670 op->bytes = 2; 4671 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 4672 fetch_register_operand(op); 4673 break; 4674 case OpCL: 4675 op->type = OP_IMM; 4676 op->bytes = 1; 4677 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff; 4678 break; 4679 case OpImmByte: 4680 rc = decode_imm(ctxt, op, 1, true); 4681 break; 4682 case OpOne: 4683 op->type = OP_IMM; 4684 op->bytes = 1; 4685 op->val = 1; 4686 break; 4687 case OpImm: 4688 rc = decode_imm(ctxt, op, imm_size(ctxt), true); 4689 break; 4690 case OpImm64: 4691 rc = decode_imm(ctxt, op, ctxt->op_bytes, true); 4692 break; 4693 case OpMem8: 4694 ctxt->memop.bytes = 1; 4695 if (ctxt->memop.type == OP_REG) { 4696 ctxt->memop.addr.reg = decode_register(ctxt, 4697 ctxt->modrm_rm, true); 4698 fetch_register_operand(&ctxt->memop); 4699 } 4700 goto mem_common; 4701 case OpMem16: 4702 ctxt->memop.bytes = 2; 4703 goto mem_common; 4704 case OpMem32: 4705 ctxt->memop.bytes = 4; 4706 goto mem_common; 4707 case OpImmU16: 4708 rc = decode_imm(ctxt, op, 2, false); 4709 break; 4710 case OpImmU: 4711 rc = decode_imm(ctxt, op, imm_size(ctxt), false); 4712 break; 4713 case OpSI: 4714 op->type = OP_MEM; 4715 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4716 op->addr.mem.ea = 4717 register_address(ctxt, VCPU_REGS_RSI); 4718 op->addr.mem.seg = ctxt->seg_override; 4719 op->val = 0; 4720 op->count = 1; 4721 break; 4722 case OpXLat: 4723 op->type = OP_MEM; 4724 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4725 op->addr.mem.ea = 4726 address_mask(ctxt, 4727 reg_read(ctxt, VCPU_REGS_RBX) + 4728 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff)); 4729 op->addr.mem.seg = ctxt->seg_override; 4730 op->val = 0; 4731 break; 4732 case OpImmFAddr: 4733 op->type = OP_IMM; 4734 op->addr.mem.ea = ctxt->_eip; 4735 op->bytes = ctxt->op_bytes + 2; 4736 insn_fetch_arr(op->valptr, op->bytes, ctxt); 4737 break; 4738 case OpMemFAddr: 4739 ctxt->memop.bytes = ctxt->op_bytes + 2; 4740 goto mem_common; 4741 case OpES: 4742 op->type = OP_IMM; 4743 op->val = VCPU_SREG_ES; 4744 break; 4745 case OpCS: 4746 op->type = OP_IMM; 4747 op->val = VCPU_SREG_CS; 4748 break; 4749 case OpSS: 4750 op->type = OP_IMM; 4751 op->val = VCPU_SREG_SS; 4752 break; 4753 case OpDS: 4754 op->type = OP_IMM; 4755 op->val = VCPU_SREG_DS; 4756 break; 4757 case OpFS: 4758 op->type = OP_IMM; 4759 op->val = VCPU_SREG_FS; 4760 break; 4761 case OpGS: 4762 op->type = OP_IMM; 4763 op->val = VCPU_SREG_GS; 4764 break; 4765 case OpImplicit: 4766 /* Special instructions do their own operand decoding. */ 4767 default: 4768 op->type = OP_NONE; /* Disable writeback. */ 4769 break; 4770 } 4771 4772 done: 4773 return rc; 4774 } 4775 4776 static int x86_decode_avx(struct x86_emulate_ctxt *ctxt, 4777 u8 vex_1st, u8 vex_2nd, struct opcode *opcode) 4778 { 4779 u8 vex_3rd, map, pp, l, v; 4780 int rc = X86EMUL_CONTINUE; 4781 4782 if (ctxt->rep_prefix || ctxt->op_prefix || ctxt->rex_prefix) 4783 goto ud; 4784 4785 if (vex_1st == 0xc5) { 4786 /* Expand RVVVVlpp to VEX3 format */ 4787 vex_3rd = vex_2nd & ~0x80; /* VVVVlpp from VEX2, w=0 */ 4788 vex_2nd = (vex_2nd & 0x80) | 0x61; /* R from VEX2, X=1 B=1 mmmmm=00001 */ 4789 } else { 4790 vex_3rd = insn_fetch(u8, ctxt); 4791 } 4792 4793 /* vex_2nd = RXBmmmmm, vex_3rd = wVVVVlpp. Fix polarity */ 4794 vex_2nd ^= 0xE0; /* binary 11100000 */ 4795 vex_3rd ^= 0x78; /* binary 01111000 */ 4796 4797 ctxt->rex_prefix = REX_PREFIX; 4798 ctxt->rex_bits = (vex_2nd & 0xE0) >> 5; /* RXB */ 4799 ctxt->rex_bits |= (vex_3rd & 0x80) >> 4; /* w */ 4800 if (ctxt->rex_bits && ctxt->mode != X86EMUL_MODE_PROT64) 4801 goto ud; 4802 4803 map = vex_2nd & 0x1f; 4804 v = (vex_3rd >> 3) & 0xf; 4805 l = vex_3rd & 0x4; 4806 pp = vex_3rd & 0x3; 4807 4808 ctxt->b = insn_fetch(u8, ctxt); 4809 switch (map) { 4810 case 1: 4811 ctxt->opcode_len = 2; 4812 *opcode = twobyte_table[ctxt->b]; 4813 break; 4814 case 2: 4815 ctxt->opcode_len = 3; 4816 *opcode = opcode_map_0f_38[ctxt->b]; 4817 break; 4818 case 3: 4819 /* no 0f 3a instructions are supported yet */ 4820 return X86EMUL_UNHANDLEABLE; 4821 default: 4822 goto ud; 4823 } 4824 4825 /* 4826 * No three operand instructions are supported yet; those that 4827 * *are* marked with the Avx flag reserve the VVVV flag. 4828 */ 4829 if (v) 4830 goto ud; 4831 4832 if (l) 4833 ctxt->op_bytes = 32; 4834 else 4835 ctxt->op_bytes = 16; 4836 4837 switch (pp) { 4838 case 0: break; 4839 case 1: ctxt->op_prefix = true; break; 4840 case 2: ctxt->rep_prefix = 0xf3; break; 4841 case 3: ctxt->rep_prefix = 0xf2; break; 4842 } 4843 4844 done: 4845 return rc; 4846 ud: 4847 *opcode = ud; 4848 return rc; 4849 } 4850 4851 int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len, int emulation_type) 4852 { 4853 int rc = X86EMUL_CONTINUE; 4854 int mode = ctxt->mode; 4855 int def_op_bytes, def_ad_bytes, goffset, simd_prefix; 4856 bool vex_prefix = false; 4857 bool has_seg_override = false; 4858 struct opcode opcode; 4859 u16 dummy; 4860 struct desc_struct desc; 4861 4862 ctxt->memop.type = OP_NONE; 4863 ctxt->memopp = NULL; 4864 ctxt->_eip = ctxt->eip; 4865 ctxt->fetch.ptr = ctxt->fetch.data; 4866 ctxt->fetch.end = ctxt->fetch.data + insn_len; 4867 ctxt->opcode_len = 1; 4868 ctxt->intercept = x86_intercept_none; 4869 if (insn_len > 0) 4870 memcpy(ctxt->fetch.data, insn, insn_len); 4871 else { 4872 rc = __do_insn_fetch_bytes(ctxt, 1); 4873 if (rc != X86EMUL_CONTINUE) 4874 goto done; 4875 } 4876 4877 switch (mode) { 4878 case X86EMUL_MODE_REAL: 4879 case X86EMUL_MODE_VM86: 4880 def_op_bytes = def_ad_bytes = 2; 4881 ctxt->ops->get_segment(ctxt, &dummy, &desc, NULL, VCPU_SREG_CS); 4882 if (desc.d) 4883 def_op_bytes = def_ad_bytes = 4; 4884 break; 4885 case X86EMUL_MODE_PROT16: 4886 def_op_bytes = def_ad_bytes = 2; 4887 break; 4888 case X86EMUL_MODE_PROT32: 4889 def_op_bytes = def_ad_bytes = 4; 4890 break; 4891 #ifdef CONFIG_X86_64 4892 case X86EMUL_MODE_PROT64: 4893 def_op_bytes = 4; 4894 def_ad_bytes = 8; 4895 break; 4896 #endif 4897 default: 4898 return EMULATION_FAILED; 4899 } 4900 4901 ctxt->op_bytes = def_op_bytes; 4902 ctxt->ad_bytes = def_ad_bytes; 4903 4904 /* Legacy prefixes. */ 4905 for (;;) { 4906 switch (ctxt->b = insn_fetch(u8, ctxt)) { 4907 case 0x66: /* operand-size override */ 4908 ctxt->op_prefix = true; 4909 /* switch between 2/4 bytes */ 4910 ctxt->op_bytes = def_op_bytes ^ 6; 4911 break; 4912 case 0x67: /* address-size override */ 4913 if (mode == X86EMUL_MODE_PROT64) 4914 /* switch between 4/8 bytes */ 4915 ctxt->ad_bytes = def_ad_bytes ^ 12; 4916 else 4917 /* switch between 2/4 bytes */ 4918 ctxt->ad_bytes = def_ad_bytes ^ 6; 4919 break; 4920 case 0x26: /* ES override */ 4921 has_seg_override = true; 4922 ctxt->seg_override = VCPU_SREG_ES; 4923 break; 4924 case 0x2e: /* CS override */ 4925 has_seg_override = true; 4926 ctxt->seg_override = VCPU_SREG_CS; 4927 break; 4928 case 0x36: /* SS override */ 4929 has_seg_override = true; 4930 ctxt->seg_override = VCPU_SREG_SS; 4931 break; 4932 case 0x3e: /* DS override */ 4933 has_seg_override = true; 4934 ctxt->seg_override = VCPU_SREG_DS; 4935 break; 4936 case 0x64: /* FS override */ 4937 has_seg_override = true; 4938 ctxt->seg_override = VCPU_SREG_FS; 4939 break; 4940 case 0x65: /* GS override */ 4941 has_seg_override = true; 4942 ctxt->seg_override = VCPU_SREG_GS; 4943 break; 4944 case 0x40 ... 0x4f: /* REX */ 4945 if (mode != X86EMUL_MODE_PROT64) 4946 goto done_prefixes; 4947 ctxt->rex_prefix = REX_PREFIX; 4948 ctxt->rex_bits = ctxt->b & 0xf; 4949 continue; 4950 case 0xf0: /* LOCK */ 4951 ctxt->lock_prefix = 1; 4952 break; 4953 case 0xf2: /* REPNE/REPNZ */ 4954 case 0xf3: /* REP/REPE/REPZ */ 4955 ctxt->rep_prefix = ctxt->b; 4956 break; 4957 default: 4958 goto done_prefixes; 4959 } 4960 4961 /* Any legacy prefix after a REX prefix nullifies its effect. */ 4962 ctxt->rex_prefix = REX_NONE; 4963 ctxt->rex_bits = 0; 4964 } 4965 4966 done_prefixes: 4967 4968 /* REX prefix. */ 4969 if (ctxt->rex_bits & REX_W) 4970 ctxt->op_bytes = 8; 4971 4972 /* Opcode byte(s). */ 4973 if (ctxt->b == 0xc4 || ctxt->b == 0xc5) { 4974 /* VEX or LDS/LES */ 4975 u8 vex_2nd = insn_fetch(u8, ctxt); 4976 if (mode != X86EMUL_MODE_PROT64 && (vex_2nd & 0xc0) != 0xc0) { 4977 opcode = opcode_table[ctxt->b]; 4978 ctxt->modrm = vex_2nd; 4979 /* the Mod/RM byte has been fetched already! */ 4980 goto done_modrm; 4981 } 4982 4983 vex_prefix = true; 4984 rc = x86_decode_avx(ctxt, ctxt->b, vex_2nd, &opcode); 4985 if (rc != X86EMUL_CONTINUE) 4986 goto done; 4987 } else if (ctxt->b == 0x0f) { 4988 /* Two- or three-byte opcode */ 4989 ctxt->opcode_len = 2; 4990 ctxt->b = insn_fetch(u8, ctxt); 4991 opcode = twobyte_table[ctxt->b]; 4992 4993 /* 0F_38 opcode map */ 4994 if (ctxt->b == 0x38) { 4995 ctxt->opcode_len = 3; 4996 ctxt->b = insn_fetch(u8, ctxt); 4997 opcode = opcode_map_0f_38[ctxt->b]; 4998 } 4999 } else { 5000 /* Opcode byte(s). */ 5001 opcode = opcode_table[ctxt->b]; 5002 } 5003 5004 if (opcode.flags & ModRM) 5005 ctxt->modrm = insn_fetch(u8, ctxt); 5006 5007 done_modrm: 5008 ctxt->d = opcode.flags; 5009 while (ctxt->d & GroupMask) { 5010 switch (ctxt->d & GroupMask) { 5011 case Group: 5012 goffset = (ctxt->modrm >> 3) & 7; 5013 opcode = opcode.u.group[goffset]; 5014 break; 5015 case GroupDual: 5016 goffset = (ctxt->modrm >> 3) & 7; 5017 if ((ctxt->modrm >> 6) == 3) 5018 opcode = opcode.u.gdual->mod3[goffset]; 5019 else 5020 opcode = opcode.u.gdual->mod012[goffset]; 5021 break; 5022 case RMExt: 5023 goffset = ctxt->modrm & 7; 5024 opcode = opcode.u.group[goffset]; 5025 break; 5026 case Prefix: 5027 if (ctxt->rep_prefix && ctxt->op_prefix) 5028 return EMULATION_FAILED; 5029 simd_prefix = ctxt->op_prefix ? 0x66 : ctxt->rep_prefix; 5030 switch (simd_prefix) { 5031 case 0x00: opcode = opcode.u.gprefix->pfx_no; break; 5032 case 0x66: opcode = opcode.u.gprefix->pfx_66; break; 5033 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break; 5034 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break; 5035 } 5036 break; 5037 case Escape: 5038 if (ctxt->modrm > 0xbf) { 5039 size_t size = ARRAY_SIZE(opcode.u.esc->high); 5040 u32 index = array_index_nospec( 5041 ctxt->modrm - 0xc0, size); 5042 5043 opcode = opcode.u.esc->high[index]; 5044 } else { 5045 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7]; 5046 } 5047 break; 5048 case InstrDual: 5049 if ((ctxt->modrm >> 6) == 3) 5050 opcode = opcode.u.idual->mod3; 5051 else 5052 opcode = opcode.u.idual->mod012; 5053 break; 5054 case ModeDual: 5055 if (ctxt->mode == X86EMUL_MODE_PROT64) 5056 opcode = opcode.u.mdual->mode64; 5057 else 5058 opcode = opcode.u.mdual->mode32; 5059 break; 5060 default: 5061 return EMULATION_FAILED; 5062 } 5063 5064 ctxt->d &= ~(u64)GroupMask; 5065 ctxt->d |= opcode.flags; 5066 } 5067 5068 ctxt->is_branch = opcode.flags & IsBranch; 5069 5070 /* Unrecognised? */ 5071 if (ctxt->d == 0) 5072 return EMULATION_FAILED; 5073 5074 if (unlikely(vex_prefix)) { 5075 /* 5076 * Only specifically marked instructions support VEX. Since many 5077 * instructions support it but are not annotated, return not implemented 5078 * rather than #UD. 5079 */ 5080 if (!(ctxt->d & Avx)) 5081 return EMULATION_FAILED; 5082 5083 if (!(ctxt->d & AlignMask)) 5084 ctxt->d |= Unaligned; 5085 } 5086 5087 ctxt->execute = opcode.u.execute; 5088 5089 /* 5090 * Reject emulation if KVM might need to emulate shadow stack updates 5091 * and/or indirect branch tracking enforcement, which the emulator 5092 * doesn't support. 5093 */ 5094 if ((is_ibt_instruction(ctxt) || is_shstk_instruction(ctxt)) && 5095 ctxt->ops->get_cr(ctxt, 4) & X86_CR4_CET) { 5096 u64 u_cet = 0, s_cet = 0; 5097 5098 /* 5099 * Check both User and Supervisor on far transfers as inter- 5100 * privilege level transfers are impacted by CET at the target 5101 * privilege level, and that is not known at this time. The 5102 * expectation is that the guest will not require emulation of 5103 * any CET-affected instructions at any privilege level. 5104 */ 5105 if (!(ctxt->d & NearBranch)) 5106 u_cet = s_cet = CET_SHSTK_EN | CET_ENDBR_EN; 5107 else if (ctxt->ops->cpl(ctxt) == 3) 5108 u_cet = CET_SHSTK_EN | CET_ENDBR_EN; 5109 else 5110 s_cet = CET_SHSTK_EN | CET_ENDBR_EN; 5111 5112 if ((u_cet && ctxt->ops->get_msr(ctxt, MSR_IA32_U_CET, &u_cet)) || 5113 (s_cet && ctxt->ops->get_msr(ctxt, MSR_IA32_S_CET, &s_cet))) 5114 return EMULATION_FAILED; 5115 5116 if ((u_cet | s_cet) & CET_SHSTK_EN && is_shstk_instruction(ctxt)) 5117 return EMULATION_FAILED; 5118 5119 if ((u_cet | s_cet) & CET_ENDBR_EN && is_ibt_instruction(ctxt)) 5120 return EMULATION_FAILED; 5121 } 5122 5123 if (unlikely(emulation_type & EMULTYPE_TRAP_UD) && 5124 likely(!(ctxt->d & EmulateOnUD))) 5125 return EMULATION_FAILED; 5126 5127 if (unlikely(ctxt->d & 5128 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch| 5129 No16))) { 5130 /* 5131 * These are copied unconditionally here, and checked unconditionally 5132 * in x86_emulate_insn. 5133 */ 5134 ctxt->check_perm = opcode.check_perm; 5135 ctxt->intercept = opcode.intercept; 5136 5137 if (ctxt->d & NotImpl) 5138 return EMULATION_FAILED; 5139 5140 if (mode == X86EMUL_MODE_PROT64) { 5141 if (ctxt->op_bytes == 4 && (ctxt->d & Stack)) 5142 ctxt->op_bytes = 8; 5143 else if (ctxt->d & NearBranch) 5144 ctxt->op_bytes = 8; 5145 } 5146 5147 if (ctxt->d & Op3264) { 5148 if (mode == X86EMUL_MODE_PROT64) 5149 ctxt->op_bytes = 8; 5150 else 5151 ctxt->op_bytes = 4; 5152 } 5153 5154 if ((ctxt->d & No16) && ctxt->op_bytes == 2) 5155 ctxt->op_bytes = 4; 5156 5157 if (vex_prefix) 5158 ; 5159 else if (ctxt->d & Sse) 5160 ctxt->op_bytes = 16, ctxt->d &= ~Avx; 5161 else if (ctxt->d & Mmx) 5162 ctxt->op_bytes = 8; 5163 } 5164 5165 /* ModRM and SIB bytes. */ 5166 if (ctxt->d & ModRM) { 5167 rc = decode_modrm(ctxt, &ctxt->memop); 5168 if (!has_seg_override) { 5169 has_seg_override = true; 5170 ctxt->seg_override = ctxt->modrm_seg; 5171 } 5172 } else if (ctxt->d & MemAbs) 5173 rc = decode_abs(ctxt, &ctxt->memop); 5174 if (rc != X86EMUL_CONTINUE) 5175 goto done; 5176 5177 if (!has_seg_override) 5178 ctxt->seg_override = VCPU_SREG_DS; 5179 5180 ctxt->memop.addr.mem.seg = ctxt->seg_override; 5181 5182 /* 5183 * Decode and fetch the source operand: register, memory 5184 * or immediate. 5185 */ 5186 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask); 5187 if (rc != X86EMUL_CONTINUE) 5188 goto done; 5189 5190 /* 5191 * Decode and fetch the second source operand: register, memory 5192 * or immediate. 5193 */ 5194 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask); 5195 if (rc != X86EMUL_CONTINUE) 5196 goto done; 5197 5198 /* Decode and fetch the destination operand: register or memory. */ 5199 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask); 5200 5201 if (ctxt->rip_relative && likely(ctxt->memopp)) 5202 ctxt->memopp->addr.mem.ea = address_mask(ctxt, 5203 ctxt->memopp->addr.mem.ea + ctxt->_eip); 5204 5205 done: 5206 if (rc == X86EMUL_PROPAGATE_FAULT) 5207 ctxt->have_exception = true; 5208 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK; 5209 } 5210 5211 bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt) 5212 { 5213 return ctxt->d & PageTable; 5214 } 5215 5216 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt) 5217 { 5218 /* The second termination condition only applies for REPE 5219 * and REPNE. Test if the repeat string operation prefix is 5220 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the 5221 * corresponding termination condition according to: 5222 * - if REPE/REPZ and ZF = 0 then done 5223 * - if REPNE/REPNZ and ZF = 1 then done 5224 */ 5225 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) || 5226 (ctxt->b == 0xae) || (ctxt->b == 0xaf)) 5227 && (((ctxt->rep_prefix == REPE_PREFIX) && 5228 ((ctxt->eflags & X86_EFLAGS_ZF) == 0)) 5229 || ((ctxt->rep_prefix == REPNE_PREFIX) && 5230 ((ctxt->eflags & X86_EFLAGS_ZF) == X86_EFLAGS_ZF)))) 5231 return true; 5232 5233 return false; 5234 } 5235 5236 static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt) 5237 { 5238 int rc; 5239 5240 kvm_fpu_get(); 5241 rc = asm_safe("fwait"); 5242 kvm_fpu_put(); 5243 5244 if (unlikely(rc != X86EMUL_CONTINUE)) 5245 return emulate_exception(ctxt, MF_VECTOR, 0, false); 5246 5247 return X86EMUL_CONTINUE; 5248 } 5249 5250 static void fetch_possible_mmx_operand(struct operand *op) 5251 { 5252 if (op->type == OP_MM) 5253 kvm_read_mmx_reg(op->addr.mm, &op->mm_val); 5254 } 5255 5256 void init_decode_cache(struct x86_emulate_ctxt *ctxt) 5257 { 5258 /* Clear fields that are set conditionally but read without a guard. */ 5259 ctxt->rip_relative = false; 5260 ctxt->rex_prefix = REX_NONE; 5261 ctxt->rex_bits = 0; 5262 ctxt->lock_prefix = 0; 5263 ctxt->op_prefix = false; 5264 ctxt->rep_prefix = 0; 5265 ctxt->regs_valid = 0; 5266 ctxt->regs_dirty = 0; 5267 5268 ctxt->io_read.pos = 0; 5269 ctxt->io_read.end = 0; 5270 ctxt->mem_read.end = 0; 5271 } 5272 5273 int x86_emulate_insn(struct x86_emulate_ctxt *ctxt, bool check_intercepts) 5274 { 5275 const struct x86_emulate_ops *ops = ctxt->ops; 5276 int rc = X86EMUL_CONTINUE; 5277 int saved_dst_type = ctxt->dst.type; 5278 5279 ctxt->mem_read.pos = 0; 5280 5281 /* LOCK prefix is allowed only with some instructions */ 5282 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) { 5283 rc = emulate_ud(ctxt); 5284 goto done; 5285 } 5286 5287 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) { 5288 rc = emulate_ud(ctxt); 5289 goto done; 5290 } 5291 5292 if (unlikely(ctxt->d & 5293 (No64|Undefined|Avx|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) { 5294 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) || 5295 (ctxt->d & Undefined)) { 5296 rc = emulate_ud(ctxt); 5297 goto done; 5298 } 5299 5300 if ((ctxt->d & (Avx|Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM))) { 5301 rc = emulate_ud(ctxt); 5302 goto done; 5303 } 5304 5305 if (ctxt->d & Avx) { 5306 u64 xcr = 0; 5307 if (!(ops->get_cr(ctxt, 4) & X86_CR4_OSXSAVE) 5308 || ops->get_xcr(ctxt, 0, &xcr) 5309 || !(xcr & XFEATURE_MASK_YMM)) { 5310 rc = emulate_ud(ctxt); 5311 goto done; 5312 } 5313 } else if (ctxt->d & Sse) { 5314 if (!(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR)) { 5315 rc = emulate_ud(ctxt); 5316 goto done; 5317 } 5318 } 5319 5320 if ((ctxt->d & (Avx|Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) { 5321 rc = emulate_nm(ctxt); 5322 goto done; 5323 } 5324 5325 if (ctxt->d & Mmx) { 5326 rc = flush_pending_x87_faults(ctxt); 5327 if (rc != X86EMUL_CONTINUE) 5328 goto done; 5329 /* 5330 * Now that we know the fpu is exception safe, we can fetch 5331 * operands from it. 5332 */ 5333 fetch_possible_mmx_operand(&ctxt->src); 5334 fetch_possible_mmx_operand(&ctxt->src2); 5335 if (!(ctxt->d & Mov)) 5336 fetch_possible_mmx_operand(&ctxt->dst); 5337 } 5338 5339 if (unlikely(check_intercepts) && ctxt->intercept) { 5340 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5341 X86_ICPT_PRE_EXCEPT); 5342 if (rc != X86EMUL_CONTINUE) 5343 goto done; 5344 } 5345 5346 /* Instruction can only be executed in protected mode */ 5347 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) { 5348 rc = emulate_ud(ctxt); 5349 goto done; 5350 } 5351 5352 /* Privileged instruction can be executed only in CPL=0 */ 5353 if ((ctxt->d & Priv) && ops->cpl(ctxt)) { 5354 if (ctxt->d & PrivUD) 5355 rc = emulate_ud(ctxt); 5356 else 5357 rc = emulate_gp(ctxt, 0); 5358 goto done; 5359 } 5360 5361 /* Do instruction specific permission checks */ 5362 if (ctxt->d & CheckPerm) { 5363 rc = ctxt->check_perm(ctxt); 5364 if (rc != X86EMUL_CONTINUE) 5365 goto done; 5366 } 5367 5368 if (unlikely(check_intercepts) && (ctxt->d & Intercept)) { 5369 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5370 X86_ICPT_POST_EXCEPT); 5371 if (rc != X86EMUL_CONTINUE) 5372 goto done; 5373 } 5374 5375 if (ctxt->rep_prefix && (ctxt->d & String)) { 5376 /* All REP prefixes have the same first termination condition */ 5377 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) { 5378 string_registers_quirk(ctxt); 5379 ctxt->eip = ctxt->_eip; 5380 ctxt->eflags &= ~X86_EFLAGS_RF; 5381 goto done; 5382 } 5383 } 5384 } 5385 5386 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) { 5387 rc = segmented_read(ctxt, ctxt->src.addr.mem, 5388 ctxt->src.valptr, ctxt->src.bytes); 5389 if (rc != X86EMUL_CONTINUE) 5390 goto done; 5391 ctxt->src.orig_val64 = ctxt->src.val64; 5392 } 5393 5394 if (ctxt->src2.type == OP_MEM) { 5395 rc = segmented_read(ctxt, ctxt->src2.addr.mem, 5396 &ctxt->src2.val, ctxt->src2.bytes); 5397 if (rc != X86EMUL_CONTINUE) 5398 goto done; 5399 } 5400 5401 if ((ctxt->d & DstMask) == ImplicitOps) 5402 goto special_insn; 5403 5404 5405 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) { 5406 /* optimisation - avoid slow emulated read if Mov */ 5407 rc = segmented_read(ctxt, ctxt->dst.addr.mem, 5408 &ctxt->dst.val, ctxt->dst.bytes); 5409 if (rc != X86EMUL_CONTINUE) { 5410 if (!(ctxt->d & NoWrite) && 5411 rc == X86EMUL_PROPAGATE_FAULT && 5412 ctxt->exception.vector == PF_VECTOR) 5413 ctxt->exception.error_code |= PFERR_WRITE_MASK; 5414 goto done; 5415 } 5416 } 5417 /* Copy full 64-bit value for CMPXCHG8B. */ 5418 ctxt->dst.orig_val64 = ctxt->dst.val64; 5419 5420 special_insn: 5421 5422 if (unlikely(check_intercepts) && (ctxt->d & Intercept)) { 5423 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5424 X86_ICPT_POST_MEMACCESS); 5425 if (rc != X86EMUL_CONTINUE) 5426 goto done; 5427 } 5428 5429 if (ctxt->rep_prefix && (ctxt->d & String)) 5430 ctxt->eflags |= X86_EFLAGS_RF; 5431 else 5432 ctxt->eflags &= ~X86_EFLAGS_RF; 5433 5434 if (ctxt->execute) { 5435 rc = ctxt->execute(ctxt); 5436 if (rc != X86EMUL_CONTINUE) 5437 goto done; 5438 goto writeback; 5439 } 5440 5441 if (ctxt->opcode_len == 2) 5442 goto twobyte_insn; 5443 else if (ctxt->opcode_len == 3) 5444 goto threebyte_insn; 5445 5446 switch (ctxt->b) { 5447 case 0x70 ... 0x7f: /* jcc (short) */ 5448 if (test_cc(ctxt->b, ctxt->eflags)) 5449 rc = jmp_rel(ctxt, ctxt->src.val); 5450 break; 5451 case 0x8d: /* lea r16/r32, m */ 5452 ctxt->dst.val = ctxt->src.addr.mem.ea; 5453 break; 5454 case 0x90 ... 0x97: /* nop / xchg reg, rax */ 5455 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX)) 5456 ctxt->dst.type = OP_NONE; 5457 else 5458 rc = em_xchg(ctxt); 5459 break; 5460 case 0x98: /* cbw/cwde/cdqe */ 5461 switch (ctxt->op_bytes) { 5462 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break; 5463 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break; 5464 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break; 5465 } 5466 break; 5467 case 0xcc: /* int3 */ 5468 rc = emulate_int(ctxt, 3); 5469 break; 5470 case 0xcd: /* int n */ 5471 rc = emulate_int(ctxt, ctxt->src.val); 5472 break; 5473 case 0xce: /* into */ 5474 if (ctxt->eflags & X86_EFLAGS_OF) 5475 rc = emulate_int(ctxt, 4); 5476 break; 5477 case 0xe9: /* jmp rel */ 5478 case 0xeb: /* jmp rel short */ 5479 rc = jmp_rel(ctxt, ctxt->src.val); 5480 ctxt->dst.type = OP_NONE; /* Disable writeback. */ 5481 break; 5482 case 0xf4: /* hlt */ 5483 ctxt->ops->halt(ctxt); 5484 break; 5485 case 0xf5: /* cmc */ 5486 /* complement carry flag from eflags reg */ 5487 ctxt->eflags ^= X86_EFLAGS_CF; 5488 break; 5489 case 0xf8: /* clc */ 5490 ctxt->eflags &= ~X86_EFLAGS_CF; 5491 break; 5492 case 0xf9: /* stc */ 5493 ctxt->eflags |= X86_EFLAGS_CF; 5494 break; 5495 case 0xfc: /* cld */ 5496 ctxt->eflags &= ~X86_EFLAGS_DF; 5497 break; 5498 case 0xfd: /* std */ 5499 ctxt->eflags |= X86_EFLAGS_DF; 5500 break; 5501 default: 5502 goto cannot_emulate; 5503 } 5504 5505 if (rc != X86EMUL_CONTINUE) 5506 goto done; 5507 5508 writeback: 5509 if (ctxt->d & SrcWrite) { 5510 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR); 5511 rc = writeback(ctxt, &ctxt->src); 5512 if (rc != X86EMUL_CONTINUE) 5513 goto done; 5514 } 5515 if (!(ctxt->d & NoWrite)) { 5516 rc = writeback(ctxt, &ctxt->dst); 5517 if (rc != X86EMUL_CONTINUE) 5518 goto done; 5519 } 5520 5521 /* 5522 * restore dst type in case the decoding will be reused 5523 * (happens for string instruction ) 5524 */ 5525 ctxt->dst.type = saved_dst_type; 5526 5527 if ((ctxt->d & SrcMask) == SrcSI) 5528 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src); 5529 5530 if ((ctxt->d & DstMask) == DstDI) 5531 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst); 5532 5533 if (ctxt->rep_prefix && (ctxt->d & String)) { 5534 unsigned int count; 5535 struct read_cache *r = &ctxt->io_read; 5536 if ((ctxt->d & SrcMask) == SrcSI) 5537 count = ctxt->src.count; 5538 else 5539 count = ctxt->dst.count; 5540 register_address_increment(ctxt, VCPU_REGS_RCX, -count); 5541 5542 if (!string_insn_completed(ctxt)) { 5543 /* 5544 * Re-enter guest when pio read ahead buffer is empty 5545 * or, if it is not used, after each 1024 iteration. 5546 */ 5547 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) && 5548 (r->end == 0 || r->end != r->pos)) { 5549 /* 5550 * Reset read cache. Usually happens before 5551 * decode, but since instruction is restarted 5552 * we have to do it here. 5553 */ 5554 ctxt->mem_read.end = 0; 5555 writeback_registers(ctxt); 5556 return EMULATION_RESTART; 5557 } 5558 goto done; /* skip rip writeback */ 5559 } 5560 ctxt->eflags &= ~X86_EFLAGS_RF; 5561 } 5562 5563 ctxt->eip = ctxt->_eip; 5564 if (ctxt->mode != X86EMUL_MODE_PROT64) 5565 ctxt->eip = (u32)ctxt->_eip; 5566 5567 done: 5568 if (rc == X86EMUL_PROPAGATE_FAULT) { 5569 if (KVM_EMULATOR_BUG_ON(ctxt->exception.vector > 0x1f, ctxt)) 5570 return EMULATION_FAILED; 5571 ctxt->have_exception = true; 5572 } 5573 if (rc == X86EMUL_INTERCEPTED) 5574 return EMULATION_INTERCEPTED; 5575 5576 if (rc == X86EMUL_CONTINUE) 5577 writeback_registers(ctxt); 5578 5579 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 5580 5581 twobyte_insn: 5582 switch (ctxt->b) { 5583 case 0x09: /* wbinvd */ 5584 (ctxt->ops->wbinvd)(ctxt); 5585 break; 5586 case 0x08: /* invd */ 5587 case 0x0d: /* GrpP (prefetch) */ 5588 case 0x18: /* Grp16 (prefetch/nop) */ 5589 case 0x1f: /* nop */ 5590 break; 5591 case 0x20: /* mov cr, reg */ 5592 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg); 5593 break; 5594 case 0x21: /* mov from dr to reg */ 5595 ctxt->dst.val = ops->get_dr(ctxt, ctxt->modrm_reg); 5596 break; 5597 case 0x40 ... 0x4f: /* cmov */ 5598 if (test_cc(ctxt->b, ctxt->eflags)) 5599 ctxt->dst.val = ctxt->src.val; 5600 else if (ctxt->op_bytes != 4) 5601 ctxt->dst.type = OP_NONE; /* no writeback */ 5602 break; 5603 case 0x80 ... 0x8f: /* jnz rel, etc*/ 5604 if (test_cc(ctxt->b, ctxt->eflags)) 5605 rc = jmp_rel(ctxt, ctxt->src.val); 5606 break; 5607 case 0x90 ... 0x9f: /* setcc r/m8 */ 5608 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags); 5609 break; 5610 case 0xb6 ... 0xb7: /* movzx */ 5611 ctxt->dst.bytes = ctxt->op_bytes; 5612 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val 5613 : (u16) ctxt->src.val; 5614 break; 5615 case 0xbe ... 0xbf: /* movsx */ 5616 ctxt->dst.bytes = ctxt->op_bytes; 5617 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val : 5618 (s16) ctxt->src.val; 5619 break; 5620 default: 5621 goto cannot_emulate; 5622 } 5623 5624 threebyte_insn: 5625 5626 if (rc != X86EMUL_CONTINUE) 5627 goto done; 5628 5629 goto writeback; 5630 5631 cannot_emulate: 5632 return EMULATION_FAILED; 5633 } 5634 5635 void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt) 5636 { 5637 invalidate_registers(ctxt); 5638 } 5639 5640 void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt) 5641 { 5642 writeback_registers(ctxt); 5643 } 5644 5645 bool emulator_can_use_gpa(struct x86_emulate_ctxt *ctxt) 5646 { 5647 if (ctxt->rep_prefix && (ctxt->d & String)) 5648 return false; 5649 5650 if (ctxt->d & TwoMemOp) 5651 return false; 5652 5653 return true; 5654 } 5655