1 /****************************************************************************** 2 * emulate.c 3 * 4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. 5 * 6 * Copyright (c) 2005 Keir Fraser 7 * 8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode 9 * privileged instructions: 10 * 11 * Copyright (C) 2006 Qumranet 12 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 13 * 14 * Avi Kivity <avi@qumranet.com> 15 * Yaniv Kamay <yaniv@qumranet.com> 16 * 17 * This work is licensed under the terms of the GNU GPL, version 2. See 18 * the COPYING file in the top-level directory. 19 * 20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 21 */ 22 23 #include <linux/kvm_host.h> 24 #include "kvm_cache_regs.h" 25 #include <linux/module.h> 26 #include <asm/kvm_emulate.h> 27 28 #include "x86.h" 29 #include "tss.h" 30 31 /* 32 * Operand types 33 */ 34 #define OpNone 0ull 35 #define OpImplicit 1ull /* No generic decode */ 36 #define OpReg 2ull /* Register */ 37 #define OpMem 3ull /* Memory */ 38 #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */ 39 #define OpDI 5ull /* ES:DI/EDI/RDI */ 40 #define OpMem64 6ull /* Memory, 64-bit */ 41 #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */ 42 #define OpDX 8ull /* DX register */ 43 #define OpCL 9ull /* CL register (for shifts) */ 44 #define OpImmByte 10ull /* 8-bit sign extended immediate */ 45 #define OpOne 11ull /* Implied 1 */ 46 #define OpImm 12ull /* Sign extended immediate */ 47 #define OpMem16 13ull /* Memory operand (16-bit). */ 48 #define OpMem32 14ull /* Memory operand (32-bit). */ 49 #define OpImmU 15ull /* Immediate operand, zero extended */ 50 #define OpSI 16ull /* SI/ESI/RSI */ 51 #define OpImmFAddr 17ull /* Immediate far address */ 52 #define OpMemFAddr 18ull /* Far address in memory */ 53 #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */ 54 #define OpES 20ull /* ES */ 55 #define OpCS 21ull /* CS */ 56 #define OpSS 22ull /* SS */ 57 #define OpDS 23ull /* DS */ 58 #define OpFS 24ull /* FS */ 59 #define OpGS 25ull /* GS */ 60 #define OpMem8 26ull /* 8-bit zero extended memory operand */ 61 62 #define OpBits 5 /* Width of operand field */ 63 #define OpMask ((1ull << OpBits) - 1) 64 65 /* 66 * Opcode effective-address decode tables. 67 * Note that we only emulate instructions that have at least one memory 68 * operand (excluding implicit stack references). We assume that stack 69 * references and instruction fetches will never occur in special memory 70 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need 71 * not be handled. 72 */ 73 74 /* Operand sizes: 8-bit operands or specified/overridden size. */ 75 #define ByteOp (1<<0) /* 8-bit operands. */ 76 /* Destination operand type. */ 77 #define DstShift 1 78 #define ImplicitOps (OpImplicit << DstShift) 79 #define DstReg (OpReg << DstShift) 80 #define DstMem (OpMem << DstShift) 81 #define DstAcc (OpAcc << DstShift) 82 #define DstDI (OpDI << DstShift) 83 #define DstMem64 (OpMem64 << DstShift) 84 #define DstImmUByte (OpImmUByte << DstShift) 85 #define DstDX (OpDX << DstShift) 86 #define DstMask (OpMask << DstShift) 87 /* Source operand type. */ 88 #define SrcShift 6 89 #define SrcNone (OpNone << SrcShift) 90 #define SrcReg (OpReg << SrcShift) 91 #define SrcMem (OpMem << SrcShift) 92 #define SrcMem16 (OpMem16 << SrcShift) 93 #define SrcMem32 (OpMem32 << SrcShift) 94 #define SrcImm (OpImm << SrcShift) 95 #define SrcImmByte (OpImmByte << SrcShift) 96 #define SrcOne (OpOne << SrcShift) 97 #define SrcImmUByte (OpImmUByte << SrcShift) 98 #define SrcImmU (OpImmU << SrcShift) 99 #define SrcSI (OpSI << SrcShift) 100 #define SrcImmFAddr (OpImmFAddr << SrcShift) 101 #define SrcMemFAddr (OpMemFAddr << SrcShift) 102 #define SrcAcc (OpAcc << SrcShift) 103 #define SrcImmU16 (OpImmU16 << SrcShift) 104 #define SrcDX (OpDX << SrcShift) 105 #define SrcMem8 (OpMem8 << SrcShift) 106 #define SrcMask (OpMask << SrcShift) 107 #define BitOp (1<<11) 108 #define MemAbs (1<<12) /* Memory operand is absolute displacement */ 109 #define String (1<<13) /* String instruction (rep capable) */ 110 #define Stack (1<<14) /* Stack instruction (push/pop) */ 111 #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */ 112 #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */ 113 #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */ 114 #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */ 115 #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */ 116 #define Sse (1<<18) /* SSE Vector instruction */ 117 /* Generic ModRM decode. */ 118 #define ModRM (1<<19) 119 /* Destination is only written; never read. */ 120 #define Mov (1<<20) 121 /* Misc flags */ 122 #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */ 123 #define VendorSpecific (1<<22) /* Vendor specific instruction */ 124 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ 125 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ 126 #define Undefined (1<<25) /* No Such Instruction */ 127 #define Lock (1<<26) /* lock prefix is allowed for the instruction */ 128 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ 129 #define No64 (1<<28) 130 #define PageTable (1 << 29) /* instruction used to write page table */ 131 /* Source 2 operand type */ 132 #define Src2Shift (30) 133 #define Src2None (OpNone << Src2Shift) 134 #define Src2CL (OpCL << Src2Shift) 135 #define Src2ImmByte (OpImmByte << Src2Shift) 136 #define Src2One (OpOne << Src2Shift) 137 #define Src2Imm (OpImm << Src2Shift) 138 #define Src2ES (OpES << Src2Shift) 139 #define Src2CS (OpCS << Src2Shift) 140 #define Src2SS (OpSS << Src2Shift) 141 #define Src2DS (OpDS << Src2Shift) 142 #define Src2FS (OpFS << Src2Shift) 143 #define Src2GS (OpGS << Src2Shift) 144 #define Src2Mask (OpMask << Src2Shift) 145 #define Mmx ((u64)1 << 40) /* MMX Vector instruction */ 146 #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */ 147 #define Unaligned ((u64)1 << 42) /* Explicitly unaligned (e.g. MOVDQU) */ 148 #define Avx ((u64)1 << 43) /* Advanced Vector Extensions */ 149 150 #define X2(x...) x, x 151 #define X3(x...) X2(x), x 152 #define X4(x...) X2(x), X2(x) 153 #define X5(x...) X4(x), x 154 #define X6(x...) X4(x), X2(x) 155 #define X7(x...) X4(x), X3(x) 156 #define X8(x...) X4(x), X4(x) 157 #define X16(x...) X8(x), X8(x) 158 159 struct opcode { 160 u64 flags : 56; 161 u64 intercept : 8; 162 union { 163 int (*execute)(struct x86_emulate_ctxt *ctxt); 164 struct opcode *group; 165 struct group_dual *gdual; 166 struct gprefix *gprefix; 167 } u; 168 int (*check_perm)(struct x86_emulate_ctxt *ctxt); 169 }; 170 171 struct group_dual { 172 struct opcode mod012[8]; 173 struct opcode mod3[8]; 174 }; 175 176 struct gprefix { 177 struct opcode pfx_no; 178 struct opcode pfx_66; 179 struct opcode pfx_f2; 180 struct opcode pfx_f3; 181 }; 182 183 /* EFLAGS bit definitions. */ 184 #define EFLG_ID (1<<21) 185 #define EFLG_VIP (1<<20) 186 #define EFLG_VIF (1<<19) 187 #define EFLG_AC (1<<18) 188 #define EFLG_VM (1<<17) 189 #define EFLG_RF (1<<16) 190 #define EFLG_IOPL (3<<12) 191 #define EFLG_NT (1<<14) 192 #define EFLG_OF (1<<11) 193 #define EFLG_DF (1<<10) 194 #define EFLG_IF (1<<9) 195 #define EFLG_TF (1<<8) 196 #define EFLG_SF (1<<7) 197 #define EFLG_ZF (1<<6) 198 #define EFLG_AF (1<<4) 199 #define EFLG_PF (1<<2) 200 #define EFLG_CF (1<<0) 201 202 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a 203 #define EFLG_RESERVED_ONE_MASK 2 204 205 /* 206 * Instruction emulation: 207 * Most instructions are emulated directly via a fragment of inline assembly 208 * code. This allows us to save/restore EFLAGS and thus very easily pick up 209 * any modified flags. 210 */ 211 212 #if defined(CONFIG_X86_64) 213 #define _LO32 "k" /* force 32-bit operand */ 214 #define _STK "%%rsp" /* stack pointer */ 215 #elif defined(__i386__) 216 #define _LO32 "" /* force 32-bit operand */ 217 #define _STK "%%esp" /* stack pointer */ 218 #endif 219 220 /* 221 * These EFLAGS bits are restored from saved value during emulation, and 222 * any changes are written back to the saved value after emulation. 223 */ 224 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) 225 226 /* Before executing instruction: restore necessary bits in EFLAGS. */ 227 #define _PRE_EFLAGS(_sav, _msk, _tmp) \ 228 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \ 229 "movl %"_sav",%"_LO32 _tmp"; " \ 230 "push %"_tmp"; " \ 231 "push %"_tmp"; " \ 232 "movl %"_msk",%"_LO32 _tmp"; " \ 233 "andl %"_LO32 _tmp",("_STK"); " \ 234 "pushf; " \ 235 "notl %"_LO32 _tmp"; " \ 236 "andl %"_LO32 _tmp",("_STK"); " \ 237 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \ 238 "pop %"_tmp"; " \ 239 "orl %"_LO32 _tmp",("_STK"); " \ 240 "popf; " \ 241 "pop %"_sav"; " 242 243 /* After executing instruction: write-back necessary bits in EFLAGS. */ 244 #define _POST_EFLAGS(_sav, _msk, _tmp) \ 245 /* _sav |= EFLAGS & _msk; */ \ 246 "pushf; " \ 247 "pop %"_tmp"; " \ 248 "andl %"_msk",%"_LO32 _tmp"; " \ 249 "orl %"_LO32 _tmp",%"_sav"; " 250 251 #ifdef CONFIG_X86_64 252 #define ON64(x) x 253 #else 254 #define ON64(x) 255 #endif 256 257 #define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype) \ 258 do { \ 259 __asm__ __volatile__ ( \ 260 _PRE_EFLAGS("0", "4", "2") \ 261 _op _suffix " %"_x"3,%1; " \ 262 _POST_EFLAGS("0", "4", "2") \ 263 : "=m" ((ctxt)->eflags), \ 264 "+q" (*(_dsttype*)&(ctxt)->dst.val), \ 265 "=&r" (_tmp) \ 266 : _y ((ctxt)->src.val), "i" (EFLAGS_MASK)); \ 267 } while (0) 268 269 270 /* Raw emulation: instruction has two explicit operands. */ 271 #define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy) \ 272 do { \ 273 unsigned long _tmp; \ 274 \ 275 switch ((ctxt)->dst.bytes) { \ 276 case 2: \ 277 ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16); \ 278 break; \ 279 case 4: \ 280 ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32); \ 281 break; \ 282 case 8: \ 283 ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \ 284 break; \ 285 } \ 286 } while (0) 287 288 #define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \ 289 do { \ 290 unsigned long _tmp; \ 291 switch ((ctxt)->dst.bytes) { \ 292 case 1: \ 293 ____emulate_2op(ctxt,_op,_bx,_by,"b",u8); \ 294 break; \ 295 default: \ 296 __emulate_2op_nobyte(ctxt, _op, \ 297 _wx, _wy, _lx, _ly, _qx, _qy); \ 298 break; \ 299 } \ 300 } while (0) 301 302 /* Source operand is byte-sized and may be restricted to just %cl. */ 303 #define emulate_2op_SrcB(ctxt, _op) \ 304 __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c") 305 306 /* Source operand is byte, word, long or quad sized. */ 307 #define emulate_2op_SrcV(ctxt, _op) \ 308 __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r") 309 310 /* Source operand is word, long or quad sized. */ 311 #define emulate_2op_SrcV_nobyte(ctxt, _op) \ 312 __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r") 313 314 /* Instruction has three operands and one operand is stored in ECX register */ 315 #define __emulate_2op_cl(ctxt, _op, _suffix, _type) \ 316 do { \ 317 unsigned long _tmp; \ 318 _type _clv = (ctxt)->src2.val; \ 319 _type _srcv = (ctxt)->src.val; \ 320 _type _dstv = (ctxt)->dst.val; \ 321 \ 322 __asm__ __volatile__ ( \ 323 _PRE_EFLAGS("0", "5", "2") \ 324 _op _suffix " %4,%1 \n" \ 325 _POST_EFLAGS("0", "5", "2") \ 326 : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \ 327 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \ 328 ); \ 329 \ 330 (ctxt)->src2.val = (unsigned long) _clv; \ 331 (ctxt)->src2.val = (unsigned long) _srcv; \ 332 (ctxt)->dst.val = (unsigned long) _dstv; \ 333 } while (0) 334 335 #define emulate_2op_cl(ctxt, _op) \ 336 do { \ 337 switch ((ctxt)->dst.bytes) { \ 338 case 2: \ 339 __emulate_2op_cl(ctxt, _op, "w", u16); \ 340 break; \ 341 case 4: \ 342 __emulate_2op_cl(ctxt, _op, "l", u32); \ 343 break; \ 344 case 8: \ 345 ON64(__emulate_2op_cl(ctxt, _op, "q", ulong)); \ 346 break; \ 347 } \ 348 } while (0) 349 350 #define __emulate_1op(ctxt, _op, _suffix) \ 351 do { \ 352 unsigned long _tmp; \ 353 \ 354 __asm__ __volatile__ ( \ 355 _PRE_EFLAGS("0", "3", "2") \ 356 _op _suffix " %1; " \ 357 _POST_EFLAGS("0", "3", "2") \ 358 : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \ 359 "=&r" (_tmp) \ 360 : "i" (EFLAGS_MASK)); \ 361 } while (0) 362 363 /* Instruction has only one explicit operand (no source operand). */ 364 #define emulate_1op(ctxt, _op) \ 365 do { \ 366 switch ((ctxt)->dst.bytes) { \ 367 case 1: __emulate_1op(ctxt, _op, "b"); break; \ 368 case 2: __emulate_1op(ctxt, _op, "w"); break; \ 369 case 4: __emulate_1op(ctxt, _op, "l"); break; \ 370 case 8: ON64(__emulate_1op(ctxt, _op, "q")); break; \ 371 } \ 372 } while (0) 373 374 #define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex) \ 375 do { \ 376 unsigned long _tmp; \ 377 ulong *rax = &(ctxt)->regs[VCPU_REGS_RAX]; \ 378 ulong *rdx = &(ctxt)->regs[VCPU_REGS_RDX]; \ 379 \ 380 __asm__ __volatile__ ( \ 381 _PRE_EFLAGS("0", "5", "1") \ 382 "1: \n\t" \ 383 _op _suffix " %6; " \ 384 "2: \n\t" \ 385 _POST_EFLAGS("0", "5", "1") \ 386 ".pushsection .fixup,\"ax\" \n\t" \ 387 "3: movb $1, %4 \n\t" \ 388 "jmp 2b \n\t" \ 389 ".popsection \n\t" \ 390 _ASM_EXTABLE(1b, 3b) \ 391 : "=m" ((ctxt)->eflags), "=&r" (_tmp), \ 392 "+a" (*rax), "+d" (*rdx), "+qm"(_ex) \ 393 : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val), \ 394 "a" (*rax), "d" (*rdx)); \ 395 } while (0) 396 397 /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */ 398 #define emulate_1op_rax_rdx(ctxt, _op, _ex) \ 399 do { \ 400 switch((ctxt)->src.bytes) { \ 401 case 1: \ 402 __emulate_1op_rax_rdx(ctxt, _op, "b", _ex); \ 403 break; \ 404 case 2: \ 405 __emulate_1op_rax_rdx(ctxt, _op, "w", _ex); \ 406 break; \ 407 case 4: \ 408 __emulate_1op_rax_rdx(ctxt, _op, "l", _ex); \ 409 break; \ 410 case 8: ON64( \ 411 __emulate_1op_rax_rdx(ctxt, _op, "q", _ex)); \ 412 break; \ 413 } \ 414 } while (0) 415 416 static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt, 417 enum x86_intercept intercept, 418 enum x86_intercept_stage stage) 419 { 420 struct x86_instruction_info info = { 421 .intercept = intercept, 422 .rep_prefix = ctxt->rep_prefix, 423 .modrm_mod = ctxt->modrm_mod, 424 .modrm_reg = ctxt->modrm_reg, 425 .modrm_rm = ctxt->modrm_rm, 426 .src_val = ctxt->src.val64, 427 .src_bytes = ctxt->src.bytes, 428 .dst_bytes = ctxt->dst.bytes, 429 .ad_bytes = ctxt->ad_bytes, 430 .next_rip = ctxt->eip, 431 }; 432 433 return ctxt->ops->intercept(ctxt, &info, stage); 434 } 435 436 static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt) 437 { 438 return (1UL << (ctxt->ad_bytes << 3)) - 1; 439 } 440 441 /* Access/update address held in a register, based on addressing mode. */ 442 static inline unsigned long 443 address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg) 444 { 445 if (ctxt->ad_bytes == sizeof(unsigned long)) 446 return reg; 447 else 448 return reg & ad_mask(ctxt); 449 } 450 451 static inline unsigned long 452 register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg) 453 { 454 return address_mask(ctxt, reg); 455 } 456 457 static inline void 458 register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc) 459 { 460 if (ctxt->ad_bytes == sizeof(unsigned long)) 461 *reg += inc; 462 else 463 *reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt)); 464 } 465 466 static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel) 467 { 468 register_address_increment(ctxt, &ctxt->_eip, rel); 469 } 470 471 static u32 desc_limit_scaled(struct desc_struct *desc) 472 { 473 u32 limit = get_desc_limit(desc); 474 475 return desc->g ? (limit << 12) | 0xfff : limit; 476 } 477 478 static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg) 479 { 480 ctxt->has_seg_override = true; 481 ctxt->seg_override = seg; 482 } 483 484 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) 485 { 486 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) 487 return 0; 488 489 return ctxt->ops->get_cached_segment_base(ctxt, seg); 490 } 491 492 static unsigned seg_override(struct x86_emulate_ctxt *ctxt) 493 { 494 if (!ctxt->has_seg_override) 495 return 0; 496 497 return ctxt->seg_override; 498 } 499 500 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, 501 u32 error, bool valid) 502 { 503 ctxt->exception.vector = vec; 504 ctxt->exception.error_code = error; 505 ctxt->exception.error_code_valid = valid; 506 return X86EMUL_PROPAGATE_FAULT; 507 } 508 509 static int emulate_db(struct x86_emulate_ctxt *ctxt) 510 { 511 return emulate_exception(ctxt, DB_VECTOR, 0, false); 512 } 513 514 static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err) 515 { 516 return emulate_exception(ctxt, GP_VECTOR, err, true); 517 } 518 519 static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err) 520 { 521 return emulate_exception(ctxt, SS_VECTOR, err, true); 522 } 523 524 static int emulate_ud(struct x86_emulate_ctxt *ctxt) 525 { 526 return emulate_exception(ctxt, UD_VECTOR, 0, false); 527 } 528 529 static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err) 530 { 531 return emulate_exception(ctxt, TS_VECTOR, err, true); 532 } 533 534 static int emulate_de(struct x86_emulate_ctxt *ctxt) 535 { 536 return emulate_exception(ctxt, DE_VECTOR, 0, false); 537 } 538 539 static int emulate_nm(struct x86_emulate_ctxt *ctxt) 540 { 541 return emulate_exception(ctxt, NM_VECTOR, 0, false); 542 } 543 544 static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg) 545 { 546 u16 selector; 547 struct desc_struct desc; 548 549 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg); 550 return selector; 551 } 552 553 static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector, 554 unsigned seg) 555 { 556 u16 dummy; 557 u32 base3; 558 struct desc_struct desc; 559 560 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg); 561 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg); 562 } 563 564 /* 565 * x86 defines three classes of vector instructions: explicitly 566 * aligned, explicitly unaligned, and the rest, which change behaviour 567 * depending on whether they're AVX encoded or not. 568 * 569 * Also included is CMPXCHG16B which is not a vector instruction, yet it is 570 * subject to the same check. 571 */ 572 static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size) 573 { 574 if (likely(size < 16)) 575 return false; 576 577 if (ctxt->d & Aligned) 578 return true; 579 else if (ctxt->d & Unaligned) 580 return false; 581 else if (ctxt->d & Avx) 582 return false; 583 else 584 return true; 585 } 586 587 static int __linearize(struct x86_emulate_ctxt *ctxt, 588 struct segmented_address addr, 589 unsigned size, bool write, bool fetch, 590 ulong *linear) 591 { 592 struct desc_struct desc; 593 bool usable; 594 ulong la; 595 u32 lim; 596 u16 sel; 597 unsigned cpl, rpl; 598 599 la = seg_base(ctxt, addr.seg) + addr.ea; 600 switch (ctxt->mode) { 601 case X86EMUL_MODE_REAL: 602 break; 603 case X86EMUL_MODE_PROT64: 604 if (((signed long)la << 16) >> 16 != la) 605 return emulate_gp(ctxt, 0); 606 break; 607 default: 608 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL, 609 addr.seg); 610 if (!usable) 611 goto bad; 612 /* code segment or read-only data segment */ 613 if (((desc.type & 8) || !(desc.type & 2)) && write) 614 goto bad; 615 /* unreadable code segment */ 616 if (!fetch && (desc.type & 8) && !(desc.type & 2)) 617 goto bad; 618 lim = desc_limit_scaled(&desc); 619 if ((desc.type & 8) || !(desc.type & 4)) { 620 /* expand-up segment */ 621 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim) 622 goto bad; 623 } else { 624 /* exapand-down segment */ 625 if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim) 626 goto bad; 627 lim = desc.d ? 0xffffffff : 0xffff; 628 if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim) 629 goto bad; 630 } 631 cpl = ctxt->ops->cpl(ctxt); 632 rpl = sel & 3; 633 cpl = max(cpl, rpl); 634 if (!(desc.type & 8)) { 635 /* data segment */ 636 if (cpl > desc.dpl) 637 goto bad; 638 } else if ((desc.type & 8) && !(desc.type & 4)) { 639 /* nonconforming code segment */ 640 if (cpl != desc.dpl) 641 goto bad; 642 } else if ((desc.type & 8) && (desc.type & 4)) { 643 /* conforming code segment */ 644 if (cpl < desc.dpl) 645 goto bad; 646 } 647 break; 648 } 649 if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8) 650 la &= (u32)-1; 651 if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0)) 652 return emulate_gp(ctxt, 0); 653 *linear = la; 654 return X86EMUL_CONTINUE; 655 bad: 656 if (addr.seg == VCPU_SREG_SS) 657 return emulate_ss(ctxt, addr.seg); 658 else 659 return emulate_gp(ctxt, addr.seg); 660 } 661 662 static int linearize(struct x86_emulate_ctxt *ctxt, 663 struct segmented_address addr, 664 unsigned size, bool write, 665 ulong *linear) 666 { 667 return __linearize(ctxt, addr, size, write, false, linear); 668 } 669 670 671 static int segmented_read_std(struct x86_emulate_ctxt *ctxt, 672 struct segmented_address addr, 673 void *data, 674 unsigned size) 675 { 676 int rc; 677 ulong linear; 678 679 rc = linearize(ctxt, addr, size, false, &linear); 680 if (rc != X86EMUL_CONTINUE) 681 return rc; 682 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception); 683 } 684 685 /* 686 * Fetch the next byte of the instruction being emulated which is pointed to 687 * by ctxt->_eip, then increment ctxt->_eip. 688 * 689 * Also prefetch the remaining bytes of the instruction without crossing page 690 * boundary if they are not in fetch_cache yet. 691 */ 692 static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest) 693 { 694 struct fetch_cache *fc = &ctxt->fetch; 695 int rc; 696 int size, cur_size; 697 698 if (ctxt->_eip == fc->end) { 699 unsigned long linear; 700 struct segmented_address addr = { .seg = VCPU_SREG_CS, 701 .ea = ctxt->_eip }; 702 cur_size = fc->end - fc->start; 703 size = min(15UL - cur_size, 704 PAGE_SIZE - offset_in_page(ctxt->_eip)); 705 rc = __linearize(ctxt, addr, size, false, true, &linear); 706 if (unlikely(rc != X86EMUL_CONTINUE)) 707 return rc; 708 rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size, 709 size, &ctxt->exception); 710 if (unlikely(rc != X86EMUL_CONTINUE)) 711 return rc; 712 fc->end += size; 713 } 714 *dest = fc->data[ctxt->_eip - fc->start]; 715 ctxt->_eip++; 716 return X86EMUL_CONTINUE; 717 } 718 719 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt, 720 void *dest, unsigned size) 721 { 722 int rc; 723 724 /* x86 instructions are limited to 15 bytes. */ 725 if (unlikely(ctxt->_eip + size - ctxt->eip > 15)) 726 return X86EMUL_UNHANDLEABLE; 727 while (size--) { 728 rc = do_insn_fetch_byte(ctxt, dest++); 729 if (rc != X86EMUL_CONTINUE) 730 return rc; 731 } 732 return X86EMUL_CONTINUE; 733 } 734 735 /* Fetch next part of the instruction being emulated. */ 736 #define insn_fetch(_type, _ctxt) \ 737 ({ unsigned long _x; \ 738 rc = do_insn_fetch(_ctxt, &_x, sizeof(_type)); \ 739 if (rc != X86EMUL_CONTINUE) \ 740 goto done; \ 741 (_type)_x; \ 742 }) 743 744 #define insn_fetch_arr(_arr, _size, _ctxt) \ 745 ({ rc = do_insn_fetch(_ctxt, _arr, (_size)); \ 746 if (rc != X86EMUL_CONTINUE) \ 747 goto done; \ 748 }) 749 750 /* 751 * Given the 'reg' portion of a ModRM byte, and a register block, return a 752 * pointer into the block that addresses the relevant register. 753 * @highbyte_regs specifies whether to decode AH,CH,DH,BH. 754 */ 755 static void *decode_register(u8 modrm_reg, unsigned long *regs, 756 int highbyte_regs) 757 { 758 void *p; 759 760 p = ®s[modrm_reg]; 761 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) 762 p = (unsigned char *)®s[modrm_reg & 3] + 1; 763 return p; 764 } 765 766 static int read_descriptor(struct x86_emulate_ctxt *ctxt, 767 struct segmented_address addr, 768 u16 *size, unsigned long *address, int op_bytes) 769 { 770 int rc; 771 772 if (op_bytes == 2) 773 op_bytes = 3; 774 *address = 0; 775 rc = segmented_read_std(ctxt, addr, size, 2); 776 if (rc != X86EMUL_CONTINUE) 777 return rc; 778 addr.ea += 2; 779 rc = segmented_read_std(ctxt, addr, address, op_bytes); 780 return rc; 781 } 782 783 static int test_cc(unsigned int condition, unsigned int flags) 784 { 785 int rc = 0; 786 787 switch ((condition & 15) >> 1) { 788 case 0: /* o */ 789 rc |= (flags & EFLG_OF); 790 break; 791 case 1: /* b/c/nae */ 792 rc |= (flags & EFLG_CF); 793 break; 794 case 2: /* z/e */ 795 rc |= (flags & EFLG_ZF); 796 break; 797 case 3: /* be/na */ 798 rc |= (flags & (EFLG_CF|EFLG_ZF)); 799 break; 800 case 4: /* s */ 801 rc |= (flags & EFLG_SF); 802 break; 803 case 5: /* p/pe */ 804 rc |= (flags & EFLG_PF); 805 break; 806 case 7: /* le/ng */ 807 rc |= (flags & EFLG_ZF); 808 /* fall through */ 809 case 6: /* l/nge */ 810 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF)); 811 break; 812 } 813 814 /* Odd condition identifiers (lsb == 1) have inverted sense. */ 815 return (!!rc ^ (condition & 1)); 816 } 817 818 static void fetch_register_operand(struct operand *op) 819 { 820 switch (op->bytes) { 821 case 1: 822 op->val = *(u8 *)op->addr.reg; 823 break; 824 case 2: 825 op->val = *(u16 *)op->addr.reg; 826 break; 827 case 4: 828 op->val = *(u32 *)op->addr.reg; 829 break; 830 case 8: 831 op->val = *(u64 *)op->addr.reg; 832 break; 833 } 834 } 835 836 static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg) 837 { 838 ctxt->ops->get_fpu(ctxt); 839 switch (reg) { 840 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break; 841 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break; 842 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break; 843 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break; 844 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break; 845 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break; 846 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break; 847 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break; 848 #ifdef CONFIG_X86_64 849 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break; 850 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break; 851 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break; 852 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break; 853 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break; 854 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break; 855 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break; 856 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break; 857 #endif 858 default: BUG(); 859 } 860 ctxt->ops->put_fpu(ctxt); 861 } 862 863 static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, 864 int reg) 865 { 866 ctxt->ops->get_fpu(ctxt); 867 switch (reg) { 868 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break; 869 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break; 870 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break; 871 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break; 872 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break; 873 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break; 874 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break; 875 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break; 876 #ifdef CONFIG_X86_64 877 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break; 878 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break; 879 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break; 880 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break; 881 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break; 882 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break; 883 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break; 884 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break; 885 #endif 886 default: BUG(); 887 } 888 ctxt->ops->put_fpu(ctxt); 889 } 890 891 static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) 892 { 893 ctxt->ops->get_fpu(ctxt); 894 switch (reg) { 895 case 0: asm("movq %%mm0, %0" : "=m"(*data)); break; 896 case 1: asm("movq %%mm1, %0" : "=m"(*data)); break; 897 case 2: asm("movq %%mm2, %0" : "=m"(*data)); break; 898 case 3: asm("movq %%mm3, %0" : "=m"(*data)); break; 899 case 4: asm("movq %%mm4, %0" : "=m"(*data)); break; 900 case 5: asm("movq %%mm5, %0" : "=m"(*data)); break; 901 case 6: asm("movq %%mm6, %0" : "=m"(*data)); break; 902 case 7: asm("movq %%mm7, %0" : "=m"(*data)); break; 903 default: BUG(); 904 } 905 ctxt->ops->put_fpu(ctxt); 906 } 907 908 static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg) 909 { 910 ctxt->ops->get_fpu(ctxt); 911 switch (reg) { 912 case 0: asm("movq %0, %%mm0" : : "m"(*data)); break; 913 case 1: asm("movq %0, %%mm1" : : "m"(*data)); break; 914 case 2: asm("movq %0, %%mm2" : : "m"(*data)); break; 915 case 3: asm("movq %0, %%mm3" : : "m"(*data)); break; 916 case 4: asm("movq %0, %%mm4" : : "m"(*data)); break; 917 case 5: asm("movq %0, %%mm5" : : "m"(*data)); break; 918 case 6: asm("movq %0, %%mm6" : : "m"(*data)); break; 919 case 7: asm("movq %0, %%mm7" : : "m"(*data)); break; 920 default: BUG(); 921 } 922 ctxt->ops->put_fpu(ctxt); 923 } 924 925 static void decode_register_operand(struct x86_emulate_ctxt *ctxt, 926 struct operand *op) 927 { 928 unsigned reg = ctxt->modrm_reg; 929 int highbyte_regs = ctxt->rex_prefix == 0; 930 931 if (!(ctxt->d & ModRM)) 932 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3); 933 934 if (ctxt->d & Sse) { 935 op->type = OP_XMM; 936 op->bytes = 16; 937 op->addr.xmm = reg; 938 read_sse_reg(ctxt, &op->vec_val, reg); 939 return; 940 } 941 if (ctxt->d & Mmx) { 942 reg &= 7; 943 op->type = OP_MM; 944 op->bytes = 8; 945 op->addr.mm = reg; 946 return; 947 } 948 949 op->type = OP_REG; 950 if (ctxt->d & ByteOp) { 951 op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs); 952 op->bytes = 1; 953 } else { 954 op->addr.reg = decode_register(reg, ctxt->regs, 0); 955 op->bytes = ctxt->op_bytes; 956 } 957 fetch_register_operand(op); 958 op->orig_val = op->val; 959 } 960 961 static int decode_modrm(struct x86_emulate_ctxt *ctxt, 962 struct operand *op) 963 { 964 u8 sib; 965 int index_reg = 0, base_reg = 0, scale; 966 int rc = X86EMUL_CONTINUE; 967 ulong modrm_ea = 0; 968 969 if (ctxt->rex_prefix) { 970 ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1; /* REX.R */ 971 index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */ 972 ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */ 973 } 974 975 ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6; 976 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3; 977 ctxt->modrm_rm |= (ctxt->modrm & 0x07); 978 ctxt->modrm_seg = VCPU_SREG_DS; 979 980 if (ctxt->modrm_mod == 3) { 981 op->type = OP_REG; 982 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 983 op->addr.reg = decode_register(ctxt->modrm_rm, 984 ctxt->regs, ctxt->d & ByteOp); 985 if (ctxt->d & Sse) { 986 op->type = OP_XMM; 987 op->bytes = 16; 988 op->addr.xmm = ctxt->modrm_rm; 989 read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm); 990 return rc; 991 } 992 if (ctxt->d & Mmx) { 993 op->type = OP_MM; 994 op->bytes = 8; 995 op->addr.xmm = ctxt->modrm_rm & 7; 996 return rc; 997 } 998 fetch_register_operand(op); 999 return rc; 1000 } 1001 1002 op->type = OP_MEM; 1003 1004 if (ctxt->ad_bytes == 2) { 1005 unsigned bx = ctxt->regs[VCPU_REGS_RBX]; 1006 unsigned bp = ctxt->regs[VCPU_REGS_RBP]; 1007 unsigned si = ctxt->regs[VCPU_REGS_RSI]; 1008 unsigned di = ctxt->regs[VCPU_REGS_RDI]; 1009 1010 /* 16-bit ModR/M decode. */ 1011 switch (ctxt->modrm_mod) { 1012 case 0: 1013 if (ctxt->modrm_rm == 6) 1014 modrm_ea += insn_fetch(u16, ctxt); 1015 break; 1016 case 1: 1017 modrm_ea += insn_fetch(s8, ctxt); 1018 break; 1019 case 2: 1020 modrm_ea += insn_fetch(u16, ctxt); 1021 break; 1022 } 1023 switch (ctxt->modrm_rm) { 1024 case 0: 1025 modrm_ea += bx + si; 1026 break; 1027 case 1: 1028 modrm_ea += bx + di; 1029 break; 1030 case 2: 1031 modrm_ea += bp + si; 1032 break; 1033 case 3: 1034 modrm_ea += bp + di; 1035 break; 1036 case 4: 1037 modrm_ea += si; 1038 break; 1039 case 5: 1040 modrm_ea += di; 1041 break; 1042 case 6: 1043 if (ctxt->modrm_mod != 0) 1044 modrm_ea += bp; 1045 break; 1046 case 7: 1047 modrm_ea += bx; 1048 break; 1049 } 1050 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 || 1051 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0)) 1052 ctxt->modrm_seg = VCPU_SREG_SS; 1053 modrm_ea = (u16)modrm_ea; 1054 } else { 1055 /* 32/64-bit ModR/M decode. */ 1056 if ((ctxt->modrm_rm & 7) == 4) { 1057 sib = insn_fetch(u8, ctxt); 1058 index_reg |= (sib >> 3) & 7; 1059 base_reg |= sib & 7; 1060 scale = sib >> 6; 1061 1062 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0) 1063 modrm_ea += insn_fetch(s32, ctxt); 1064 else 1065 modrm_ea += ctxt->regs[base_reg]; 1066 if (index_reg != 4) 1067 modrm_ea += ctxt->regs[index_reg] << scale; 1068 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) { 1069 if (ctxt->mode == X86EMUL_MODE_PROT64) 1070 ctxt->rip_relative = 1; 1071 } else 1072 modrm_ea += ctxt->regs[ctxt->modrm_rm]; 1073 switch (ctxt->modrm_mod) { 1074 case 0: 1075 if (ctxt->modrm_rm == 5) 1076 modrm_ea += insn_fetch(s32, ctxt); 1077 break; 1078 case 1: 1079 modrm_ea += insn_fetch(s8, ctxt); 1080 break; 1081 case 2: 1082 modrm_ea += insn_fetch(s32, ctxt); 1083 break; 1084 } 1085 } 1086 op->addr.mem.ea = modrm_ea; 1087 done: 1088 return rc; 1089 } 1090 1091 static int decode_abs(struct x86_emulate_ctxt *ctxt, 1092 struct operand *op) 1093 { 1094 int rc = X86EMUL_CONTINUE; 1095 1096 op->type = OP_MEM; 1097 switch (ctxt->ad_bytes) { 1098 case 2: 1099 op->addr.mem.ea = insn_fetch(u16, ctxt); 1100 break; 1101 case 4: 1102 op->addr.mem.ea = insn_fetch(u32, ctxt); 1103 break; 1104 case 8: 1105 op->addr.mem.ea = insn_fetch(u64, ctxt); 1106 break; 1107 } 1108 done: 1109 return rc; 1110 } 1111 1112 static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt) 1113 { 1114 long sv = 0, mask; 1115 1116 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) { 1117 mask = ~(ctxt->dst.bytes * 8 - 1); 1118 1119 if (ctxt->src.bytes == 2) 1120 sv = (s16)ctxt->src.val & (s16)mask; 1121 else if (ctxt->src.bytes == 4) 1122 sv = (s32)ctxt->src.val & (s32)mask; 1123 1124 ctxt->dst.addr.mem.ea += (sv >> 3); 1125 } 1126 1127 /* only subword offset */ 1128 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; 1129 } 1130 1131 static int read_emulated(struct x86_emulate_ctxt *ctxt, 1132 unsigned long addr, void *dest, unsigned size) 1133 { 1134 int rc; 1135 struct read_cache *mc = &ctxt->mem_read; 1136 1137 while (size) { 1138 int n = min(size, 8u); 1139 size -= n; 1140 if (mc->pos < mc->end) 1141 goto read_cached; 1142 1143 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n, 1144 &ctxt->exception); 1145 if (rc != X86EMUL_CONTINUE) 1146 return rc; 1147 mc->end += n; 1148 1149 read_cached: 1150 memcpy(dest, mc->data + mc->pos, n); 1151 mc->pos += n; 1152 dest += n; 1153 addr += n; 1154 } 1155 return X86EMUL_CONTINUE; 1156 } 1157 1158 static int segmented_read(struct x86_emulate_ctxt *ctxt, 1159 struct segmented_address addr, 1160 void *data, 1161 unsigned size) 1162 { 1163 int rc; 1164 ulong linear; 1165 1166 rc = linearize(ctxt, addr, size, false, &linear); 1167 if (rc != X86EMUL_CONTINUE) 1168 return rc; 1169 return read_emulated(ctxt, linear, data, size); 1170 } 1171 1172 static int segmented_write(struct x86_emulate_ctxt *ctxt, 1173 struct segmented_address addr, 1174 const void *data, 1175 unsigned size) 1176 { 1177 int rc; 1178 ulong linear; 1179 1180 rc = linearize(ctxt, addr, size, true, &linear); 1181 if (rc != X86EMUL_CONTINUE) 1182 return rc; 1183 return ctxt->ops->write_emulated(ctxt, linear, data, size, 1184 &ctxt->exception); 1185 } 1186 1187 static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt, 1188 struct segmented_address addr, 1189 const void *orig_data, const void *data, 1190 unsigned size) 1191 { 1192 int rc; 1193 ulong linear; 1194 1195 rc = linearize(ctxt, addr, size, true, &linear); 1196 if (rc != X86EMUL_CONTINUE) 1197 return rc; 1198 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data, 1199 size, &ctxt->exception); 1200 } 1201 1202 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, 1203 unsigned int size, unsigned short port, 1204 void *dest) 1205 { 1206 struct read_cache *rc = &ctxt->io_read; 1207 1208 if (rc->pos == rc->end) { /* refill pio read ahead */ 1209 unsigned int in_page, n; 1210 unsigned int count = ctxt->rep_prefix ? 1211 address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) : 1; 1212 in_page = (ctxt->eflags & EFLG_DF) ? 1213 offset_in_page(ctxt->regs[VCPU_REGS_RDI]) : 1214 PAGE_SIZE - offset_in_page(ctxt->regs[VCPU_REGS_RDI]); 1215 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size, 1216 count); 1217 if (n == 0) 1218 n = 1; 1219 rc->pos = rc->end = 0; 1220 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n)) 1221 return 0; 1222 rc->end = n * size; 1223 } 1224 1225 memcpy(dest, rc->data + rc->pos, size); 1226 rc->pos += size; 1227 return 1; 1228 } 1229 1230 static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt, 1231 u16 index, struct desc_struct *desc) 1232 { 1233 struct desc_ptr dt; 1234 ulong addr; 1235 1236 ctxt->ops->get_idt(ctxt, &dt); 1237 1238 if (dt.size < index * 8 + 7) 1239 return emulate_gp(ctxt, index << 3 | 0x2); 1240 1241 addr = dt.address + index * 8; 1242 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc, 1243 &ctxt->exception); 1244 } 1245 1246 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, 1247 u16 selector, struct desc_ptr *dt) 1248 { 1249 struct x86_emulate_ops *ops = ctxt->ops; 1250 1251 if (selector & 1 << 2) { 1252 struct desc_struct desc; 1253 u16 sel; 1254 1255 memset (dt, 0, sizeof *dt); 1256 if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR)) 1257 return; 1258 1259 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ 1260 dt->address = get_desc_base(&desc); 1261 } else 1262 ops->get_gdt(ctxt, dt); 1263 } 1264 1265 /* allowed just for 8 bytes segments */ 1266 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1267 u16 selector, struct desc_struct *desc) 1268 { 1269 struct desc_ptr dt; 1270 u16 index = selector >> 3; 1271 ulong addr; 1272 1273 get_descriptor_table_ptr(ctxt, selector, &dt); 1274 1275 if (dt.size < index * 8 + 7) 1276 return emulate_gp(ctxt, selector & 0xfffc); 1277 1278 addr = dt.address + index * 8; 1279 return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc, 1280 &ctxt->exception); 1281 } 1282 1283 /* allowed just for 8 bytes segments */ 1284 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1285 u16 selector, struct desc_struct *desc) 1286 { 1287 struct desc_ptr dt; 1288 u16 index = selector >> 3; 1289 ulong addr; 1290 1291 get_descriptor_table_ptr(ctxt, selector, &dt); 1292 1293 if (dt.size < index * 8 + 7) 1294 return emulate_gp(ctxt, selector & 0xfffc); 1295 1296 addr = dt.address + index * 8; 1297 return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc, 1298 &ctxt->exception); 1299 } 1300 1301 /* Does not support long mode */ 1302 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1303 u16 selector, int seg) 1304 { 1305 struct desc_struct seg_desc; 1306 u8 dpl, rpl, cpl; 1307 unsigned err_vec = GP_VECTOR; 1308 u32 err_code = 0; 1309 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ 1310 int ret; 1311 1312 memset(&seg_desc, 0, sizeof seg_desc); 1313 1314 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) 1315 || ctxt->mode == X86EMUL_MODE_REAL) { 1316 /* set real mode segment descriptor */ 1317 set_desc_base(&seg_desc, selector << 4); 1318 set_desc_limit(&seg_desc, 0xffff); 1319 seg_desc.type = 3; 1320 seg_desc.p = 1; 1321 seg_desc.s = 1; 1322 if (ctxt->mode == X86EMUL_MODE_VM86) 1323 seg_desc.dpl = 3; 1324 goto load; 1325 } 1326 1327 /* NULL selector is not valid for TR, CS and SS */ 1328 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR) 1329 && null_selector) 1330 goto exception; 1331 1332 /* TR should be in GDT only */ 1333 if (seg == VCPU_SREG_TR && (selector & (1 << 2))) 1334 goto exception; 1335 1336 if (null_selector) /* for NULL selector skip all following checks */ 1337 goto load; 1338 1339 ret = read_segment_descriptor(ctxt, selector, &seg_desc); 1340 if (ret != X86EMUL_CONTINUE) 1341 return ret; 1342 1343 err_code = selector & 0xfffc; 1344 err_vec = GP_VECTOR; 1345 1346 /* can't load system descriptor into segment selecor */ 1347 if (seg <= VCPU_SREG_GS && !seg_desc.s) 1348 goto exception; 1349 1350 if (!seg_desc.p) { 1351 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; 1352 goto exception; 1353 } 1354 1355 rpl = selector & 3; 1356 dpl = seg_desc.dpl; 1357 cpl = ctxt->ops->cpl(ctxt); 1358 1359 switch (seg) { 1360 case VCPU_SREG_SS: 1361 /* 1362 * segment is not a writable data segment or segment 1363 * selector's RPL != CPL or segment selector's RPL != CPL 1364 */ 1365 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) 1366 goto exception; 1367 break; 1368 case VCPU_SREG_CS: 1369 if (!(seg_desc.type & 8)) 1370 goto exception; 1371 1372 if (seg_desc.type & 4) { 1373 /* conforming */ 1374 if (dpl > cpl) 1375 goto exception; 1376 } else { 1377 /* nonconforming */ 1378 if (rpl > cpl || dpl != cpl) 1379 goto exception; 1380 } 1381 /* CS(RPL) <- CPL */ 1382 selector = (selector & 0xfffc) | cpl; 1383 break; 1384 case VCPU_SREG_TR: 1385 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) 1386 goto exception; 1387 break; 1388 case VCPU_SREG_LDTR: 1389 if (seg_desc.s || seg_desc.type != 2) 1390 goto exception; 1391 break; 1392 default: /* DS, ES, FS, or GS */ 1393 /* 1394 * segment is not a data or readable code segment or 1395 * ((segment is a data or nonconforming code segment) 1396 * and (both RPL and CPL > DPL)) 1397 */ 1398 if ((seg_desc.type & 0xa) == 0x8 || 1399 (((seg_desc.type & 0xc) != 0xc) && 1400 (rpl > dpl && cpl > dpl))) 1401 goto exception; 1402 break; 1403 } 1404 1405 if (seg_desc.s) { 1406 /* mark segment as accessed */ 1407 seg_desc.type |= 1; 1408 ret = write_segment_descriptor(ctxt, selector, &seg_desc); 1409 if (ret != X86EMUL_CONTINUE) 1410 return ret; 1411 } 1412 load: 1413 ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg); 1414 return X86EMUL_CONTINUE; 1415 exception: 1416 emulate_exception(ctxt, err_vec, err_code, true); 1417 return X86EMUL_PROPAGATE_FAULT; 1418 } 1419 1420 static void write_register_operand(struct operand *op) 1421 { 1422 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ 1423 switch (op->bytes) { 1424 case 1: 1425 *(u8 *)op->addr.reg = (u8)op->val; 1426 break; 1427 case 2: 1428 *(u16 *)op->addr.reg = (u16)op->val; 1429 break; 1430 case 4: 1431 *op->addr.reg = (u32)op->val; 1432 break; /* 64b: zero-extend */ 1433 case 8: 1434 *op->addr.reg = op->val; 1435 break; 1436 } 1437 } 1438 1439 static int writeback(struct x86_emulate_ctxt *ctxt) 1440 { 1441 int rc; 1442 1443 switch (ctxt->dst.type) { 1444 case OP_REG: 1445 write_register_operand(&ctxt->dst); 1446 break; 1447 case OP_MEM: 1448 if (ctxt->lock_prefix) 1449 rc = segmented_cmpxchg(ctxt, 1450 ctxt->dst.addr.mem, 1451 &ctxt->dst.orig_val, 1452 &ctxt->dst.val, 1453 ctxt->dst.bytes); 1454 else 1455 rc = segmented_write(ctxt, 1456 ctxt->dst.addr.mem, 1457 &ctxt->dst.val, 1458 ctxt->dst.bytes); 1459 if (rc != X86EMUL_CONTINUE) 1460 return rc; 1461 break; 1462 case OP_XMM: 1463 write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm); 1464 break; 1465 case OP_MM: 1466 write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm); 1467 break; 1468 case OP_NONE: 1469 /* no writeback */ 1470 break; 1471 default: 1472 break; 1473 } 1474 return X86EMUL_CONTINUE; 1475 } 1476 1477 static int em_push(struct x86_emulate_ctxt *ctxt) 1478 { 1479 struct segmented_address addr; 1480 1481 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -ctxt->op_bytes); 1482 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]); 1483 addr.seg = VCPU_SREG_SS; 1484 1485 /* Disable writeback. */ 1486 ctxt->dst.type = OP_NONE; 1487 return segmented_write(ctxt, addr, &ctxt->src.val, ctxt->op_bytes); 1488 } 1489 1490 static int emulate_pop(struct x86_emulate_ctxt *ctxt, 1491 void *dest, int len) 1492 { 1493 int rc; 1494 struct segmented_address addr; 1495 1496 addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]); 1497 addr.seg = VCPU_SREG_SS; 1498 rc = segmented_read(ctxt, addr, dest, len); 1499 if (rc != X86EMUL_CONTINUE) 1500 return rc; 1501 1502 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len); 1503 return rc; 1504 } 1505 1506 static int em_pop(struct x86_emulate_ctxt *ctxt) 1507 { 1508 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1509 } 1510 1511 static int emulate_popf(struct x86_emulate_ctxt *ctxt, 1512 void *dest, int len) 1513 { 1514 int rc; 1515 unsigned long val, change_mask; 1516 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; 1517 int cpl = ctxt->ops->cpl(ctxt); 1518 1519 rc = emulate_pop(ctxt, &val, len); 1520 if (rc != X86EMUL_CONTINUE) 1521 return rc; 1522 1523 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF 1524 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID; 1525 1526 switch(ctxt->mode) { 1527 case X86EMUL_MODE_PROT64: 1528 case X86EMUL_MODE_PROT32: 1529 case X86EMUL_MODE_PROT16: 1530 if (cpl == 0) 1531 change_mask |= EFLG_IOPL; 1532 if (cpl <= iopl) 1533 change_mask |= EFLG_IF; 1534 break; 1535 case X86EMUL_MODE_VM86: 1536 if (iopl < 3) 1537 return emulate_gp(ctxt, 0); 1538 change_mask |= EFLG_IF; 1539 break; 1540 default: /* real mode */ 1541 change_mask |= (EFLG_IOPL | EFLG_IF); 1542 break; 1543 } 1544 1545 *(unsigned long *)dest = 1546 (ctxt->eflags & ~change_mask) | (val & change_mask); 1547 1548 return rc; 1549 } 1550 1551 static int em_popf(struct x86_emulate_ctxt *ctxt) 1552 { 1553 ctxt->dst.type = OP_REG; 1554 ctxt->dst.addr.reg = &ctxt->eflags; 1555 ctxt->dst.bytes = ctxt->op_bytes; 1556 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1557 } 1558 1559 static int em_push_sreg(struct x86_emulate_ctxt *ctxt) 1560 { 1561 int seg = ctxt->src2.val; 1562 1563 ctxt->src.val = get_segment_selector(ctxt, seg); 1564 1565 return em_push(ctxt); 1566 } 1567 1568 static int em_pop_sreg(struct x86_emulate_ctxt *ctxt) 1569 { 1570 int seg = ctxt->src2.val; 1571 unsigned long selector; 1572 int rc; 1573 1574 rc = emulate_pop(ctxt, &selector, ctxt->op_bytes); 1575 if (rc != X86EMUL_CONTINUE) 1576 return rc; 1577 1578 rc = load_segment_descriptor(ctxt, (u16)selector, seg); 1579 return rc; 1580 } 1581 1582 static int em_pusha(struct x86_emulate_ctxt *ctxt) 1583 { 1584 unsigned long old_esp = ctxt->regs[VCPU_REGS_RSP]; 1585 int rc = X86EMUL_CONTINUE; 1586 int reg = VCPU_REGS_RAX; 1587 1588 while (reg <= VCPU_REGS_RDI) { 1589 (reg == VCPU_REGS_RSP) ? 1590 (ctxt->src.val = old_esp) : (ctxt->src.val = ctxt->regs[reg]); 1591 1592 rc = em_push(ctxt); 1593 if (rc != X86EMUL_CONTINUE) 1594 return rc; 1595 1596 ++reg; 1597 } 1598 1599 return rc; 1600 } 1601 1602 static int em_pushf(struct x86_emulate_ctxt *ctxt) 1603 { 1604 ctxt->src.val = (unsigned long)ctxt->eflags; 1605 return em_push(ctxt); 1606 } 1607 1608 static int em_popa(struct x86_emulate_ctxt *ctxt) 1609 { 1610 int rc = X86EMUL_CONTINUE; 1611 int reg = VCPU_REGS_RDI; 1612 1613 while (reg >= VCPU_REGS_RAX) { 1614 if (reg == VCPU_REGS_RSP) { 1615 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], 1616 ctxt->op_bytes); 1617 --reg; 1618 } 1619 1620 rc = emulate_pop(ctxt, &ctxt->regs[reg], ctxt->op_bytes); 1621 if (rc != X86EMUL_CONTINUE) 1622 break; 1623 --reg; 1624 } 1625 return rc; 1626 } 1627 1628 int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) 1629 { 1630 struct x86_emulate_ops *ops = ctxt->ops; 1631 int rc; 1632 struct desc_ptr dt; 1633 gva_t cs_addr; 1634 gva_t eip_addr; 1635 u16 cs, eip; 1636 1637 /* TODO: Add limit checks */ 1638 ctxt->src.val = ctxt->eflags; 1639 rc = em_push(ctxt); 1640 if (rc != X86EMUL_CONTINUE) 1641 return rc; 1642 1643 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC); 1644 1645 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS); 1646 rc = em_push(ctxt); 1647 if (rc != X86EMUL_CONTINUE) 1648 return rc; 1649 1650 ctxt->src.val = ctxt->_eip; 1651 rc = em_push(ctxt); 1652 if (rc != X86EMUL_CONTINUE) 1653 return rc; 1654 1655 ops->get_idt(ctxt, &dt); 1656 1657 eip_addr = dt.address + (irq << 2); 1658 cs_addr = dt.address + (irq << 2) + 2; 1659 1660 rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception); 1661 if (rc != X86EMUL_CONTINUE) 1662 return rc; 1663 1664 rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception); 1665 if (rc != X86EMUL_CONTINUE) 1666 return rc; 1667 1668 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS); 1669 if (rc != X86EMUL_CONTINUE) 1670 return rc; 1671 1672 ctxt->_eip = eip; 1673 1674 return rc; 1675 } 1676 1677 static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq) 1678 { 1679 switch(ctxt->mode) { 1680 case X86EMUL_MODE_REAL: 1681 return emulate_int_real(ctxt, irq); 1682 case X86EMUL_MODE_VM86: 1683 case X86EMUL_MODE_PROT16: 1684 case X86EMUL_MODE_PROT32: 1685 case X86EMUL_MODE_PROT64: 1686 default: 1687 /* Protected mode interrupts unimplemented yet */ 1688 return X86EMUL_UNHANDLEABLE; 1689 } 1690 } 1691 1692 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt) 1693 { 1694 int rc = X86EMUL_CONTINUE; 1695 unsigned long temp_eip = 0; 1696 unsigned long temp_eflags = 0; 1697 unsigned long cs = 0; 1698 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF | 1699 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF | 1700 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */ 1701 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP; 1702 1703 /* TODO: Add stack limit check */ 1704 1705 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes); 1706 1707 if (rc != X86EMUL_CONTINUE) 1708 return rc; 1709 1710 if (temp_eip & ~0xffff) 1711 return emulate_gp(ctxt, 0); 1712 1713 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 1714 1715 if (rc != X86EMUL_CONTINUE) 1716 return rc; 1717 1718 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes); 1719 1720 if (rc != X86EMUL_CONTINUE) 1721 return rc; 1722 1723 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); 1724 1725 if (rc != X86EMUL_CONTINUE) 1726 return rc; 1727 1728 ctxt->_eip = temp_eip; 1729 1730 1731 if (ctxt->op_bytes == 4) 1732 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); 1733 else if (ctxt->op_bytes == 2) { 1734 ctxt->eflags &= ~0xffff; 1735 ctxt->eflags |= temp_eflags; 1736 } 1737 1738 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ 1739 ctxt->eflags |= EFLG_RESERVED_ONE_MASK; 1740 1741 return rc; 1742 } 1743 1744 static int em_iret(struct x86_emulate_ctxt *ctxt) 1745 { 1746 switch(ctxt->mode) { 1747 case X86EMUL_MODE_REAL: 1748 return emulate_iret_real(ctxt); 1749 case X86EMUL_MODE_VM86: 1750 case X86EMUL_MODE_PROT16: 1751 case X86EMUL_MODE_PROT32: 1752 case X86EMUL_MODE_PROT64: 1753 default: 1754 /* iret from protected mode unimplemented yet */ 1755 return X86EMUL_UNHANDLEABLE; 1756 } 1757 } 1758 1759 static int em_jmp_far(struct x86_emulate_ctxt *ctxt) 1760 { 1761 int rc; 1762 unsigned short sel; 1763 1764 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 1765 1766 rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS); 1767 if (rc != X86EMUL_CONTINUE) 1768 return rc; 1769 1770 ctxt->_eip = 0; 1771 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes); 1772 return X86EMUL_CONTINUE; 1773 } 1774 1775 static int em_grp2(struct x86_emulate_ctxt *ctxt) 1776 { 1777 switch (ctxt->modrm_reg) { 1778 case 0: /* rol */ 1779 emulate_2op_SrcB(ctxt, "rol"); 1780 break; 1781 case 1: /* ror */ 1782 emulate_2op_SrcB(ctxt, "ror"); 1783 break; 1784 case 2: /* rcl */ 1785 emulate_2op_SrcB(ctxt, "rcl"); 1786 break; 1787 case 3: /* rcr */ 1788 emulate_2op_SrcB(ctxt, "rcr"); 1789 break; 1790 case 4: /* sal/shl */ 1791 case 6: /* sal/shl */ 1792 emulate_2op_SrcB(ctxt, "sal"); 1793 break; 1794 case 5: /* shr */ 1795 emulate_2op_SrcB(ctxt, "shr"); 1796 break; 1797 case 7: /* sar */ 1798 emulate_2op_SrcB(ctxt, "sar"); 1799 break; 1800 } 1801 return X86EMUL_CONTINUE; 1802 } 1803 1804 static int em_not(struct x86_emulate_ctxt *ctxt) 1805 { 1806 ctxt->dst.val = ~ctxt->dst.val; 1807 return X86EMUL_CONTINUE; 1808 } 1809 1810 static int em_neg(struct x86_emulate_ctxt *ctxt) 1811 { 1812 emulate_1op(ctxt, "neg"); 1813 return X86EMUL_CONTINUE; 1814 } 1815 1816 static int em_mul_ex(struct x86_emulate_ctxt *ctxt) 1817 { 1818 u8 ex = 0; 1819 1820 emulate_1op_rax_rdx(ctxt, "mul", ex); 1821 return X86EMUL_CONTINUE; 1822 } 1823 1824 static int em_imul_ex(struct x86_emulate_ctxt *ctxt) 1825 { 1826 u8 ex = 0; 1827 1828 emulate_1op_rax_rdx(ctxt, "imul", ex); 1829 return X86EMUL_CONTINUE; 1830 } 1831 1832 static int em_div_ex(struct x86_emulate_ctxt *ctxt) 1833 { 1834 u8 de = 0; 1835 1836 emulate_1op_rax_rdx(ctxt, "div", de); 1837 if (de) 1838 return emulate_de(ctxt); 1839 return X86EMUL_CONTINUE; 1840 } 1841 1842 static int em_idiv_ex(struct x86_emulate_ctxt *ctxt) 1843 { 1844 u8 de = 0; 1845 1846 emulate_1op_rax_rdx(ctxt, "idiv", de); 1847 if (de) 1848 return emulate_de(ctxt); 1849 return X86EMUL_CONTINUE; 1850 } 1851 1852 static int em_grp45(struct x86_emulate_ctxt *ctxt) 1853 { 1854 int rc = X86EMUL_CONTINUE; 1855 1856 switch (ctxt->modrm_reg) { 1857 case 0: /* inc */ 1858 emulate_1op(ctxt, "inc"); 1859 break; 1860 case 1: /* dec */ 1861 emulate_1op(ctxt, "dec"); 1862 break; 1863 case 2: /* call near abs */ { 1864 long int old_eip; 1865 old_eip = ctxt->_eip; 1866 ctxt->_eip = ctxt->src.val; 1867 ctxt->src.val = old_eip; 1868 rc = em_push(ctxt); 1869 break; 1870 } 1871 case 4: /* jmp abs */ 1872 ctxt->_eip = ctxt->src.val; 1873 break; 1874 case 5: /* jmp far */ 1875 rc = em_jmp_far(ctxt); 1876 break; 1877 case 6: /* push */ 1878 rc = em_push(ctxt); 1879 break; 1880 } 1881 return rc; 1882 } 1883 1884 static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt) 1885 { 1886 u64 old = ctxt->dst.orig_val64; 1887 1888 if (((u32) (old >> 0) != (u32) ctxt->regs[VCPU_REGS_RAX]) || 1889 ((u32) (old >> 32) != (u32) ctxt->regs[VCPU_REGS_RDX])) { 1890 ctxt->regs[VCPU_REGS_RAX] = (u32) (old >> 0); 1891 ctxt->regs[VCPU_REGS_RDX] = (u32) (old >> 32); 1892 ctxt->eflags &= ~EFLG_ZF; 1893 } else { 1894 ctxt->dst.val64 = ((u64)ctxt->regs[VCPU_REGS_RCX] << 32) | 1895 (u32) ctxt->regs[VCPU_REGS_RBX]; 1896 1897 ctxt->eflags |= EFLG_ZF; 1898 } 1899 return X86EMUL_CONTINUE; 1900 } 1901 1902 static int em_ret(struct x86_emulate_ctxt *ctxt) 1903 { 1904 ctxt->dst.type = OP_REG; 1905 ctxt->dst.addr.reg = &ctxt->_eip; 1906 ctxt->dst.bytes = ctxt->op_bytes; 1907 return em_pop(ctxt); 1908 } 1909 1910 static int em_ret_far(struct x86_emulate_ctxt *ctxt) 1911 { 1912 int rc; 1913 unsigned long cs; 1914 1915 rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes); 1916 if (rc != X86EMUL_CONTINUE) 1917 return rc; 1918 if (ctxt->op_bytes == 4) 1919 ctxt->_eip = (u32)ctxt->_eip; 1920 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 1921 if (rc != X86EMUL_CONTINUE) 1922 return rc; 1923 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); 1924 return rc; 1925 } 1926 1927 static int em_cmpxchg(struct x86_emulate_ctxt *ctxt) 1928 { 1929 /* Save real source value, then compare EAX against destination. */ 1930 ctxt->src.orig_val = ctxt->src.val; 1931 ctxt->src.val = ctxt->regs[VCPU_REGS_RAX]; 1932 emulate_2op_SrcV(ctxt, "cmp"); 1933 1934 if (ctxt->eflags & EFLG_ZF) { 1935 /* Success: write back to memory. */ 1936 ctxt->dst.val = ctxt->src.orig_val; 1937 } else { 1938 /* Failure: write the value we saw to EAX. */ 1939 ctxt->dst.type = OP_REG; 1940 ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX]; 1941 } 1942 return X86EMUL_CONTINUE; 1943 } 1944 1945 static int em_lseg(struct x86_emulate_ctxt *ctxt) 1946 { 1947 int seg = ctxt->src2.val; 1948 unsigned short sel; 1949 int rc; 1950 1951 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 1952 1953 rc = load_segment_descriptor(ctxt, sel, seg); 1954 if (rc != X86EMUL_CONTINUE) 1955 return rc; 1956 1957 ctxt->dst.val = ctxt->src.val; 1958 return rc; 1959 } 1960 1961 static void 1962 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt, 1963 struct desc_struct *cs, struct desc_struct *ss) 1964 { 1965 u16 selector; 1966 1967 memset(cs, 0, sizeof(struct desc_struct)); 1968 ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS); 1969 memset(ss, 0, sizeof(struct desc_struct)); 1970 1971 cs->l = 0; /* will be adjusted later */ 1972 set_desc_base(cs, 0); /* flat segment */ 1973 cs->g = 1; /* 4kb granularity */ 1974 set_desc_limit(cs, 0xfffff); /* 4GB limit */ 1975 cs->type = 0x0b; /* Read, Execute, Accessed */ 1976 cs->s = 1; 1977 cs->dpl = 0; /* will be adjusted later */ 1978 cs->p = 1; 1979 cs->d = 1; 1980 1981 set_desc_base(ss, 0); /* flat segment */ 1982 set_desc_limit(ss, 0xfffff); /* 4GB limit */ 1983 ss->g = 1; /* 4kb granularity */ 1984 ss->s = 1; 1985 ss->type = 0x03; /* Read/Write, Accessed */ 1986 ss->d = 1; /* 32bit stack segment */ 1987 ss->dpl = 0; 1988 ss->p = 1; 1989 } 1990 1991 static bool vendor_intel(struct x86_emulate_ctxt *ctxt) 1992 { 1993 u32 eax, ebx, ecx, edx; 1994 1995 eax = ecx = 0; 1996 return ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx) 1997 && ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx 1998 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx 1999 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx; 2000 } 2001 2002 static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt) 2003 { 2004 struct x86_emulate_ops *ops = ctxt->ops; 2005 u32 eax, ebx, ecx, edx; 2006 2007 /* 2008 * syscall should always be enabled in longmode - so only become 2009 * vendor specific (cpuid) if other modes are active... 2010 */ 2011 if (ctxt->mode == X86EMUL_MODE_PROT64) 2012 return true; 2013 2014 eax = 0x00000000; 2015 ecx = 0x00000000; 2016 if (ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx)) { 2017 /* 2018 * Intel ("GenuineIntel") 2019 * remark: Intel CPUs only support "syscall" in 64bit 2020 * longmode. Also an 64bit guest with a 2021 * 32bit compat-app running will #UD !! While this 2022 * behaviour can be fixed (by emulating) into AMD 2023 * response - CPUs of AMD can't behave like Intel. 2024 */ 2025 if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx && 2026 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx && 2027 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx) 2028 return false; 2029 2030 /* AMD ("AuthenticAMD") */ 2031 if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx && 2032 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx && 2033 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx) 2034 return true; 2035 2036 /* AMD ("AMDisbetter!") */ 2037 if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx && 2038 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx && 2039 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx) 2040 return true; 2041 } 2042 2043 /* default: (not Intel, not AMD), apply Intel's stricter rules... */ 2044 return false; 2045 } 2046 2047 static int em_syscall(struct x86_emulate_ctxt *ctxt) 2048 { 2049 struct x86_emulate_ops *ops = ctxt->ops; 2050 struct desc_struct cs, ss; 2051 u64 msr_data; 2052 u16 cs_sel, ss_sel; 2053 u64 efer = 0; 2054 2055 /* syscall is not available in real mode */ 2056 if (ctxt->mode == X86EMUL_MODE_REAL || 2057 ctxt->mode == X86EMUL_MODE_VM86) 2058 return emulate_ud(ctxt); 2059 2060 if (!(em_syscall_is_enabled(ctxt))) 2061 return emulate_ud(ctxt); 2062 2063 ops->get_msr(ctxt, MSR_EFER, &efer); 2064 setup_syscalls_segments(ctxt, &cs, &ss); 2065 2066 if (!(efer & EFER_SCE)) 2067 return emulate_ud(ctxt); 2068 2069 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2070 msr_data >>= 32; 2071 cs_sel = (u16)(msr_data & 0xfffc); 2072 ss_sel = (u16)(msr_data + 8); 2073 2074 if (efer & EFER_LMA) { 2075 cs.d = 0; 2076 cs.l = 1; 2077 } 2078 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2079 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2080 2081 ctxt->regs[VCPU_REGS_RCX] = ctxt->_eip; 2082 if (efer & EFER_LMA) { 2083 #ifdef CONFIG_X86_64 2084 ctxt->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF; 2085 2086 ops->get_msr(ctxt, 2087 ctxt->mode == X86EMUL_MODE_PROT64 ? 2088 MSR_LSTAR : MSR_CSTAR, &msr_data); 2089 ctxt->_eip = msr_data; 2090 2091 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data); 2092 ctxt->eflags &= ~(msr_data | EFLG_RF); 2093 #endif 2094 } else { 2095 /* legacy mode */ 2096 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2097 ctxt->_eip = (u32)msr_data; 2098 2099 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); 2100 } 2101 2102 return X86EMUL_CONTINUE; 2103 } 2104 2105 static int em_sysenter(struct x86_emulate_ctxt *ctxt) 2106 { 2107 struct x86_emulate_ops *ops = ctxt->ops; 2108 struct desc_struct cs, ss; 2109 u64 msr_data; 2110 u16 cs_sel, ss_sel; 2111 u64 efer = 0; 2112 2113 ops->get_msr(ctxt, MSR_EFER, &efer); 2114 /* inject #GP if in real mode */ 2115 if (ctxt->mode == X86EMUL_MODE_REAL) 2116 return emulate_gp(ctxt, 0); 2117 2118 /* 2119 * Not recognized on AMD in compat mode (but is recognized in legacy 2120 * mode). 2121 */ 2122 if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA) 2123 && !vendor_intel(ctxt)) 2124 return emulate_ud(ctxt); 2125 2126 /* XXX sysenter/sysexit have not been tested in 64bit mode. 2127 * Therefore, we inject an #UD. 2128 */ 2129 if (ctxt->mode == X86EMUL_MODE_PROT64) 2130 return emulate_ud(ctxt); 2131 2132 setup_syscalls_segments(ctxt, &cs, &ss); 2133 2134 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2135 switch (ctxt->mode) { 2136 case X86EMUL_MODE_PROT32: 2137 if ((msr_data & 0xfffc) == 0x0) 2138 return emulate_gp(ctxt, 0); 2139 break; 2140 case X86EMUL_MODE_PROT64: 2141 if (msr_data == 0x0) 2142 return emulate_gp(ctxt, 0); 2143 break; 2144 } 2145 2146 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF); 2147 cs_sel = (u16)msr_data; 2148 cs_sel &= ~SELECTOR_RPL_MASK; 2149 ss_sel = cs_sel + 8; 2150 ss_sel &= ~SELECTOR_RPL_MASK; 2151 if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) { 2152 cs.d = 0; 2153 cs.l = 1; 2154 } 2155 2156 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2157 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2158 2159 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data); 2160 ctxt->_eip = msr_data; 2161 2162 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data); 2163 ctxt->regs[VCPU_REGS_RSP] = msr_data; 2164 2165 return X86EMUL_CONTINUE; 2166 } 2167 2168 static int em_sysexit(struct x86_emulate_ctxt *ctxt) 2169 { 2170 struct x86_emulate_ops *ops = ctxt->ops; 2171 struct desc_struct cs, ss; 2172 u64 msr_data; 2173 int usermode; 2174 u16 cs_sel = 0, ss_sel = 0; 2175 2176 /* inject #GP if in real mode or Virtual 8086 mode */ 2177 if (ctxt->mode == X86EMUL_MODE_REAL || 2178 ctxt->mode == X86EMUL_MODE_VM86) 2179 return emulate_gp(ctxt, 0); 2180 2181 setup_syscalls_segments(ctxt, &cs, &ss); 2182 2183 if ((ctxt->rex_prefix & 0x8) != 0x0) 2184 usermode = X86EMUL_MODE_PROT64; 2185 else 2186 usermode = X86EMUL_MODE_PROT32; 2187 2188 cs.dpl = 3; 2189 ss.dpl = 3; 2190 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2191 switch (usermode) { 2192 case X86EMUL_MODE_PROT32: 2193 cs_sel = (u16)(msr_data + 16); 2194 if ((msr_data & 0xfffc) == 0x0) 2195 return emulate_gp(ctxt, 0); 2196 ss_sel = (u16)(msr_data + 24); 2197 break; 2198 case X86EMUL_MODE_PROT64: 2199 cs_sel = (u16)(msr_data + 32); 2200 if (msr_data == 0x0) 2201 return emulate_gp(ctxt, 0); 2202 ss_sel = cs_sel + 8; 2203 cs.d = 0; 2204 cs.l = 1; 2205 break; 2206 } 2207 cs_sel |= SELECTOR_RPL_MASK; 2208 ss_sel |= SELECTOR_RPL_MASK; 2209 2210 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2211 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2212 2213 ctxt->_eip = ctxt->regs[VCPU_REGS_RDX]; 2214 ctxt->regs[VCPU_REGS_RSP] = ctxt->regs[VCPU_REGS_RCX]; 2215 2216 return X86EMUL_CONTINUE; 2217 } 2218 2219 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt) 2220 { 2221 int iopl; 2222 if (ctxt->mode == X86EMUL_MODE_REAL) 2223 return false; 2224 if (ctxt->mode == X86EMUL_MODE_VM86) 2225 return true; 2226 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; 2227 return ctxt->ops->cpl(ctxt) > iopl; 2228 } 2229 2230 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, 2231 u16 port, u16 len) 2232 { 2233 struct x86_emulate_ops *ops = ctxt->ops; 2234 struct desc_struct tr_seg; 2235 u32 base3; 2236 int r; 2237 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7; 2238 unsigned mask = (1 << len) - 1; 2239 unsigned long base; 2240 2241 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR); 2242 if (!tr_seg.p) 2243 return false; 2244 if (desc_limit_scaled(&tr_seg) < 103) 2245 return false; 2246 base = get_desc_base(&tr_seg); 2247 #ifdef CONFIG_X86_64 2248 base |= ((u64)base3) << 32; 2249 #endif 2250 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL); 2251 if (r != X86EMUL_CONTINUE) 2252 return false; 2253 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) 2254 return false; 2255 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL); 2256 if (r != X86EMUL_CONTINUE) 2257 return false; 2258 if ((perm >> bit_idx) & mask) 2259 return false; 2260 return true; 2261 } 2262 2263 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, 2264 u16 port, u16 len) 2265 { 2266 if (ctxt->perm_ok) 2267 return true; 2268 2269 if (emulator_bad_iopl(ctxt)) 2270 if (!emulator_io_port_access_allowed(ctxt, port, len)) 2271 return false; 2272 2273 ctxt->perm_ok = true; 2274 2275 return true; 2276 } 2277 2278 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, 2279 struct tss_segment_16 *tss) 2280 { 2281 tss->ip = ctxt->_eip; 2282 tss->flag = ctxt->eflags; 2283 tss->ax = ctxt->regs[VCPU_REGS_RAX]; 2284 tss->cx = ctxt->regs[VCPU_REGS_RCX]; 2285 tss->dx = ctxt->regs[VCPU_REGS_RDX]; 2286 tss->bx = ctxt->regs[VCPU_REGS_RBX]; 2287 tss->sp = ctxt->regs[VCPU_REGS_RSP]; 2288 tss->bp = ctxt->regs[VCPU_REGS_RBP]; 2289 tss->si = ctxt->regs[VCPU_REGS_RSI]; 2290 tss->di = ctxt->regs[VCPU_REGS_RDI]; 2291 2292 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 2293 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 2294 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 2295 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 2296 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR); 2297 } 2298 2299 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, 2300 struct tss_segment_16 *tss) 2301 { 2302 int ret; 2303 2304 ctxt->_eip = tss->ip; 2305 ctxt->eflags = tss->flag | 2; 2306 ctxt->regs[VCPU_REGS_RAX] = tss->ax; 2307 ctxt->regs[VCPU_REGS_RCX] = tss->cx; 2308 ctxt->regs[VCPU_REGS_RDX] = tss->dx; 2309 ctxt->regs[VCPU_REGS_RBX] = tss->bx; 2310 ctxt->regs[VCPU_REGS_RSP] = tss->sp; 2311 ctxt->regs[VCPU_REGS_RBP] = tss->bp; 2312 ctxt->regs[VCPU_REGS_RSI] = tss->si; 2313 ctxt->regs[VCPU_REGS_RDI] = tss->di; 2314 2315 /* 2316 * SDM says that segment selectors are loaded before segment 2317 * descriptors 2318 */ 2319 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR); 2320 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 2321 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 2322 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 2323 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 2324 2325 /* 2326 * Now load segment descriptors. If fault happenes at this stage 2327 * it is handled in a context of new task 2328 */ 2329 ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR); 2330 if (ret != X86EMUL_CONTINUE) 2331 return ret; 2332 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES); 2333 if (ret != X86EMUL_CONTINUE) 2334 return ret; 2335 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS); 2336 if (ret != X86EMUL_CONTINUE) 2337 return ret; 2338 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS); 2339 if (ret != X86EMUL_CONTINUE) 2340 return ret; 2341 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS); 2342 if (ret != X86EMUL_CONTINUE) 2343 return ret; 2344 2345 return X86EMUL_CONTINUE; 2346 } 2347 2348 static int task_switch_16(struct x86_emulate_ctxt *ctxt, 2349 u16 tss_selector, u16 old_tss_sel, 2350 ulong old_tss_base, struct desc_struct *new_desc) 2351 { 2352 struct x86_emulate_ops *ops = ctxt->ops; 2353 struct tss_segment_16 tss_seg; 2354 int ret; 2355 u32 new_tss_base = get_desc_base(new_desc); 2356 2357 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, 2358 &ctxt->exception); 2359 if (ret != X86EMUL_CONTINUE) 2360 /* FIXME: need to provide precise fault address */ 2361 return ret; 2362 2363 save_state_to_tss16(ctxt, &tss_seg); 2364 2365 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, 2366 &ctxt->exception); 2367 if (ret != X86EMUL_CONTINUE) 2368 /* FIXME: need to provide precise fault address */ 2369 return ret; 2370 2371 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, 2372 &ctxt->exception); 2373 if (ret != X86EMUL_CONTINUE) 2374 /* FIXME: need to provide precise fault address */ 2375 return ret; 2376 2377 if (old_tss_sel != 0xffff) { 2378 tss_seg.prev_task_link = old_tss_sel; 2379 2380 ret = ops->write_std(ctxt, new_tss_base, 2381 &tss_seg.prev_task_link, 2382 sizeof tss_seg.prev_task_link, 2383 &ctxt->exception); 2384 if (ret != X86EMUL_CONTINUE) 2385 /* FIXME: need to provide precise fault address */ 2386 return ret; 2387 } 2388 2389 return load_state_from_tss16(ctxt, &tss_seg); 2390 } 2391 2392 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, 2393 struct tss_segment_32 *tss) 2394 { 2395 tss->cr3 = ctxt->ops->get_cr(ctxt, 3); 2396 tss->eip = ctxt->_eip; 2397 tss->eflags = ctxt->eflags; 2398 tss->eax = ctxt->regs[VCPU_REGS_RAX]; 2399 tss->ecx = ctxt->regs[VCPU_REGS_RCX]; 2400 tss->edx = ctxt->regs[VCPU_REGS_RDX]; 2401 tss->ebx = ctxt->regs[VCPU_REGS_RBX]; 2402 tss->esp = ctxt->regs[VCPU_REGS_RSP]; 2403 tss->ebp = ctxt->regs[VCPU_REGS_RBP]; 2404 tss->esi = ctxt->regs[VCPU_REGS_RSI]; 2405 tss->edi = ctxt->regs[VCPU_REGS_RDI]; 2406 2407 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 2408 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 2409 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 2410 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 2411 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS); 2412 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS); 2413 tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR); 2414 } 2415 2416 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, 2417 struct tss_segment_32 *tss) 2418 { 2419 int ret; 2420 2421 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3)) 2422 return emulate_gp(ctxt, 0); 2423 ctxt->_eip = tss->eip; 2424 ctxt->eflags = tss->eflags | 2; 2425 2426 /* General purpose registers */ 2427 ctxt->regs[VCPU_REGS_RAX] = tss->eax; 2428 ctxt->regs[VCPU_REGS_RCX] = tss->ecx; 2429 ctxt->regs[VCPU_REGS_RDX] = tss->edx; 2430 ctxt->regs[VCPU_REGS_RBX] = tss->ebx; 2431 ctxt->regs[VCPU_REGS_RSP] = tss->esp; 2432 ctxt->regs[VCPU_REGS_RBP] = tss->ebp; 2433 ctxt->regs[VCPU_REGS_RSI] = tss->esi; 2434 ctxt->regs[VCPU_REGS_RDI] = tss->edi; 2435 2436 /* 2437 * SDM says that segment selectors are loaded before segment 2438 * descriptors 2439 */ 2440 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); 2441 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 2442 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 2443 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 2444 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 2445 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS); 2446 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS); 2447 2448 /* 2449 * If we're switching between Protected Mode and VM86, we need to make 2450 * sure to update the mode before loading the segment descriptors so 2451 * that the selectors are interpreted correctly. 2452 * 2453 * Need to get rflags to the vcpu struct immediately because it 2454 * influences the CPL which is checked at least when loading the segment 2455 * descriptors and when pushing an error code to the new kernel stack. 2456 * 2457 * TODO Introduce a separate ctxt->ops->set_cpl callback 2458 */ 2459 if (ctxt->eflags & X86_EFLAGS_VM) 2460 ctxt->mode = X86EMUL_MODE_VM86; 2461 else 2462 ctxt->mode = X86EMUL_MODE_PROT32; 2463 2464 ctxt->ops->set_rflags(ctxt, ctxt->eflags); 2465 2466 /* 2467 * Now load segment descriptors. If fault happenes at this stage 2468 * it is handled in a context of new task 2469 */ 2470 ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); 2471 if (ret != X86EMUL_CONTINUE) 2472 return ret; 2473 ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES); 2474 if (ret != X86EMUL_CONTINUE) 2475 return ret; 2476 ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS); 2477 if (ret != X86EMUL_CONTINUE) 2478 return ret; 2479 ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS); 2480 if (ret != X86EMUL_CONTINUE) 2481 return ret; 2482 ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS); 2483 if (ret != X86EMUL_CONTINUE) 2484 return ret; 2485 ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS); 2486 if (ret != X86EMUL_CONTINUE) 2487 return ret; 2488 ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS); 2489 if (ret != X86EMUL_CONTINUE) 2490 return ret; 2491 2492 return X86EMUL_CONTINUE; 2493 } 2494 2495 static int task_switch_32(struct x86_emulate_ctxt *ctxt, 2496 u16 tss_selector, u16 old_tss_sel, 2497 ulong old_tss_base, struct desc_struct *new_desc) 2498 { 2499 struct x86_emulate_ops *ops = ctxt->ops; 2500 struct tss_segment_32 tss_seg; 2501 int ret; 2502 u32 new_tss_base = get_desc_base(new_desc); 2503 2504 ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, 2505 &ctxt->exception); 2506 if (ret != X86EMUL_CONTINUE) 2507 /* FIXME: need to provide precise fault address */ 2508 return ret; 2509 2510 save_state_to_tss32(ctxt, &tss_seg); 2511 2512 ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg, 2513 &ctxt->exception); 2514 if (ret != X86EMUL_CONTINUE) 2515 /* FIXME: need to provide precise fault address */ 2516 return ret; 2517 2518 ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg, 2519 &ctxt->exception); 2520 if (ret != X86EMUL_CONTINUE) 2521 /* FIXME: need to provide precise fault address */ 2522 return ret; 2523 2524 if (old_tss_sel != 0xffff) { 2525 tss_seg.prev_task_link = old_tss_sel; 2526 2527 ret = ops->write_std(ctxt, new_tss_base, 2528 &tss_seg.prev_task_link, 2529 sizeof tss_seg.prev_task_link, 2530 &ctxt->exception); 2531 if (ret != X86EMUL_CONTINUE) 2532 /* FIXME: need to provide precise fault address */ 2533 return ret; 2534 } 2535 2536 return load_state_from_tss32(ctxt, &tss_seg); 2537 } 2538 2539 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, 2540 u16 tss_selector, int idt_index, int reason, 2541 bool has_error_code, u32 error_code) 2542 { 2543 struct x86_emulate_ops *ops = ctxt->ops; 2544 struct desc_struct curr_tss_desc, next_tss_desc; 2545 int ret; 2546 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR); 2547 ulong old_tss_base = 2548 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR); 2549 u32 desc_limit; 2550 2551 /* FIXME: old_tss_base == ~0 ? */ 2552 2553 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc); 2554 if (ret != X86EMUL_CONTINUE) 2555 return ret; 2556 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); 2557 if (ret != X86EMUL_CONTINUE) 2558 return ret; 2559 2560 /* FIXME: check that next_tss_desc is tss */ 2561 2562 /* 2563 * Check privileges. The three cases are task switch caused by... 2564 * 2565 * 1. jmp/call/int to task gate: Check against DPL of the task gate 2566 * 2. Exception/IRQ/iret: No check is performed 2567 * 3. jmp/call to TSS: Check agains DPL of the TSS 2568 */ 2569 if (reason == TASK_SWITCH_GATE) { 2570 if (idt_index != -1) { 2571 /* Software interrupts */ 2572 struct desc_struct task_gate_desc; 2573 int dpl; 2574 2575 ret = read_interrupt_descriptor(ctxt, idt_index, 2576 &task_gate_desc); 2577 if (ret != X86EMUL_CONTINUE) 2578 return ret; 2579 2580 dpl = task_gate_desc.dpl; 2581 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) 2582 return emulate_gp(ctxt, (idt_index << 3) | 0x2); 2583 } 2584 } else if (reason != TASK_SWITCH_IRET) { 2585 int dpl = next_tss_desc.dpl; 2586 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) 2587 return emulate_gp(ctxt, tss_selector); 2588 } 2589 2590 2591 desc_limit = desc_limit_scaled(&next_tss_desc); 2592 if (!next_tss_desc.p || 2593 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || 2594 desc_limit < 0x2b)) { 2595 emulate_ts(ctxt, tss_selector & 0xfffc); 2596 return X86EMUL_PROPAGATE_FAULT; 2597 } 2598 2599 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { 2600 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ 2601 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); 2602 } 2603 2604 if (reason == TASK_SWITCH_IRET) 2605 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; 2606 2607 /* set back link to prev task only if NT bit is set in eflags 2608 note that old_tss_sel is not used afetr this point */ 2609 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) 2610 old_tss_sel = 0xffff; 2611 2612 if (next_tss_desc.type & 8) 2613 ret = task_switch_32(ctxt, tss_selector, old_tss_sel, 2614 old_tss_base, &next_tss_desc); 2615 else 2616 ret = task_switch_16(ctxt, tss_selector, old_tss_sel, 2617 old_tss_base, &next_tss_desc); 2618 if (ret != X86EMUL_CONTINUE) 2619 return ret; 2620 2621 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) 2622 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; 2623 2624 if (reason != TASK_SWITCH_IRET) { 2625 next_tss_desc.type |= (1 << 1); /* set busy flag */ 2626 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc); 2627 } 2628 2629 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS); 2630 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR); 2631 2632 if (has_error_code) { 2633 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; 2634 ctxt->lock_prefix = 0; 2635 ctxt->src.val = (unsigned long) error_code; 2636 ret = em_push(ctxt); 2637 } 2638 2639 return ret; 2640 } 2641 2642 int emulator_task_switch(struct x86_emulate_ctxt *ctxt, 2643 u16 tss_selector, int idt_index, int reason, 2644 bool has_error_code, u32 error_code) 2645 { 2646 int rc; 2647 2648 ctxt->_eip = ctxt->eip; 2649 ctxt->dst.type = OP_NONE; 2650 2651 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason, 2652 has_error_code, error_code); 2653 2654 if (rc == X86EMUL_CONTINUE) 2655 ctxt->eip = ctxt->_eip; 2656 2657 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 2658 } 2659 2660 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg, 2661 int reg, struct operand *op) 2662 { 2663 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1; 2664 2665 register_address_increment(ctxt, &ctxt->regs[reg], df * op->bytes); 2666 op->addr.mem.ea = register_address(ctxt, ctxt->regs[reg]); 2667 op->addr.mem.seg = seg; 2668 } 2669 2670 static int em_das(struct x86_emulate_ctxt *ctxt) 2671 { 2672 u8 al, old_al; 2673 bool af, cf, old_cf; 2674 2675 cf = ctxt->eflags & X86_EFLAGS_CF; 2676 al = ctxt->dst.val; 2677 2678 old_al = al; 2679 old_cf = cf; 2680 cf = false; 2681 af = ctxt->eflags & X86_EFLAGS_AF; 2682 if ((al & 0x0f) > 9 || af) { 2683 al -= 6; 2684 cf = old_cf | (al >= 250); 2685 af = true; 2686 } else { 2687 af = false; 2688 } 2689 if (old_al > 0x99 || old_cf) { 2690 al -= 0x60; 2691 cf = true; 2692 } 2693 2694 ctxt->dst.val = al; 2695 /* Set PF, ZF, SF */ 2696 ctxt->src.type = OP_IMM; 2697 ctxt->src.val = 0; 2698 ctxt->src.bytes = 1; 2699 emulate_2op_SrcV(ctxt, "or"); 2700 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); 2701 if (cf) 2702 ctxt->eflags |= X86_EFLAGS_CF; 2703 if (af) 2704 ctxt->eflags |= X86_EFLAGS_AF; 2705 return X86EMUL_CONTINUE; 2706 } 2707 2708 static int em_call(struct x86_emulate_ctxt *ctxt) 2709 { 2710 long rel = ctxt->src.val; 2711 2712 ctxt->src.val = (unsigned long)ctxt->_eip; 2713 jmp_rel(ctxt, rel); 2714 return em_push(ctxt); 2715 } 2716 2717 static int em_call_far(struct x86_emulate_ctxt *ctxt) 2718 { 2719 u16 sel, old_cs; 2720 ulong old_eip; 2721 int rc; 2722 2723 old_cs = get_segment_selector(ctxt, VCPU_SREG_CS); 2724 old_eip = ctxt->_eip; 2725 2726 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2727 if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS)) 2728 return X86EMUL_CONTINUE; 2729 2730 ctxt->_eip = 0; 2731 memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes); 2732 2733 ctxt->src.val = old_cs; 2734 rc = em_push(ctxt); 2735 if (rc != X86EMUL_CONTINUE) 2736 return rc; 2737 2738 ctxt->src.val = old_eip; 2739 return em_push(ctxt); 2740 } 2741 2742 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) 2743 { 2744 int rc; 2745 2746 ctxt->dst.type = OP_REG; 2747 ctxt->dst.addr.reg = &ctxt->_eip; 2748 ctxt->dst.bytes = ctxt->op_bytes; 2749 rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); 2750 if (rc != X86EMUL_CONTINUE) 2751 return rc; 2752 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val); 2753 return X86EMUL_CONTINUE; 2754 } 2755 2756 static int em_add(struct x86_emulate_ctxt *ctxt) 2757 { 2758 emulate_2op_SrcV(ctxt, "add"); 2759 return X86EMUL_CONTINUE; 2760 } 2761 2762 static int em_or(struct x86_emulate_ctxt *ctxt) 2763 { 2764 emulate_2op_SrcV(ctxt, "or"); 2765 return X86EMUL_CONTINUE; 2766 } 2767 2768 static int em_adc(struct x86_emulate_ctxt *ctxt) 2769 { 2770 emulate_2op_SrcV(ctxt, "adc"); 2771 return X86EMUL_CONTINUE; 2772 } 2773 2774 static int em_sbb(struct x86_emulate_ctxt *ctxt) 2775 { 2776 emulate_2op_SrcV(ctxt, "sbb"); 2777 return X86EMUL_CONTINUE; 2778 } 2779 2780 static int em_and(struct x86_emulate_ctxt *ctxt) 2781 { 2782 emulate_2op_SrcV(ctxt, "and"); 2783 return X86EMUL_CONTINUE; 2784 } 2785 2786 static int em_sub(struct x86_emulate_ctxt *ctxt) 2787 { 2788 emulate_2op_SrcV(ctxt, "sub"); 2789 return X86EMUL_CONTINUE; 2790 } 2791 2792 static int em_xor(struct x86_emulate_ctxt *ctxt) 2793 { 2794 emulate_2op_SrcV(ctxt, "xor"); 2795 return X86EMUL_CONTINUE; 2796 } 2797 2798 static int em_cmp(struct x86_emulate_ctxt *ctxt) 2799 { 2800 emulate_2op_SrcV(ctxt, "cmp"); 2801 /* Disable writeback. */ 2802 ctxt->dst.type = OP_NONE; 2803 return X86EMUL_CONTINUE; 2804 } 2805 2806 static int em_test(struct x86_emulate_ctxt *ctxt) 2807 { 2808 emulate_2op_SrcV(ctxt, "test"); 2809 /* Disable writeback. */ 2810 ctxt->dst.type = OP_NONE; 2811 return X86EMUL_CONTINUE; 2812 } 2813 2814 static int em_xchg(struct x86_emulate_ctxt *ctxt) 2815 { 2816 /* Write back the register source. */ 2817 ctxt->src.val = ctxt->dst.val; 2818 write_register_operand(&ctxt->src); 2819 2820 /* Write back the memory destination with implicit LOCK prefix. */ 2821 ctxt->dst.val = ctxt->src.orig_val; 2822 ctxt->lock_prefix = 1; 2823 return X86EMUL_CONTINUE; 2824 } 2825 2826 static int em_imul(struct x86_emulate_ctxt *ctxt) 2827 { 2828 emulate_2op_SrcV_nobyte(ctxt, "imul"); 2829 return X86EMUL_CONTINUE; 2830 } 2831 2832 static int em_imul_3op(struct x86_emulate_ctxt *ctxt) 2833 { 2834 ctxt->dst.val = ctxt->src2.val; 2835 return em_imul(ctxt); 2836 } 2837 2838 static int em_cwd(struct x86_emulate_ctxt *ctxt) 2839 { 2840 ctxt->dst.type = OP_REG; 2841 ctxt->dst.bytes = ctxt->src.bytes; 2842 ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX]; 2843 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1); 2844 2845 return X86EMUL_CONTINUE; 2846 } 2847 2848 static int em_rdtsc(struct x86_emulate_ctxt *ctxt) 2849 { 2850 u64 tsc = 0; 2851 2852 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc); 2853 ctxt->regs[VCPU_REGS_RAX] = (u32)tsc; 2854 ctxt->regs[VCPU_REGS_RDX] = tsc >> 32; 2855 return X86EMUL_CONTINUE; 2856 } 2857 2858 static int em_rdpmc(struct x86_emulate_ctxt *ctxt) 2859 { 2860 u64 pmc; 2861 2862 if (ctxt->ops->read_pmc(ctxt, ctxt->regs[VCPU_REGS_RCX], &pmc)) 2863 return emulate_gp(ctxt, 0); 2864 ctxt->regs[VCPU_REGS_RAX] = (u32)pmc; 2865 ctxt->regs[VCPU_REGS_RDX] = pmc >> 32; 2866 return X86EMUL_CONTINUE; 2867 } 2868 2869 static int em_mov(struct x86_emulate_ctxt *ctxt) 2870 { 2871 memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes); 2872 return X86EMUL_CONTINUE; 2873 } 2874 2875 static int em_cr_write(struct x86_emulate_ctxt *ctxt) 2876 { 2877 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) 2878 return emulate_gp(ctxt, 0); 2879 2880 /* Disable writeback. */ 2881 ctxt->dst.type = OP_NONE; 2882 return X86EMUL_CONTINUE; 2883 } 2884 2885 static int em_dr_write(struct x86_emulate_ctxt *ctxt) 2886 { 2887 unsigned long val; 2888 2889 if (ctxt->mode == X86EMUL_MODE_PROT64) 2890 val = ctxt->src.val & ~0ULL; 2891 else 2892 val = ctxt->src.val & ~0U; 2893 2894 /* #UD condition is already handled. */ 2895 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0) 2896 return emulate_gp(ctxt, 0); 2897 2898 /* Disable writeback. */ 2899 ctxt->dst.type = OP_NONE; 2900 return X86EMUL_CONTINUE; 2901 } 2902 2903 static int em_wrmsr(struct x86_emulate_ctxt *ctxt) 2904 { 2905 u64 msr_data; 2906 2907 msr_data = (u32)ctxt->regs[VCPU_REGS_RAX] 2908 | ((u64)ctxt->regs[VCPU_REGS_RDX] << 32); 2909 if (ctxt->ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data)) 2910 return emulate_gp(ctxt, 0); 2911 2912 return X86EMUL_CONTINUE; 2913 } 2914 2915 static int em_rdmsr(struct x86_emulate_ctxt *ctxt) 2916 { 2917 u64 msr_data; 2918 2919 if (ctxt->ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data)) 2920 return emulate_gp(ctxt, 0); 2921 2922 ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data; 2923 ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32; 2924 return X86EMUL_CONTINUE; 2925 } 2926 2927 static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt) 2928 { 2929 if (ctxt->modrm_reg > VCPU_SREG_GS) 2930 return emulate_ud(ctxt); 2931 2932 ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg); 2933 return X86EMUL_CONTINUE; 2934 } 2935 2936 static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt) 2937 { 2938 u16 sel = ctxt->src.val; 2939 2940 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS) 2941 return emulate_ud(ctxt); 2942 2943 if (ctxt->modrm_reg == VCPU_SREG_SS) 2944 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; 2945 2946 /* Disable writeback. */ 2947 ctxt->dst.type = OP_NONE; 2948 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg); 2949 } 2950 2951 static int em_invlpg(struct x86_emulate_ctxt *ctxt) 2952 { 2953 int rc; 2954 ulong linear; 2955 2956 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear); 2957 if (rc == X86EMUL_CONTINUE) 2958 ctxt->ops->invlpg(ctxt, linear); 2959 /* Disable writeback. */ 2960 ctxt->dst.type = OP_NONE; 2961 return X86EMUL_CONTINUE; 2962 } 2963 2964 static int em_clts(struct x86_emulate_ctxt *ctxt) 2965 { 2966 ulong cr0; 2967 2968 cr0 = ctxt->ops->get_cr(ctxt, 0); 2969 cr0 &= ~X86_CR0_TS; 2970 ctxt->ops->set_cr(ctxt, 0, cr0); 2971 return X86EMUL_CONTINUE; 2972 } 2973 2974 static int em_vmcall(struct x86_emulate_ctxt *ctxt) 2975 { 2976 int rc; 2977 2978 if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1) 2979 return X86EMUL_UNHANDLEABLE; 2980 2981 rc = ctxt->ops->fix_hypercall(ctxt); 2982 if (rc != X86EMUL_CONTINUE) 2983 return rc; 2984 2985 /* Let the processor re-execute the fixed hypercall */ 2986 ctxt->_eip = ctxt->eip; 2987 /* Disable writeback. */ 2988 ctxt->dst.type = OP_NONE; 2989 return X86EMUL_CONTINUE; 2990 } 2991 2992 static int em_lgdt(struct x86_emulate_ctxt *ctxt) 2993 { 2994 struct desc_ptr desc_ptr; 2995 int rc; 2996 2997 rc = read_descriptor(ctxt, ctxt->src.addr.mem, 2998 &desc_ptr.size, &desc_ptr.address, 2999 ctxt->op_bytes); 3000 if (rc != X86EMUL_CONTINUE) 3001 return rc; 3002 ctxt->ops->set_gdt(ctxt, &desc_ptr); 3003 /* Disable writeback. */ 3004 ctxt->dst.type = OP_NONE; 3005 return X86EMUL_CONTINUE; 3006 } 3007 3008 static int em_vmmcall(struct x86_emulate_ctxt *ctxt) 3009 { 3010 int rc; 3011 3012 rc = ctxt->ops->fix_hypercall(ctxt); 3013 3014 /* Disable writeback. */ 3015 ctxt->dst.type = OP_NONE; 3016 return rc; 3017 } 3018 3019 static int em_lidt(struct x86_emulate_ctxt *ctxt) 3020 { 3021 struct desc_ptr desc_ptr; 3022 int rc; 3023 3024 rc = read_descriptor(ctxt, ctxt->src.addr.mem, 3025 &desc_ptr.size, &desc_ptr.address, 3026 ctxt->op_bytes); 3027 if (rc != X86EMUL_CONTINUE) 3028 return rc; 3029 ctxt->ops->set_idt(ctxt, &desc_ptr); 3030 /* Disable writeback. */ 3031 ctxt->dst.type = OP_NONE; 3032 return X86EMUL_CONTINUE; 3033 } 3034 3035 static int em_smsw(struct x86_emulate_ctxt *ctxt) 3036 { 3037 ctxt->dst.bytes = 2; 3038 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0); 3039 return X86EMUL_CONTINUE; 3040 } 3041 3042 static int em_lmsw(struct x86_emulate_ctxt *ctxt) 3043 { 3044 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul) 3045 | (ctxt->src.val & 0x0f)); 3046 ctxt->dst.type = OP_NONE; 3047 return X86EMUL_CONTINUE; 3048 } 3049 3050 static int em_loop(struct x86_emulate_ctxt *ctxt) 3051 { 3052 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1); 3053 if ((address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) != 0) && 3054 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags))) 3055 jmp_rel(ctxt, ctxt->src.val); 3056 3057 return X86EMUL_CONTINUE; 3058 } 3059 3060 static int em_jcxz(struct x86_emulate_ctxt *ctxt) 3061 { 3062 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) 3063 jmp_rel(ctxt, ctxt->src.val); 3064 3065 return X86EMUL_CONTINUE; 3066 } 3067 3068 static int em_in(struct x86_emulate_ctxt *ctxt) 3069 { 3070 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val, 3071 &ctxt->dst.val)) 3072 return X86EMUL_IO_NEEDED; 3073 3074 return X86EMUL_CONTINUE; 3075 } 3076 3077 static int em_out(struct x86_emulate_ctxt *ctxt) 3078 { 3079 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val, 3080 &ctxt->src.val, 1); 3081 /* Disable writeback. */ 3082 ctxt->dst.type = OP_NONE; 3083 return X86EMUL_CONTINUE; 3084 } 3085 3086 static int em_cli(struct x86_emulate_ctxt *ctxt) 3087 { 3088 if (emulator_bad_iopl(ctxt)) 3089 return emulate_gp(ctxt, 0); 3090 3091 ctxt->eflags &= ~X86_EFLAGS_IF; 3092 return X86EMUL_CONTINUE; 3093 } 3094 3095 static int em_sti(struct x86_emulate_ctxt *ctxt) 3096 { 3097 if (emulator_bad_iopl(ctxt)) 3098 return emulate_gp(ctxt, 0); 3099 3100 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; 3101 ctxt->eflags |= X86_EFLAGS_IF; 3102 return X86EMUL_CONTINUE; 3103 } 3104 3105 static int em_bt(struct x86_emulate_ctxt *ctxt) 3106 { 3107 /* Disable writeback. */ 3108 ctxt->dst.type = OP_NONE; 3109 /* only subword offset */ 3110 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; 3111 3112 emulate_2op_SrcV_nobyte(ctxt, "bt"); 3113 return X86EMUL_CONTINUE; 3114 } 3115 3116 static int em_bts(struct x86_emulate_ctxt *ctxt) 3117 { 3118 emulate_2op_SrcV_nobyte(ctxt, "bts"); 3119 return X86EMUL_CONTINUE; 3120 } 3121 3122 static int em_btr(struct x86_emulate_ctxt *ctxt) 3123 { 3124 emulate_2op_SrcV_nobyte(ctxt, "btr"); 3125 return X86EMUL_CONTINUE; 3126 } 3127 3128 static int em_btc(struct x86_emulate_ctxt *ctxt) 3129 { 3130 emulate_2op_SrcV_nobyte(ctxt, "btc"); 3131 return X86EMUL_CONTINUE; 3132 } 3133 3134 static int em_bsf(struct x86_emulate_ctxt *ctxt) 3135 { 3136 emulate_2op_SrcV_nobyte(ctxt, "bsf"); 3137 return X86EMUL_CONTINUE; 3138 } 3139 3140 static int em_bsr(struct x86_emulate_ctxt *ctxt) 3141 { 3142 emulate_2op_SrcV_nobyte(ctxt, "bsr"); 3143 return X86EMUL_CONTINUE; 3144 } 3145 3146 static bool valid_cr(int nr) 3147 { 3148 switch (nr) { 3149 case 0: 3150 case 2 ... 4: 3151 case 8: 3152 return true; 3153 default: 3154 return false; 3155 } 3156 } 3157 3158 static int check_cr_read(struct x86_emulate_ctxt *ctxt) 3159 { 3160 if (!valid_cr(ctxt->modrm_reg)) 3161 return emulate_ud(ctxt); 3162 3163 return X86EMUL_CONTINUE; 3164 } 3165 3166 static int check_cr_write(struct x86_emulate_ctxt *ctxt) 3167 { 3168 u64 new_val = ctxt->src.val64; 3169 int cr = ctxt->modrm_reg; 3170 u64 efer = 0; 3171 3172 static u64 cr_reserved_bits[] = { 3173 0xffffffff00000000ULL, 3174 0, 0, 0, /* CR3 checked later */ 3175 CR4_RESERVED_BITS, 3176 0, 0, 0, 3177 CR8_RESERVED_BITS, 3178 }; 3179 3180 if (!valid_cr(cr)) 3181 return emulate_ud(ctxt); 3182 3183 if (new_val & cr_reserved_bits[cr]) 3184 return emulate_gp(ctxt, 0); 3185 3186 switch (cr) { 3187 case 0: { 3188 u64 cr4; 3189 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) || 3190 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD))) 3191 return emulate_gp(ctxt, 0); 3192 3193 cr4 = ctxt->ops->get_cr(ctxt, 4); 3194 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 3195 3196 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) && 3197 !(cr4 & X86_CR4_PAE)) 3198 return emulate_gp(ctxt, 0); 3199 3200 break; 3201 } 3202 case 3: { 3203 u64 rsvd = 0; 3204 3205 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 3206 if (efer & EFER_LMA) 3207 rsvd = CR3_L_MODE_RESERVED_BITS; 3208 else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE) 3209 rsvd = CR3_PAE_RESERVED_BITS; 3210 else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG) 3211 rsvd = CR3_NONPAE_RESERVED_BITS; 3212 3213 if (new_val & rsvd) 3214 return emulate_gp(ctxt, 0); 3215 3216 break; 3217 } 3218 case 4: { 3219 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 3220 3221 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE)) 3222 return emulate_gp(ctxt, 0); 3223 3224 break; 3225 } 3226 } 3227 3228 return X86EMUL_CONTINUE; 3229 } 3230 3231 static int check_dr7_gd(struct x86_emulate_ctxt *ctxt) 3232 { 3233 unsigned long dr7; 3234 3235 ctxt->ops->get_dr(ctxt, 7, &dr7); 3236 3237 /* Check if DR7.Global_Enable is set */ 3238 return dr7 & (1 << 13); 3239 } 3240 3241 static int check_dr_read(struct x86_emulate_ctxt *ctxt) 3242 { 3243 int dr = ctxt->modrm_reg; 3244 u64 cr4; 3245 3246 if (dr > 7) 3247 return emulate_ud(ctxt); 3248 3249 cr4 = ctxt->ops->get_cr(ctxt, 4); 3250 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5)) 3251 return emulate_ud(ctxt); 3252 3253 if (check_dr7_gd(ctxt)) 3254 return emulate_db(ctxt); 3255 3256 return X86EMUL_CONTINUE; 3257 } 3258 3259 static int check_dr_write(struct x86_emulate_ctxt *ctxt) 3260 { 3261 u64 new_val = ctxt->src.val64; 3262 int dr = ctxt->modrm_reg; 3263 3264 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL)) 3265 return emulate_gp(ctxt, 0); 3266 3267 return check_dr_read(ctxt); 3268 } 3269 3270 static int check_svme(struct x86_emulate_ctxt *ctxt) 3271 { 3272 u64 efer; 3273 3274 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 3275 3276 if (!(efer & EFER_SVME)) 3277 return emulate_ud(ctxt); 3278 3279 return X86EMUL_CONTINUE; 3280 } 3281 3282 static int check_svme_pa(struct x86_emulate_ctxt *ctxt) 3283 { 3284 u64 rax = ctxt->regs[VCPU_REGS_RAX]; 3285 3286 /* Valid physical address? */ 3287 if (rax & 0xffff000000000000ULL) 3288 return emulate_gp(ctxt, 0); 3289 3290 return check_svme(ctxt); 3291 } 3292 3293 static int check_rdtsc(struct x86_emulate_ctxt *ctxt) 3294 { 3295 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 3296 3297 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt)) 3298 return emulate_ud(ctxt); 3299 3300 return X86EMUL_CONTINUE; 3301 } 3302 3303 static int check_rdpmc(struct x86_emulate_ctxt *ctxt) 3304 { 3305 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 3306 u64 rcx = ctxt->regs[VCPU_REGS_RCX]; 3307 3308 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) || 3309 (rcx > 3)) 3310 return emulate_gp(ctxt, 0); 3311 3312 return X86EMUL_CONTINUE; 3313 } 3314 3315 static int check_perm_in(struct x86_emulate_ctxt *ctxt) 3316 { 3317 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u); 3318 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes)) 3319 return emulate_gp(ctxt, 0); 3320 3321 return X86EMUL_CONTINUE; 3322 } 3323 3324 static int check_perm_out(struct x86_emulate_ctxt *ctxt) 3325 { 3326 ctxt->src.bytes = min(ctxt->src.bytes, 4u); 3327 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes)) 3328 return emulate_gp(ctxt, 0); 3329 3330 return X86EMUL_CONTINUE; 3331 } 3332 3333 #define D(_y) { .flags = (_y) } 3334 #define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i } 3335 #define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \ 3336 .check_perm = (_p) } 3337 #define N D(0) 3338 #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) } 3339 #define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) } 3340 #define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) } 3341 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } 3342 #define II(_f, _e, _i) \ 3343 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i } 3344 #define IIP(_f, _e, _i, _p) \ 3345 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \ 3346 .check_perm = (_p) } 3347 #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) } 3348 3349 #define D2bv(_f) D((_f) | ByteOp), D(_f) 3350 #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p) 3351 #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) 3352 #define I2bvIP(_f, _e, _i, _p) \ 3353 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p) 3354 3355 #define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e), \ 3356 I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \ 3357 I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e) 3358 3359 static struct opcode group7_rm1[] = { 3360 DI(SrcNone | Priv, monitor), 3361 DI(SrcNone | Priv, mwait), 3362 N, N, N, N, N, N, 3363 }; 3364 3365 static struct opcode group7_rm3[] = { 3366 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa), 3367 II(SrcNone | Prot | VendorSpecific, em_vmmcall, vmmcall), 3368 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa), 3369 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa), 3370 DIP(SrcNone | Prot | Priv, stgi, check_svme), 3371 DIP(SrcNone | Prot | Priv, clgi, check_svme), 3372 DIP(SrcNone | Prot | Priv, skinit, check_svme), 3373 DIP(SrcNone | Prot | Priv, invlpga, check_svme), 3374 }; 3375 3376 static struct opcode group7_rm7[] = { 3377 N, 3378 DIP(SrcNone, rdtscp, check_rdtsc), 3379 N, N, N, N, N, N, 3380 }; 3381 3382 static struct opcode group1[] = { 3383 I(Lock, em_add), 3384 I(Lock | PageTable, em_or), 3385 I(Lock, em_adc), 3386 I(Lock, em_sbb), 3387 I(Lock | PageTable, em_and), 3388 I(Lock, em_sub), 3389 I(Lock, em_xor), 3390 I(0, em_cmp), 3391 }; 3392 3393 static struct opcode group1A[] = { 3394 I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N, 3395 }; 3396 3397 static struct opcode group3[] = { 3398 I(DstMem | SrcImm, em_test), 3399 I(DstMem | SrcImm, em_test), 3400 I(DstMem | SrcNone | Lock, em_not), 3401 I(DstMem | SrcNone | Lock, em_neg), 3402 I(SrcMem, em_mul_ex), 3403 I(SrcMem, em_imul_ex), 3404 I(SrcMem, em_div_ex), 3405 I(SrcMem, em_idiv_ex), 3406 }; 3407 3408 static struct opcode group4[] = { 3409 I(ByteOp | DstMem | SrcNone | Lock, em_grp45), 3410 I(ByteOp | DstMem | SrcNone | Lock, em_grp45), 3411 N, N, N, N, N, N, 3412 }; 3413 3414 static struct opcode group5[] = { 3415 I(DstMem | SrcNone | Lock, em_grp45), 3416 I(DstMem | SrcNone | Lock, em_grp45), 3417 I(SrcMem | Stack, em_grp45), 3418 I(SrcMemFAddr | ImplicitOps | Stack, em_call_far), 3419 I(SrcMem | Stack, em_grp45), 3420 I(SrcMemFAddr | ImplicitOps, em_grp45), 3421 I(SrcMem | Stack, em_grp45), N, 3422 }; 3423 3424 static struct opcode group6[] = { 3425 DI(Prot, sldt), 3426 DI(Prot, str), 3427 DI(Prot | Priv, lldt), 3428 DI(Prot | Priv, ltr), 3429 N, N, N, N, 3430 }; 3431 3432 static struct group_dual group7 = { { 3433 DI(Mov | DstMem | Priv, sgdt), 3434 DI(Mov | DstMem | Priv, sidt), 3435 II(SrcMem | Priv, em_lgdt, lgdt), 3436 II(SrcMem | Priv, em_lidt, lidt), 3437 II(SrcNone | DstMem | Mov, em_smsw, smsw), N, 3438 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), 3439 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg), 3440 }, { 3441 I(SrcNone | Priv | VendorSpecific, em_vmcall), 3442 EXT(0, group7_rm1), 3443 N, EXT(0, group7_rm3), 3444 II(SrcNone | DstMem | Mov, em_smsw, smsw), N, 3445 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), 3446 EXT(0, group7_rm7), 3447 } }; 3448 3449 static struct opcode group8[] = { 3450 N, N, N, N, 3451 I(DstMem | SrcImmByte, em_bt), 3452 I(DstMem | SrcImmByte | Lock | PageTable, em_bts), 3453 I(DstMem | SrcImmByte | Lock, em_btr), 3454 I(DstMem | SrcImmByte | Lock | PageTable, em_btc), 3455 }; 3456 3457 static struct group_dual group9 = { { 3458 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N, 3459 }, { 3460 N, N, N, N, N, N, N, N, 3461 } }; 3462 3463 static struct opcode group11[] = { 3464 I(DstMem | SrcImm | Mov | PageTable, em_mov), 3465 X7(D(Undefined)), 3466 }; 3467 3468 static struct gprefix pfx_0f_6f_0f_7f = { 3469 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov), 3470 }; 3471 3472 static struct gprefix pfx_vmovntpx = { 3473 I(0, em_mov), N, N, N, 3474 }; 3475 3476 static struct opcode opcode_table[256] = { 3477 /* 0x00 - 0x07 */ 3478 I6ALU(Lock, em_add), 3479 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg), 3480 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg), 3481 /* 0x08 - 0x0F */ 3482 I6ALU(Lock | PageTable, em_or), 3483 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg), 3484 N, 3485 /* 0x10 - 0x17 */ 3486 I6ALU(Lock, em_adc), 3487 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg), 3488 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg), 3489 /* 0x18 - 0x1F */ 3490 I6ALU(Lock, em_sbb), 3491 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg), 3492 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg), 3493 /* 0x20 - 0x27 */ 3494 I6ALU(Lock | PageTable, em_and), N, N, 3495 /* 0x28 - 0x2F */ 3496 I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das), 3497 /* 0x30 - 0x37 */ 3498 I6ALU(Lock, em_xor), N, N, 3499 /* 0x38 - 0x3F */ 3500 I6ALU(0, em_cmp), N, N, 3501 /* 0x40 - 0x4F */ 3502 X16(D(DstReg)), 3503 /* 0x50 - 0x57 */ 3504 X8(I(SrcReg | Stack, em_push)), 3505 /* 0x58 - 0x5F */ 3506 X8(I(DstReg | Stack, em_pop)), 3507 /* 0x60 - 0x67 */ 3508 I(ImplicitOps | Stack | No64, em_pusha), 3509 I(ImplicitOps | Stack | No64, em_popa), 3510 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ , 3511 N, N, N, N, 3512 /* 0x68 - 0x6F */ 3513 I(SrcImm | Mov | Stack, em_push), 3514 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), 3515 I(SrcImmByte | Mov | Stack, em_push), 3516 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), 3517 I2bvIP(DstDI | SrcDX | Mov | String, em_in, ins, check_perm_in), /* insb, insw/insd */ 3518 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */ 3519 /* 0x70 - 0x7F */ 3520 X16(D(SrcImmByte)), 3521 /* 0x80 - 0x87 */ 3522 G(ByteOp | DstMem | SrcImm, group1), 3523 G(DstMem | SrcImm, group1), 3524 G(ByteOp | DstMem | SrcImm | No64, group1), 3525 G(DstMem | SrcImmByte, group1), 3526 I2bv(DstMem | SrcReg | ModRM, em_test), 3527 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg), 3528 /* 0x88 - 0x8F */ 3529 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov), 3530 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov), 3531 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg), 3532 D(ModRM | SrcMem | NoAccess | DstReg), 3533 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm), 3534 G(0, group1A), 3535 /* 0x90 - 0x97 */ 3536 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)), 3537 /* 0x98 - 0x9F */ 3538 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), 3539 I(SrcImmFAddr | No64, em_call_far), N, 3540 II(ImplicitOps | Stack, em_pushf, pushf), 3541 II(ImplicitOps | Stack, em_popf, popf), N, N, 3542 /* 0xA0 - 0xA7 */ 3543 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), 3544 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov), 3545 I2bv(SrcSI | DstDI | Mov | String, em_mov), 3546 I2bv(SrcSI | DstDI | String, em_cmp), 3547 /* 0xA8 - 0xAF */ 3548 I2bv(DstAcc | SrcImm, em_test), 3549 I2bv(SrcAcc | DstDI | Mov | String, em_mov), 3550 I2bv(SrcSI | DstAcc | Mov | String, em_mov), 3551 I2bv(SrcAcc | DstDI | String, em_cmp), 3552 /* 0xB0 - 0xB7 */ 3553 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), 3554 /* 0xB8 - 0xBF */ 3555 X8(I(DstReg | SrcImm | Mov, em_mov)), 3556 /* 0xC0 - 0xC7 */ 3557 D2bv(DstMem | SrcImmByte | ModRM), 3558 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm), 3559 I(ImplicitOps | Stack, em_ret), 3560 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg), 3561 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg), 3562 G(ByteOp, group11), G(0, group11), 3563 /* 0xC8 - 0xCF */ 3564 N, N, N, I(ImplicitOps | Stack, em_ret_far), 3565 D(ImplicitOps), DI(SrcImmByte, intn), 3566 D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret), 3567 /* 0xD0 - 0xD7 */ 3568 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM), 3569 N, N, N, N, 3570 /* 0xD8 - 0xDF */ 3571 N, N, N, N, N, N, N, N, 3572 /* 0xE0 - 0xE7 */ 3573 X3(I(SrcImmByte, em_loop)), 3574 I(SrcImmByte, em_jcxz), 3575 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in), 3576 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out), 3577 /* 0xE8 - 0xEF */ 3578 I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps), 3579 I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps), 3580 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in), 3581 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out), 3582 /* 0xF0 - 0xF7 */ 3583 N, DI(ImplicitOps, icebp), N, N, 3584 DI(ImplicitOps | Priv, hlt), D(ImplicitOps), 3585 G(ByteOp, group3), G(0, group3), 3586 /* 0xF8 - 0xFF */ 3587 D(ImplicitOps), D(ImplicitOps), 3588 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti), 3589 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), 3590 }; 3591 3592 static struct opcode twobyte_table[256] = { 3593 /* 0x00 - 0x0F */ 3594 G(0, group6), GD(0, &group7), N, N, 3595 N, I(ImplicitOps | VendorSpecific, em_syscall), 3596 II(ImplicitOps | Priv, em_clts, clts), N, 3597 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, 3598 N, D(ImplicitOps | ModRM), N, N, 3599 /* 0x10 - 0x1F */ 3600 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N, 3601 /* 0x20 - 0x2F */ 3602 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read), 3603 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read), 3604 IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write), 3605 IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write), 3606 N, N, N, N, 3607 N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx), 3608 N, N, N, N, 3609 /* 0x30 - 0x3F */ 3610 II(ImplicitOps | Priv, em_wrmsr, wrmsr), 3611 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc), 3612 II(ImplicitOps | Priv, em_rdmsr, rdmsr), 3613 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc), 3614 I(ImplicitOps | VendorSpecific, em_sysenter), 3615 I(ImplicitOps | Priv | VendorSpecific, em_sysexit), 3616 N, N, 3617 N, N, N, N, N, N, N, N, 3618 /* 0x40 - 0x4F */ 3619 X16(D(DstReg | SrcMem | ModRM | Mov)), 3620 /* 0x50 - 0x5F */ 3621 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 3622 /* 0x60 - 0x6F */ 3623 N, N, N, N, 3624 N, N, N, N, 3625 N, N, N, N, 3626 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f), 3627 /* 0x70 - 0x7F */ 3628 N, N, N, N, 3629 N, N, N, N, 3630 N, N, N, N, 3631 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f), 3632 /* 0x80 - 0x8F */ 3633 X16(D(SrcImm)), 3634 /* 0x90 - 0x9F */ 3635 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), 3636 /* 0xA0 - 0xA7 */ 3637 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg), 3638 DI(ImplicitOps, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt), 3639 D(DstMem | SrcReg | Src2ImmByte | ModRM), 3640 D(DstMem | SrcReg | Src2CL | ModRM), N, N, 3641 /* 0xA8 - 0xAF */ 3642 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg), 3643 DI(ImplicitOps, rsm), 3644 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts), 3645 D(DstMem | SrcReg | Src2ImmByte | ModRM), 3646 D(DstMem | SrcReg | Src2CL | ModRM), 3647 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul), 3648 /* 0xB0 - 0xB7 */ 3649 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg), 3650 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg), 3651 I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr), 3652 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg), 3653 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg), 3654 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 3655 /* 0xB8 - 0xBF */ 3656 N, N, 3657 G(BitOp, group8), 3658 I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc), 3659 I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr), 3660 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 3661 /* 0xC0 - 0xCF */ 3662 D2bv(DstMem | SrcReg | ModRM | Lock), 3663 N, D(DstMem | SrcReg | ModRM | Mov), 3664 N, N, N, GD(0, &group9), 3665 N, N, N, N, N, N, N, N, 3666 /* 0xD0 - 0xDF */ 3667 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 3668 /* 0xE0 - 0xEF */ 3669 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 3670 /* 0xF0 - 0xFF */ 3671 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N 3672 }; 3673 3674 #undef D 3675 #undef N 3676 #undef G 3677 #undef GD 3678 #undef I 3679 #undef GP 3680 #undef EXT 3681 3682 #undef D2bv 3683 #undef D2bvIP 3684 #undef I2bv 3685 #undef I2bvIP 3686 #undef I6ALU 3687 3688 static unsigned imm_size(struct x86_emulate_ctxt *ctxt) 3689 { 3690 unsigned size; 3691 3692 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 3693 if (size == 8) 3694 size = 4; 3695 return size; 3696 } 3697 3698 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, 3699 unsigned size, bool sign_extension) 3700 { 3701 int rc = X86EMUL_CONTINUE; 3702 3703 op->type = OP_IMM; 3704 op->bytes = size; 3705 op->addr.mem.ea = ctxt->_eip; 3706 /* NB. Immediates are sign-extended as necessary. */ 3707 switch (op->bytes) { 3708 case 1: 3709 op->val = insn_fetch(s8, ctxt); 3710 break; 3711 case 2: 3712 op->val = insn_fetch(s16, ctxt); 3713 break; 3714 case 4: 3715 op->val = insn_fetch(s32, ctxt); 3716 break; 3717 } 3718 if (!sign_extension) { 3719 switch (op->bytes) { 3720 case 1: 3721 op->val &= 0xff; 3722 break; 3723 case 2: 3724 op->val &= 0xffff; 3725 break; 3726 case 4: 3727 op->val &= 0xffffffff; 3728 break; 3729 } 3730 } 3731 done: 3732 return rc; 3733 } 3734 3735 static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op, 3736 unsigned d) 3737 { 3738 int rc = X86EMUL_CONTINUE; 3739 3740 switch (d) { 3741 case OpReg: 3742 decode_register_operand(ctxt, op); 3743 break; 3744 case OpImmUByte: 3745 rc = decode_imm(ctxt, op, 1, false); 3746 break; 3747 case OpMem: 3748 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 3749 mem_common: 3750 *op = ctxt->memop; 3751 ctxt->memopp = op; 3752 if ((ctxt->d & BitOp) && op == &ctxt->dst) 3753 fetch_bit_operand(ctxt); 3754 op->orig_val = op->val; 3755 break; 3756 case OpMem64: 3757 ctxt->memop.bytes = 8; 3758 goto mem_common; 3759 case OpAcc: 3760 op->type = OP_REG; 3761 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 3762 op->addr.reg = &ctxt->regs[VCPU_REGS_RAX]; 3763 fetch_register_operand(op); 3764 op->orig_val = op->val; 3765 break; 3766 case OpDI: 3767 op->type = OP_MEM; 3768 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 3769 op->addr.mem.ea = 3770 register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]); 3771 op->addr.mem.seg = VCPU_SREG_ES; 3772 op->val = 0; 3773 break; 3774 case OpDX: 3775 op->type = OP_REG; 3776 op->bytes = 2; 3777 op->addr.reg = &ctxt->regs[VCPU_REGS_RDX]; 3778 fetch_register_operand(op); 3779 break; 3780 case OpCL: 3781 op->bytes = 1; 3782 op->val = ctxt->regs[VCPU_REGS_RCX] & 0xff; 3783 break; 3784 case OpImmByte: 3785 rc = decode_imm(ctxt, op, 1, true); 3786 break; 3787 case OpOne: 3788 op->bytes = 1; 3789 op->val = 1; 3790 break; 3791 case OpImm: 3792 rc = decode_imm(ctxt, op, imm_size(ctxt), true); 3793 break; 3794 case OpMem8: 3795 ctxt->memop.bytes = 1; 3796 goto mem_common; 3797 case OpMem16: 3798 ctxt->memop.bytes = 2; 3799 goto mem_common; 3800 case OpMem32: 3801 ctxt->memop.bytes = 4; 3802 goto mem_common; 3803 case OpImmU16: 3804 rc = decode_imm(ctxt, op, 2, false); 3805 break; 3806 case OpImmU: 3807 rc = decode_imm(ctxt, op, imm_size(ctxt), false); 3808 break; 3809 case OpSI: 3810 op->type = OP_MEM; 3811 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 3812 op->addr.mem.ea = 3813 register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]); 3814 op->addr.mem.seg = seg_override(ctxt); 3815 op->val = 0; 3816 break; 3817 case OpImmFAddr: 3818 op->type = OP_IMM; 3819 op->addr.mem.ea = ctxt->_eip; 3820 op->bytes = ctxt->op_bytes + 2; 3821 insn_fetch_arr(op->valptr, op->bytes, ctxt); 3822 break; 3823 case OpMemFAddr: 3824 ctxt->memop.bytes = ctxt->op_bytes + 2; 3825 goto mem_common; 3826 case OpES: 3827 op->val = VCPU_SREG_ES; 3828 break; 3829 case OpCS: 3830 op->val = VCPU_SREG_CS; 3831 break; 3832 case OpSS: 3833 op->val = VCPU_SREG_SS; 3834 break; 3835 case OpDS: 3836 op->val = VCPU_SREG_DS; 3837 break; 3838 case OpFS: 3839 op->val = VCPU_SREG_FS; 3840 break; 3841 case OpGS: 3842 op->val = VCPU_SREG_GS; 3843 break; 3844 case OpImplicit: 3845 /* Special instructions do their own operand decoding. */ 3846 default: 3847 op->type = OP_NONE; /* Disable writeback. */ 3848 break; 3849 } 3850 3851 done: 3852 return rc; 3853 } 3854 3855 int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len) 3856 { 3857 int rc = X86EMUL_CONTINUE; 3858 int mode = ctxt->mode; 3859 int def_op_bytes, def_ad_bytes, goffset, simd_prefix; 3860 bool op_prefix = false; 3861 struct opcode opcode; 3862 3863 ctxt->memop.type = OP_NONE; 3864 ctxt->memopp = NULL; 3865 ctxt->_eip = ctxt->eip; 3866 ctxt->fetch.start = ctxt->_eip; 3867 ctxt->fetch.end = ctxt->fetch.start + insn_len; 3868 if (insn_len > 0) 3869 memcpy(ctxt->fetch.data, insn, insn_len); 3870 3871 switch (mode) { 3872 case X86EMUL_MODE_REAL: 3873 case X86EMUL_MODE_VM86: 3874 case X86EMUL_MODE_PROT16: 3875 def_op_bytes = def_ad_bytes = 2; 3876 break; 3877 case X86EMUL_MODE_PROT32: 3878 def_op_bytes = def_ad_bytes = 4; 3879 break; 3880 #ifdef CONFIG_X86_64 3881 case X86EMUL_MODE_PROT64: 3882 def_op_bytes = 4; 3883 def_ad_bytes = 8; 3884 break; 3885 #endif 3886 default: 3887 return EMULATION_FAILED; 3888 } 3889 3890 ctxt->op_bytes = def_op_bytes; 3891 ctxt->ad_bytes = def_ad_bytes; 3892 3893 /* Legacy prefixes. */ 3894 for (;;) { 3895 switch (ctxt->b = insn_fetch(u8, ctxt)) { 3896 case 0x66: /* operand-size override */ 3897 op_prefix = true; 3898 /* switch between 2/4 bytes */ 3899 ctxt->op_bytes = def_op_bytes ^ 6; 3900 break; 3901 case 0x67: /* address-size override */ 3902 if (mode == X86EMUL_MODE_PROT64) 3903 /* switch between 4/8 bytes */ 3904 ctxt->ad_bytes = def_ad_bytes ^ 12; 3905 else 3906 /* switch between 2/4 bytes */ 3907 ctxt->ad_bytes = def_ad_bytes ^ 6; 3908 break; 3909 case 0x26: /* ES override */ 3910 case 0x2e: /* CS override */ 3911 case 0x36: /* SS override */ 3912 case 0x3e: /* DS override */ 3913 set_seg_override(ctxt, (ctxt->b >> 3) & 3); 3914 break; 3915 case 0x64: /* FS override */ 3916 case 0x65: /* GS override */ 3917 set_seg_override(ctxt, ctxt->b & 7); 3918 break; 3919 case 0x40 ... 0x4f: /* REX */ 3920 if (mode != X86EMUL_MODE_PROT64) 3921 goto done_prefixes; 3922 ctxt->rex_prefix = ctxt->b; 3923 continue; 3924 case 0xf0: /* LOCK */ 3925 ctxt->lock_prefix = 1; 3926 break; 3927 case 0xf2: /* REPNE/REPNZ */ 3928 case 0xf3: /* REP/REPE/REPZ */ 3929 ctxt->rep_prefix = ctxt->b; 3930 break; 3931 default: 3932 goto done_prefixes; 3933 } 3934 3935 /* Any legacy prefix after a REX prefix nullifies its effect. */ 3936 3937 ctxt->rex_prefix = 0; 3938 } 3939 3940 done_prefixes: 3941 3942 /* REX prefix. */ 3943 if (ctxt->rex_prefix & 8) 3944 ctxt->op_bytes = 8; /* REX.W */ 3945 3946 /* Opcode byte(s). */ 3947 opcode = opcode_table[ctxt->b]; 3948 /* Two-byte opcode? */ 3949 if (ctxt->b == 0x0f) { 3950 ctxt->twobyte = 1; 3951 ctxt->b = insn_fetch(u8, ctxt); 3952 opcode = twobyte_table[ctxt->b]; 3953 } 3954 ctxt->d = opcode.flags; 3955 3956 if (ctxt->d & ModRM) 3957 ctxt->modrm = insn_fetch(u8, ctxt); 3958 3959 while (ctxt->d & GroupMask) { 3960 switch (ctxt->d & GroupMask) { 3961 case Group: 3962 goffset = (ctxt->modrm >> 3) & 7; 3963 opcode = opcode.u.group[goffset]; 3964 break; 3965 case GroupDual: 3966 goffset = (ctxt->modrm >> 3) & 7; 3967 if ((ctxt->modrm >> 6) == 3) 3968 opcode = opcode.u.gdual->mod3[goffset]; 3969 else 3970 opcode = opcode.u.gdual->mod012[goffset]; 3971 break; 3972 case RMExt: 3973 goffset = ctxt->modrm & 7; 3974 opcode = opcode.u.group[goffset]; 3975 break; 3976 case Prefix: 3977 if (ctxt->rep_prefix && op_prefix) 3978 return EMULATION_FAILED; 3979 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix; 3980 switch (simd_prefix) { 3981 case 0x00: opcode = opcode.u.gprefix->pfx_no; break; 3982 case 0x66: opcode = opcode.u.gprefix->pfx_66; break; 3983 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break; 3984 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break; 3985 } 3986 break; 3987 default: 3988 return EMULATION_FAILED; 3989 } 3990 3991 ctxt->d &= ~(u64)GroupMask; 3992 ctxt->d |= opcode.flags; 3993 } 3994 3995 ctxt->execute = opcode.u.execute; 3996 ctxt->check_perm = opcode.check_perm; 3997 ctxt->intercept = opcode.intercept; 3998 3999 /* Unrecognised? */ 4000 if (ctxt->d == 0 || (ctxt->d & Undefined)) 4001 return EMULATION_FAILED; 4002 4003 if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn) 4004 return EMULATION_FAILED; 4005 4006 if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack)) 4007 ctxt->op_bytes = 8; 4008 4009 if (ctxt->d & Op3264) { 4010 if (mode == X86EMUL_MODE_PROT64) 4011 ctxt->op_bytes = 8; 4012 else 4013 ctxt->op_bytes = 4; 4014 } 4015 4016 if (ctxt->d & Sse) 4017 ctxt->op_bytes = 16; 4018 else if (ctxt->d & Mmx) 4019 ctxt->op_bytes = 8; 4020 4021 /* ModRM and SIB bytes. */ 4022 if (ctxt->d & ModRM) { 4023 rc = decode_modrm(ctxt, &ctxt->memop); 4024 if (!ctxt->has_seg_override) 4025 set_seg_override(ctxt, ctxt->modrm_seg); 4026 } else if (ctxt->d & MemAbs) 4027 rc = decode_abs(ctxt, &ctxt->memop); 4028 if (rc != X86EMUL_CONTINUE) 4029 goto done; 4030 4031 if (!ctxt->has_seg_override) 4032 set_seg_override(ctxt, VCPU_SREG_DS); 4033 4034 ctxt->memop.addr.mem.seg = seg_override(ctxt); 4035 4036 if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8) 4037 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea; 4038 4039 /* 4040 * Decode and fetch the source operand: register, memory 4041 * or immediate. 4042 */ 4043 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask); 4044 if (rc != X86EMUL_CONTINUE) 4045 goto done; 4046 4047 /* 4048 * Decode and fetch the second source operand: register, memory 4049 * or immediate. 4050 */ 4051 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask); 4052 if (rc != X86EMUL_CONTINUE) 4053 goto done; 4054 4055 /* Decode and fetch the destination operand: register or memory. */ 4056 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask); 4057 4058 done: 4059 if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative) 4060 ctxt->memopp->addr.mem.ea += ctxt->_eip; 4061 4062 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK; 4063 } 4064 4065 bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt) 4066 { 4067 return ctxt->d & PageTable; 4068 } 4069 4070 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt) 4071 { 4072 /* The second termination condition only applies for REPE 4073 * and REPNE. Test if the repeat string operation prefix is 4074 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the 4075 * corresponding termination condition according to: 4076 * - if REPE/REPZ and ZF = 0 then done 4077 * - if REPNE/REPNZ and ZF = 1 then done 4078 */ 4079 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) || 4080 (ctxt->b == 0xae) || (ctxt->b == 0xaf)) 4081 && (((ctxt->rep_prefix == REPE_PREFIX) && 4082 ((ctxt->eflags & EFLG_ZF) == 0)) 4083 || ((ctxt->rep_prefix == REPNE_PREFIX) && 4084 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)))) 4085 return true; 4086 4087 return false; 4088 } 4089 4090 static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt) 4091 { 4092 bool fault = false; 4093 4094 ctxt->ops->get_fpu(ctxt); 4095 asm volatile("1: fwait \n\t" 4096 "2: \n\t" 4097 ".pushsection .fixup,\"ax\" \n\t" 4098 "3: \n\t" 4099 "movb $1, %[fault] \n\t" 4100 "jmp 2b \n\t" 4101 ".popsection \n\t" 4102 _ASM_EXTABLE(1b, 3b) 4103 : [fault]"+qm"(fault)); 4104 ctxt->ops->put_fpu(ctxt); 4105 4106 if (unlikely(fault)) 4107 return emulate_exception(ctxt, MF_VECTOR, 0, false); 4108 4109 return X86EMUL_CONTINUE; 4110 } 4111 4112 static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt, 4113 struct operand *op) 4114 { 4115 if (op->type == OP_MM) 4116 read_mmx_reg(ctxt, &op->mm_val, op->addr.mm); 4117 } 4118 4119 int x86_emulate_insn(struct x86_emulate_ctxt *ctxt) 4120 { 4121 struct x86_emulate_ops *ops = ctxt->ops; 4122 int rc = X86EMUL_CONTINUE; 4123 int saved_dst_type = ctxt->dst.type; 4124 4125 ctxt->mem_read.pos = 0; 4126 4127 if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) { 4128 rc = emulate_ud(ctxt); 4129 goto done; 4130 } 4131 4132 /* LOCK prefix is allowed only with some instructions */ 4133 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) { 4134 rc = emulate_ud(ctxt); 4135 goto done; 4136 } 4137 4138 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) { 4139 rc = emulate_ud(ctxt); 4140 goto done; 4141 } 4142 4143 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM))) 4144 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) { 4145 rc = emulate_ud(ctxt); 4146 goto done; 4147 } 4148 4149 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) { 4150 rc = emulate_nm(ctxt); 4151 goto done; 4152 } 4153 4154 if (ctxt->d & Mmx) { 4155 rc = flush_pending_x87_faults(ctxt); 4156 if (rc != X86EMUL_CONTINUE) 4157 goto done; 4158 /* 4159 * Now that we know the fpu is exception safe, we can fetch 4160 * operands from it. 4161 */ 4162 fetch_possible_mmx_operand(ctxt, &ctxt->src); 4163 fetch_possible_mmx_operand(ctxt, &ctxt->src2); 4164 if (!(ctxt->d & Mov)) 4165 fetch_possible_mmx_operand(ctxt, &ctxt->dst); 4166 } 4167 4168 if (unlikely(ctxt->guest_mode) && ctxt->intercept) { 4169 rc = emulator_check_intercept(ctxt, ctxt->intercept, 4170 X86_ICPT_PRE_EXCEPT); 4171 if (rc != X86EMUL_CONTINUE) 4172 goto done; 4173 } 4174 4175 /* Privileged instruction can be executed only in CPL=0 */ 4176 if ((ctxt->d & Priv) && ops->cpl(ctxt)) { 4177 rc = emulate_gp(ctxt, 0); 4178 goto done; 4179 } 4180 4181 /* Instruction can only be executed in protected mode */ 4182 if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) { 4183 rc = emulate_ud(ctxt); 4184 goto done; 4185 } 4186 4187 /* Do instruction specific permission checks */ 4188 if (ctxt->check_perm) { 4189 rc = ctxt->check_perm(ctxt); 4190 if (rc != X86EMUL_CONTINUE) 4191 goto done; 4192 } 4193 4194 if (unlikely(ctxt->guest_mode) && ctxt->intercept) { 4195 rc = emulator_check_intercept(ctxt, ctxt->intercept, 4196 X86_ICPT_POST_EXCEPT); 4197 if (rc != X86EMUL_CONTINUE) 4198 goto done; 4199 } 4200 4201 if (ctxt->rep_prefix && (ctxt->d & String)) { 4202 /* All REP prefixes have the same first termination condition */ 4203 if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) { 4204 ctxt->eip = ctxt->_eip; 4205 goto done; 4206 } 4207 } 4208 4209 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) { 4210 rc = segmented_read(ctxt, ctxt->src.addr.mem, 4211 ctxt->src.valptr, ctxt->src.bytes); 4212 if (rc != X86EMUL_CONTINUE) 4213 goto done; 4214 ctxt->src.orig_val64 = ctxt->src.val64; 4215 } 4216 4217 if (ctxt->src2.type == OP_MEM) { 4218 rc = segmented_read(ctxt, ctxt->src2.addr.mem, 4219 &ctxt->src2.val, ctxt->src2.bytes); 4220 if (rc != X86EMUL_CONTINUE) 4221 goto done; 4222 } 4223 4224 if ((ctxt->d & DstMask) == ImplicitOps) 4225 goto special_insn; 4226 4227 4228 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) { 4229 /* optimisation - avoid slow emulated read if Mov */ 4230 rc = segmented_read(ctxt, ctxt->dst.addr.mem, 4231 &ctxt->dst.val, ctxt->dst.bytes); 4232 if (rc != X86EMUL_CONTINUE) 4233 goto done; 4234 } 4235 ctxt->dst.orig_val = ctxt->dst.val; 4236 4237 special_insn: 4238 4239 if (unlikely(ctxt->guest_mode) && ctxt->intercept) { 4240 rc = emulator_check_intercept(ctxt, ctxt->intercept, 4241 X86_ICPT_POST_MEMACCESS); 4242 if (rc != X86EMUL_CONTINUE) 4243 goto done; 4244 } 4245 4246 if (ctxt->execute) { 4247 rc = ctxt->execute(ctxt); 4248 if (rc != X86EMUL_CONTINUE) 4249 goto done; 4250 goto writeback; 4251 } 4252 4253 if (ctxt->twobyte) 4254 goto twobyte_insn; 4255 4256 switch (ctxt->b) { 4257 case 0x40 ... 0x47: /* inc r16/r32 */ 4258 emulate_1op(ctxt, "inc"); 4259 break; 4260 case 0x48 ... 0x4f: /* dec r16/r32 */ 4261 emulate_1op(ctxt, "dec"); 4262 break; 4263 case 0x63: /* movsxd */ 4264 if (ctxt->mode != X86EMUL_MODE_PROT64) 4265 goto cannot_emulate; 4266 ctxt->dst.val = (s32) ctxt->src.val; 4267 break; 4268 case 0x70 ... 0x7f: /* jcc (short) */ 4269 if (test_cc(ctxt->b, ctxt->eflags)) 4270 jmp_rel(ctxt, ctxt->src.val); 4271 break; 4272 case 0x8d: /* lea r16/r32, m */ 4273 ctxt->dst.val = ctxt->src.addr.mem.ea; 4274 break; 4275 case 0x90 ... 0x97: /* nop / xchg reg, rax */ 4276 if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX]) 4277 break; 4278 rc = em_xchg(ctxt); 4279 break; 4280 case 0x98: /* cbw/cwde/cdqe */ 4281 switch (ctxt->op_bytes) { 4282 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break; 4283 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break; 4284 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break; 4285 } 4286 break; 4287 case 0xc0 ... 0xc1: 4288 rc = em_grp2(ctxt); 4289 break; 4290 case 0xcc: /* int3 */ 4291 rc = emulate_int(ctxt, 3); 4292 break; 4293 case 0xcd: /* int n */ 4294 rc = emulate_int(ctxt, ctxt->src.val); 4295 break; 4296 case 0xce: /* into */ 4297 if (ctxt->eflags & EFLG_OF) 4298 rc = emulate_int(ctxt, 4); 4299 break; 4300 case 0xd0 ... 0xd1: /* Grp2 */ 4301 rc = em_grp2(ctxt); 4302 break; 4303 case 0xd2 ... 0xd3: /* Grp2 */ 4304 ctxt->src.val = ctxt->regs[VCPU_REGS_RCX]; 4305 rc = em_grp2(ctxt); 4306 break; 4307 case 0xe9: /* jmp rel */ 4308 case 0xeb: /* jmp rel short */ 4309 jmp_rel(ctxt, ctxt->src.val); 4310 ctxt->dst.type = OP_NONE; /* Disable writeback. */ 4311 break; 4312 case 0xf4: /* hlt */ 4313 ctxt->ops->halt(ctxt); 4314 break; 4315 case 0xf5: /* cmc */ 4316 /* complement carry flag from eflags reg */ 4317 ctxt->eflags ^= EFLG_CF; 4318 break; 4319 case 0xf8: /* clc */ 4320 ctxt->eflags &= ~EFLG_CF; 4321 break; 4322 case 0xf9: /* stc */ 4323 ctxt->eflags |= EFLG_CF; 4324 break; 4325 case 0xfc: /* cld */ 4326 ctxt->eflags &= ~EFLG_DF; 4327 break; 4328 case 0xfd: /* std */ 4329 ctxt->eflags |= EFLG_DF; 4330 break; 4331 default: 4332 goto cannot_emulate; 4333 } 4334 4335 if (rc != X86EMUL_CONTINUE) 4336 goto done; 4337 4338 writeback: 4339 rc = writeback(ctxt); 4340 if (rc != X86EMUL_CONTINUE) 4341 goto done; 4342 4343 /* 4344 * restore dst type in case the decoding will be reused 4345 * (happens for string instruction ) 4346 */ 4347 ctxt->dst.type = saved_dst_type; 4348 4349 if ((ctxt->d & SrcMask) == SrcSI) 4350 string_addr_inc(ctxt, seg_override(ctxt), 4351 VCPU_REGS_RSI, &ctxt->src); 4352 4353 if ((ctxt->d & DstMask) == DstDI) 4354 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI, 4355 &ctxt->dst); 4356 4357 if (ctxt->rep_prefix && (ctxt->d & String)) { 4358 struct read_cache *r = &ctxt->io_read; 4359 register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1); 4360 4361 if (!string_insn_completed(ctxt)) { 4362 /* 4363 * Re-enter guest when pio read ahead buffer is empty 4364 * or, if it is not used, after each 1024 iteration. 4365 */ 4366 if ((r->end != 0 || ctxt->regs[VCPU_REGS_RCX] & 0x3ff) && 4367 (r->end == 0 || r->end != r->pos)) { 4368 /* 4369 * Reset read cache. Usually happens before 4370 * decode, but since instruction is restarted 4371 * we have to do it here. 4372 */ 4373 ctxt->mem_read.end = 0; 4374 return EMULATION_RESTART; 4375 } 4376 goto done; /* skip rip writeback */ 4377 } 4378 } 4379 4380 ctxt->eip = ctxt->_eip; 4381 4382 done: 4383 if (rc == X86EMUL_PROPAGATE_FAULT) 4384 ctxt->have_exception = true; 4385 if (rc == X86EMUL_INTERCEPTED) 4386 return EMULATION_INTERCEPTED; 4387 4388 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 4389 4390 twobyte_insn: 4391 switch (ctxt->b) { 4392 case 0x09: /* wbinvd */ 4393 (ctxt->ops->wbinvd)(ctxt); 4394 break; 4395 case 0x08: /* invd */ 4396 case 0x0d: /* GrpP (prefetch) */ 4397 case 0x18: /* Grp16 (prefetch/nop) */ 4398 break; 4399 case 0x20: /* mov cr, reg */ 4400 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg); 4401 break; 4402 case 0x21: /* mov from dr to reg */ 4403 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val); 4404 break; 4405 case 0x40 ... 0x4f: /* cmov */ 4406 ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val; 4407 if (!test_cc(ctxt->b, ctxt->eflags)) 4408 ctxt->dst.type = OP_NONE; /* no writeback */ 4409 break; 4410 case 0x80 ... 0x8f: /* jnz rel, etc*/ 4411 if (test_cc(ctxt->b, ctxt->eflags)) 4412 jmp_rel(ctxt, ctxt->src.val); 4413 break; 4414 case 0x90 ... 0x9f: /* setcc r/m8 */ 4415 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags); 4416 break; 4417 case 0xa4: /* shld imm8, r, r/m */ 4418 case 0xa5: /* shld cl, r, r/m */ 4419 emulate_2op_cl(ctxt, "shld"); 4420 break; 4421 case 0xac: /* shrd imm8, r, r/m */ 4422 case 0xad: /* shrd cl, r, r/m */ 4423 emulate_2op_cl(ctxt, "shrd"); 4424 break; 4425 case 0xae: /* clflush */ 4426 break; 4427 case 0xb6 ... 0xb7: /* movzx */ 4428 ctxt->dst.bytes = ctxt->op_bytes; 4429 ctxt->dst.val = (ctxt->d & ByteOp) ? (u8) ctxt->src.val 4430 : (u16) ctxt->src.val; 4431 break; 4432 case 0xbe ... 0xbf: /* movsx */ 4433 ctxt->dst.bytes = ctxt->op_bytes; 4434 ctxt->dst.val = (ctxt->d & ByteOp) ? (s8) ctxt->src.val : 4435 (s16) ctxt->src.val; 4436 break; 4437 case 0xc0 ... 0xc1: /* xadd */ 4438 emulate_2op_SrcV(ctxt, "add"); 4439 /* Write back the register source. */ 4440 ctxt->src.val = ctxt->dst.orig_val; 4441 write_register_operand(&ctxt->src); 4442 break; 4443 case 0xc3: /* movnti */ 4444 ctxt->dst.bytes = ctxt->op_bytes; 4445 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val : 4446 (u64) ctxt->src.val; 4447 break; 4448 default: 4449 goto cannot_emulate; 4450 } 4451 4452 if (rc != X86EMUL_CONTINUE) 4453 goto done; 4454 4455 goto writeback; 4456 4457 cannot_emulate: 4458 return EMULATION_FAILED; 4459 } 4460