1 // SPDX-License-Identifier: GPL-2.0-only 2 /****************************************************************************** 3 * emulate.c 4 * 5 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. 6 * 7 * Copyright (c) 2005 Keir Fraser 8 * 9 * Linux coding style, mod r/m decoder, segment base fixes, real-mode 10 * privileged instructions: 11 * 12 * Copyright (C) 2006 Qumranet 13 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 14 * 15 * Avi Kivity <avi@qumranet.com> 16 * Yaniv Kamay <yaniv@qumranet.com> 17 * 18 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 19 */ 20 21 #include <linux/kvm_host.h> 22 #include "kvm_cache_regs.h" 23 #include "kvm_emulate.h" 24 #include <linux/stringify.h> 25 #include <asm/debugreg.h> 26 #include <asm/nospec-branch.h> 27 #include <asm/ibt.h> 28 29 #include "x86.h" 30 #include "tss.h" 31 #include "mmu.h" 32 #include "pmu.h" 33 34 /* 35 * Operand types 36 */ 37 #define OpNone 0ull 38 #define OpImplicit 1ull /* No generic decode */ 39 #define OpReg 2ull /* Register */ 40 #define OpMem 3ull /* Memory */ 41 #define OpAcc 4ull /* Accumulator: AL/AX/EAX/RAX */ 42 #define OpDI 5ull /* ES:DI/EDI/RDI */ 43 #define OpMem64 6ull /* Memory, 64-bit */ 44 #define OpImmUByte 7ull /* Zero-extended 8-bit immediate */ 45 #define OpDX 8ull /* DX register */ 46 #define OpCL 9ull /* CL register (for shifts) */ 47 #define OpImmByte 10ull /* 8-bit sign extended immediate */ 48 #define OpOne 11ull /* Implied 1 */ 49 #define OpImm 12ull /* Sign extended up to 32-bit immediate */ 50 #define OpMem16 13ull /* Memory operand (16-bit). */ 51 #define OpMem32 14ull /* Memory operand (32-bit). */ 52 #define OpImmU 15ull /* Immediate operand, zero extended */ 53 #define OpSI 16ull /* SI/ESI/RSI */ 54 #define OpImmFAddr 17ull /* Immediate far address */ 55 #define OpMemFAddr 18ull /* Far address in memory */ 56 #define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */ 57 #define OpES 20ull /* ES */ 58 #define OpCS 21ull /* CS */ 59 #define OpSS 22ull /* SS */ 60 #define OpDS 23ull /* DS */ 61 #define OpFS 24ull /* FS */ 62 #define OpGS 25ull /* GS */ 63 #define OpMem8 26ull /* 8-bit zero extended memory operand */ 64 #define OpImm64 27ull /* Sign extended 16/32/64-bit immediate */ 65 #define OpXLat 28ull /* memory at BX/EBX/RBX + zero-extended AL */ 66 #define OpAccLo 29ull /* Low part of extended acc (AX/AX/EAX/RAX) */ 67 #define OpAccHi 30ull /* High part of extended acc (-/DX/EDX/RDX) */ 68 69 #define OpBits 5 /* Width of operand field */ 70 #define OpMask ((1ull << OpBits) - 1) 71 72 /* 73 * Opcode effective-address decode tables. 74 * Note that we only emulate instructions that have at least one memory 75 * operand (excluding implicit stack references). We assume that stack 76 * references and instruction fetches will never occur in special memory 77 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need 78 * not be handled. 79 */ 80 81 /* Operand sizes: 8-bit operands or specified/overridden size. */ 82 #define ByteOp (1<<0) /* 8-bit operands. */ 83 /* Destination operand type. */ 84 #define DstShift 1 85 #define ImplicitOps (OpImplicit << DstShift) 86 #define DstReg (OpReg << DstShift) 87 #define DstMem (OpMem << DstShift) 88 #define DstAcc (OpAcc << DstShift) 89 #define DstDI (OpDI << DstShift) 90 #define DstMem64 (OpMem64 << DstShift) 91 #define DstMem16 (OpMem16 << DstShift) 92 #define DstImmUByte (OpImmUByte << DstShift) 93 #define DstDX (OpDX << DstShift) 94 #define DstAccLo (OpAccLo << DstShift) 95 #define DstMask (OpMask << DstShift) 96 /* Source operand type. */ 97 #define SrcShift 6 98 #define SrcNone (OpNone << SrcShift) 99 #define SrcReg (OpReg << SrcShift) 100 #define SrcMem (OpMem << SrcShift) 101 #define SrcMem16 (OpMem16 << SrcShift) 102 #define SrcMem32 (OpMem32 << SrcShift) 103 #define SrcImm (OpImm << SrcShift) 104 #define SrcImmByte (OpImmByte << SrcShift) 105 #define SrcOne (OpOne << SrcShift) 106 #define SrcImmUByte (OpImmUByte << SrcShift) 107 #define SrcImmU (OpImmU << SrcShift) 108 #define SrcSI (OpSI << SrcShift) 109 #define SrcXLat (OpXLat << SrcShift) 110 #define SrcImmFAddr (OpImmFAddr << SrcShift) 111 #define SrcMemFAddr (OpMemFAddr << SrcShift) 112 #define SrcAcc (OpAcc << SrcShift) 113 #define SrcImmU16 (OpImmU16 << SrcShift) 114 #define SrcImm64 (OpImm64 << SrcShift) 115 #define SrcDX (OpDX << SrcShift) 116 #define SrcMem8 (OpMem8 << SrcShift) 117 #define SrcAccHi (OpAccHi << SrcShift) 118 #define SrcMask (OpMask << SrcShift) 119 #define BitOp (1<<11) 120 #define MemAbs (1<<12) /* Memory operand is absolute displacement */ 121 #define String (1<<13) /* String instruction (rep capable) */ 122 #define Stack (1<<14) /* Stack instruction (push/pop) */ 123 #define GroupMask (7<<15) /* Opcode uses one of the group mechanisms */ 124 #define Group (1<<15) /* Bits 3:5 of modrm byte extend opcode */ 125 #define GroupDual (2<<15) /* Alternate decoding of mod == 3 */ 126 #define Prefix (3<<15) /* Instruction varies with 66/f2/f3 prefix */ 127 #define RMExt (4<<15) /* Opcode extension in ModRM r/m if mod == 3 */ 128 #define Escape (5<<15) /* Escape to coprocessor instruction */ 129 #define InstrDual (6<<15) /* Alternate instruction decoding of mod == 3 */ 130 #define ModeDual (7<<15) /* Different instruction for 32/64 bit */ 131 #define Sse (1<<18) /* SSE Vector instruction */ 132 /* Generic ModRM decode. */ 133 #define ModRM (1<<19) 134 /* Destination is only written; never read. */ 135 #define Mov (1<<20) 136 /* Misc flags */ 137 #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */ 138 #define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */ 139 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */ 140 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */ 141 #define Undefined (1<<25) /* No Such Instruction */ 142 #define Lock (1<<26) /* lock prefix is allowed for the instruction */ 143 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */ 144 #define No64 (1<<28) 145 #define PageTable (1 << 29) /* instruction used to write page table */ 146 #define NotImpl (1 << 30) /* instruction is not implemented */ 147 /* Source 2 operand type */ 148 #define Src2Shift (31) 149 #define Src2None (OpNone << Src2Shift) 150 #define Src2Mem (OpMem << Src2Shift) 151 #define Src2CL (OpCL << Src2Shift) 152 #define Src2ImmByte (OpImmByte << Src2Shift) 153 #define Src2One (OpOne << Src2Shift) 154 #define Src2Imm (OpImm << Src2Shift) 155 #define Src2ES (OpES << Src2Shift) 156 #define Src2CS (OpCS << Src2Shift) 157 #define Src2SS (OpSS << Src2Shift) 158 #define Src2DS (OpDS << Src2Shift) 159 #define Src2FS (OpFS << Src2Shift) 160 #define Src2GS (OpGS << Src2Shift) 161 #define Src2Mask (OpMask << Src2Shift) 162 #define Mmx ((u64)1 << 40) /* MMX Vector instruction */ 163 #define AlignMask ((u64)7 << 41) 164 #define Aligned ((u64)1 << 41) /* Explicitly aligned (e.g. MOVDQA) */ 165 #define Unaligned ((u64)2 << 41) /* Explicitly unaligned (e.g. MOVDQU) */ 166 #define Avx ((u64)3 << 41) /* Advanced Vector Extensions */ 167 #define Aligned16 ((u64)4 << 41) /* Aligned to 16 byte boundary (e.g. FXSAVE) */ 168 #define Fastop ((u64)1 << 44) /* Use opcode::u.fastop */ 169 #define NoWrite ((u64)1 << 45) /* No writeback */ 170 #define SrcWrite ((u64)1 << 46) /* Write back src operand */ 171 #define NoMod ((u64)1 << 47) /* Mod field is ignored */ 172 #define Intercept ((u64)1 << 48) /* Has valid intercept field */ 173 #define CheckPerm ((u64)1 << 49) /* Has valid check_perm field */ 174 #define PrivUD ((u64)1 << 51) /* #UD instead of #GP on CPL > 0 */ 175 #define NearBranch ((u64)1 << 52) /* Near branches */ 176 #define No16 ((u64)1 << 53) /* No 16 bit operand */ 177 #define IncSP ((u64)1 << 54) /* SP is incremented before ModRM calc */ 178 #define TwoMemOp ((u64)1 << 55) /* Instruction has two memory operand */ 179 #define IsBranch ((u64)1 << 56) /* Instruction is considered a branch. */ 180 181 #define DstXacc (DstAccLo | SrcAccHi | SrcWrite) 182 183 #define X2(x...) x, x 184 #define X3(x...) X2(x), x 185 #define X4(x...) X2(x), X2(x) 186 #define X5(x...) X4(x), x 187 #define X6(x...) X4(x), X2(x) 188 #define X7(x...) X4(x), X3(x) 189 #define X8(x...) X4(x), X4(x) 190 #define X16(x...) X8(x), X8(x) 191 192 #define NR_FASTOP (ilog2(sizeof(ulong)) + 1) 193 #define FASTOP_SIZE (8 * (1 + HAS_KERNEL_IBT)) 194 195 struct opcode { 196 u64 flags; 197 u8 intercept; 198 u8 pad[7]; 199 union { 200 int (*execute)(struct x86_emulate_ctxt *ctxt); 201 const struct opcode *group; 202 const struct group_dual *gdual; 203 const struct gprefix *gprefix; 204 const struct escape *esc; 205 const struct instr_dual *idual; 206 const struct mode_dual *mdual; 207 void (*fastop)(struct fastop *fake); 208 } u; 209 int (*check_perm)(struct x86_emulate_ctxt *ctxt); 210 }; 211 212 struct group_dual { 213 struct opcode mod012[8]; 214 struct opcode mod3[8]; 215 }; 216 217 struct gprefix { 218 struct opcode pfx_no; 219 struct opcode pfx_66; 220 struct opcode pfx_f2; 221 struct opcode pfx_f3; 222 }; 223 224 struct escape { 225 struct opcode op[8]; 226 struct opcode high[64]; 227 }; 228 229 struct instr_dual { 230 struct opcode mod012; 231 struct opcode mod3; 232 }; 233 234 struct mode_dual { 235 struct opcode mode32; 236 struct opcode mode64; 237 }; 238 239 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a 240 241 enum x86_transfer_type { 242 X86_TRANSFER_NONE, 243 X86_TRANSFER_CALL_JMP, 244 X86_TRANSFER_RET, 245 X86_TRANSFER_TASK_SWITCH, 246 }; 247 248 static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr) 249 { 250 if (!(ctxt->regs_valid & (1 << nr))) { 251 ctxt->regs_valid |= 1 << nr; 252 ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr); 253 } 254 return ctxt->_regs[nr]; 255 } 256 257 static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr) 258 { 259 ctxt->regs_valid |= 1 << nr; 260 ctxt->regs_dirty |= 1 << nr; 261 return &ctxt->_regs[nr]; 262 } 263 264 static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr) 265 { 266 reg_read(ctxt, nr); 267 return reg_write(ctxt, nr); 268 } 269 270 static void writeback_registers(struct x86_emulate_ctxt *ctxt) 271 { 272 unsigned reg; 273 274 for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16) 275 ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]); 276 } 277 278 static void invalidate_registers(struct x86_emulate_ctxt *ctxt) 279 { 280 ctxt->regs_dirty = 0; 281 ctxt->regs_valid = 0; 282 } 283 284 /* 285 * These EFLAGS bits are restored from saved value during emulation, and 286 * any changes are written back to the saved value after emulation. 287 */ 288 #define EFLAGS_MASK (X86_EFLAGS_OF|X86_EFLAGS_SF|X86_EFLAGS_ZF|X86_EFLAGS_AF|\ 289 X86_EFLAGS_PF|X86_EFLAGS_CF) 290 291 #ifdef CONFIG_X86_64 292 #define ON64(x) x 293 #else 294 #define ON64(x) 295 #endif 296 297 /* 298 * fastop functions have a special calling convention: 299 * 300 * dst: rax (in/out) 301 * src: rdx (in/out) 302 * src2: rcx (in) 303 * flags: rflags (in/out) 304 * ex: rsi (in:fastop pointer, out:zero if exception) 305 * 306 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for 307 * different operand sizes can be reached by calculation, rather than a jump 308 * table (which would be bigger than the code). 309 */ 310 static int fastop(struct x86_emulate_ctxt *ctxt, fastop_t fop); 311 312 #define __FOP_FUNC(name) \ 313 ".align " __stringify(FASTOP_SIZE) " \n\t" \ 314 ".type " name ", @function \n\t" \ 315 name ":\n\t" \ 316 ASM_ENDBR 317 318 #define FOP_FUNC(name) \ 319 __FOP_FUNC(#name) 320 321 #define __FOP_RET(name) \ 322 "11: " ASM_RET \ 323 ".size " name ", .-" name "\n\t" 324 325 #define FOP_RET(name) \ 326 __FOP_RET(#name) 327 328 #define __FOP_START(op, align) \ 329 extern void em_##op(struct fastop *fake); \ 330 asm(".pushsection .text, \"ax\" \n\t" \ 331 ".global em_" #op " \n\t" \ 332 ".align " __stringify(align) " \n\t" \ 333 "em_" #op ":\n\t" 334 335 #define FOP_START(op) __FOP_START(op, FASTOP_SIZE) 336 337 #define FOP_END \ 338 ".popsection") 339 340 #define __FOPNOP(name) \ 341 __FOP_FUNC(name) \ 342 __FOP_RET(name) 343 344 #define FOPNOP() \ 345 __FOPNOP(__stringify(__UNIQUE_ID(nop))) 346 347 #define FOP1E(op, dst) \ 348 __FOP_FUNC(#op "_" #dst) \ 349 "10: " #op " %" #dst " \n\t" \ 350 __FOP_RET(#op "_" #dst) 351 352 #define FOP1EEX(op, dst) \ 353 FOP1E(op, dst) _ASM_EXTABLE_TYPE_REG(10b, 11b, EX_TYPE_ZERO_REG, %%esi) 354 355 #define FASTOP1(op) \ 356 FOP_START(op) \ 357 FOP1E(op##b, al) \ 358 FOP1E(op##w, ax) \ 359 FOP1E(op##l, eax) \ 360 ON64(FOP1E(op##q, rax)) \ 361 FOP_END 362 363 /* 1-operand, using src2 (for MUL/DIV r/m) */ 364 #define FASTOP1SRC2(op, name) \ 365 FOP_START(name) \ 366 FOP1E(op, cl) \ 367 FOP1E(op, cx) \ 368 FOP1E(op, ecx) \ 369 ON64(FOP1E(op, rcx)) \ 370 FOP_END 371 372 /* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */ 373 #define FASTOP1SRC2EX(op, name) \ 374 FOP_START(name) \ 375 FOP1EEX(op, cl) \ 376 FOP1EEX(op, cx) \ 377 FOP1EEX(op, ecx) \ 378 ON64(FOP1EEX(op, rcx)) \ 379 FOP_END 380 381 #define FOP2E(op, dst, src) \ 382 __FOP_FUNC(#op "_" #dst "_" #src) \ 383 #op " %" #src ", %" #dst " \n\t" \ 384 __FOP_RET(#op "_" #dst "_" #src) 385 386 #define FASTOP2(op) \ 387 FOP_START(op) \ 388 FOP2E(op##b, al, dl) \ 389 FOP2E(op##w, ax, dx) \ 390 FOP2E(op##l, eax, edx) \ 391 ON64(FOP2E(op##q, rax, rdx)) \ 392 FOP_END 393 394 /* 2 operand, word only */ 395 #define FASTOP2W(op) \ 396 FOP_START(op) \ 397 FOPNOP() \ 398 FOP2E(op##w, ax, dx) \ 399 FOP2E(op##l, eax, edx) \ 400 ON64(FOP2E(op##q, rax, rdx)) \ 401 FOP_END 402 403 /* 2 operand, src is CL */ 404 #define FASTOP2CL(op) \ 405 FOP_START(op) \ 406 FOP2E(op##b, al, cl) \ 407 FOP2E(op##w, ax, cl) \ 408 FOP2E(op##l, eax, cl) \ 409 ON64(FOP2E(op##q, rax, cl)) \ 410 FOP_END 411 412 /* 2 operand, src and dest are reversed */ 413 #define FASTOP2R(op, name) \ 414 FOP_START(name) \ 415 FOP2E(op##b, dl, al) \ 416 FOP2E(op##w, dx, ax) \ 417 FOP2E(op##l, edx, eax) \ 418 ON64(FOP2E(op##q, rdx, rax)) \ 419 FOP_END 420 421 #define FOP3E(op, dst, src, src2) \ 422 __FOP_FUNC(#op "_" #dst "_" #src "_" #src2) \ 423 #op " %" #src2 ", %" #src ", %" #dst " \n\t"\ 424 __FOP_RET(#op "_" #dst "_" #src "_" #src2) 425 426 /* 3-operand, word-only, src2=cl */ 427 #define FASTOP3WCL(op) \ 428 FOP_START(op) \ 429 FOPNOP() \ 430 FOP3E(op##w, ax, dx, cl) \ 431 FOP3E(op##l, eax, edx, cl) \ 432 ON64(FOP3E(op##q, rax, rdx, cl)) \ 433 FOP_END 434 435 /* Special case for SETcc - 1 instruction per cc */ 436 437 /* 438 * Depending on .config the SETcc functions look like: 439 * 440 * ENDBR [4 bytes; CONFIG_X86_KERNEL_IBT] 441 * SETcc %al [3 bytes] 442 * RET | JMP __x86_return_thunk [1,5 bytes; CONFIG_RETHUNK] 443 * INT3 [1 byte; CONFIG_SLS] 444 */ 445 #define RET_LENGTH (1 + (4 * IS_ENABLED(CONFIG_RETHUNK)) + \ 446 IS_ENABLED(CONFIG_SLS)) 447 #define SETCC_LENGTH (ENDBR_INSN_SIZE + 3 + RET_LENGTH) 448 #define SETCC_ALIGN (4 << ((SETCC_LENGTH > 4) & 1) << ((SETCC_LENGTH > 8) & 1)) 449 static_assert(SETCC_LENGTH <= SETCC_ALIGN); 450 451 #define FOP_SETCC(op) \ 452 ".align " __stringify(SETCC_ALIGN) " \n\t" \ 453 ".type " #op ", @function \n\t" \ 454 #op ": \n\t" \ 455 ASM_ENDBR \ 456 #op " %al \n\t" \ 457 __FOP_RET(#op) \ 458 ".skip " __stringify(SETCC_ALIGN) " - (.-" #op "), 0xcc \n\t" 459 460 __FOP_START(setcc, SETCC_ALIGN) 461 FOP_SETCC(seto) 462 FOP_SETCC(setno) 463 FOP_SETCC(setc) 464 FOP_SETCC(setnc) 465 FOP_SETCC(setz) 466 FOP_SETCC(setnz) 467 FOP_SETCC(setbe) 468 FOP_SETCC(setnbe) 469 FOP_SETCC(sets) 470 FOP_SETCC(setns) 471 FOP_SETCC(setp) 472 FOP_SETCC(setnp) 473 FOP_SETCC(setl) 474 FOP_SETCC(setnl) 475 FOP_SETCC(setle) 476 FOP_SETCC(setnle) 477 FOP_END; 478 479 FOP_START(salc) 480 FOP_FUNC(salc) 481 "pushf; sbb %al, %al; popf \n\t" 482 FOP_RET(salc) 483 FOP_END; 484 485 /* 486 * XXX: inoutclob user must know where the argument is being expanded. 487 * Relying on CONFIG_CC_HAS_ASM_GOTO would allow us to remove _fault. 488 */ 489 #define asm_safe(insn, inoutclob...) \ 490 ({ \ 491 int _fault = 0; \ 492 \ 493 asm volatile("1:" insn "\n" \ 494 "2:\n" \ 495 _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_ONE_REG, %[_fault]) \ 496 : [_fault] "+r"(_fault) inoutclob ); \ 497 \ 498 _fault ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; \ 499 }) 500 501 static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt, 502 enum x86_intercept intercept, 503 enum x86_intercept_stage stage) 504 { 505 struct x86_instruction_info info = { 506 .intercept = intercept, 507 .rep_prefix = ctxt->rep_prefix, 508 .modrm_mod = ctxt->modrm_mod, 509 .modrm_reg = ctxt->modrm_reg, 510 .modrm_rm = ctxt->modrm_rm, 511 .src_val = ctxt->src.val64, 512 .dst_val = ctxt->dst.val64, 513 .src_bytes = ctxt->src.bytes, 514 .dst_bytes = ctxt->dst.bytes, 515 .ad_bytes = ctxt->ad_bytes, 516 .next_rip = ctxt->eip, 517 }; 518 519 return ctxt->ops->intercept(ctxt, &info, stage); 520 } 521 522 static void assign_masked(ulong *dest, ulong src, ulong mask) 523 { 524 *dest = (*dest & ~mask) | (src & mask); 525 } 526 527 static void assign_register(unsigned long *reg, u64 val, int bytes) 528 { 529 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */ 530 switch (bytes) { 531 case 1: 532 *(u8 *)reg = (u8)val; 533 break; 534 case 2: 535 *(u16 *)reg = (u16)val; 536 break; 537 case 4: 538 *reg = (u32)val; 539 break; /* 64b: zero-extend */ 540 case 8: 541 *reg = val; 542 break; 543 } 544 } 545 546 static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt) 547 { 548 return (1UL << (ctxt->ad_bytes << 3)) - 1; 549 } 550 551 static ulong stack_mask(struct x86_emulate_ctxt *ctxt) 552 { 553 u16 sel; 554 struct desc_struct ss; 555 556 if (ctxt->mode == X86EMUL_MODE_PROT64) 557 return ~0UL; 558 ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS); 559 return ~0U >> ((ss.d ^ 1) * 16); /* d=0: 0xffff; d=1: 0xffffffff */ 560 } 561 562 static int stack_size(struct x86_emulate_ctxt *ctxt) 563 { 564 return (__fls(stack_mask(ctxt)) + 1) >> 3; 565 } 566 567 /* Access/update address held in a register, based on addressing mode. */ 568 static inline unsigned long 569 address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg) 570 { 571 if (ctxt->ad_bytes == sizeof(unsigned long)) 572 return reg; 573 else 574 return reg & ad_mask(ctxt); 575 } 576 577 static inline unsigned long 578 register_address(struct x86_emulate_ctxt *ctxt, int reg) 579 { 580 return address_mask(ctxt, reg_read(ctxt, reg)); 581 } 582 583 static void masked_increment(ulong *reg, ulong mask, int inc) 584 { 585 assign_masked(reg, *reg + inc, mask); 586 } 587 588 static inline void 589 register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc) 590 { 591 ulong *preg = reg_rmw(ctxt, reg); 592 593 assign_register(preg, *preg + inc, ctxt->ad_bytes); 594 } 595 596 static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc) 597 { 598 masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc); 599 } 600 601 static u32 desc_limit_scaled(struct desc_struct *desc) 602 { 603 u32 limit = get_desc_limit(desc); 604 605 return desc->g ? (limit << 12) | 0xfff : limit; 606 } 607 608 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg) 609 { 610 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS) 611 return 0; 612 613 return ctxt->ops->get_cached_segment_base(ctxt, seg); 614 } 615 616 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec, 617 u32 error, bool valid) 618 { 619 WARN_ON(vec > 0x1f); 620 ctxt->exception.vector = vec; 621 ctxt->exception.error_code = error; 622 ctxt->exception.error_code_valid = valid; 623 return X86EMUL_PROPAGATE_FAULT; 624 } 625 626 static int emulate_db(struct x86_emulate_ctxt *ctxt) 627 { 628 return emulate_exception(ctxt, DB_VECTOR, 0, false); 629 } 630 631 static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err) 632 { 633 return emulate_exception(ctxt, GP_VECTOR, err, true); 634 } 635 636 static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err) 637 { 638 return emulate_exception(ctxt, SS_VECTOR, err, true); 639 } 640 641 static int emulate_ud(struct x86_emulate_ctxt *ctxt) 642 { 643 return emulate_exception(ctxt, UD_VECTOR, 0, false); 644 } 645 646 static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err) 647 { 648 return emulate_exception(ctxt, TS_VECTOR, err, true); 649 } 650 651 static int emulate_de(struct x86_emulate_ctxt *ctxt) 652 { 653 return emulate_exception(ctxt, DE_VECTOR, 0, false); 654 } 655 656 static int emulate_nm(struct x86_emulate_ctxt *ctxt) 657 { 658 return emulate_exception(ctxt, NM_VECTOR, 0, false); 659 } 660 661 static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg) 662 { 663 u16 selector; 664 struct desc_struct desc; 665 666 ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg); 667 return selector; 668 } 669 670 static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector, 671 unsigned seg) 672 { 673 u16 dummy; 674 u32 base3; 675 struct desc_struct desc; 676 677 ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg); 678 ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg); 679 } 680 681 static inline u8 ctxt_virt_addr_bits(struct x86_emulate_ctxt *ctxt) 682 { 683 return (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_LA57) ? 57 : 48; 684 } 685 686 static inline bool emul_is_noncanonical_address(u64 la, 687 struct x86_emulate_ctxt *ctxt) 688 { 689 return !__is_canonical_address(la, ctxt_virt_addr_bits(ctxt)); 690 } 691 692 /* 693 * x86 defines three classes of vector instructions: explicitly 694 * aligned, explicitly unaligned, and the rest, which change behaviour 695 * depending on whether they're AVX encoded or not. 696 * 697 * Also included is CMPXCHG16B which is not a vector instruction, yet it is 698 * subject to the same check. FXSAVE and FXRSTOR are checked here too as their 699 * 512 bytes of data must be aligned to a 16 byte boundary. 700 */ 701 static unsigned insn_alignment(struct x86_emulate_ctxt *ctxt, unsigned size) 702 { 703 u64 alignment = ctxt->d & AlignMask; 704 705 if (likely(size < 16)) 706 return 1; 707 708 switch (alignment) { 709 case Unaligned: 710 case Avx: 711 return 1; 712 case Aligned16: 713 return 16; 714 case Aligned: 715 default: 716 return size; 717 } 718 } 719 720 static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt, 721 struct segmented_address addr, 722 unsigned *max_size, unsigned size, 723 bool write, bool fetch, 724 enum x86emul_mode mode, ulong *linear) 725 { 726 struct desc_struct desc; 727 bool usable; 728 ulong la; 729 u32 lim; 730 u16 sel; 731 u8 va_bits; 732 733 la = seg_base(ctxt, addr.seg) + addr.ea; 734 *max_size = 0; 735 switch (mode) { 736 case X86EMUL_MODE_PROT64: 737 *linear = la; 738 va_bits = ctxt_virt_addr_bits(ctxt); 739 if (!__is_canonical_address(la, va_bits)) 740 goto bad; 741 742 *max_size = min_t(u64, ~0u, (1ull << va_bits) - la); 743 if (size > *max_size) 744 goto bad; 745 break; 746 default: 747 *linear = la = (u32)la; 748 usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL, 749 addr.seg); 750 if (!usable) 751 goto bad; 752 /* code segment in protected mode or read-only data segment */ 753 if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8)) 754 || !(desc.type & 2)) && write) 755 goto bad; 756 /* unreadable code segment */ 757 if (!fetch && (desc.type & 8) && !(desc.type & 2)) 758 goto bad; 759 lim = desc_limit_scaled(&desc); 760 if (!(desc.type & 8) && (desc.type & 4)) { 761 /* expand-down segment */ 762 if (addr.ea <= lim) 763 goto bad; 764 lim = desc.d ? 0xffffffff : 0xffff; 765 } 766 if (addr.ea > lim) 767 goto bad; 768 if (lim == 0xffffffff) 769 *max_size = ~0u; 770 else { 771 *max_size = (u64)lim + 1 - addr.ea; 772 if (size > *max_size) 773 goto bad; 774 } 775 break; 776 } 777 if (la & (insn_alignment(ctxt, size) - 1)) 778 return emulate_gp(ctxt, 0); 779 return X86EMUL_CONTINUE; 780 bad: 781 if (addr.seg == VCPU_SREG_SS) 782 return emulate_ss(ctxt, 0); 783 else 784 return emulate_gp(ctxt, 0); 785 } 786 787 static int linearize(struct x86_emulate_ctxt *ctxt, 788 struct segmented_address addr, 789 unsigned size, bool write, 790 ulong *linear) 791 { 792 unsigned max_size; 793 return __linearize(ctxt, addr, &max_size, size, write, false, 794 ctxt->mode, linear); 795 } 796 797 static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst, 798 enum x86emul_mode mode) 799 { 800 ulong linear; 801 int rc; 802 unsigned max_size; 803 struct segmented_address addr = { .seg = VCPU_SREG_CS, 804 .ea = dst }; 805 806 if (ctxt->op_bytes != sizeof(unsigned long)) 807 addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1); 808 rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear); 809 if (rc == X86EMUL_CONTINUE) 810 ctxt->_eip = addr.ea; 811 return rc; 812 } 813 814 static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst) 815 { 816 return assign_eip(ctxt, dst, ctxt->mode); 817 } 818 819 static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst, 820 const struct desc_struct *cs_desc) 821 { 822 enum x86emul_mode mode = ctxt->mode; 823 int rc; 824 825 #ifdef CONFIG_X86_64 826 if (ctxt->mode >= X86EMUL_MODE_PROT16) { 827 if (cs_desc->l) { 828 u64 efer = 0; 829 830 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 831 if (efer & EFER_LMA) 832 mode = X86EMUL_MODE_PROT64; 833 } else 834 mode = X86EMUL_MODE_PROT32; /* temporary value */ 835 } 836 #endif 837 if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32) 838 mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16; 839 rc = assign_eip(ctxt, dst, mode); 840 if (rc == X86EMUL_CONTINUE) 841 ctxt->mode = mode; 842 return rc; 843 } 844 845 static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel) 846 { 847 return assign_eip_near(ctxt, ctxt->_eip + rel); 848 } 849 850 static int linear_read_system(struct x86_emulate_ctxt *ctxt, ulong linear, 851 void *data, unsigned size) 852 { 853 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception, true); 854 } 855 856 static int linear_write_system(struct x86_emulate_ctxt *ctxt, 857 ulong linear, void *data, 858 unsigned int size) 859 { 860 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception, true); 861 } 862 863 static int segmented_read_std(struct x86_emulate_ctxt *ctxt, 864 struct segmented_address addr, 865 void *data, 866 unsigned size) 867 { 868 int rc; 869 ulong linear; 870 871 rc = linearize(ctxt, addr, size, false, &linear); 872 if (rc != X86EMUL_CONTINUE) 873 return rc; 874 return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception, false); 875 } 876 877 static int segmented_write_std(struct x86_emulate_ctxt *ctxt, 878 struct segmented_address addr, 879 void *data, 880 unsigned int size) 881 { 882 int rc; 883 ulong linear; 884 885 rc = linearize(ctxt, addr, size, true, &linear); 886 if (rc != X86EMUL_CONTINUE) 887 return rc; 888 return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception, false); 889 } 890 891 /* 892 * Prefetch the remaining bytes of the instruction without crossing page 893 * boundary if they are not in fetch_cache yet. 894 */ 895 static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size) 896 { 897 int rc; 898 unsigned size, max_size; 899 unsigned long linear; 900 int cur_size = ctxt->fetch.end - ctxt->fetch.data; 901 struct segmented_address addr = { .seg = VCPU_SREG_CS, 902 .ea = ctxt->eip + cur_size }; 903 904 /* 905 * We do not know exactly how many bytes will be needed, and 906 * __linearize is expensive, so fetch as much as possible. We 907 * just have to avoid going beyond the 15 byte limit, the end 908 * of the segment, or the end of the page. 909 * 910 * __linearize is called with size 0 so that it does not do any 911 * boundary check itself. Instead, we use max_size to check 912 * against op_size. 913 */ 914 rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode, 915 &linear); 916 if (unlikely(rc != X86EMUL_CONTINUE)) 917 return rc; 918 919 size = min_t(unsigned, 15UL ^ cur_size, max_size); 920 size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear)); 921 922 /* 923 * One instruction can only straddle two pages, 924 * and one has been loaded at the beginning of 925 * x86_decode_insn. So, if not enough bytes 926 * still, we must have hit the 15-byte boundary. 927 */ 928 if (unlikely(size < op_size)) 929 return emulate_gp(ctxt, 0); 930 931 rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end, 932 size, &ctxt->exception); 933 if (unlikely(rc != X86EMUL_CONTINUE)) 934 return rc; 935 ctxt->fetch.end += size; 936 return X86EMUL_CONTINUE; 937 } 938 939 static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, 940 unsigned size) 941 { 942 unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr; 943 944 if (unlikely(done_size < size)) 945 return __do_insn_fetch_bytes(ctxt, size - done_size); 946 else 947 return X86EMUL_CONTINUE; 948 } 949 950 /* Fetch next part of the instruction being emulated. */ 951 #define insn_fetch(_type, _ctxt) \ 952 ({ _type _x; \ 953 \ 954 rc = do_insn_fetch_bytes(_ctxt, sizeof(_type)); \ 955 if (rc != X86EMUL_CONTINUE) \ 956 goto done; \ 957 ctxt->_eip += sizeof(_type); \ 958 memcpy(&_x, ctxt->fetch.ptr, sizeof(_type)); \ 959 ctxt->fetch.ptr += sizeof(_type); \ 960 _x; \ 961 }) 962 963 #define insn_fetch_arr(_arr, _size, _ctxt) \ 964 ({ \ 965 rc = do_insn_fetch_bytes(_ctxt, _size); \ 966 if (rc != X86EMUL_CONTINUE) \ 967 goto done; \ 968 ctxt->_eip += (_size); \ 969 memcpy(_arr, ctxt->fetch.ptr, _size); \ 970 ctxt->fetch.ptr += (_size); \ 971 }) 972 973 /* 974 * Given the 'reg' portion of a ModRM byte, and a register block, return a 975 * pointer into the block that addresses the relevant register. 976 * @highbyte_regs specifies whether to decode AH,CH,DH,BH. 977 */ 978 static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg, 979 int byteop) 980 { 981 void *p; 982 int highbyte_regs = (ctxt->rex_prefix == 0) && byteop; 983 984 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) 985 p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1; 986 else 987 p = reg_rmw(ctxt, modrm_reg); 988 return p; 989 } 990 991 static int read_descriptor(struct x86_emulate_ctxt *ctxt, 992 struct segmented_address addr, 993 u16 *size, unsigned long *address, int op_bytes) 994 { 995 int rc; 996 997 if (op_bytes == 2) 998 op_bytes = 3; 999 *address = 0; 1000 rc = segmented_read_std(ctxt, addr, size, 2); 1001 if (rc != X86EMUL_CONTINUE) 1002 return rc; 1003 addr.ea += 2; 1004 rc = segmented_read_std(ctxt, addr, address, op_bytes); 1005 return rc; 1006 } 1007 1008 FASTOP2(add); 1009 FASTOP2(or); 1010 FASTOP2(adc); 1011 FASTOP2(sbb); 1012 FASTOP2(and); 1013 FASTOP2(sub); 1014 FASTOP2(xor); 1015 FASTOP2(cmp); 1016 FASTOP2(test); 1017 1018 FASTOP1SRC2(mul, mul_ex); 1019 FASTOP1SRC2(imul, imul_ex); 1020 FASTOP1SRC2EX(div, div_ex); 1021 FASTOP1SRC2EX(idiv, idiv_ex); 1022 1023 FASTOP3WCL(shld); 1024 FASTOP3WCL(shrd); 1025 1026 FASTOP2W(imul); 1027 1028 FASTOP1(not); 1029 FASTOP1(neg); 1030 FASTOP1(inc); 1031 FASTOP1(dec); 1032 1033 FASTOP2CL(rol); 1034 FASTOP2CL(ror); 1035 FASTOP2CL(rcl); 1036 FASTOP2CL(rcr); 1037 FASTOP2CL(shl); 1038 FASTOP2CL(shr); 1039 FASTOP2CL(sar); 1040 1041 FASTOP2W(bsf); 1042 FASTOP2W(bsr); 1043 FASTOP2W(bt); 1044 FASTOP2W(bts); 1045 FASTOP2W(btr); 1046 FASTOP2W(btc); 1047 1048 FASTOP2(xadd); 1049 1050 FASTOP2R(cmp, cmp_r); 1051 1052 static int em_bsf_c(struct x86_emulate_ctxt *ctxt) 1053 { 1054 /* If src is zero, do not writeback, but update flags */ 1055 if (ctxt->src.val == 0) 1056 ctxt->dst.type = OP_NONE; 1057 return fastop(ctxt, em_bsf); 1058 } 1059 1060 static int em_bsr_c(struct x86_emulate_ctxt *ctxt) 1061 { 1062 /* If src is zero, do not writeback, but update flags */ 1063 if (ctxt->src.val == 0) 1064 ctxt->dst.type = OP_NONE; 1065 return fastop(ctxt, em_bsr); 1066 } 1067 1068 static __always_inline u8 test_cc(unsigned int condition, unsigned long flags) 1069 { 1070 u8 rc; 1071 void (*fop)(void) = (void *)em_setcc + SETCC_ALIGN * (condition & 0xf); 1072 1073 flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF; 1074 asm("push %[flags]; popf; " CALL_NOSPEC 1075 : "=a"(rc) : [thunk_target]"r"(fop), [flags]"r"(flags)); 1076 return rc; 1077 } 1078 1079 static void fetch_register_operand(struct operand *op) 1080 { 1081 switch (op->bytes) { 1082 case 1: 1083 op->val = *(u8 *)op->addr.reg; 1084 break; 1085 case 2: 1086 op->val = *(u16 *)op->addr.reg; 1087 break; 1088 case 4: 1089 op->val = *(u32 *)op->addr.reg; 1090 break; 1091 case 8: 1092 op->val = *(u64 *)op->addr.reg; 1093 break; 1094 } 1095 } 1096 1097 static int em_fninit(struct x86_emulate_ctxt *ctxt) 1098 { 1099 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1100 return emulate_nm(ctxt); 1101 1102 kvm_fpu_get(); 1103 asm volatile("fninit"); 1104 kvm_fpu_put(); 1105 return X86EMUL_CONTINUE; 1106 } 1107 1108 static int em_fnstcw(struct x86_emulate_ctxt *ctxt) 1109 { 1110 u16 fcw; 1111 1112 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1113 return emulate_nm(ctxt); 1114 1115 kvm_fpu_get(); 1116 asm volatile("fnstcw %0": "+m"(fcw)); 1117 kvm_fpu_put(); 1118 1119 ctxt->dst.val = fcw; 1120 1121 return X86EMUL_CONTINUE; 1122 } 1123 1124 static int em_fnstsw(struct x86_emulate_ctxt *ctxt) 1125 { 1126 u16 fsw; 1127 1128 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 1129 return emulate_nm(ctxt); 1130 1131 kvm_fpu_get(); 1132 asm volatile("fnstsw %0": "+m"(fsw)); 1133 kvm_fpu_put(); 1134 1135 ctxt->dst.val = fsw; 1136 1137 return X86EMUL_CONTINUE; 1138 } 1139 1140 static void decode_register_operand(struct x86_emulate_ctxt *ctxt, 1141 struct operand *op) 1142 { 1143 unsigned reg = ctxt->modrm_reg; 1144 1145 if (!(ctxt->d & ModRM)) 1146 reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3); 1147 1148 if (ctxt->d & Sse) { 1149 op->type = OP_XMM; 1150 op->bytes = 16; 1151 op->addr.xmm = reg; 1152 kvm_read_sse_reg(reg, &op->vec_val); 1153 return; 1154 } 1155 if (ctxt->d & Mmx) { 1156 reg &= 7; 1157 op->type = OP_MM; 1158 op->bytes = 8; 1159 op->addr.mm = reg; 1160 return; 1161 } 1162 1163 op->type = OP_REG; 1164 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 1165 op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp); 1166 1167 fetch_register_operand(op); 1168 op->orig_val = op->val; 1169 } 1170 1171 static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg) 1172 { 1173 if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP) 1174 ctxt->modrm_seg = VCPU_SREG_SS; 1175 } 1176 1177 static int decode_modrm(struct x86_emulate_ctxt *ctxt, 1178 struct operand *op) 1179 { 1180 u8 sib; 1181 int index_reg, base_reg, scale; 1182 int rc = X86EMUL_CONTINUE; 1183 ulong modrm_ea = 0; 1184 1185 ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */ 1186 index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */ 1187 base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */ 1188 1189 ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6; 1190 ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3; 1191 ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07); 1192 ctxt->modrm_seg = VCPU_SREG_DS; 1193 1194 if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) { 1195 op->type = OP_REG; 1196 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 1197 op->addr.reg = decode_register(ctxt, ctxt->modrm_rm, 1198 ctxt->d & ByteOp); 1199 if (ctxt->d & Sse) { 1200 op->type = OP_XMM; 1201 op->bytes = 16; 1202 op->addr.xmm = ctxt->modrm_rm; 1203 kvm_read_sse_reg(ctxt->modrm_rm, &op->vec_val); 1204 return rc; 1205 } 1206 if (ctxt->d & Mmx) { 1207 op->type = OP_MM; 1208 op->bytes = 8; 1209 op->addr.mm = ctxt->modrm_rm & 7; 1210 return rc; 1211 } 1212 fetch_register_operand(op); 1213 return rc; 1214 } 1215 1216 op->type = OP_MEM; 1217 1218 if (ctxt->ad_bytes == 2) { 1219 unsigned bx = reg_read(ctxt, VCPU_REGS_RBX); 1220 unsigned bp = reg_read(ctxt, VCPU_REGS_RBP); 1221 unsigned si = reg_read(ctxt, VCPU_REGS_RSI); 1222 unsigned di = reg_read(ctxt, VCPU_REGS_RDI); 1223 1224 /* 16-bit ModR/M decode. */ 1225 switch (ctxt->modrm_mod) { 1226 case 0: 1227 if (ctxt->modrm_rm == 6) 1228 modrm_ea += insn_fetch(u16, ctxt); 1229 break; 1230 case 1: 1231 modrm_ea += insn_fetch(s8, ctxt); 1232 break; 1233 case 2: 1234 modrm_ea += insn_fetch(u16, ctxt); 1235 break; 1236 } 1237 switch (ctxt->modrm_rm) { 1238 case 0: 1239 modrm_ea += bx + si; 1240 break; 1241 case 1: 1242 modrm_ea += bx + di; 1243 break; 1244 case 2: 1245 modrm_ea += bp + si; 1246 break; 1247 case 3: 1248 modrm_ea += bp + di; 1249 break; 1250 case 4: 1251 modrm_ea += si; 1252 break; 1253 case 5: 1254 modrm_ea += di; 1255 break; 1256 case 6: 1257 if (ctxt->modrm_mod != 0) 1258 modrm_ea += bp; 1259 break; 1260 case 7: 1261 modrm_ea += bx; 1262 break; 1263 } 1264 if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 || 1265 (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0)) 1266 ctxt->modrm_seg = VCPU_SREG_SS; 1267 modrm_ea = (u16)modrm_ea; 1268 } else { 1269 /* 32/64-bit ModR/M decode. */ 1270 if ((ctxt->modrm_rm & 7) == 4) { 1271 sib = insn_fetch(u8, ctxt); 1272 index_reg |= (sib >> 3) & 7; 1273 base_reg |= sib & 7; 1274 scale = sib >> 6; 1275 1276 if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0) 1277 modrm_ea += insn_fetch(s32, ctxt); 1278 else { 1279 modrm_ea += reg_read(ctxt, base_reg); 1280 adjust_modrm_seg(ctxt, base_reg); 1281 /* Increment ESP on POP [ESP] */ 1282 if ((ctxt->d & IncSP) && 1283 base_reg == VCPU_REGS_RSP) 1284 modrm_ea += ctxt->op_bytes; 1285 } 1286 if (index_reg != 4) 1287 modrm_ea += reg_read(ctxt, index_reg) << scale; 1288 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) { 1289 modrm_ea += insn_fetch(s32, ctxt); 1290 if (ctxt->mode == X86EMUL_MODE_PROT64) 1291 ctxt->rip_relative = 1; 1292 } else { 1293 base_reg = ctxt->modrm_rm; 1294 modrm_ea += reg_read(ctxt, base_reg); 1295 adjust_modrm_seg(ctxt, base_reg); 1296 } 1297 switch (ctxt->modrm_mod) { 1298 case 1: 1299 modrm_ea += insn_fetch(s8, ctxt); 1300 break; 1301 case 2: 1302 modrm_ea += insn_fetch(s32, ctxt); 1303 break; 1304 } 1305 } 1306 op->addr.mem.ea = modrm_ea; 1307 if (ctxt->ad_bytes != 8) 1308 ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea; 1309 1310 done: 1311 return rc; 1312 } 1313 1314 static int decode_abs(struct x86_emulate_ctxt *ctxt, 1315 struct operand *op) 1316 { 1317 int rc = X86EMUL_CONTINUE; 1318 1319 op->type = OP_MEM; 1320 switch (ctxt->ad_bytes) { 1321 case 2: 1322 op->addr.mem.ea = insn_fetch(u16, ctxt); 1323 break; 1324 case 4: 1325 op->addr.mem.ea = insn_fetch(u32, ctxt); 1326 break; 1327 case 8: 1328 op->addr.mem.ea = insn_fetch(u64, ctxt); 1329 break; 1330 } 1331 done: 1332 return rc; 1333 } 1334 1335 static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt) 1336 { 1337 long sv = 0, mask; 1338 1339 if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) { 1340 mask = ~((long)ctxt->dst.bytes * 8 - 1); 1341 1342 if (ctxt->src.bytes == 2) 1343 sv = (s16)ctxt->src.val & (s16)mask; 1344 else if (ctxt->src.bytes == 4) 1345 sv = (s32)ctxt->src.val & (s32)mask; 1346 else 1347 sv = (s64)ctxt->src.val & (s64)mask; 1348 1349 ctxt->dst.addr.mem.ea = address_mask(ctxt, 1350 ctxt->dst.addr.mem.ea + (sv >> 3)); 1351 } 1352 1353 /* only subword offset */ 1354 ctxt->src.val &= (ctxt->dst.bytes << 3) - 1; 1355 } 1356 1357 static int read_emulated(struct x86_emulate_ctxt *ctxt, 1358 unsigned long addr, void *dest, unsigned size) 1359 { 1360 int rc; 1361 struct read_cache *mc = &ctxt->mem_read; 1362 1363 if (mc->pos < mc->end) 1364 goto read_cached; 1365 1366 WARN_ON((mc->end + size) >= sizeof(mc->data)); 1367 1368 rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size, 1369 &ctxt->exception); 1370 if (rc != X86EMUL_CONTINUE) 1371 return rc; 1372 1373 mc->end += size; 1374 1375 read_cached: 1376 memcpy(dest, mc->data + mc->pos, size); 1377 mc->pos += size; 1378 return X86EMUL_CONTINUE; 1379 } 1380 1381 static int segmented_read(struct x86_emulate_ctxt *ctxt, 1382 struct segmented_address addr, 1383 void *data, 1384 unsigned size) 1385 { 1386 int rc; 1387 ulong linear; 1388 1389 rc = linearize(ctxt, addr, size, false, &linear); 1390 if (rc != X86EMUL_CONTINUE) 1391 return rc; 1392 return read_emulated(ctxt, linear, data, size); 1393 } 1394 1395 static int segmented_write(struct x86_emulate_ctxt *ctxt, 1396 struct segmented_address addr, 1397 const void *data, 1398 unsigned size) 1399 { 1400 int rc; 1401 ulong linear; 1402 1403 rc = linearize(ctxt, addr, size, true, &linear); 1404 if (rc != X86EMUL_CONTINUE) 1405 return rc; 1406 return ctxt->ops->write_emulated(ctxt, linear, data, size, 1407 &ctxt->exception); 1408 } 1409 1410 static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt, 1411 struct segmented_address addr, 1412 const void *orig_data, const void *data, 1413 unsigned size) 1414 { 1415 int rc; 1416 ulong linear; 1417 1418 rc = linearize(ctxt, addr, size, true, &linear); 1419 if (rc != X86EMUL_CONTINUE) 1420 return rc; 1421 return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data, 1422 size, &ctxt->exception); 1423 } 1424 1425 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt, 1426 unsigned int size, unsigned short port, 1427 void *dest) 1428 { 1429 struct read_cache *rc = &ctxt->io_read; 1430 1431 if (rc->pos == rc->end) { /* refill pio read ahead */ 1432 unsigned int in_page, n; 1433 unsigned int count = ctxt->rep_prefix ? 1434 address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1; 1435 in_page = (ctxt->eflags & X86_EFLAGS_DF) ? 1436 offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) : 1437 PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)); 1438 n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count); 1439 if (n == 0) 1440 n = 1; 1441 rc->pos = rc->end = 0; 1442 if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n)) 1443 return 0; 1444 rc->end = n * size; 1445 } 1446 1447 if (ctxt->rep_prefix && (ctxt->d & String) && 1448 !(ctxt->eflags & X86_EFLAGS_DF)) { 1449 ctxt->dst.data = rc->data + rc->pos; 1450 ctxt->dst.type = OP_MEM_STR; 1451 ctxt->dst.count = (rc->end - rc->pos) / size; 1452 rc->pos = rc->end; 1453 } else { 1454 memcpy(dest, rc->data + rc->pos, size); 1455 rc->pos += size; 1456 } 1457 return 1; 1458 } 1459 1460 static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt, 1461 u16 index, struct desc_struct *desc) 1462 { 1463 struct desc_ptr dt; 1464 ulong addr; 1465 1466 ctxt->ops->get_idt(ctxt, &dt); 1467 1468 if (dt.size < index * 8 + 7) 1469 return emulate_gp(ctxt, index << 3 | 0x2); 1470 1471 addr = dt.address + index * 8; 1472 return linear_read_system(ctxt, addr, desc, sizeof(*desc)); 1473 } 1474 1475 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt, 1476 u16 selector, struct desc_ptr *dt) 1477 { 1478 const struct x86_emulate_ops *ops = ctxt->ops; 1479 u32 base3 = 0; 1480 1481 if (selector & 1 << 2) { 1482 struct desc_struct desc; 1483 u16 sel; 1484 1485 memset(dt, 0, sizeof(*dt)); 1486 if (!ops->get_segment(ctxt, &sel, &desc, &base3, 1487 VCPU_SREG_LDTR)) 1488 return; 1489 1490 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */ 1491 dt->address = get_desc_base(&desc) | ((u64)base3 << 32); 1492 } else 1493 ops->get_gdt(ctxt, dt); 1494 } 1495 1496 static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt, 1497 u16 selector, ulong *desc_addr_p) 1498 { 1499 struct desc_ptr dt; 1500 u16 index = selector >> 3; 1501 ulong addr; 1502 1503 get_descriptor_table_ptr(ctxt, selector, &dt); 1504 1505 if (dt.size < index * 8 + 7) 1506 return emulate_gp(ctxt, selector & 0xfffc); 1507 1508 addr = dt.address + index * 8; 1509 1510 #ifdef CONFIG_X86_64 1511 if (addr >> 32 != 0) { 1512 u64 efer = 0; 1513 1514 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 1515 if (!(efer & EFER_LMA)) 1516 addr &= (u32)-1; 1517 } 1518 #endif 1519 1520 *desc_addr_p = addr; 1521 return X86EMUL_CONTINUE; 1522 } 1523 1524 /* allowed just for 8 bytes segments */ 1525 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1526 u16 selector, struct desc_struct *desc, 1527 ulong *desc_addr_p) 1528 { 1529 int rc; 1530 1531 rc = get_descriptor_ptr(ctxt, selector, desc_addr_p); 1532 if (rc != X86EMUL_CONTINUE) 1533 return rc; 1534 1535 return linear_read_system(ctxt, *desc_addr_p, desc, sizeof(*desc)); 1536 } 1537 1538 /* allowed just for 8 bytes segments */ 1539 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1540 u16 selector, struct desc_struct *desc) 1541 { 1542 int rc; 1543 ulong addr; 1544 1545 rc = get_descriptor_ptr(ctxt, selector, &addr); 1546 if (rc != X86EMUL_CONTINUE) 1547 return rc; 1548 1549 return linear_write_system(ctxt, addr, desc, sizeof(*desc)); 1550 } 1551 1552 static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1553 u16 selector, int seg, u8 cpl, 1554 enum x86_transfer_type transfer, 1555 struct desc_struct *desc) 1556 { 1557 struct desc_struct seg_desc, old_desc; 1558 u8 dpl, rpl; 1559 unsigned err_vec = GP_VECTOR; 1560 u32 err_code = 0; 1561 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */ 1562 ulong desc_addr; 1563 int ret; 1564 u16 dummy; 1565 u32 base3 = 0; 1566 1567 memset(&seg_desc, 0, sizeof(seg_desc)); 1568 1569 if (ctxt->mode == X86EMUL_MODE_REAL) { 1570 /* set real mode segment descriptor (keep limit etc. for 1571 * unreal mode) */ 1572 ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg); 1573 set_desc_base(&seg_desc, selector << 4); 1574 goto load; 1575 } else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) { 1576 /* VM86 needs a clean new segment descriptor */ 1577 set_desc_base(&seg_desc, selector << 4); 1578 set_desc_limit(&seg_desc, 0xffff); 1579 seg_desc.type = 3; 1580 seg_desc.p = 1; 1581 seg_desc.s = 1; 1582 seg_desc.dpl = 3; 1583 goto load; 1584 } 1585 1586 rpl = selector & 3; 1587 1588 /* TR should be in GDT only */ 1589 if (seg == VCPU_SREG_TR && (selector & (1 << 2))) 1590 goto exception; 1591 1592 /* NULL selector is not valid for TR, CS and (except for long mode) SS */ 1593 if (null_selector) { 1594 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_TR) 1595 goto exception; 1596 1597 if (seg == VCPU_SREG_SS) { 1598 if (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl) 1599 goto exception; 1600 1601 /* 1602 * ctxt->ops->set_segment expects the CPL to be in 1603 * SS.DPL, so fake an expand-up 32-bit data segment. 1604 */ 1605 seg_desc.type = 3; 1606 seg_desc.p = 1; 1607 seg_desc.s = 1; 1608 seg_desc.dpl = cpl; 1609 seg_desc.d = 1; 1610 seg_desc.g = 1; 1611 } 1612 1613 /* Skip all following checks */ 1614 goto load; 1615 } 1616 1617 ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr); 1618 if (ret != X86EMUL_CONTINUE) 1619 return ret; 1620 1621 err_code = selector & 0xfffc; 1622 err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR : 1623 GP_VECTOR; 1624 1625 /* can't load system descriptor into segment selector */ 1626 if (seg <= VCPU_SREG_GS && !seg_desc.s) { 1627 if (transfer == X86_TRANSFER_CALL_JMP) 1628 return X86EMUL_UNHANDLEABLE; 1629 goto exception; 1630 } 1631 1632 dpl = seg_desc.dpl; 1633 1634 switch (seg) { 1635 case VCPU_SREG_SS: 1636 /* 1637 * segment is not a writable data segment or segment 1638 * selector's RPL != CPL or segment selector's RPL != CPL 1639 */ 1640 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl) 1641 goto exception; 1642 break; 1643 case VCPU_SREG_CS: 1644 if (!(seg_desc.type & 8)) 1645 goto exception; 1646 1647 if (transfer == X86_TRANSFER_RET) { 1648 /* RET can never return to an inner privilege level. */ 1649 if (rpl < cpl) 1650 goto exception; 1651 /* Outer-privilege level return is not implemented */ 1652 if (rpl > cpl) 1653 return X86EMUL_UNHANDLEABLE; 1654 } 1655 if (transfer == X86_TRANSFER_RET || transfer == X86_TRANSFER_TASK_SWITCH) { 1656 if (seg_desc.type & 4) { 1657 /* conforming */ 1658 if (dpl > rpl) 1659 goto exception; 1660 } else { 1661 /* nonconforming */ 1662 if (dpl != rpl) 1663 goto exception; 1664 } 1665 } else { /* X86_TRANSFER_CALL_JMP */ 1666 if (seg_desc.type & 4) { 1667 /* conforming */ 1668 if (dpl > cpl) 1669 goto exception; 1670 } else { 1671 /* nonconforming */ 1672 if (rpl > cpl || dpl != cpl) 1673 goto exception; 1674 } 1675 } 1676 /* in long-mode d/b must be clear if l is set */ 1677 if (seg_desc.d && seg_desc.l) { 1678 u64 efer = 0; 1679 1680 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 1681 if (efer & EFER_LMA) 1682 goto exception; 1683 } 1684 1685 /* CS(RPL) <- CPL */ 1686 selector = (selector & 0xfffc) | cpl; 1687 break; 1688 case VCPU_SREG_TR: 1689 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9)) 1690 goto exception; 1691 if (!seg_desc.p) { 1692 err_vec = NP_VECTOR; 1693 goto exception; 1694 } 1695 old_desc = seg_desc; 1696 seg_desc.type |= 2; /* busy */ 1697 ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc, 1698 sizeof(seg_desc), &ctxt->exception); 1699 if (ret != X86EMUL_CONTINUE) 1700 return ret; 1701 break; 1702 case VCPU_SREG_LDTR: 1703 if (seg_desc.s || seg_desc.type != 2) 1704 goto exception; 1705 break; 1706 default: /* DS, ES, FS, or GS */ 1707 /* 1708 * segment is not a data or readable code segment or 1709 * ((segment is a data or nonconforming code segment) 1710 * and (both RPL and CPL > DPL)) 1711 */ 1712 if ((seg_desc.type & 0xa) == 0x8 || 1713 (((seg_desc.type & 0xc) != 0xc) && 1714 (rpl > dpl && cpl > dpl))) 1715 goto exception; 1716 break; 1717 } 1718 1719 if (!seg_desc.p) { 1720 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR; 1721 goto exception; 1722 } 1723 1724 if (seg_desc.s) { 1725 /* mark segment as accessed */ 1726 if (!(seg_desc.type & 1)) { 1727 seg_desc.type |= 1; 1728 ret = write_segment_descriptor(ctxt, selector, 1729 &seg_desc); 1730 if (ret != X86EMUL_CONTINUE) 1731 return ret; 1732 } 1733 } else if (ctxt->mode == X86EMUL_MODE_PROT64) { 1734 ret = linear_read_system(ctxt, desc_addr+8, &base3, sizeof(base3)); 1735 if (ret != X86EMUL_CONTINUE) 1736 return ret; 1737 if (emul_is_noncanonical_address(get_desc_base(&seg_desc) | 1738 ((u64)base3 << 32), ctxt)) 1739 return emulate_gp(ctxt, 0); 1740 } 1741 load: 1742 ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg); 1743 if (desc) 1744 *desc = seg_desc; 1745 return X86EMUL_CONTINUE; 1746 exception: 1747 return emulate_exception(ctxt, err_vec, err_code, true); 1748 } 1749 1750 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt, 1751 u16 selector, int seg) 1752 { 1753 u8 cpl = ctxt->ops->cpl(ctxt); 1754 1755 /* 1756 * None of MOV, POP and LSS can load a NULL selector in CPL=3, but 1757 * they can load it at CPL<3 (Intel's manual says only LSS can, 1758 * but it's wrong). 1759 * 1760 * However, the Intel manual says that putting IST=1/DPL=3 in 1761 * an interrupt gate will result in SS=3 (the AMD manual instead 1762 * says it doesn't), so allow SS=3 in __load_segment_descriptor 1763 * and only forbid it here. 1764 */ 1765 if (seg == VCPU_SREG_SS && selector == 3 && 1766 ctxt->mode == X86EMUL_MODE_PROT64) 1767 return emulate_exception(ctxt, GP_VECTOR, 0, true); 1768 1769 return __load_segment_descriptor(ctxt, selector, seg, cpl, 1770 X86_TRANSFER_NONE, NULL); 1771 } 1772 1773 static void write_register_operand(struct operand *op) 1774 { 1775 return assign_register(op->addr.reg, op->val, op->bytes); 1776 } 1777 1778 static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op) 1779 { 1780 switch (op->type) { 1781 case OP_REG: 1782 write_register_operand(op); 1783 break; 1784 case OP_MEM: 1785 if (ctxt->lock_prefix) 1786 return segmented_cmpxchg(ctxt, 1787 op->addr.mem, 1788 &op->orig_val, 1789 &op->val, 1790 op->bytes); 1791 else 1792 return segmented_write(ctxt, 1793 op->addr.mem, 1794 &op->val, 1795 op->bytes); 1796 break; 1797 case OP_MEM_STR: 1798 return segmented_write(ctxt, 1799 op->addr.mem, 1800 op->data, 1801 op->bytes * op->count); 1802 break; 1803 case OP_XMM: 1804 kvm_write_sse_reg(op->addr.xmm, &op->vec_val); 1805 break; 1806 case OP_MM: 1807 kvm_write_mmx_reg(op->addr.mm, &op->mm_val); 1808 break; 1809 case OP_NONE: 1810 /* no writeback */ 1811 break; 1812 default: 1813 break; 1814 } 1815 return X86EMUL_CONTINUE; 1816 } 1817 1818 static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes) 1819 { 1820 struct segmented_address addr; 1821 1822 rsp_increment(ctxt, -bytes); 1823 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); 1824 addr.seg = VCPU_SREG_SS; 1825 1826 return segmented_write(ctxt, addr, data, bytes); 1827 } 1828 1829 static int em_push(struct x86_emulate_ctxt *ctxt) 1830 { 1831 /* Disable writeback. */ 1832 ctxt->dst.type = OP_NONE; 1833 return push(ctxt, &ctxt->src.val, ctxt->op_bytes); 1834 } 1835 1836 static int emulate_pop(struct x86_emulate_ctxt *ctxt, 1837 void *dest, int len) 1838 { 1839 int rc; 1840 struct segmented_address addr; 1841 1842 addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt); 1843 addr.seg = VCPU_SREG_SS; 1844 rc = segmented_read(ctxt, addr, dest, len); 1845 if (rc != X86EMUL_CONTINUE) 1846 return rc; 1847 1848 rsp_increment(ctxt, len); 1849 return rc; 1850 } 1851 1852 static int em_pop(struct x86_emulate_ctxt *ctxt) 1853 { 1854 return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1855 } 1856 1857 static int emulate_popf(struct x86_emulate_ctxt *ctxt, 1858 void *dest, int len) 1859 { 1860 int rc; 1861 unsigned long val, change_mask; 1862 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT; 1863 int cpl = ctxt->ops->cpl(ctxt); 1864 1865 rc = emulate_pop(ctxt, &val, len); 1866 if (rc != X86EMUL_CONTINUE) 1867 return rc; 1868 1869 change_mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | 1870 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF | 1871 X86_EFLAGS_TF | X86_EFLAGS_DF | X86_EFLAGS_NT | 1872 X86_EFLAGS_AC | X86_EFLAGS_ID; 1873 1874 switch(ctxt->mode) { 1875 case X86EMUL_MODE_PROT64: 1876 case X86EMUL_MODE_PROT32: 1877 case X86EMUL_MODE_PROT16: 1878 if (cpl == 0) 1879 change_mask |= X86_EFLAGS_IOPL; 1880 if (cpl <= iopl) 1881 change_mask |= X86_EFLAGS_IF; 1882 break; 1883 case X86EMUL_MODE_VM86: 1884 if (iopl < 3) 1885 return emulate_gp(ctxt, 0); 1886 change_mask |= X86_EFLAGS_IF; 1887 break; 1888 default: /* real mode */ 1889 change_mask |= (X86_EFLAGS_IOPL | X86_EFLAGS_IF); 1890 break; 1891 } 1892 1893 *(unsigned long *)dest = 1894 (ctxt->eflags & ~change_mask) | (val & change_mask); 1895 1896 return rc; 1897 } 1898 1899 static int em_popf(struct x86_emulate_ctxt *ctxt) 1900 { 1901 ctxt->dst.type = OP_REG; 1902 ctxt->dst.addr.reg = &ctxt->eflags; 1903 ctxt->dst.bytes = ctxt->op_bytes; 1904 return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes); 1905 } 1906 1907 static int em_enter(struct x86_emulate_ctxt *ctxt) 1908 { 1909 int rc; 1910 unsigned frame_size = ctxt->src.val; 1911 unsigned nesting_level = ctxt->src2.val & 31; 1912 ulong rbp; 1913 1914 if (nesting_level) 1915 return X86EMUL_UNHANDLEABLE; 1916 1917 rbp = reg_read(ctxt, VCPU_REGS_RBP); 1918 rc = push(ctxt, &rbp, stack_size(ctxt)); 1919 if (rc != X86EMUL_CONTINUE) 1920 return rc; 1921 assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP), 1922 stack_mask(ctxt)); 1923 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), 1924 reg_read(ctxt, VCPU_REGS_RSP) - frame_size, 1925 stack_mask(ctxt)); 1926 return X86EMUL_CONTINUE; 1927 } 1928 1929 static int em_leave(struct x86_emulate_ctxt *ctxt) 1930 { 1931 assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP), 1932 stack_mask(ctxt)); 1933 return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes); 1934 } 1935 1936 static int em_push_sreg(struct x86_emulate_ctxt *ctxt) 1937 { 1938 int seg = ctxt->src2.val; 1939 1940 ctxt->src.val = get_segment_selector(ctxt, seg); 1941 if (ctxt->op_bytes == 4) { 1942 rsp_increment(ctxt, -2); 1943 ctxt->op_bytes = 2; 1944 } 1945 1946 return em_push(ctxt); 1947 } 1948 1949 static int em_pop_sreg(struct x86_emulate_ctxt *ctxt) 1950 { 1951 int seg = ctxt->src2.val; 1952 unsigned long selector; 1953 int rc; 1954 1955 rc = emulate_pop(ctxt, &selector, 2); 1956 if (rc != X86EMUL_CONTINUE) 1957 return rc; 1958 1959 if (ctxt->modrm_reg == VCPU_SREG_SS) 1960 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; 1961 if (ctxt->op_bytes > 2) 1962 rsp_increment(ctxt, ctxt->op_bytes - 2); 1963 1964 rc = load_segment_descriptor(ctxt, (u16)selector, seg); 1965 return rc; 1966 } 1967 1968 static int em_pusha(struct x86_emulate_ctxt *ctxt) 1969 { 1970 unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP); 1971 int rc = X86EMUL_CONTINUE; 1972 int reg = VCPU_REGS_RAX; 1973 1974 while (reg <= VCPU_REGS_RDI) { 1975 (reg == VCPU_REGS_RSP) ? 1976 (ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg)); 1977 1978 rc = em_push(ctxt); 1979 if (rc != X86EMUL_CONTINUE) 1980 return rc; 1981 1982 ++reg; 1983 } 1984 1985 return rc; 1986 } 1987 1988 static int em_pushf(struct x86_emulate_ctxt *ctxt) 1989 { 1990 ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM; 1991 return em_push(ctxt); 1992 } 1993 1994 static int em_popa(struct x86_emulate_ctxt *ctxt) 1995 { 1996 int rc = X86EMUL_CONTINUE; 1997 int reg = VCPU_REGS_RDI; 1998 u32 val; 1999 2000 while (reg >= VCPU_REGS_RAX) { 2001 if (reg == VCPU_REGS_RSP) { 2002 rsp_increment(ctxt, ctxt->op_bytes); 2003 --reg; 2004 } 2005 2006 rc = emulate_pop(ctxt, &val, ctxt->op_bytes); 2007 if (rc != X86EMUL_CONTINUE) 2008 break; 2009 assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes); 2010 --reg; 2011 } 2012 return rc; 2013 } 2014 2015 static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) 2016 { 2017 const struct x86_emulate_ops *ops = ctxt->ops; 2018 int rc; 2019 struct desc_ptr dt; 2020 gva_t cs_addr; 2021 gva_t eip_addr; 2022 u16 cs, eip; 2023 2024 /* TODO: Add limit checks */ 2025 ctxt->src.val = ctxt->eflags; 2026 rc = em_push(ctxt); 2027 if (rc != X86EMUL_CONTINUE) 2028 return rc; 2029 2030 ctxt->eflags &= ~(X86_EFLAGS_IF | X86_EFLAGS_TF | X86_EFLAGS_AC); 2031 2032 ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS); 2033 rc = em_push(ctxt); 2034 if (rc != X86EMUL_CONTINUE) 2035 return rc; 2036 2037 ctxt->src.val = ctxt->_eip; 2038 rc = em_push(ctxt); 2039 if (rc != X86EMUL_CONTINUE) 2040 return rc; 2041 2042 ops->get_idt(ctxt, &dt); 2043 2044 eip_addr = dt.address + (irq << 2); 2045 cs_addr = dt.address + (irq << 2) + 2; 2046 2047 rc = linear_read_system(ctxt, cs_addr, &cs, 2); 2048 if (rc != X86EMUL_CONTINUE) 2049 return rc; 2050 2051 rc = linear_read_system(ctxt, eip_addr, &eip, 2); 2052 if (rc != X86EMUL_CONTINUE) 2053 return rc; 2054 2055 rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS); 2056 if (rc != X86EMUL_CONTINUE) 2057 return rc; 2058 2059 ctxt->_eip = eip; 2060 2061 return rc; 2062 } 2063 2064 int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq) 2065 { 2066 int rc; 2067 2068 invalidate_registers(ctxt); 2069 rc = __emulate_int_real(ctxt, irq); 2070 if (rc == X86EMUL_CONTINUE) 2071 writeback_registers(ctxt); 2072 return rc; 2073 } 2074 2075 static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq) 2076 { 2077 switch(ctxt->mode) { 2078 case X86EMUL_MODE_REAL: 2079 return __emulate_int_real(ctxt, irq); 2080 case X86EMUL_MODE_VM86: 2081 case X86EMUL_MODE_PROT16: 2082 case X86EMUL_MODE_PROT32: 2083 case X86EMUL_MODE_PROT64: 2084 default: 2085 /* Protected mode interrupts unimplemented yet */ 2086 return X86EMUL_UNHANDLEABLE; 2087 } 2088 } 2089 2090 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt) 2091 { 2092 int rc = X86EMUL_CONTINUE; 2093 unsigned long temp_eip = 0; 2094 unsigned long temp_eflags = 0; 2095 unsigned long cs = 0; 2096 unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | 2097 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_TF | 2098 X86_EFLAGS_IF | X86_EFLAGS_DF | X86_EFLAGS_OF | 2099 X86_EFLAGS_IOPL | X86_EFLAGS_NT | X86_EFLAGS_RF | 2100 X86_EFLAGS_AC | X86_EFLAGS_ID | 2101 X86_EFLAGS_FIXED; 2102 unsigned long vm86_mask = X86_EFLAGS_VM | X86_EFLAGS_VIF | 2103 X86_EFLAGS_VIP; 2104 2105 /* TODO: Add stack limit check */ 2106 2107 rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes); 2108 2109 if (rc != X86EMUL_CONTINUE) 2110 return rc; 2111 2112 if (temp_eip & ~0xffff) 2113 return emulate_gp(ctxt, 0); 2114 2115 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 2116 2117 if (rc != X86EMUL_CONTINUE) 2118 return rc; 2119 2120 rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes); 2121 2122 if (rc != X86EMUL_CONTINUE) 2123 return rc; 2124 2125 rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS); 2126 2127 if (rc != X86EMUL_CONTINUE) 2128 return rc; 2129 2130 ctxt->_eip = temp_eip; 2131 2132 if (ctxt->op_bytes == 4) 2133 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask)); 2134 else if (ctxt->op_bytes == 2) { 2135 ctxt->eflags &= ~0xffff; 2136 ctxt->eflags |= temp_eflags; 2137 } 2138 2139 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */ 2140 ctxt->eflags |= X86_EFLAGS_FIXED; 2141 ctxt->ops->set_nmi_mask(ctxt, false); 2142 2143 return rc; 2144 } 2145 2146 static int em_iret(struct x86_emulate_ctxt *ctxt) 2147 { 2148 switch(ctxt->mode) { 2149 case X86EMUL_MODE_REAL: 2150 return emulate_iret_real(ctxt); 2151 case X86EMUL_MODE_VM86: 2152 case X86EMUL_MODE_PROT16: 2153 case X86EMUL_MODE_PROT32: 2154 case X86EMUL_MODE_PROT64: 2155 default: 2156 /* iret from protected mode unimplemented yet */ 2157 return X86EMUL_UNHANDLEABLE; 2158 } 2159 } 2160 2161 static int em_jmp_far(struct x86_emulate_ctxt *ctxt) 2162 { 2163 int rc; 2164 unsigned short sel; 2165 struct desc_struct new_desc; 2166 u8 cpl = ctxt->ops->cpl(ctxt); 2167 2168 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2169 2170 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, 2171 X86_TRANSFER_CALL_JMP, 2172 &new_desc); 2173 if (rc != X86EMUL_CONTINUE) 2174 return rc; 2175 2176 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc); 2177 /* Error handling is not implemented. */ 2178 if (rc != X86EMUL_CONTINUE) 2179 return X86EMUL_UNHANDLEABLE; 2180 2181 return rc; 2182 } 2183 2184 static int em_jmp_abs(struct x86_emulate_ctxt *ctxt) 2185 { 2186 return assign_eip_near(ctxt, ctxt->src.val); 2187 } 2188 2189 static int em_call_near_abs(struct x86_emulate_ctxt *ctxt) 2190 { 2191 int rc; 2192 long int old_eip; 2193 2194 old_eip = ctxt->_eip; 2195 rc = assign_eip_near(ctxt, ctxt->src.val); 2196 if (rc != X86EMUL_CONTINUE) 2197 return rc; 2198 ctxt->src.val = old_eip; 2199 rc = em_push(ctxt); 2200 return rc; 2201 } 2202 2203 static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt) 2204 { 2205 u64 old = ctxt->dst.orig_val64; 2206 2207 if (ctxt->dst.bytes == 16) 2208 return X86EMUL_UNHANDLEABLE; 2209 2210 if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) || 2211 ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) { 2212 *reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0); 2213 *reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32); 2214 ctxt->eflags &= ~X86_EFLAGS_ZF; 2215 } else { 2216 ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) | 2217 (u32) reg_read(ctxt, VCPU_REGS_RBX); 2218 2219 ctxt->eflags |= X86_EFLAGS_ZF; 2220 } 2221 return X86EMUL_CONTINUE; 2222 } 2223 2224 static int em_ret(struct x86_emulate_ctxt *ctxt) 2225 { 2226 int rc; 2227 unsigned long eip; 2228 2229 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 2230 if (rc != X86EMUL_CONTINUE) 2231 return rc; 2232 2233 return assign_eip_near(ctxt, eip); 2234 } 2235 2236 static int em_ret_far(struct x86_emulate_ctxt *ctxt) 2237 { 2238 int rc; 2239 unsigned long eip, cs; 2240 int cpl = ctxt->ops->cpl(ctxt); 2241 struct desc_struct new_desc; 2242 2243 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 2244 if (rc != X86EMUL_CONTINUE) 2245 return rc; 2246 rc = emulate_pop(ctxt, &cs, ctxt->op_bytes); 2247 if (rc != X86EMUL_CONTINUE) 2248 return rc; 2249 rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl, 2250 X86_TRANSFER_RET, 2251 &new_desc); 2252 if (rc != X86EMUL_CONTINUE) 2253 return rc; 2254 rc = assign_eip_far(ctxt, eip, &new_desc); 2255 /* Error handling is not implemented. */ 2256 if (rc != X86EMUL_CONTINUE) 2257 return X86EMUL_UNHANDLEABLE; 2258 2259 return rc; 2260 } 2261 2262 static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt) 2263 { 2264 int rc; 2265 2266 rc = em_ret_far(ctxt); 2267 if (rc != X86EMUL_CONTINUE) 2268 return rc; 2269 rsp_increment(ctxt, ctxt->src.val); 2270 return X86EMUL_CONTINUE; 2271 } 2272 2273 static int em_cmpxchg(struct x86_emulate_ctxt *ctxt) 2274 { 2275 /* Save real source value, then compare EAX against destination. */ 2276 ctxt->dst.orig_val = ctxt->dst.val; 2277 ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX); 2278 ctxt->src.orig_val = ctxt->src.val; 2279 ctxt->src.val = ctxt->dst.orig_val; 2280 fastop(ctxt, em_cmp); 2281 2282 if (ctxt->eflags & X86_EFLAGS_ZF) { 2283 /* Success: write back to memory; no update of EAX */ 2284 ctxt->src.type = OP_NONE; 2285 ctxt->dst.val = ctxt->src.orig_val; 2286 } else { 2287 /* Failure: write the value we saw to EAX. */ 2288 ctxt->src.type = OP_REG; 2289 ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 2290 ctxt->src.val = ctxt->dst.orig_val; 2291 /* Create write-cycle to dest by writing the same value */ 2292 ctxt->dst.val = ctxt->dst.orig_val; 2293 } 2294 return X86EMUL_CONTINUE; 2295 } 2296 2297 static int em_lseg(struct x86_emulate_ctxt *ctxt) 2298 { 2299 int seg = ctxt->src2.val; 2300 unsigned short sel; 2301 int rc; 2302 2303 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 2304 2305 rc = load_segment_descriptor(ctxt, sel, seg); 2306 if (rc != X86EMUL_CONTINUE) 2307 return rc; 2308 2309 ctxt->dst.val = ctxt->src.val; 2310 return rc; 2311 } 2312 2313 static int emulator_has_longmode(struct x86_emulate_ctxt *ctxt) 2314 { 2315 #ifdef CONFIG_X86_64 2316 return ctxt->ops->guest_has_long_mode(ctxt); 2317 #else 2318 return false; 2319 #endif 2320 } 2321 2322 static void rsm_set_desc_flags(struct desc_struct *desc, u32 flags) 2323 { 2324 desc->g = (flags >> 23) & 1; 2325 desc->d = (flags >> 22) & 1; 2326 desc->l = (flags >> 21) & 1; 2327 desc->avl = (flags >> 20) & 1; 2328 desc->p = (flags >> 15) & 1; 2329 desc->dpl = (flags >> 13) & 3; 2330 desc->s = (flags >> 12) & 1; 2331 desc->type = (flags >> 8) & 15; 2332 } 2333 2334 static int rsm_load_seg_32(struct x86_emulate_ctxt *ctxt, const char *smstate, 2335 int n) 2336 { 2337 struct desc_struct desc; 2338 int offset; 2339 u16 selector; 2340 2341 selector = GET_SMSTATE(u32, smstate, 0x7fa8 + n * 4); 2342 2343 if (n < 3) 2344 offset = 0x7f84 + n * 12; 2345 else 2346 offset = 0x7f2c + (n - 3) * 12; 2347 2348 set_desc_base(&desc, GET_SMSTATE(u32, smstate, offset + 8)); 2349 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, offset + 4)); 2350 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, offset)); 2351 ctxt->ops->set_segment(ctxt, selector, &desc, 0, n); 2352 return X86EMUL_CONTINUE; 2353 } 2354 2355 #ifdef CONFIG_X86_64 2356 static int rsm_load_seg_64(struct x86_emulate_ctxt *ctxt, const char *smstate, 2357 int n) 2358 { 2359 struct desc_struct desc; 2360 int offset; 2361 u16 selector; 2362 u32 base3; 2363 2364 offset = 0x7e00 + n * 16; 2365 2366 selector = GET_SMSTATE(u16, smstate, offset); 2367 rsm_set_desc_flags(&desc, GET_SMSTATE(u16, smstate, offset + 2) << 8); 2368 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, offset + 4)); 2369 set_desc_base(&desc, GET_SMSTATE(u32, smstate, offset + 8)); 2370 base3 = GET_SMSTATE(u32, smstate, offset + 12); 2371 2372 ctxt->ops->set_segment(ctxt, selector, &desc, base3, n); 2373 return X86EMUL_CONTINUE; 2374 } 2375 #endif 2376 2377 static int rsm_enter_protected_mode(struct x86_emulate_ctxt *ctxt, 2378 u64 cr0, u64 cr3, u64 cr4) 2379 { 2380 int bad; 2381 u64 pcid; 2382 2383 /* In order to later set CR4.PCIDE, CR3[11:0] must be zero. */ 2384 pcid = 0; 2385 if (cr4 & X86_CR4_PCIDE) { 2386 pcid = cr3 & 0xfff; 2387 cr3 &= ~0xfff; 2388 } 2389 2390 bad = ctxt->ops->set_cr(ctxt, 3, cr3); 2391 if (bad) 2392 return X86EMUL_UNHANDLEABLE; 2393 2394 /* 2395 * First enable PAE, long mode needs it before CR0.PG = 1 is set. 2396 * Then enable protected mode. However, PCID cannot be enabled 2397 * if EFER.LMA=0, so set it separately. 2398 */ 2399 bad = ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE); 2400 if (bad) 2401 return X86EMUL_UNHANDLEABLE; 2402 2403 bad = ctxt->ops->set_cr(ctxt, 0, cr0); 2404 if (bad) 2405 return X86EMUL_UNHANDLEABLE; 2406 2407 if (cr4 & X86_CR4_PCIDE) { 2408 bad = ctxt->ops->set_cr(ctxt, 4, cr4); 2409 if (bad) 2410 return X86EMUL_UNHANDLEABLE; 2411 if (pcid) { 2412 bad = ctxt->ops->set_cr(ctxt, 3, cr3 | pcid); 2413 if (bad) 2414 return X86EMUL_UNHANDLEABLE; 2415 } 2416 2417 } 2418 2419 return X86EMUL_CONTINUE; 2420 } 2421 2422 static int rsm_load_state_32(struct x86_emulate_ctxt *ctxt, 2423 const char *smstate) 2424 { 2425 struct desc_struct desc; 2426 struct desc_ptr dt; 2427 u16 selector; 2428 u32 val, cr0, cr3, cr4; 2429 int i; 2430 2431 cr0 = GET_SMSTATE(u32, smstate, 0x7ffc); 2432 cr3 = GET_SMSTATE(u32, smstate, 0x7ff8); 2433 ctxt->eflags = GET_SMSTATE(u32, smstate, 0x7ff4) | X86_EFLAGS_FIXED; 2434 ctxt->_eip = GET_SMSTATE(u32, smstate, 0x7ff0); 2435 2436 for (i = 0; i < 8; i++) 2437 *reg_write(ctxt, i) = GET_SMSTATE(u32, smstate, 0x7fd0 + i * 4); 2438 2439 val = GET_SMSTATE(u32, smstate, 0x7fcc); 2440 2441 if (ctxt->ops->set_dr(ctxt, 6, val)) 2442 return X86EMUL_UNHANDLEABLE; 2443 2444 val = GET_SMSTATE(u32, smstate, 0x7fc8); 2445 2446 if (ctxt->ops->set_dr(ctxt, 7, val)) 2447 return X86EMUL_UNHANDLEABLE; 2448 2449 selector = GET_SMSTATE(u32, smstate, 0x7fc4); 2450 set_desc_base(&desc, GET_SMSTATE(u32, smstate, 0x7f64)); 2451 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, 0x7f60)); 2452 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, 0x7f5c)); 2453 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_TR); 2454 2455 selector = GET_SMSTATE(u32, smstate, 0x7fc0); 2456 set_desc_base(&desc, GET_SMSTATE(u32, smstate, 0x7f80)); 2457 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, 0x7f7c)); 2458 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, 0x7f78)); 2459 ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_LDTR); 2460 2461 dt.address = GET_SMSTATE(u32, smstate, 0x7f74); 2462 dt.size = GET_SMSTATE(u32, smstate, 0x7f70); 2463 ctxt->ops->set_gdt(ctxt, &dt); 2464 2465 dt.address = GET_SMSTATE(u32, smstate, 0x7f58); 2466 dt.size = GET_SMSTATE(u32, smstate, 0x7f54); 2467 ctxt->ops->set_idt(ctxt, &dt); 2468 2469 for (i = 0; i < 6; i++) { 2470 int r = rsm_load_seg_32(ctxt, smstate, i); 2471 if (r != X86EMUL_CONTINUE) 2472 return r; 2473 } 2474 2475 cr4 = GET_SMSTATE(u32, smstate, 0x7f14); 2476 2477 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smstate, 0x7ef8)); 2478 2479 return rsm_enter_protected_mode(ctxt, cr0, cr3, cr4); 2480 } 2481 2482 #ifdef CONFIG_X86_64 2483 static int rsm_load_state_64(struct x86_emulate_ctxt *ctxt, 2484 const char *smstate) 2485 { 2486 struct desc_struct desc; 2487 struct desc_ptr dt; 2488 u64 val, cr0, cr3, cr4; 2489 u32 base3; 2490 u16 selector; 2491 int i, r; 2492 2493 for (i = 0; i < 16; i++) 2494 *reg_write(ctxt, i) = GET_SMSTATE(u64, smstate, 0x7ff8 - i * 8); 2495 2496 ctxt->_eip = GET_SMSTATE(u64, smstate, 0x7f78); 2497 ctxt->eflags = GET_SMSTATE(u32, smstate, 0x7f70) | X86_EFLAGS_FIXED; 2498 2499 val = GET_SMSTATE(u64, smstate, 0x7f68); 2500 2501 if (ctxt->ops->set_dr(ctxt, 6, val)) 2502 return X86EMUL_UNHANDLEABLE; 2503 2504 val = GET_SMSTATE(u64, smstate, 0x7f60); 2505 2506 if (ctxt->ops->set_dr(ctxt, 7, val)) 2507 return X86EMUL_UNHANDLEABLE; 2508 2509 cr0 = GET_SMSTATE(u64, smstate, 0x7f58); 2510 cr3 = GET_SMSTATE(u64, smstate, 0x7f50); 2511 cr4 = GET_SMSTATE(u64, smstate, 0x7f48); 2512 ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smstate, 0x7f00)); 2513 val = GET_SMSTATE(u64, smstate, 0x7ed0); 2514 2515 if (ctxt->ops->set_msr(ctxt, MSR_EFER, val & ~EFER_LMA)) 2516 return X86EMUL_UNHANDLEABLE; 2517 2518 selector = GET_SMSTATE(u32, smstate, 0x7e90); 2519 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, 0x7e92) << 8); 2520 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, 0x7e94)); 2521 set_desc_base(&desc, GET_SMSTATE(u32, smstate, 0x7e98)); 2522 base3 = GET_SMSTATE(u32, smstate, 0x7e9c); 2523 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_TR); 2524 2525 dt.size = GET_SMSTATE(u32, smstate, 0x7e84); 2526 dt.address = GET_SMSTATE(u64, smstate, 0x7e88); 2527 ctxt->ops->set_idt(ctxt, &dt); 2528 2529 selector = GET_SMSTATE(u32, smstate, 0x7e70); 2530 rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smstate, 0x7e72) << 8); 2531 set_desc_limit(&desc, GET_SMSTATE(u32, smstate, 0x7e74)); 2532 set_desc_base(&desc, GET_SMSTATE(u32, smstate, 0x7e78)); 2533 base3 = GET_SMSTATE(u32, smstate, 0x7e7c); 2534 ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_LDTR); 2535 2536 dt.size = GET_SMSTATE(u32, smstate, 0x7e64); 2537 dt.address = GET_SMSTATE(u64, smstate, 0x7e68); 2538 ctxt->ops->set_gdt(ctxt, &dt); 2539 2540 r = rsm_enter_protected_mode(ctxt, cr0, cr3, cr4); 2541 if (r != X86EMUL_CONTINUE) 2542 return r; 2543 2544 for (i = 0; i < 6; i++) { 2545 r = rsm_load_seg_64(ctxt, smstate, i); 2546 if (r != X86EMUL_CONTINUE) 2547 return r; 2548 } 2549 2550 return X86EMUL_CONTINUE; 2551 } 2552 #endif 2553 2554 static int em_rsm(struct x86_emulate_ctxt *ctxt) 2555 { 2556 unsigned long cr0, cr4, efer; 2557 char buf[512]; 2558 u64 smbase; 2559 int ret; 2560 2561 if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_MASK) == 0) 2562 return emulate_ud(ctxt); 2563 2564 smbase = ctxt->ops->get_smbase(ctxt); 2565 2566 ret = ctxt->ops->read_phys(ctxt, smbase + 0xfe00, buf, sizeof(buf)); 2567 if (ret != X86EMUL_CONTINUE) 2568 return X86EMUL_UNHANDLEABLE; 2569 2570 if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_INSIDE_NMI_MASK) == 0) 2571 ctxt->ops->set_nmi_mask(ctxt, false); 2572 2573 ctxt->ops->exiting_smm(ctxt); 2574 2575 /* 2576 * Get back to real mode, to prepare a safe state in which to load 2577 * CR0/CR3/CR4/EFER. It's all a bit more complicated if the vCPU 2578 * supports long mode. 2579 */ 2580 if (emulator_has_longmode(ctxt)) { 2581 struct desc_struct cs_desc; 2582 2583 /* Zero CR4.PCIDE before CR0.PG. */ 2584 cr4 = ctxt->ops->get_cr(ctxt, 4); 2585 if (cr4 & X86_CR4_PCIDE) 2586 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE); 2587 2588 /* A 32-bit code segment is required to clear EFER.LMA. */ 2589 memset(&cs_desc, 0, sizeof(cs_desc)); 2590 cs_desc.type = 0xb; 2591 cs_desc.s = cs_desc.g = cs_desc.p = 1; 2592 ctxt->ops->set_segment(ctxt, 0, &cs_desc, 0, VCPU_SREG_CS); 2593 } 2594 2595 /* For the 64-bit case, this will clear EFER.LMA. */ 2596 cr0 = ctxt->ops->get_cr(ctxt, 0); 2597 if (cr0 & X86_CR0_PE) 2598 ctxt->ops->set_cr(ctxt, 0, cr0 & ~(X86_CR0_PG | X86_CR0_PE)); 2599 2600 if (emulator_has_longmode(ctxt)) { 2601 /* Clear CR4.PAE before clearing EFER.LME. */ 2602 cr4 = ctxt->ops->get_cr(ctxt, 4); 2603 if (cr4 & X86_CR4_PAE) 2604 ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PAE); 2605 2606 /* And finally go back to 32-bit mode. */ 2607 efer = 0; 2608 ctxt->ops->set_msr(ctxt, MSR_EFER, efer); 2609 } 2610 2611 /* 2612 * Give leave_smm() a chance to make ISA-specific changes to the vCPU 2613 * state (e.g. enter guest mode) before loading state from the SMM 2614 * state-save area. 2615 */ 2616 if (ctxt->ops->leave_smm(ctxt, buf)) 2617 goto emulate_shutdown; 2618 2619 #ifdef CONFIG_X86_64 2620 if (emulator_has_longmode(ctxt)) 2621 ret = rsm_load_state_64(ctxt, buf); 2622 else 2623 #endif 2624 ret = rsm_load_state_32(ctxt, buf); 2625 2626 if (ret != X86EMUL_CONTINUE) 2627 goto emulate_shutdown; 2628 2629 /* 2630 * Note, the ctxt->ops callbacks are responsible for handling side 2631 * effects when writing MSRs and CRs, e.g. MMU context resets, CPUID 2632 * runtime updates, etc... If that changes, e.g. this flow is moved 2633 * out of the emulator to make it look more like enter_smm(), then 2634 * those side effects need to be explicitly handled for both success 2635 * and shutdown. 2636 */ 2637 return X86EMUL_CONTINUE; 2638 2639 emulate_shutdown: 2640 ctxt->ops->triple_fault(ctxt); 2641 return X86EMUL_CONTINUE; 2642 } 2643 2644 static void 2645 setup_syscalls_segments(struct desc_struct *cs, struct desc_struct *ss) 2646 { 2647 cs->l = 0; /* will be adjusted later */ 2648 set_desc_base(cs, 0); /* flat segment */ 2649 cs->g = 1; /* 4kb granularity */ 2650 set_desc_limit(cs, 0xfffff); /* 4GB limit */ 2651 cs->type = 0x0b; /* Read, Execute, Accessed */ 2652 cs->s = 1; 2653 cs->dpl = 0; /* will be adjusted later */ 2654 cs->p = 1; 2655 cs->d = 1; 2656 cs->avl = 0; 2657 2658 set_desc_base(ss, 0); /* flat segment */ 2659 set_desc_limit(ss, 0xfffff); /* 4GB limit */ 2660 ss->g = 1; /* 4kb granularity */ 2661 ss->s = 1; 2662 ss->type = 0x03; /* Read/Write, Accessed */ 2663 ss->d = 1; /* 32bit stack segment */ 2664 ss->dpl = 0; 2665 ss->p = 1; 2666 ss->l = 0; 2667 ss->avl = 0; 2668 } 2669 2670 static bool vendor_intel(struct x86_emulate_ctxt *ctxt) 2671 { 2672 u32 eax, ebx, ecx, edx; 2673 2674 eax = ecx = 0; 2675 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, true); 2676 return is_guest_vendor_intel(ebx, ecx, edx); 2677 } 2678 2679 static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt) 2680 { 2681 const struct x86_emulate_ops *ops = ctxt->ops; 2682 u32 eax, ebx, ecx, edx; 2683 2684 /* 2685 * syscall should always be enabled in longmode - so only become 2686 * vendor specific (cpuid) if other modes are active... 2687 */ 2688 if (ctxt->mode == X86EMUL_MODE_PROT64) 2689 return true; 2690 2691 eax = 0x00000000; 2692 ecx = 0x00000000; 2693 ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, true); 2694 /* 2695 * remark: Intel CPUs only support "syscall" in 64bit longmode. Also a 2696 * 64bit guest with a 32bit compat-app running will #UD !! While this 2697 * behaviour can be fixed (by emulating) into AMD response - CPUs of 2698 * AMD can't behave like Intel. 2699 */ 2700 if (is_guest_vendor_intel(ebx, ecx, edx)) 2701 return false; 2702 2703 if (is_guest_vendor_amd(ebx, ecx, edx) || 2704 is_guest_vendor_hygon(ebx, ecx, edx)) 2705 return true; 2706 2707 /* 2708 * default: (not Intel, not AMD, not Hygon), apply Intel's 2709 * stricter rules... 2710 */ 2711 return false; 2712 } 2713 2714 static int em_syscall(struct x86_emulate_ctxt *ctxt) 2715 { 2716 const struct x86_emulate_ops *ops = ctxt->ops; 2717 struct desc_struct cs, ss; 2718 u64 msr_data; 2719 u16 cs_sel, ss_sel; 2720 u64 efer = 0; 2721 2722 /* syscall is not available in real mode */ 2723 if (ctxt->mode == X86EMUL_MODE_REAL || 2724 ctxt->mode == X86EMUL_MODE_VM86) 2725 return emulate_ud(ctxt); 2726 2727 if (!(em_syscall_is_enabled(ctxt))) 2728 return emulate_ud(ctxt); 2729 2730 ops->get_msr(ctxt, MSR_EFER, &efer); 2731 if (!(efer & EFER_SCE)) 2732 return emulate_ud(ctxt); 2733 2734 setup_syscalls_segments(&cs, &ss); 2735 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2736 msr_data >>= 32; 2737 cs_sel = (u16)(msr_data & 0xfffc); 2738 ss_sel = (u16)(msr_data + 8); 2739 2740 if (efer & EFER_LMA) { 2741 cs.d = 0; 2742 cs.l = 1; 2743 } 2744 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2745 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2746 2747 *reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip; 2748 if (efer & EFER_LMA) { 2749 #ifdef CONFIG_X86_64 2750 *reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags; 2751 2752 ops->get_msr(ctxt, 2753 ctxt->mode == X86EMUL_MODE_PROT64 ? 2754 MSR_LSTAR : MSR_CSTAR, &msr_data); 2755 ctxt->_eip = msr_data; 2756 2757 ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data); 2758 ctxt->eflags &= ~msr_data; 2759 ctxt->eflags |= X86_EFLAGS_FIXED; 2760 #endif 2761 } else { 2762 /* legacy mode */ 2763 ops->get_msr(ctxt, MSR_STAR, &msr_data); 2764 ctxt->_eip = (u32)msr_data; 2765 2766 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF); 2767 } 2768 2769 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0; 2770 return X86EMUL_CONTINUE; 2771 } 2772 2773 static int em_sysenter(struct x86_emulate_ctxt *ctxt) 2774 { 2775 const struct x86_emulate_ops *ops = ctxt->ops; 2776 struct desc_struct cs, ss; 2777 u64 msr_data; 2778 u16 cs_sel, ss_sel; 2779 u64 efer = 0; 2780 2781 ops->get_msr(ctxt, MSR_EFER, &efer); 2782 /* inject #GP if in real mode */ 2783 if (ctxt->mode == X86EMUL_MODE_REAL) 2784 return emulate_gp(ctxt, 0); 2785 2786 /* 2787 * Not recognized on AMD in compat mode (but is recognized in legacy 2788 * mode). 2789 */ 2790 if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA) 2791 && !vendor_intel(ctxt)) 2792 return emulate_ud(ctxt); 2793 2794 /* sysenter/sysexit have not been tested in 64bit mode. */ 2795 if (ctxt->mode == X86EMUL_MODE_PROT64) 2796 return X86EMUL_UNHANDLEABLE; 2797 2798 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2799 if ((msr_data & 0xfffc) == 0x0) 2800 return emulate_gp(ctxt, 0); 2801 2802 setup_syscalls_segments(&cs, &ss); 2803 ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF); 2804 cs_sel = (u16)msr_data & ~SEGMENT_RPL_MASK; 2805 ss_sel = cs_sel + 8; 2806 if (efer & EFER_LMA) { 2807 cs.d = 0; 2808 cs.l = 1; 2809 } 2810 2811 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2812 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2813 2814 ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data); 2815 ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data; 2816 2817 ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data); 2818 *reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data : 2819 (u32)msr_data; 2820 if (efer & EFER_LMA) 2821 ctxt->mode = X86EMUL_MODE_PROT64; 2822 2823 return X86EMUL_CONTINUE; 2824 } 2825 2826 static int em_sysexit(struct x86_emulate_ctxt *ctxt) 2827 { 2828 const struct x86_emulate_ops *ops = ctxt->ops; 2829 struct desc_struct cs, ss; 2830 u64 msr_data, rcx, rdx; 2831 int usermode; 2832 u16 cs_sel = 0, ss_sel = 0; 2833 2834 /* inject #GP if in real mode or Virtual 8086 mode */ 2835 if (ctxt->mode == X86EMUL_MODE_REAL || 2836 ctxt->mode == X86EMUL_MODE_VM86) 2837 return emulate_gp(ctxt, 0); 2838 2839 setup_syscalls_segments(&cs, &ss); 2840 2841 if ((ctxt->rex_prefix & 0x8) != 0x0) 2842 usermode = X86EMUL_MODE_PROT64; 2843 else 2844 usermode = X86EMUL_MODE_PROT32; 2845 2846 rcx = reg_read(ctxt, VCPU_REGS_RCX); 2847 rdx = reg_read(ctxt, VCPU_REGS_RDX); 2848 2849 cs.dpl = 3; 2850 ss.dpl = 3; 2851 ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data); 2852 switch (usermode) { 2853 case X86EMUL_MODE_PROT32: 2854 cs_sel = (u16)(msr_data + 16); 2855 if ((msr_data & 0xfffc) == 0x0) 2856 return emulate_gp(ctxt, 0); 2857 ss_sel = (u16)(msr_data + 24); 2858 rcx = (u32)rcx; 2859 rdx = (u32)rdx; 2860 break; 2861 case X86EMUL_MODE_PROT64: 2862 cs_sel = (u16)(msr_data + 32); 2863 if (msr_data == 0x0) 2864 return emulate_gp(ctxt, 0); 2865 ss_sel = cs_sel + 8; 2866 cs.d = 0; 2867 cs.l = 1; 2868 if (emul_is_noncanonical_address(rcx, ctxt) || 2869 emul_is_noncanonical_address(rdx, ctxt)) 2870 return emulate_gp(ctxt, 0); 2871 break; 2872 } 2873 cs_sel |= SEGMENT_RPL_MASK; 2874 ss_sel |= SEGMENT_RPL_MASK; 2875 2876 ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS); 2877 ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS); 2878 2879 ctxt->_eip = rdx; 2880 *reg_write(ctxt, VCPU_REGS_RSP) = rcx; 2881 2882 return X86EMUL_CONTINUE; 2883 } 2884 2885 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt) 2886 { 2887 int iopl; 2888 if (ctxt->mode == X86EMUL_MODE_REAL) 2889 return false; 2890 if (ctxt->mode == X86EMUL_MODE_VM86) 2891 return true; 2892 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT; 2893 return ctxt->ops->cpl(ctxt) > iopl; 2894 } 2895 2896 #define VMWARE_PORT_VMPORT (0x5658) 2897 #define VMWARE_PORT_VMRPC (0x5659) 2898 2899 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt, 2900 u16 port, u16 len) 2901 { 2902 const struct x86_emulate_ops *ops = ctxt->ops; 2903 struct desc_struct tr_seg; 2904 u32 base3; 2905 int r; 2906 u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7; 2907 unsigned mask = (1 << len) - 1; 2908 unsigned long base; 2909 2910 /* 2911 * VMware allows access to these ports even if denied 2912 * by TSS I/O permission bitmap. Mimic behavior. 2913 */ 2914 if (enable_vmware_backdoor && 2915 ((port == VMWARE_PORT_VMPORT) || (port == VMWARE_PORT_VMRPC))) 2916 return true; 2917 2918 ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR); 2919 if (!tr_seg.p) 2920 return false; 2921 if (desc_limit_scaled(&tr_seg) < 103) 2922 return false; 2923 base = get_desc_base(&tr_seg); 2924 #ifdef CONFIG_X86_64 2925 base |= ((u64)base3) << 32; 2926 #endif 2927 r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL, true); 2928 if (r != X86EMUL_CONTINUE) 2929 return false; 2930 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg)) 2931 return false; 2932 r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL, true); 2933 if (r != X86EMUL_CONTINUE) 2934 return false; 2935 if ((perm >> bit_idx) & mask) 2936 return false; 2937 return true; 2938 } 2939 2940 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt, 2941 u16 port, u16 len) 2942 { 2943 if (ctxt->perm_ok) 2944 return true; 2945 2946 if (emulator_bad_iopl(ctxt)) 2947 if (!emulator_io_port_access_allowed(ctxt, port, len)) 2948 return false; 2949 2950 ctxt->perm_ok = true; 2951 2952 return true; 2953 } 2954 2955 static void string_registers_quirk(struct x86_emulate_ctxt *ctxt) 2956 { 2957 /* 2958 * Intel CPUs mask the counter and pointers in quite strange 2959 * manner when ECX is zero due to REP-string optimizations. 2960 */ 2961 #ifdef CONFIG_X86_64 2962 if (ctxt->ad_bytes != 4 || !vendor_intel(ctxt)) 2963 return; 2964 2965 *reg_write(ctxt, VCPU_REGS_RCX) = 0; 2966 2967 switch (ctxt->b) { 2968 case 0xa4: /* movsb */ 2969 case 0xa5: /* movsd/w */ 2970 *reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1; 2971 fallthrough; 2972 case 0xaa: /* stosb */ 2973 case 0xab: /* stosd/w */ 2974 *reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1; 2975 } 2976 #endif 2977 } 2978 2979 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt, 2980 struct tss_segment_16 *tss) 2981 { 2982 tss->ip = ctxt->_eip; 2983 tss->flag = ctxt->eflags; 2984 tss->ax = reg_read(ctxt, VCPU_REGS_RAX); 2985 tss->cx = reg_read(ctxt, VCPU_REGS_RCX); 2986 tss->dx = reg_read(ctxt, VCPU_REGS_RDX); 2987 tss->bx = reg_read(ctxt, VCPU_REGS_RBX); 2988 tss->sp = reg_read(ctxt, VCPU_REGS_RSP); 2989 tss->bp = reg_read(ctxt, VCPU_REGS_RBP); 2990 tss->si = reg_read(ctxt, VCPU_REGS_RSI); 2991 tss->di = reg_read(ctxt, VCPU_REGS_RDI); 2992 2993 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 2994 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 2995 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 2996 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 2997 tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR); 2998 } 2999 3000 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt, 3001 struct tss_segment_16 *tss) 3002 { 3003 int ret; 3004 u8 cpl; 3005 3006 ctxt->_eip = tss->ip; 3007 ctxt->eflags = tss->flag | 2; 3008 *reg_write(ctxt, VCPU_REGS_RAX) = tss->ax; 3009 *reg_write(ctxt, VCPU_REGS_RCX) = tss->cx; 3010 *reg_write(ctxt, VCPU_REGS_RDX) = tss->dx; 3011 *reg_write(ctxt, VCPU_REGS_RBX) = tss->bx; 3012 *reg_write(ctxt, VCPU_REGS_RSP) = tss->sp; 3013 *reg_write(ctxt, VCPU_REGS_RBP) = tss->bp; 3014 *reg_write(ctxt, VCPU_REGS_RSI) = tss->si; 3015 *reg_write(ctxt, VCPU_REGS_RDI) = tss->di; 3016 3017 /* 3018 * SDM says that segment selectors are loaded before segment 3019 * descriptors 3020 */ 3021 set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR); 3022 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 3023 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 3024 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 3025 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 3026 3027 cpl = tss->cs & 3; 3028 3029 /* 3030 * Now load segment descriptors. If fault happens at this stage 3031 * it is handled in a context of new task 3032 */ 3033 ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, 3034 X86_TRANSFER_TASK_SWITCH, NULL); 3035 if (ret != X86EMUL_CONTINUE) 3036 return ret; 3037 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, 3038 X86_TRANSFER_TASK_SWITCH, NULL); 3039 if (ret != X86EMUL_CONTINUE) 3040 return ret; 3041 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, 3042 X86_TRANSFER_TASK_SWITCH, NULL); 3043 if (ret != X86EMUL_CONTINUE) 3044 return ret; 3045 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, 3046 X86_TRANSFER_TASK_SWITCH, NULL); 3047 if (ret != X86EMUL_CONTINUE) 3048 return ret; 3049 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, 3050 X86_TRANSFER_TASK_SWITCH, NULL); 3051 if (ret != X86EMUL_CONTINUE) 3052 return ret; 3053 3054 return X86EMUL_CONTINUE; 3055 } 3056 3057 static int task_switch_16(struct x86_emulate_ctxt *ctxt, u16 old_tss_sel, 3058 ulong old_tss_base, struct desc_struct *new_desc) 3059 { 3060 struct tss_segment_16 tss_seg; 3061 int ret; 3062 u32 new_tss_base = get_desc_base(new_desc); 3063 3064 ret = linear_read_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg)); 3065 if (ret != X86EMUL_CONTINUE) 3066 return ret; 3067 3068 save_state_to_tss16(ctxt, &tss_seg); 3069 3070 ret = linear_write_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg)); 3071 if (ret != X86EMUL_CONTINUE) 3072 return ret; 3073 3074 ret = linear_read_system(ctxt, new_tss_base, &tss_seg, sizeof(tss_seg)); 3075 if (ret != X86EMUL_CONTINUE) 3076 return ret; 3077 3078 if (old_tss_sel != 0xffff) { 3079 tss_seg.prev_task_link = old_tss_sel; 3080 3081 ret = linear_write_system(ctxt, new_tss_base, 3082 &tss_seg.prev_task_link, 3083 sizeof(tss_seg.prev_task_link)); 3084 if (ret != X86EMUL_CONTINUE) 3085 return ret; 3086 } 3087 3088 return load_state_from_tss16(ctxt, &tss_seg); 3089 } 3090 3091 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt, 3092 struct tss_segment_32 *tss) 3093 { 3094 /* CR3 and ldt selector are not saved intentionally */ 3095 tss->eip = ctxt->_eip; 3096 tss->eflags = ctxt->eflags; 3097 tss->eax = reg_read(ctxt, VCPU_REGS_RAX); 3098 tss->ecx = reg_read(ctxt, VCPU_REGS_RCX); 3099 tss->edx = reg_read(ctxt, VCPU_REGS_RDX); 3100 tss->ebx = reg_read(ctxt, VCPU_REGS_RBX); 3101 tss->esp = reg_read(ctxt, VCPU_REGS_RSP); 3102 tss->ebp = reg_read(ctxt, VCPU_REGS_RBP); 3103 tss->esi = reg_read(ctxt, VCPU_REGS_RSI); 3104 tss->edi = reg_read(ctxt, VCPU_REGS_RDI); 3105 3106 tss->es = get_segment_selector(ctxt, VCPU_SREG_ES); 3107 tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS); 3108 tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS); 3109 tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS); 3110 tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS); 3111 tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS); 3112 } 3113 3114 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt, 3115 struct tss_segment_32 *tss) 3116 { 3117 int ret; 3118 u8 cpl; 3119 3120 if (ctxt->ops->set_cr(ctxt, 3, tss->cr3)) 3121 return emulate_gp(ctxt, 0); 3122 ctxt->_eip = tss->eip; 3123 ctxt->eflags = tss->eflags | 2; 3124 3125 /* General purpose registers */ 3126 *reg_write(ctxt, VCPU_REGS_RAX) = tss->eax; 3127 *reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx; 3128 *reg_write(ctxt, VCPU_REGS_RDX) = tss->edx; 3129 *reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx; 3130 *reg_write(ctxt, VCPU_REGS_RSP) = tss->esp; 3131 *reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp; 3132 *reg_write(ctxt, VCPU_REGS_RSI) = tss->esi; 3133 *reg_write(ctxt, VCPU_REGS_RDI) = tss->edi; 3134 3135 /* 3136 * SDM says that segment selectors are loaded before segment 3137 * descriptors. This is important because CPL checks will 3138 * use CS.RPL. 3139 */ 3140 set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR); 3141 set_segment_selector(ctxt, tss->es, VCPU_SREG_ES); 3142 set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS); 3143 set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS); 3144 set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS); 3145 set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS); 3146 set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS); 3147 3148 /* 3149 * If we're switching between Protected Mode and VM86, we need to make 3150 * sure to update the mode before loading the segment descriptors so 3151 * that the selectors are interpreted correctly. 3152 */ 3153 if (ctxt->eflags & X86_EFLAGS_VM) { 3154 ctxt->mode = X86EMUL_MODE_VM86; 3155 cpl = 3; 3156 } else { 3157 ctxt->mode = X86EMUL_MODE_PROT32; 3158 cpl = tss->cs & 3; 3159 } 3160 3161 /* 3162 * Now load segment descriptors. If fault happens at this stage 3163 * it is handled in a context of new task 3164 */ 3165 ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, 3166 cpl, X86_TRANSFER_TASK_SWITCH, NULL); 3167 if (ret != X86EMUL_CONTINUE) 3168 return ret; 3169 ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, 3170 X86_TRANSFER_TASK_SWITCH, NULL); 3171 if (ret != X86EMUL_CONTINUE) 3172 return ret; 3173 ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, 3174 X86_TRANSFER_TASK_SWITCH, NULL); 3175 if (ret != X86EMUL_CONTINUE) 3176 return ret; 3177 ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, 3178 X86_TRANSFER_TASK_SWITCH, NULL); 3179 if (ret != X86EMUL_CONTINUE) 3180 return ret; 3181 ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, 3182 X86_TRANSFER_TASK_SWITCH, NULL); 3183 if (ret != X86EMUL_CONTINUE) 3184 return ret; 3185 ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, 3186 X86_TRANSFER_TASK_SWITCH, NULL); 3187 if (ret != X86EMUL_CONTINUE) 3188 return ret; 3189 ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, 3190 X86_TRANSFER_TASK_SWITCH, NULL); 3191 3192 return ret; 3193 } 3194 3195 static int task_switch_32(struct x86_emulate_ctxt *ctxt, u16 old_tss_sel, 3196 ulong old_tss_base, struct desc_struct *new_desc) 3197 { 3198 struct tss_segment_32 tss_seg; 3199 int ret; 3200 u32 new_tss_base = get_desc_base(new_desc); 3201 u32 eip_offset = offsetof(struct tss_segment_32, eip); 3202 u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector); 3203 3204 ret = linear_read_system(ctxt, old_tss_base, &tss_seg, sizeof(tss_seg)); 3205 if (ret != X86EMUL_CONTINUE) 3206 return ret; 3207 3208 save_state_to_tss32(ctxt, &tss_seg); 3209 3210 /* Only GP registers and segment selectors are saved */ 3211 ret = linear_write_system(ctxt, old_tss_base + eip_offset, &tss_seg.eip, 3212 ldt_sel_offset - eip_offset); 3213 if (ret != X86EMUL_CONTINUE) 3214 return ret; 3215 3216 ret = linear_read_system(ctxt, new_tss_base, &tss_seg, sizeof(tss_seg)); 3217 if (ret != X86EMUL_CONTINUE) 3218 return ret; 3219 3220 if (old_tss_sel != 0xffff) { 3221 tss_seg.prev_task_link = old_tss_sel; 3222 3223 ret = linear_write_system(ctxt, new_tss_base, 3224 &tss_seg.prev_task_link, 3225 sizeof(tss_seg.prev_task_link)); 3226 if (ret != X86EMUL_CONTINUE) 3227 return ret; 3228 } 3229 3230 return load_state_from_tss32(ctxt, &tss_seg); 3231 } 3232 3233 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt, 3234 u16 tss_selector, int idt_index, int reason, 3235 bool has_error_code, u32 error_code) 3236 { 3237 const struct x86_emulate_ops *ops = ctxt->ops; 3238 struct desc_struct curr_tss_desc, next_tss_desc; 3239 int ret; 3240 u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR); 3241 ulong old_tss_base = 3242 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR); 3243 u32 desc_limit; 3244 ulong desc_addr, dr7; 3245 3246 /* FIXME: old_tss_base == ~0 ? */ 3247 3248 ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr); 3249 if (ret != X86EMUL_CONTINUE) 3250 return ret; 3251 ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr); 3252 if (ret != X86EMUL_CONTINUE) 3253 return ret; 3254 3255 /* FIXME: check that next_tss_desc is tss */ 3256 3257 /* 3258 * Check privileges. The three cases are task switch caused by... 3259 * 3260 * 1. jmp/call/int to task gate: Check against DPL of the task gate 3261 * 2. Exception/IRQ/iret: No check is performed 3262 * 3. jmp/call to TSS/task-gate: No check is performed since the 3263 * hardware checks it before exiting. 3264 */ 3265 if (reason == TASK_SWITCH_GATE) { 3266 if (idt_index != -1) { 3267 /* Software interrupts */ 3268 struct desc_struct task_gate_desc; 3269 int dpl; 3270 3271 ret = read_interrupt_descriptor(ctxt, idt_index, 3272 &task_gate_desc); 3273 if (ret != X86EMUL_CONTINUE) 3274 return ret; 3275 3276 dpl = task_gate_desc.dpl; 3277 if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl) 3278 return emulate_gp(ctxt, (idt_index << 3) | 0x2); 3279 } 3280 } 3281 3282 desc_limit = desc_limit_scaled(&next_tss_desc); 3283 if (!next_tss_desc.p || 3284 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || 3285 desc_limit < 0x2b)) { 3286 return emulate_ts(ctxt, tss_selector & 0xfffc); 3287 } 3288 3289 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) { 3290 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */ 3291 write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc); 3292 } 3293 3294 if (reason == TASK_SWITCH_IRET) 3295 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT; 3296 3297 /* set back link to prev task only if NT bit is set in eflags 3298 note that old_tss_sel is not used after this point */ 3299 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE) 3300 old_tss_sel = 0xffff; 3301 3302 if (next_tss_desc.type & 8) 3303 ret = task_switch_32(ctxt, old_tss_sel, old_tss_base, &next_tss_desc); 3304 else 3305 ret = task_switch_16(ctxt, old_tss_sel, 3306 old_tss_base, &next_tss_desc); 3307 if (ret != X86EMUL_CONTINUE) 3308 return ret; 3309 3310 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) 3311 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT; 3312 3313 if (reason != TASK_SWITCH_IRET) { 3314 next_tss_desc.type |= (1 << 1); /* set busy flag */ 3315 write_segment_descriptor(ctxt, tss_selector, &next_tss_desc); 3316 } 3317 3318 ops->set_cr(ctxt, 0, ops->get_cr(ctxt, 0) | X86_CR0_TS); 3319 ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR); 3320 3321 if (has_error_code) { 3322 ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2; 3323 ctxt->lock_prefix = 0; 3324 ctxt->src.val = (unsigned long) error_code; 3325 ret = em_push(ctxt); 3326 } 3327 3328 ops->get_dr(ctxt, 7, &dr7); 3329 ops->set_dr(ctxt, 7, dr7 & ~(DR_LOCAL_ENABLE_MASK | DR_LOCAL_SLOWDOWN)); 3330 3331 return ret; 3332 } 3333 3334 int emulator_task_switch(struct x86_emulate_ctxt *ctxt, 3335 u16 tss_selector, int idt_index, int reason, 3336 bool has_error_code, u32 error_code) 3337 { 3338 int rc; 3339 3340 invalidate_registers(ctxt); 3341 ctxt->_eip = ctxt->eip; 3342 ctxt->dst.type = OP_NONE; 3343 3344 rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason, 3345 has_error_code, error_code); 3346 3347 if (rc == X86EMUL_CONTINUE) { 3348 ctxt->eip = ctxt->_eip; 3349 writeback_registers(ctxt); 3350 } 3351 3352 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 3353 } 3354 3355 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg, 3356 struct operand *op) 3357 { 3358 int df = (ctxt->eflags & X86_EFLAGS_DF) ? -op->count : op->count; 3359 3360 register_address_increment(ctxt, reg, df * op->bytes); 3361 op->addr.mem.ea = register_address(ctxt, reg); 3362 } 3363 3364 static int em_das(struct x86_emulate_ctxt *ctxt) 3365 { 3366 u8 al, old_al; 3367 bool af, cf, old_cf; 3368 3369 cf = ctxt->eflags & X86_EFLAGS_CF; 3370 al = ctxt->dst.val; 3371 3372 old_al = al; 3373 old_cf = cf; 3374 cf = false; 3375 af = ctxt->eflags & X86_EFLAGS_AF; 3376 if ((al & 0x0f) > 9 || af) { 3377 al -= 6; 3378 cf = old_cf | (al >= 250); 3379 af = true; 3380 } else { 3381 af = false; 3382 } 3383 if (old_al > 0x99 || old_cf) { 3384 al -= 0x60; 3385 cf = true; 3386 } 3387 3388 ctxt->dst.val = al; 3389 /* Set PF, ZF, SF */ 3390 ctxt->src.type = OP_IMM; 3391 ctxt->src.val = 0; 3392 ctxt->src.bytes = 1; 3393 fastop(ctxt, em_or); 3394 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF); 3395 if (cf) 3396 ctxt->eflags |= X86_EFLAGS_CF; 3397 if (af) 3398 ctxt->eflags |= X86_EFLAGS_AF; 3399 return X86EMUL_CONTINUE; 3400 } 3401 3402 static int em_aam(struct x86_emulate_ctxt *ctxt) 3403 { 3404 u8 al, ah; 3405 3406 if (ctxt->src.val == 0) 3407 return emulate_de(ctxt); 3408 3409 al = ctxt->dst.val & 0xff; 3410 ah = al / ctxt->src.val; 3411 al %= ctxt->src.val; 3412 3413 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8); 3414 3415 /* Set PF, ZF, SF */ 3416 ctxt->src.type = OP_IMM; 3417 ctxt->src.val = 0; 3418 ctxt->src.bytes = 1; 3419 fastop(ctxt, em_or); 3420 3421 return X86EMUL_CONTINUE; 3422 } 3423 3424 static int em_aad(struct x86_emulate_ctxt *ctxt) 3425 { 3426 u8 al = ctxt->dst.val & 0xff; 3427 u8 ah = (ctxt->dst.val >> 8) & 0xff; 3428 3429 al = (al + (ah * ctxt->src.val)) & 0xff; 3430 3431 ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al; 3432 3433 /* Set PF, ZF, SF */ 3434 ctxt->src.type = OP_IMM; 3435 ctxt->src.val = 0; 3436 ctxt->src.bytes = 1; 3437 fastop(ctxt, em_or); 3438 3439 return X86EMUL_CONTINUE; 3440 } 3441 3442 static int em_call(struct x86_emulate_ctxt *ctxt) 3443 { 3444 int rc; 3445 long rel = ctxt->src.val; 3446 3447 ctxt->src.val = (unsigned long)ctxt->_eip; 3448 rc = jmp_rel(ctxt, rel); 3449 if (rc != X86EMUL_CONTINUE) 3450 return rc; 3451 return em_push(ctxt); 3452 } 3453 3454 static int em_call_far(struct x86_emulate_ctxt *ctxt) 3455 { 3456 u16 sel, old_cs; 3457 ulong old_eip; 3458 int rc; 3459 struct desc_struct old_desc, new_desc; 3460 const struct x86_emulate_ops *ops = ctxt->ops; 3461 int cpl = ctxt->ops->cpl(ctxt); 3462 enum x86emul_mode prev_mode = ctxt->mode; 3463 3464 old_eip = ctxt->_eip; 3465 ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS); 3466 3467 memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2); 3468 rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, 3469 X86_TRANSFER_CALL_JMP, &new_desc); 3470 if (rc != X86EMUL_CONTINUE) 3471 return rc; 3472 3473 rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc); 3474 if (rc != X86EMUL_CONTINUE) 3475 goto fail; 3476 3477 ctxt->src.val = old_cs; 3478 rc = em_push(ctxt); 3479 if (rc != X86EMUL_CONTINUE) 3480 goto fail; 3481 3482 ctxt->src.val = old_eip; 3483 rc = em_push(ctxt); 3484 /* If we failed, we tainted the memory, but the very least we should 3485 restore cs */ 3486 if (rc != X86EMUL_CONTINUE) { 3487 pr_warn_once("faulting far call emulation tainted memory\n"); 3488 goto fail; 3489 } 3490 return rc; 3491 fail: 3492 ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS); 3493 ctxt->mode = prev_mode; 3494 return rc; 3495 3496 } 3497 3498 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt) 3499 { 3500 int rc; 3501 unsigned long eip; 3502 3503 rc = emulate_pop(ctxt, &eip, ctxt->op_bytes); 3504 if (rc != X86EMUL_CONTINUE) 3505 return rc; 3506 rc = assign_eip_near(ctxt, eip); 3507 if (rc != X86EMUL_CONTINUE) 3508 return rc; 3509 rsp_increment(ctxt, ctxt->src.val); 3510 return X86EMUL_CONTINUE; 3511 } 3512 3513 static int em_xchg(struct x86_emulate_ctxt *ctxt) 3514 { 3515 /* Write back the register source. */ 3516 ctxt->src.val = ctxt->dst.val; 3517 write_register_operand(&ctxt->src); 3518 3519 /* Write back the memory destination with implicit LOCK prefix. */ 3520 ctxt->dst.val = ctxt->src.orig_val; 3521 ctxt->lock_prefix = 1; 3522 return X86EMUL_CONTINUE; 3523 } 3524 3525 static int em_imul_3op(struct x86_emulate_ctxt *ctxt) 3526 { 3527 ctxt->dst.val = ctxt->src2.val; 3528 return fastop(ctxt, em_imul); 3529 } 3530 3531 static int em_cwd(struct x86_emulate_ctxt *ctxt) 3532 { 3533 ctxt->dst.type = OP_REG; 3534 ctxt->dst.bytes = ctxt->src.bytes; 3535 ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 3536 ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1); 3537 3538 return X86EMUL_CONTINUE; 3539 } 3540 3541 static int em_rdpid(struct x86_emulate_ctxt *ctxt) 3542 { 3543 u64 tsc_aux = 0; 3544 3545 if (!ctxt->ops->guest_has_rdpid(ctxt)) 3546 return emulate_ud(ctxt); 3547 3548 ctxt->ops->get_msr(ctxt, MSR_TSC_AUX, &tsc_aux); 3549 ctxt->dst.val = tsc_aux; 3550 return X86EMUL_CONTINUE; 3551 } 3552 3553 static int em_rdtsc(struct x86_emulate_ctxt *ctxt) 3554 { 3555 u64 tsc = 0; 3556 3557 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc); 3558 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc; 3559 *reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32; 3560 return X86EMUL_CONTINUE; 3561 } 3562 3563 static int em_rdpmc(struct x86_emulate_ctxt *ctxt) 3564 { 3565 u64 pmc; 3566 3567 if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc)) 3568 return emulate_gp(ctxt, 0); 3569 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc; 3570 *reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32; 3571 return X86EMUL_CONTINUE; 3572 } 3573 3574 static int em_mov(struct x86_emulate_ctxt *ctxt) 3575 { 3576 memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr)); 3577 return X86EMUL_CONTINUE; 3578 } 3579 3580 static int em_movbe(struct x86_emulate_ctxt *ctxt) 3581 { 3582 u16 tmp; 3583 3584 if (!ctxt->ops->guest_has_movbe(ctxt)) 3585 return emulate_ud(ctxt); 3586 3587 switch (ctxt->op_bytes) { 3588 case 2: 3589 /* 3590 * From MOVBE definition: "...When the operand size is 16 bits, 3591 * the upper word of the destination register remains unchanged 3592 * ..." 3593 * 3594 * Both casting ->valptr and ->val to u16 breaks strict aliasing 3595 * rules so we have to do the operation almost per hand. 3596 */ 3597 tmp = (u16)ctxt->src.val; 3598 ctxt->dst.val &= ~0xffffUL; 3599 ctxt->dst.val |= (unsigned long)swab16(tmp); 3600 break; 3601 case 4: 3602 ctxt->dst.val = swab32((u32)ctxt->src.val); 3603 break; 3604 case 8: 3605 ctxt->dst.val = swab64(ctxt->src.val); 3606 break; 3607 default: 3608 BUG(); 3609 } 3610 return X86EMUL_CONTINUE; 3611 } 3612 3613 static int em_cr_write(struct x86_emulate_ctxt *ctxt) 3614 { 3615 if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) 3616 return emulate_gp(ctxt, 0); 3617 3618 /* Disable writeback. */ 3619 ctxt->dst.type = OP_NONE; 3620 return X86EMUL_CONTINUE; 3621 } 3622 3623 static int em_dr_write(struct x86_emulate_ctxt *ctxt) 3624 { 3625 unsigned long val; 3626 3627 if (ctxt->mode == X86EMUL_MODE_PROT64) 3628 val = ctxt->src.val & ~0ULL; 3629 else 3630 val = ctxt->src.val & ~0U; 3631 3632 /* #UD condition is already handled. */ 3633 if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0) 3634 return emulate_gp(ctxt, 0); 3635 3636 /* Disable writeback. */ 3637 ctxt->dst.type = OP_NONE; 3638 return X86EMUL_CONTINUE; 3639 } 3640 3641 static int em_wrmsr(struct x86_emulate_ctxt *ctxt) 3642 { 3643 u64 msr_index = reg_read(ctxt, VCPU_REGS_RCX); 3644 u64 msr_data; 3645 int r; 3646 3647 msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX) 3648 | ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32); 3649 r = ctxt->ops->set_msr_with_filter(ctxt, msr_index, msr_data); 3650 3651 if (r == X86EMUL_IO_NEEDED) 3652 return r; 3653 3654 if (r > 0) 3655 return emulate_gp(ctxt, 0); 3656 3657 return r < 0 ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; 3658 } 3659 3660 static int em_rdmsr(struct x86_emulate_ctxt *ctxt) 3661 { 3662 u64 msr_index = reg_read(ctxt, VCPU_REGS_RCX); 3663 u64 msr_data; 3664 int r; 3665 3666 r = ctxt->ops->get_msr_with_filter(ctxt, msr_index, &msr_data); 3667 3668 if (r == X86EMUL_IO_NEEDED) 3669 return r; 3670 3671 if (r) 3672 return emulate_gp(ctxt, 0); 3673 3674 *reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data; 3675 *reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32; 3676 return X86EMUL_CONTINUE; 3677 } 3678 3679 static int em_store_sreg(struct x86_emulate_ctxt *ctxt, int segment) 3680 { 3681 if (segment > VCPU_SREG_GS && 3682 (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) && 3683 ctxt->ops->cpl(ctxt) > 0) 3684 return emulate_gp(ctxt, 0); 3685 3686 ctxt->dst.val = get_segment_selector(ctxt, segment); 3687 if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM) 3688 ctxt->dst.bytes = 2; 3689 return X86EMUL_CONTINUE; 3690 } 3691 3692 static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt) 3693 { 3694 if (ctxt->modrm_reg > VCPU_SREG_GS) 3695 return emulate_ud(ctxt); 3696 3697 return em_store_sreg(ctxt, ctxt->modrm_reg); 3698 } 3699 3700 static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt) 3701 { 3702 u16 sel = ctxt->src.val; 3703 3704 if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS) 3705 return emulate_ud(ctxt); 3706 3707 if (ctxt->modrm_reg == VCPU_SREG_SS) 3708 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS; 3709 3710 /* Disable writeback. */ 3711 ctxt->dst.type = OP_NONE; 3712 return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg); 3713 } 3714 3715 static int em_sldt(struct x86_emulate_ctxt *ctxt) 3716 { 3717 return em_store_sreg(ctxt, VCPU_SREG_LDTR); 3718 } 3719 3720 static int em_lldt(struct x86_emulate_ctxt *ctxt) 3721 { 3722 u16 sel = ctxt->src.val; 3723 3724 /* Disable writeback. */ 3725 ctxt->dst.type = OP_NONE; 3726 return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR); 3727 } 3728 3729 static int em_str(struct x86_emulate_ctxt *ctxt) 3730 { 3731 return em_store_sreg(ctxt, VCPU_SREG_TR); 3732 } 3733 3734 static int em_ltr(struct x86_emulate_ctxt *ctxt) 3735 { 3736 u16 sel = ctxt->src.val; 3737 3738 /* Disable writeback. */ 3739 ctxt->dst.type = OP_NONE; 3740 return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR); 3741 } 3742 3743 static int em_invlpg(struct x86_emulate_ctxt *ctxt) 3744 { 3745 int rc; 3746 ulong linear; 3747 3748 rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear); 3749 if (rc == X86EMUL_CONTINUE) 3750 ctxt->ops->invlpg(ctxt, linear); 3751 /* Disable writeback. */ 3752 ctxt->dst.type = OP_NONE; 3753 return X86EMUL_CONTINUE; 3754 } 3755 3756 static int em_clts(struct x86_emulate_ctxt *ctxt) 3757 { 3758 ulong cr0; 3759 3760 cr0 = ctxt->ops->get_cr(ctxt, 0); 3761 cr0 &= ~X86_CR0_TS; 3762 ctxt->ops->set_cr(ctxt, 0, cr0); 3763 return X86EMUL_CONTINUE; 3764 } 3765 3766 static int em_hypercall(struct x86_emulate_ctxt *ctxt) 3767 { 3768 int rc = ctxt->ops->fix_hypercall(ctxt); 3769 3770 if (rc != X86EMUL_CONTINUE) 3771 return rc; 3772 3773 /* Let the processor re-execute the fixed hypercall */ 3774 ctxt->_eip = ctxt->eip; 3775 /* Disable writeback. */ 3776 ctxt->dst.type = OP_NONE; 3777 return X86EMUL_CONTINUE; 3778 } 3779 3780 static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt, 3781 void (*get)(struct x86_emulate_ctxt *ctxt, 3782 struct desc_ptr *ptr)) 3783 { 3784 struct desc_ptr desc_ptr; 3785 3786 if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) && 3787 ctxt->ops->cpl(ctxt) > 0) 3788 return emulate_gp(ctxt, 0); 3789 3790 if (ctxt->mode == X86EMUL_MODE_PROT64) 3791 ctxt->op_bytes = 8; 3792 get(ctxt, &desc_ptr); 3793 if (ctxt->op_bytes == 2) { 3794 ctxt->op_bytes = 4; 3795 desc_ptr.address &= 0x00ffffff; 3796 } 3797 /* Disable writeback. */ 3798 ctxt->dst.type = OP_NONE; 3799 return segmented_write_std(ctxt, ctxt->dst.addr.mem, 3800 &desc_ptr, 2 + ctxt->op_bytes); 3801 } 3802 3803 static int em_sgdt(struct x86_emulate_ctxt *ctxt) 3804 { 3805 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt); 3806 } 3807 3808 static int em_sidt(struct x86_emulate_ctxt *ctxt) 3809 { 3810 return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt); 3811 } 3812 3813 static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt) 3814 { 3815 struct desc_ptr desc_ptr; 3816 int rc; 3817 3818 if (ctxt->mode == X86EMUL_MODE_PROT64) 3819 ctxt->op_bytes = 8; 3820 rc = read_descriptor(ctxt, ctxt->src.addr.mem, 3821 &desc_ptr.size, &desc_ptr.address, 3822 ctxt->op_bytes); 3823 if (rc != X86EMUL_CONTINUE) 3824 return rc; 3825 if (ctxt->mode == X86EMUL_MODE_PROT64 && 3826 emul_is_noncanonical_address(desc_ptr.address, ctxt)) 3827 return emulate_gp(ctxt, 0); 3828 if (lgdt) 3829 ctxt->ops->set_gdt(ctxt, &desc_ptr); 3830 else 3831 ctxt->ops->set_idt(ctxt, &desc_ptr); 3832 /* Disable writeback. */ 3833 ctxt->dst.type = OP_NONE; 3834 return X86EMUL_CONTINUE; 3835 } 3836 3837 static int em_lgdt(struct x86_emulate_ctxt *ctxt) 3838 { 3839 return em_lgdt_lidt(ctxt, true); 3840 } 3841 3842 static int em_lidt(struct x86_emulate_ctxt *ctxt) 3843 { 3844 return em_lgdt_lidt(ctxt, false); 3845 } 3846 3847 static int em_smsw(struct x86_emulate_ctxt *ctxt) 3848 { 3849 if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) && 3850 ctxt->ops->cpl(ctxt) > 0) 3851 return emulate_gp(ctxt, 0); 3852 3853 if (ctxt->dst.type == OP_MEM) 3854 ctxt->dst.bytes = 2; 3855 ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0); 3856 return X86EMUL_CONTINUE; 3857 } 3858 3859 static int em_lmsw(struct x86_emulate_ctxt *ctxt) 3860 { 3861 ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul) 3862 | (ctxt->src.val & 0x0f)); 3863 ctxt->dst.type = OP_NONE; 3864 return X86EMUL_CONTINUE; 3865 } 3866 3867 static int em_loop(struct x86_emulate_ctxt *ctxt) 3868 { 3869 int rc = X86EMUL_CONTINUE; 3870 3871 register_address_increment(ctxt, VCPU_REGS_RCX, -1); 3872 if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) && 3873 (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags))) 3874 rc = jmp_rel(ctxt, ctxt->src.val); 3875 3876 return rc; 3877 } 3878 3879 static int em_jcxz(struct x86_emulate_ctxt *ctxt) 3880 { 3881 int rc = X86EMUL_CONTINUE; 3882 3883 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) 3884 rc = jmp_rel(ctxt, ctxt->src.val); 3885 3886 return rc; 3887 } 3888 3889 static int em_in(struct x86_emulate_ctxt *ctxt) 3890 { 3891 if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val, 3892 &ctxt->dst.val)) 3893 return X86EMUL_IO_NEEDED; 3894 3895 return X86EMUL_CONTINUE; 3896 } 3897 3898 static int em_out(struct x86_emulate_ctxt *ctxt) 3899 { 3900 ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val, 3901 &ctxt->src.val, 1); 3902 /* Disable writeback. */ 3903 ctxt->dst.type = OP_NONE; 3904 return X86EMUL_CONTINUE; 3905 } 3906 3907 static int em_cli(struct x86_emulate_ctxt *ctxt) 3908 { 3909 if (emulator_bad_iopl(ctxt)) 3910 return emulate_gp(ctxt, 0); 3911 3912 ctxt->eflags &= ~X86_EFLAGS_IF; 3913 return X86EMUL_CONTINUE; 3914 } 3915 3916 static int em_sti(struct x86_emulate_ctxt *ctxt) 3917 { 3918 if (emulator_bad_iopl(ctxt)) 3919 return emulate_gp(ctxt, 0); 3920 3921 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI; 3922 ctxt->eflags |= X86_EFLAGS_IF; 3923 return X86EMUL_CONTINUE; 3924 } 3925 3926 static int em_cpuid(struct x86_emulate_ctxt *ctxt) 3927 { 3928 u32 eax, ebx, ecx, edx; 3929 u64 msr = 0; 3930 3931 ctxt->ops->get_msr(ctxt, MSR_MISC_FEATURES_ENABLES, &msr); 3932 if (msr & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT && 3933 ctxt->ops->cpl(ctxt)) { 3934 return emulate_gp(ctxt, 0); 3935 } 3936 3937 eax = reg_read(ctxt, VCPU_REGS_RAX); 3938 ecx = reg_read(ctxt, VCPU_REGS_RCX); 3939 ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false); 3940 *reg_write(ctxt, VCPU_REGS_RAX) = eax; 3941 *reg_write(ctxt, VCPU_REGS_RBX) = ebx; 3942 *reg_write(ctxt, VCPU_REGS_RCX) = ecx; 3943 *reg_write(ctxt, VCPU_REGS_RDX) = edx; 3944 return X86EMUL_CONTINUE; 3945 } 3946 3947 static int em_sahf(struct x86_emulate_ctxt *ctxt) 3948 { 3949 u32 flags; 3950 3951 flags = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF | 3952 X86_EFLAGS_SF; 3953 flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8; 3954 3955 ctxt->eflags &= ~0xffUL; 3956 ctxt->eflags |= flags | X86_EFLAGS_FIXED; 3957 return X86EMUL_CONTINUE; 3958 } 3959 3960 static int em_lahf(struct x86_emulate_ctxt *ctxt) 3961 { 3962 *reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL; 3963 *reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8; 3964 return X86EMUL_CONTINUE; 3965 } 3966 3967 static int em_bswap(struct x86_emulate_ctxt *ctxt) 3968 { 3969 switch (ctxt->op_bytes) { 3970 #ifdef CONFIG_X86_64 3971 case 8: 3972 asm("bswap %0" : "+r"(ctxt->dst.val)); 3973 break; 3974 #endif 3975 default: 3976 asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val)); 3977 break; 3978 } 3979 return X86EMUL_CONTINUE; 3980 } 3981 3982 static int em_clflush(struct x86_emulate_ctxt *ctxt) 3983 { 3984 /* emulating clflush regardless of cpuid */ 3985 return X86EMUL_CONTINUE; 3986 } 3987 3988 static int em_clflushopt(struct x86_emulate_ctxt *ctxt) 3989 { 3990 /* emulating clflushopt regardless of cpuid */ 3991 return X86EMUL_CONTINUE; 3992 } 3993 3994 static int em_movsxd(struct x86_emulate_ctxt *ctxt) 3995 { 3996 ctxt->dst.val = (s32) ctxt->src.val; 3997 return X86EMUL_CONTINUE; 3998 } 3999 4000 static int check_fxsr(struct x86_emulate_ctxt *ctxt) 4001 { 4002 if (!ctxt->ops->guest_has_fxsr(ctxt)) 4003 return emulate_ud(ctxt); 4004 4005 if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM)) 4006 return emulate_nm(ctxt); 4007 4008 /* 4009 * Don't emulate a case that should never be hit, instead of working 4010 * around a lack of fxsave64/fxrstor64 on old compilers. 4011 */ 4012 if (ctxt->mode >= X86EMUL_MODE_PROT64) 4013 return X86EMUL_UNHANDLEABLE; 4014 4015 return X86EMUL_CONTINUE; 4016 } 4017 4018 /* 4019 * Hardware doesn't save and restore XMM 0-7 without CR4.OSFXSR, but does save 4020 * and restore MXCSR. 4021 */ 4022 static size_t __fxstate_size(int nregs) 4023 { 4024 return offsetof(struct fxregs_state, xmm_space[0]) + nregs * 16; 4025 } 4026 4027 static inline size_t fxstate_size(struct x86_emulate_ctxt *ctxt) 4028 { 4029 bool cr4_osfxsr; 4030 if (ctxt->mode == X86EMUL_MODE_PROT64) 4031 return __fxstate_size(16); 4032 4033 cr4_osfxsr = ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR; 4034 return __fxstate_size(cr4_osfxsr ? 8 : 0); 4035 } 4036 4037 /* 4038 * FXSAVE and FXRSTOR have 4 different formats depending on execution mode, 4039 * 1) 16 bit mode 4040 * 2) 32 bit mode 4041 * - like (1), but FIP and FDP (foo) are only 16 bit. At least Intel CPUs 4042 * preserve whole 32 bit values, though, so (1) and (2) are the same wrt. 4043 * save and restore 4044 * 3) 64-bit mode with REX.W prefix 4045 * - like (2), but XMM 8-15 are being saved and restored 4046 * 4) 64-bit mode without REX.W prefix 4047 * - like (3), but FIP and FDP are 64 bit 4048 * 4049 * Emulation uses (3) for (1) and (2) and preserves XMM 8-15 to reach the 4050 * desired result. (4) is not emulated. 4051 * 4052 * Note: Guest and host CPUID.(EAX=07H,ECX=0H):EBX[bit 13] (deprecate FPU CS 4053 * and FPU DS) should match. 4054 */ 4055 static int em_fxsave(struct x86_emulate_ctxt *ctxt) 4056 { 4057 struct fxregs_state fx_state; 4058 int rc; 4059 4060 rc = check_fxsr(ctxt); 4061 if (rc != X86EMUL_CONTINUE) 4062 return rc; 4063 4064 kvm_fpu_get(); 4065 4066 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_state)); 4067 4068 kvm_fpu_put(); 4069 4070 if (rc != X86EMUL_CONTINUE) 4071 return rc; 4072 4073 return segmented_write_std(ctxt, ctxt->memop.addr.mem, &fx_state, 4074 fxstate_size(ctxt)); 4075 } 4076 4077 /* 4078 * FXRSTOR might restore XMM registers not provided by the guest. Fill 4079 * in the host registers (via FXSAVE) instead, so they won't be modified. 4080 * (preemption has to stay disabled until FXRSTOR). 4081 * 4082 * Use noinline to keep the stack for other functions called by callers small. 4083 */ 4084 static noinline int fxregs_fixup(struct fxregs_state *fx_state, 4085 const size_t used_size) 4086 { 4087 struct fxregs_state fx_tmp; 4088 int rc; 4089 4090 rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_tmp)); 4091 memcpy((void *)fx_state + used_size, (void *)&fx_tmp + used_size, 4092 __fxstate_size(16) - used_size); 4093 4094 return rc; 4095 } 4096 4097 static int em_fxrstor(struct x86_emulate_ctxt *ctxt) 4098 { 4099 struct fxregs_state fx_state; 4100 int rc; 4101 size_t size; 4102 4103 rc = check_fxsr(ctxt); 4104 if (rc != X86EMUL_CONTINUE) 4105 return rc; 4106 4107 size = fxstate_size(ctxt); 4108 rc = segmented_read_std(ctxt, ctxt->memop.addr.mem, &fx_state, size); 4109 if (rc != X86EMUL_CONTINUE) 4110 return rc; 4111 4112 kvm_fpu_get(); 4113 4114 if (size < __fxstate_size(16)) { 4115 rc = fxregs_fixup(&fx_state, size); 4116 if (rc != X86EMUL_CONTINUE) 4117 goto out; 4118 } 4119 4120 if (fx_state.mxcsr >> 16) { 4121 rc = emulate_gp(ctxt, 0); 4122 goto out; 4123 } 4124 4125 if (rc == X86EMUL_CONTINUE) 4126 rc = asm_safe("fxrstor %[fx]", : [fx] "m"(fx_state)); 4127 4128 out: 4129 kvm_fpu_put(); 4130 4131 return rc; 4132 } 4133 4134 static int em_xsetbv(struct x86_emulate_ctxt *ctxt) 4135 { 4136 u32 eax, ecx, edx; 4137 4138 eax = reg_read(ctxt, VCPU_REGS_RAX); 4139 edx = reg_read(ctxt, VCPU_REGS_RDX); 4140 ecx = reg_read(ctxt, VCPU_REGS_RCX); 4141 4142 if (ctxt->ops->set_xcr(ctxt, ecx, ((u64)edx << 32) | eax)) 4143 return emulate_gp(ctxt, 0); 4144 4145 return X86EMUL_CONTINUE; 4146 } 4147 4148 static bool valid_cr(int nr) 4149 { 4150 switch (nr) { 4151 case 0: 4152 case 2 ... 4: 4153 case 8: 4154 return true; 4155 default: 4156 return false; 4157 } 4158 } 4159 4160 static int check_cr_access(struct x86_emulate_ctxt *ctxt) 4161 { 4162 if (!valid_cr(ctxt->modrm_reg)) 4163 return emulate_ud(ctxt); 4164 4165 return X86EMUL_CONTINUE; 4166 } 4167 4168 static int check_dr7_gd(struct x86_emulate_ctxt *ctxt) 4169 { 4170 unsigned long dr7; 4171 4172 ctxt->ops->get_dr(ctxt, 7, &dr7); 4173 4174 /* Check if DR7.Global_Enable is set */ 4175 return dr7 & (1 << 13); 4176 } 4177 4178 static int check_dr_read(struct x86_emulate_ctxt *ctxt) 4179 { 4180 int dr = ctxt->modrm_reg; 4181 u64 cr4; 4182 4183 if (dr > 7) 4184 return emulate_ud(ctxt); 4185 4186 cr4 = ctxt->ops->get_cr(ctxt, 4); 4187 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5)) 4188 return emulate_ud(ctxt); 4189 4190 if (check_dr7_gd(ctxt)) { 4191 ulong dr6; 4192 4193 ctxt->ops->get_dr(ctxt, 6, &dr6); 4194 dr6 &= ~DR_TRAP_BITS; 4195 dr6 |= DR6_BD | DR6_ACTIVE_LOW; 4196 ctxt->ops->set_dr(ctxt, 6, dr6); 4197 return emulate_db(ctxt); 4198 } 4199 4200 return X86EMUL_CONTINUE; 4201 } 4202 4203 static int check_dr_write(struct x86_emulate_ctxt *ctxt) 4204 { 4205 u64 new_val = ctxt->src.val64; 4206 int dr = ctxt->modrm_reg; 4207 4208 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL)) 4209 return emulate_gp(ctxt, 0); 4210 4211 return check_dr_read(ctxt); 4212 } 4213 4214 static int check_svme(struct x86_emulate_ctxt *ctxt) 4215 { 4216 u64 efer = 0; 4217 4218 ctxt->ops->get_msr(ctxt, MSR_EFER, &efer); 4219 4220 if (!(efer & EFER_SVME)) 4221 return emulate_ud(ctxt); 4222 4223 return X86EMUL_CONTINUE; 4224 } 4225 4226 static int check_svme_pa(struct x86_emulate_ctxt *ctxt) 4227 { 4228 u64 rax = reg_read(ctxt, VCPU_REGS_RAX); 4229 4230 /* Valid physical address? */ 4231 if (rax & 0xffff000000000000ULL) 4232 return emulate_gp(ctxt, 0); 4233 4234 return check_svme(ctxt); 4235 } 4236 4237 static int check_rdtsc(struct x86_emulate_ctxt *ctxt) 4238 { 4239 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 4240 4241 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt)) 4242 return emulate_gp(ctxt, 0); 4243 4244 return X86EMUL_CONTINUE; 4245 } 4246 4247 static int check_rdpmc(struct x86_emulate_ctxt *ctxt) 4248 { 4249 u64 cr4 = ctxt->ops->get_cr(ctxt, 4); 4250 u64 rcx = reg_read(ctxt, VCPU_REGS_RCX); 4251 4252 /* 4253 * VMware allows access to these Pseduo-PMCs even when read via RDPMC 4254 * in Ring3 when CR4.PCE=0. 4255 */ 4256 if (enable_vmware_backdoor && is_vmware_backdoor_pmc(rcx)) 4257 return X86EMUL_CONTINUE; 4258 4259 /* 4260 * If CR4.PCE is set, the SDM requires CPL=0 or CR0.PE=0. The CR0.PE 4261 * check however is unnecessary because CPL is always 0 outside 4262 * protected mode. 4263 */ 4264 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) || 4265 ctxt->ops->check_pmc(ctxt, rcx)) 4266 return emulate_gp(ctxt, 0); 4267 4268 return X86EMUL_CONTINUE; 4269 } 4270 4271 static int check_perm_in(struct x86_emulate_ctxt *ctxt) 4272 { 4273 ctxt->dst.bytes = min(ctxt->dst.bytes, 4u); 4274 if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes)) 4275 return emulate_gp(ctxt, 0); 4276 4277 return X86EMUL_CONTINUE; 4278 } 4279 4280 static int check_perm_out(struct x86_emulate_ctxt *ctxt) 4281 { 4282 ctxt->src.bytes = min(ctxt->src.bytes, 4u); 4283 if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes)) 4284 return emulate_gp(ctxt, 0); 4285 4286 return X86EMUL_CONTINUE; 4287 } 4288 4289 #define D(_y) { .flags = (_y) } 4290 #define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i } 4291 #define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \ 4292 .intercept = x86_intercept_##_i, .check_perm = (_p) } 4293 #define N D(NotImpl) 4294 #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) } 4295 #define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) } 4296 #define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) } 4297 #define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) } 4298 #define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) } 4299 #define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) } 4300 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) } 4301 #define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) } 4302 #define II(_f, _e, _i) \ 4303 { .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i } 4304 #define IIP(_f, _e, _i, _p) \ 4305 { .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \ 4306 .intercept = x86_intercept_##_i, .check_perm = (_p) } 4307 #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) } 4308 4309 #define D2bv(_f) D((_f) | ByteOp), D(_f) 4310 #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p) 4311 #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e) 4312 #define F2bv(_f, _e) F((_f) | ByteOp, _e), F(_f, _e) 4313 #define I2bvIP(_f, _e, _i, _p) \ 4314 IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p) 4315 4316 #define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e), \ 4317 F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e), \ 4318 F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e) 4319 4320 static const struct opcode group7_rm0[] = { 4321 N, 4322 I(SrcNone | Priv | EmulateOnUD, em_hypercall), 4323 N, N, N, N, N, N, 4324 }; 4325 4326 static const struct opcode group7_rm1[] = { 4327 DI(SrcNone | Priv, monitor), 4328 DI(SrcNone | Priv, mwait), 4329 N, N, N, N, N, N, 4330 }; 4331 4332 static const struct opcode group7_rm2[] = { 4333 N, 4334 II(ImplicitOps | Priv, em_xsetbv, xsetbv), 4335 N, N, N, N, N, N, 4336 }; 4337 4338 static const struct opcode group7_rm3[] = { 4339 DIP(SrcNone | Prot | Priv, vmrun, check_svme_pa), 4340 II(SrcNone | Prot | EmulateOnUD, em_hypercall, vmmcall), 4341 DIP(SrcNone | Prot | Priv, vmload, check_svme_pa), 4342 DIP(SrcNone | Prot | Priv, vmsave, check_svme_pa), 4343 DIP(SrcNone | Prot | Priv, stgi, check_svme), 4344 DIP(SrcNone | Prot | Priv, clgi, check_svme), 4345 DIP(SrcNone | Prot | Priv, skinit, check_svme), 4346 DIP(SrcNone | Prot | Priv, invlpga, check_svme), 4347 }; 4348 4349 static const struct opcode group7_rm7[] = { 4350 N, 4351 DIP(SrcNone, rdtscp, check_rdtsc), 4352 N, N, N, N, N, N, 4353 }; 4354 4355 static const struct opcode group1[] = { 4356 F(Lock, em_add), 4357 F(Lock | PageTable, em_or), 4358 F(Lock, em_adc), 4359 F(Lock, em_sbb), 4360 F(Lock | PageTable, em_and), 4361 F(Lock, em_sub), 4362 F(Lock, em_xor), 4363 F(NoWrite, em_cmp), 4364 }; 4365 4366 static const struct opcode group1A[] = { 4367 I(DstMem | SrcNone | Mov | Stack | IncSP | TwoMemOp, em_pop), N, N, N, N, N, N, N, 4368 }; 4369 4370 static const struct opcode group2[] = { 4371 F(DstMem | ModRM, em_rol), 4372 F(DstMem | ModRM, em_ror), 4373 F(DstMem | ModRM, em_rcl), 4374 F(DstMem | ModRM, em_rcr), 4375 F(DstMem | ModRM, em_shl), 4376 F(DstMem | ModRM, em_shr), 4377 F(DstMem | ModRM, em_shl), 4378 F(DstMem | ModRM, em_sar), 4379 }; 4380 4381 static const struct opcode group3[] = { 4382 F(DstMem | SrcImm | NoWrite, em_test), 4383 F(DstMem | SrcImm | NoWrite, em_test), 4384 F(DstMem | SrcNone | Lock, em_not), 4385 F(DstMem | SrcNone | Lock, em_neg), 4386 F(DstXacc | Src2Mem, em_mul_ex), 4387 F(DstXacc | Src2Mem, em_imul_ex), 4388 F(DstXacc | Src2Mem, em_div_ex), 4389 F(DstXacc | Src2Mem, em_idiv_ex), 4390 }; 4391 4392 static const struct opcode group4[] = { 4393 F(ByteOp | DstMem | SrcNone | Lock, em_inc), 4394 F(ByteOp | DstMem | SrcNone | Lock, em_dec), 4395 N, N, N, N, N, N, 4396 }; 4397 4398 static const struct opcode group5[] = { 4399 F(DstMem | SrcNone | Lock, em_inc), 4400 F(DstMem | SrcNone | Lock, em_dec), 4401 I(SrcMem | NearBranch | IsBranch, em_call_near_abs), 4402 I(SrcMemFAddr | ImplicitOps | IsBranch, em_call_far), 4403 I(SrcMem | NearBranch | IsBranch, em_jmp_abs), 4404 I(SrcMemFAddr | ImplicitOps | IsBranch, em_jmp_far), 4405 I(SrcMem | Stack | TwoMemOp, em_push), D(Undefined), 4406 }; 4407 4408 static const struct opcode group6[] = { 4409 II(Prot | DstMem, em_sldt, sldt), 4410 II(Prot | DstMem, em_str, str), 4411 II(Prot | Priv | SrcMem16, em_lldt, lldt), 4412 II(Prot | Priv | SrcMem16, em_ltr, ltr), 4413 N, N, N, N, 4414 }; 4415 4416 static const struct group_dual group7 = { { 4417 II(Mov | DstMem, em_sgdt, sgdt), 4418 II(Mov | DstMem, em_sidt, sidt), 4419 II(SrcMem | Priv, em_lgdt, lgdt), 4420 II(SrcMem | Priv, em_lidt, lidt), 4421 II(SrcNone | DstMem | Mov, em_smsw, smsw), N, 4422 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), 4423 II(SrcMem | ByteOp | Priv | NoAccess, em_invlpg, invlpg), 4424 }, { 4425 EXT(0, group7_rm0), 4426 EXT(0, group7_rm1), 4427 EXT(0, group7_rm2), 4428 EXT(0, group7_rm3), 4429 II(SrcNone | DstMem | Mov, em_smsw, smsw), N, 4430 II(SrcMem16 | Mov | Priv, em_lmsw, lmsw), 4431 EXT(0, group7_rm7), 4432 } }; 4433 4434 static const struct opcode group8[] = { 4435 N, N, N, N, 4436 F(DstMem | SrcImmByte | NoWrite, em_bt), 4437 F(DstMem | SrcImmByte | Lock | PageTable, em_bts), 4438 F(DstMem | SrcImmByte | Lock, em_btr), 4439 F(DstMem | SrcImmByte | Lock | PageTable, em_btc), 4440 }; 4441 4442 /* 4443 * The "memory" destination is actually always a register, since we come 4444 * from the register case of group9. 4445 */ 4446 static const struct gprefix pfx_0f_c7_7 = { 4447 N, N, N, II(DstMem | ModRM | Op3264 | EmulateOnUD, em_rdpid, rdpid), 4448 }; 4449 4450 4451 static const struct group_dual group9 = { { 4452 N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N, 4453 }, { 4454 N, N, N, N, N, N, N, 4455 GP(0, &pfx_0f_c7_7), 4456 } }; 4457 4458 static const struct opcode group11[] = { 4459 I(DstMem | SrcImm | Mov | PageTable, em_mov), 4460 X7(D(Undefined)), 4461 }; 4462 4463 static const struct gprefix pfx_0f_ae_7 = { 4464 I(SrcMem | ByteOp, em_clflush), I(SrcMem | ByteOp, em_clflushopt), N, N, 4465 }; 4466 4467 static const struct group_dual group15 = { { 4468 I(ModRM | Aligned16, em_fxsave), 4469 I(ModRM | Aligned16, em_fxrstor), 4470 N, N, N, N, N, GP(0, &pfx_0f_ae_7), 4471 }, { 4472 N, N, N, N, N, N, N, N, 4473 } }; 4474 4475 static const struct gprefix pfx_0f_6f_0f_7f = { 4476 I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov), 4477 }; 4478 4479 static const struct instr_dual instr_dual_0f_2b = { 4480 I(0, em_mov), N 4481 }; 4482 4483 static const struct gprefix pfx_0f_2b = { 4484 ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N, 4485 }; 4486 4487 static const struct gprefix pfx_0f_10_0f_11 = { 4488 I(Unaligned, em_mov), I(Unaligned, em_mov), N, N, 4489 }; 4490 4491 static const struct gprefix pfx_0f_28_0f_29 = { 4492 I(Aligned, em_mov), I(Aligned, em_mov), N, N, 4493 }; 4494 4495 static const struct gprefix pfx_0f_e7 = { 4496 N, I(Sse, em_mov), N, N, 4497 }; 4498 4499 static const struct escape escape_d9 = { { 4500 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw), 4501 }, { 4502 /* 0xC0 - 0xC7 */ 4503 N, N, N, N, N, N, N, N, 4504 /* 0xC8 - 0xCF */ 4505 N, N, N, N, N, N, N, N, 4506 /* 0xD0 - 0xC7 */ 4507 N, N, N, N, N, N, N, N, 4508 /* 0xD8 - 0xDF */ 4509 N, N, N, N, N, N, N, N, 4510 /* 0xE0 - 0xE7 */ 4511 N, N, N, N, N, N, N, N, 4512 /* 0xE8 - 0xEF */ 4513 N, N, N, N, N, N, N, N, 4514 /* 0xF0 - 0xF7 */ 4515 N, N, N, N, N, N, N, N, 4516 /* 0xF8 - 0xFF */ 4517 N, N, N, N, N, N, N, N, 4518 } }; 4519 4520 static const struct escape escape_db = { { 4521 N, N, N, N, N, N, N, N, 4522 }, { 4523 /* 0xC0 - 0xC7 */ 4524 N, N, N, N, N, N, N, N, 4525 /* 0xC8 - 0xCF */ 4526 N, N, N, N, N, N, N, N, 4527 /* 0xD0 - 0xC7 */ 4528 N, N, N, N, N, N, N, N, 4529 /* 0xD8 - 0xDF */ 4530 N, N, N, N, N, N, N, N, 4531 /* 0xE0 - 0xE7 */ 4532 N, N, N, I(ImplicitOps, em_fninit), N, N, N, N, 4533 /* 0xE8 - 0xEF */ 4534 N, N, N, N, N, N, N, N, 4535 /* 0xF0 - 0xF7 */ 4536 N, N, N, N, N, N, N, N, 4537 /* 0xF8 - 0xFF */ 4538 N, N, N, N, N, N, N, N, 4539 } }; 4540 4541 static const struct escape escape_dd = { { 4542 N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw), 4543 }, { 4544 /* 0xC0 - 0xC7 */ 4545 N, N, N, N, N, N, N, N, 4546 /* 0xC8 - 0xCF */ 4547 N, N, N, N, N, N, N, N, 4548 /* 0xD0 - 0xC7 */ 4549 N, N, N, N, N, N, N, N, 4550 /* 0xD8 - 0xDF */ 4551 N, N, N, N, N, N, N, N, 4552 /* 0xE0 - 0xE7 */ 4553 N, N, N, N, N, N, N, N, 4554 /* 0xE8 - 0xEF */ 4555 N, N, N, N, N, N, N, N, 4556 /* 0xF0 - 0xF7 */ 4557 N, N, N, N, N, N, N, N, 4558 /* 0xF8 - 0xFF */ 4559 N, N, N, N, N, N, N, N, 4560 } }; 4561 4562 static const struct instr_dual instr_dual_0f_c3 = { 4563 I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N 4564 }; 4565 4566 static const struct mode_dual mode_dual_63 = { 4567 N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd) 4568 }; 4569 4570 static const struct opcode opcode_table[256] = { 4571 /* 0x00 - 0x07 */ 4572 F6ALU(Lock, em_add), 4573 I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg), 4574 I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg), 4575 /* 0x08 - 0x0F */ 4576 F6ALU(Lock | PageTable, em_or), 4577 I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg), 4578 N, 4579 /* 0x10 - 0x17 */ 4580 F6ALU(Lock, em_adc), 4581 I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg), 4582 I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg), 4583 /* 0x18 - 0x1F */ 4584 F6ALU(Lock, em_sbb), 4585 I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg), 4586 I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg), 4587 /* 0x20 - 0x27 */ 4588 F6ALU(Lock | PageTable, em_and), N, N, 4589 /* 0x28 - 0x2F */ 4590 F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das), 4591 /* 0x30 - 0x37 */ 4592 F6ALU(Lock, em_xor), N, N, 4593 /* 0x38 - 0x3F */ 4594 F6ALU(NoWrite, em_cmp), N, N, 4595 /* 0x40 - 0x4F */ 4596 X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)), 4597 /* 0x50 - 0x57 */ 4598 X8(I(SrcReg | Stack, em_push)), 4599 /* 0x58 - 0x5F */ 4600 X8(I(DstReg | Stack, em_pop)), 4601 /* 0x60 - 0x67 */ 4602 I(ImplicitOps | Stack | No64, em_pusha), 4603 I(ImplicitOps | Stack | No64, em_popa), 4604 N, MD(ModRM, &mode_dual_63), 4605 N, N, N, N, 4606 /* 0x68 - 0x6F */ 4607 I(SrcImm | Mov | Stack, em_push), 4608 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op), 4609 I(SrcImmByte | Mov | Stack, em_push), 4610 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op), 4611 I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */ 4612 I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */ 4613 /* 0x70 - 0x7F */ 4614 X16(D(SrcImmByte | NearBranch | IsBranch)), 4615 /* 0x80 - 0x87 */ 4616 G(ByteOp | DstMem | SrcImm, group1), 4617 G(DstMem | SrcImm, group1), 4618 G(ByteOp | DstMem | SrcImm | No64, group1), 4619 G(DstMem | SrcImmByte, group1), 4620 F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test), 4621 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg), 4622 /* 0x88 - 0x8F */ 4623 I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov), 4624 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov), 4625 I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg), 4626 D(ModRM | SrcMem | NoAccess | DstReg), 4627 I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm), 4628 G(0, group1A), 4629 /* 0x90 - 0x97 */ 4630 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)), 4631 /* 0x98 - 0x9F */ 4632 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd), 4633 I(SrcImmFAddr | No64 | IsBranch, em_call_far), N, 4634 II(ImplicitOps | Stack, em_pushf, pushf), 4635 II(ImplicitOps | Stack, em_popf, popf), 4636 I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf), 4637 /* 0xA0 - 0xA7 */ 4638 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), 4639 I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov), 4640 I2bv(SrcSI | DstDI | Mov | String | TwoMemOp, em_mov), 4641 F2bv(SrcSI | DstDI | String | NoWrite | TwoMemOp, em_cmp_r), 4642 /* 0xA8 - 0xAF */ 4643 F2bv(DstAcc | SrcImm | NoWrite, em_test), 4644 I2bv(SrcAcc | DstDI | Mov | String, em_mov), 4645 I2bv(SrcSI | DstAcc | Mov | String, em_mov), 4646 F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r), 4647 /* 0xB0 - 0xB7 */ 4648 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), 4649 /* 0xB8 - 0xBF */ 4650 X8(I(DstReg | SrcImm64 | Mov, em_mov)), 4651 /* 0xC0 - 0xC7 */ 4652 G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2), 4653 I(ImplicitOps | NearBranch | SrcImmU16 | IsBranch, em_ret_near_imm), 4654 I(ImplicitOps | NearBranch | IsBranch, em_ret), 4655 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg), 4656 I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg), 4657 G(ByteOp, group11), G(0, group11), 4658 /* 0xC8 - 0xCF */ 4659 I(Stack | SrcImmU16 | Src2ImmByte | IsBranch, em_enter), 4660 I(Stack | IsBranch, em_leave), 4661 I(ImplicitOps | SrcImmU16 | IsBranch, em_ret_far_imm), 4662 I(ImplicitOps | IsBranch, em_ret_far), 4663 D(ImplicitOps | IsBranch), DI(SrcImmByte | IsBranch, intn), 4664 D(ImplicitOps | No64 | IsBranch), 4665 II(ImplicitOps | IsBranch, em_iret, iret), 4666 /* 0xD0 - 0xD7 */ 4667 G(Src2One | ByteOp, group2), G(Src2One, group2), 4668 G(Src2CL | ByteOp, group2), G(Src2CL, group2), 4669 I(DstAcc | SrcImmUByte | No64, em_aam), 4670 I(DstAcc | SrcImmUByte | No64, em_aad), 4671 F(DstAcc | ByteOp | No64, em_salc), 4672 I(DstAcc | SrcXLat | ByteOp, em_mov), 4673 /* 0xD8 - 0xDF */ 4674 N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N, 4675 /* 0xE0 - 0xE7 */ 4676 X3(I(SrcImmByte | NearBranch | IsBranch, em_loop)), 4677 I(SrcImmByte | NearBranch | IsBranch, em_jcxz), 4678 I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in), 4679 I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out), 4680 /* 0xE8 - 0xEF */ 4681 I(SrcImm | NearBranch | IsBranch, em_call), 4682 D(SrcImm | ImplicitOps | NearBranch | IsBranch), 4683 I(SrcImmFAddr | No64 | IsBranch, em_jmp_far), 4684 D(SrcImmByte | ImplicitOps | NearBranch | IsBranch), 4685 I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in), 4686 I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out), 4687 /* 0xF0 - 0xF7 */ 4688 N, DI(ImplicitOps, icebp), N, N, 4689 DI(ImplicitOps | Priv, hlt), D(ImplicitOps), 4690 G(ByteOp, group3), G(0, group3), 4691 /* 0xF8 - 0xFF */ 4692 D(ImplicitOps), D(ImplicitOps), 4693 I(ImplicitOps, em_cli), I(ImplicitOps, em_sti), 4694 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5), 4695 }; 4696 4697 static const struct opcode twobyte_table[256] = { 4698 /* 0x00 - 0x0F */ 4699 G(0, group6), GD(0, &group7), N, N, 4700 N, I(ImplicitOps | EmulateOnUD | IsBranch, em_syscall), 4701 II(ImplicitOps | Priv, em_clts, clts), N, 4702 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N, 4703 N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N, 4704 /* 0x10 - 0x1F */ 4705 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_10_0f_11), 4706 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_10_0f_11), 4707 N, N, N, N, N, N, 4708 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 4 * prefetch + 4 * reserved NOP */ 4709 D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N, 4710 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */ 4711 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */ 4712 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* 8 * reserved NOP */ 4713 D(ImplicitOps | ModRM | SrcMem | NoAccess), /* NOP + 7 * reserved NOP */ 4714 /* 0x20 - 0x2F */ 4715 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_access), 4716 DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read), 4717 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write, 4718 check_cr_access), 4719 IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write, 4720 check_dr_write), 4721 N, N, N, N, 4722 GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29), 4723 GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29), 4724 N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b), 4725 N, N, N, N, 4726 /* 0x30 - 0x3F */ 4727 II(ImplicitOps | Priv, em_wrmsr, wrmsr), 4728 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc), 4729 II(ImplicitOps | Priv, em_rdmsr, rdmsr), 4730 IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc), 4731 I(ImplicitOps | EmulateOnUD | IsBranch, em_sysenter), 4732 I(ImplicitOps | Priv | EmulateOnUD | IsBranch, em_sysexit), 4733 N, N, 4734 N, N, N, N, N, N, N, N, 4735 /* 0x40 - 0x4F */ 4736 X16(D(DstReg | SrcMem | ModRM)), 4737 /* 0x50 - 0x5F */ 4738 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 4739 /* 0x60 - 0x6F */ 4740 N, N, N, N, 4741 N, N, N, N, 4742 N, N, N, N, 4743 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f), 4744 /* 0x70 - 0x7F */ 4745 N, N, N, N, 4746 N, N, N, N, 4747 N, N, N, N, 4748 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f), 4749 /* 0x80 - 0x8F */ 4750 X16(D(SrcImm | NearBranch | IsBranch)), 4751 /* 0x90 - 0x9F */ 4752 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), 4753 /* 0xA0 - 0xA7 */ 4754 I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg), 4755 II(ImplicitOps, em_cpuid, cpuid), 4756 F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt), 4757 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld), 4758 F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N, 4759 /* 0xA8 - 0xAF */ 4760 I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg), 4761 II(EmulateOnUD | ImplicitOps, em_rsm, rsm), 4762 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts), 4763 F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd), 4764 F(DstMem | SrcReg | Src2CL | ModRM, em_shrd), 4765 GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul), 4766 /* 0xB0 - 0xB7 */ 4767 I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg), 4768 I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg), 4769 F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr), 4770 I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg), 4771 I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg), 4772 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 4773 /* 0xB8 - 0xBF */ 4774 N, N, 4775 G(BitOp, group8), 4776 F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc), 4777 I(DstReg | SrcMem | ModRM, em_bsf_c), 4778 I(DstReg | SrcMem | ModRM, em_bsr_c), 4779 D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov), 4780 /* 0xC0 - 0xC7 */ 4781 F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd), 4782 N, ID(0, &instr_dual_0f_c3), 4783 N, N, N, GD(0, &group9), 4784 /* 0xC8 - 0xCF */ 4785 X8(I(DstReg, em_bswap)), 4786 /* 0xD0 - 0xDF */ 4787 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, 4788 /* 0xE0 - 0xEF */ 4789 N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7), 4790 N, N, N, N, N, N, N, N, 4791 /* 0xF0 - 0xFF */ 4792 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N 4793 }; 4794 4795 static const struct instr_dual instr_dual_0f_38_f0 = { 4796 I(DstReg | SrcMem | Mov, em_movbe), N 4797 }; 4798 4799 static const struct instr_dual instr_dual_0f_38_f1 = { 4800 I(DstMem | SrcReg | Mov, em_movbe), N 4801 }; 4802 4803 static const struct gprefix three_byte_0f_38_f0 = { 4804 ID(0, &instr_dual_0f_38_f0), N, N, N 4805 }; 4806 4807 static const struct gprefix three_byte_0f_38_f1 = { 4808 ID(0, &instr_dual_0f_38_f1), N, N, N 4809 }; 4810 4811 /* 4812 * Insns below are selected by the prefix which indexed by the third opcode 4813 * byte. 4814 */ 4815 static const struct opcode opcode_map_0f_38[256] = { 4816 /* 0x00 - 0x7f */ 4817 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), 4818 /* 0x80 - 0xef */ 4819 X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), 4820 /* 0xf0 - 0xf1 */ 4821 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0), 4822 GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1), 4823 /* 0xf2 - 0xff */ 4824 N, N, X4(N), X8(N) 4825 }; 4826 4827 #undef D 4828 #undef N 4829 #undef G 4830 #undef GD 4831 #undef I 4832 #undef GP 4833 #undef EXT 4834 #undef MD 4835 #undef ID 4836 4837 #undef D2bv 4838 #undef D2bvIP 4839 #undef I2bv 4840 #undef I2bvIP 4841 #undef I6ALU 4842 4843 static unsigned imm_size(struct x86_emulate_ctxt *ctxt) 4844 { 4845 unsigned size; 4846 4847 size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4848 if (size == 8) 4849 size = 4; 4850 return size; 4851 } 4852 4853 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op, 4854 unsigned size, bool sign_extension) 4855 { 4856 int rc = X86EMUL_CONTINUE; 4857 4858 op->type = OP_IMM; 4859 op->bytes = size; 4860 op->addr.mem.ea = ctxt->_eip; 4861 /* NB. Immediates are sign-extended as necessary. */ 4862 switch (op->bytes) { 4863 case 1: 4864 op->val = insn_fetch(s8, ctxt); 4865 break; 4866 case 2: 4867 op->val = insn_fetch(s16, ctxt); 4868 break; 4869 case 4: 4870 op->val = insn_fetch(s32, ctxt); 4871 break; 4872 case 8: 4873 op->val = insn_fetch(s64, ctxt); 4874 break; 4875 } 4876 if (!sign_extension) { 4877 switch (op->bytes) { 4878 case 1: 4879 op->val &= 0xff; 4880 break; 4881 case 2: 4882 op->val &= 0xffff; 4883 break; 4884 case 4: 4885 op->val &= 0xffffffff; 4886 break; 4887 } 4888 } 4889 done: 4890 return rc; 4891 } 4892 4893 static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op, 4894 unsigned d) 4895 { 4896 int rc = X86EMUL_CONTINUE; 4897 4898 switch (d) { 4899 case OpReg: 4900 decode_register_operand(ctxt, op); 4901 break; 4902 case OpImmUByte: 4903 rc = decode_imm(ctxt, op, 1, false); 4904 break; 4905 case OpMem: 4906 ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4907 mem_common: 4908 *op = ctxt->memop; 4909 ctxt->memopp = op; 4910 if (ctxt->d & BitOp) 4911 fetch_bit_operand(ctxt); 4912 op->orig_val = op->val; 4913 break; 4914 case OpMem64: 4915 ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8; 4916 goto mem_common; 4917 case OpAcc: 4918 op->type = OP_REG; 4919 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4920 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 4921 fetch_register_operand(op); 4922 op->orig_val = op->val; 4923 break; 4924 case OpAccLo: 4925 op->type = OP_REG; 4926 op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes; 4927 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX); 4928 fetch_register_operand(op); 4929 op->orig_val = op->val; 4930 break; 4931 case OpAccHi: 4932 if (ctxt->d & ByteOp) { 4933 op->type = OP_NONE; 4934 break; 4935 } 4936 op->type = OP_REG; 4937 op->bytes = ctxt->op_bytes; 4938 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 4939 fetch_register_operand(op); 4940 op->orig_val = op->val; 4941 break; 4942 case OpDI: 4943 op->type = OP_MEM; 4944 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4945 op->addr.mem.ea = 4946 register_address(ctxt, VCPU_REGS_RDI); 4947 op->addr.mem.seg = VCPU_SREG_ES; 4948 op->val = 0; 4949 op->count = 1; 4950 break; 4951 case OpDX: 4952 op->type = OP_REG; 4953 op->bytes = 2; 4954 op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX); 4955 fetch_register_operand(op); 4956 break; 4957 case OpCL: 4958 op->type = OP_IMM; 4959 op->bytes = 1; 4960 op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff; 4961 break; 4962 case OpImmByte: 4963 rc = decode_imm(ctxt, op, 1, true); 4964 break; 4965 case OpOne: 4966 op->type = OP_IMM; 4967 op->bytes = 1; 4968 op->val = 1; 4969 break; 4970 case OpImm: 4971 rc = decode_imm(ctxt, op, imm_size(ctxt), true); 4972 break; 4973 case OpImm64: 4974 rc = decode_imm(ctxt, op, ctxt->op_bytes, true); 4975 break; 4976 case OpMem8: 4977 ctxt->memop.bytes = 1; 4978 if (ctxt->memop.type == OP_REG) { 4979 ctxt->memop.addr.reg = decode_register(ctxt, 4980 ctxt->modrm_rm, true); 4981 fetch_register_operand(&ctxt->memop); 4982 } 4983 goto mem_common; 4984 case OpMem16: 4985 ctxt->memop.bytes = 2; 4986 goto mem_common; 4987 case OpMem32: 4988 ctxt->memop.bytes = 4; 4989 goto mem_common; 4990 case OpImmU16: 4991 rc = decode_imm(ctxt, op, 2, false); 4992 break; 4993 case OpImmU: 4994 rc = decode_imm(ctxt, op, imm_size(ctxt), false); 4995 break; 4996 case OpSI: 4997 op->type = OP_MEM; 4998 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 4999 op->addr.mem.ea = 5000 register_address(ctxt, VCPU_REGS_RSI); 5001 op->addr.mem.seg = ctxt->seg_override; 5002 op->val = 0; 5003 op->count = 1; 5004 break; 5005 case OpXLat: 5006 op->type = OP_MEM; 5007 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes; 5008 op->addr.mem.ea = 5009 address_mask(ctxt, 5010 reg_read(ctxt, VCPU_REGS_RBX) + 5011 (reg_read(ctxt, VCPU_REGS_RAX) & 0xff)); 5012 op->addr.mem.seg = ctxt->seg_override; 5013 op->val = 0; 5014 break; 5015 case OpImmFAddr: 5016 op->type = OP_IMM; 5017 op->addr.mem.ea = ctxt->_eip; 5018 op->bytes = ctxt->op_bytes + 2; 5019 insn_fetch_arr(op->valptr, op->bytes, ctxt); 5020 break; 5021 case OpMemFAddr: 5022 ctxt->memop.bytes = ctxt->op_bytes + 2; 5023 goto mem_common; 5024 case OpES: 5025 op->type = OP_IMM; 5026 op->val = VCPU_SREG_ES; 5027 break; 5028 case OpCS: 5029 op->type = OP_IMM; 5030 op->val = VCPU_SREG_CS; 5031 break; 5032 case OpSS: 5033 op->type = OP_IMM; 5034 op->val = VCPU_SREG_SS; 5035 break; 5036 case OpDS: 5037 op->type = OP_IMM; 5038 op->val = VCPU_SREG_DS; 5039 break; 5040 case OpFS: 5041 op->type = OP_IMM; 5042 op->val = VCPU_SREG_FS; 5043 break; 5044 case OpGS: 5045 op->type = OP_IMM; 5046 op->val = VCPU_SREG_GS; 5047 break; 5048 case OpImplicit: 5049 /* Special instructions do their own operand decoding. */ 5050 default: 5051 op->type = OP_NONE; /* Disable writeback. */ 5052 break; 5053 } 5054 5055 done: 5056 return rc; 5057 } 5058 5059 int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len, int emulation_type) 5060 { 5061 int rc = X86EMUL_CONTINUE; 5062 int mode = ctxt->mode; 5063 int def_op_bytes, def_ad_bytes, goffset, simd_prefix; 5064 bool op_prefix = false; 5065 bool has_seg_override = false; 5066 struct opcode opcode; 5067 u16 dummy; 5068 struct desc_struct desc; 5069 5070 ctxt->memop.type = OP_NONE; 5071 ctxt->memopp = NULL; 5072 ctxt->_eip = ctxt->eip; 5073 ctxt->fetch.ptr = ctxt->fetch.data; 5074 ctxt->fetch.end = ctxt->fetch.data + insn_len; 5075 ctxt->opcode_len = 1; 5076 ctxt->intercept = x86_intercept_none; 5077 if (insn_len > 0) 5078 memcpy(ctxt->fetch.data, insn, insn_len); 5079 else { 5080 rc = __do_insn_fetch_bytes(ctxt, 1); 5081 if (rc != X86EMUL_CONTINUE) 5082 goto done; 5083 } 5084 5085 switch (mode) { 5086 case X86EMUL_MODE_REAL: 5087 case X86EMUL_MODE_VM86: 5088 def_op_bytes = def_ad_bytes = 2; 5089 ctxt->ops->get_segment(ctxt, &dummy, &desc, NULL, VCPU_SREG_CS); 5090 if (desc.d) 5091 def_op_bytes = def_ad_bytes = 4; 5092 break; 5093 case X86EMUL_MODE_PROT16: 5094 def_op_bytes = def_ad_bytes = 2; 5095 break; 5096 case X86EMUL_MODE_PROT32: 5097 def_op_bytes = def_ad_bytes = 4; 5098 break; 5099 #ifdef CONFIG_X86_64 5100 case X86EMUL_MODE_PROT64: 5101 def_op_bytes = 4; 5102 def_ad_bytes = 8; 5103 break; 5104 #endif 5105 default: 5106 return EMULATION_FAILED; 5107 } 5108 5109 ctxt->op_bytes = def_op_bytes; 5110 ctxt->ad_bytes = def_ad_bytes; 5111 5112 /* Legacy prefixes. */ 5113 for (;;) { 5114 switch (ctxt->b = insn_fetch(u8, ctxt)) { 5115 case 0x66: /* operand-size override */ 5116 op_prefix = true; 5117 /* switch between 2/4 bytes */ 5118 ctxt->op_bytes = def_op_bytes ^ 6; 5119 break; 5120 case 0x67: /* address-size override */ 5121 if (mode == X86EMUL_MODE_PROT64) 5122 /* switch between 4/8 bytes */ 5123 ctxt->ad_bytes = def_ad_bytes ^ 12; 5124 else 5125 /* switch between 2/4 bytes */ 5126 ctxt->ad_bytes = def_ad_bytes ^ 6; 5127 break; 5128 case 0x26: /* ES override */ 5129 has_seg_override = true; 5130 ctxt->seg_override = VCPU_SREG_ES; 5131 break; 5132 case 0x2e: /* CS override */ 5133 has_seg_override = true; 5134 ctxt->seg_override = VCPU_SREG_CS; 5135 break; 5136 case 0x36: /* SS override */ 5137 has_seg_override = true; 5138 ctxt->seg_override = VCPU_SREG_SS; 5139 break; 5140 case 0x3e: /* DS override */ 5141 has_seg_override = true; 5142 ctxt->seg_override = VCPU_SREG_DS; 5143 break; 5144 case 0x64: /* FS override */ 5145 has_seg_override = true; 5146 ctxt->seg_override = VCPU_SREG_FS; 5147 break; 5148 case 0x65: /* GS override */ 5149 has_seg_override = true; 5150 ctxt->seg_override = VCPU_SREG_GS; 5151 break; 5152 case 0x40 ... 0x4f: /* REX */ 5153 if (mode != X86EMUL_MODE_PROT64) 5154 goto done_prefixes; 5155 ctxt->rex_prefix = ctxt->b; 5156 continue; 5157 case 0xf0: /* LOCK */ 5158 ctxt->lock_prefix = 1; 5159 break; 5160 case 0xf2: /* REPNE/REPNZ */ 5161 case 0xf3: /* REP/REPE/REPZ */ 5162 ctxt->rep_prefix = ctxt->b; 5163 break; 5164 default: 5165 goto done_prefixes; 5166 } 5167 5168 /* Any legacy prefix after a REX prefix nullifies its effect. */ 5169 5170 ctxt->rex_prefix = 0; 5171 } 5172 5173 done_prefixes: 5174 5175 /* REX prefix. */ 5176 if (ctxt->rex_prefix & 8) 5177 ctxt->op_bytes = 8; /* REX.W */ 5178 5179 /* Opcode byte(s). */ 5180 opcode = opcode_table[ctxt->b]; 5181 /* Two-byte opcode? */ 5182 if (ctxt->b == 0x0f) { 5183 ctxt->opcode_len = 2; 5184 ctxt->b = insn_fetch(u8, ctxt); 5185 opcode = twobyte_table[ctxt->b]; 5186 5187 /* 0F_38 opcode map */ 5188 if (ctxt->b == 0x38) { 5189 ctxt->opcode_len = 3; 5190 ctxt->b = insn_fetch(u8, ctxt); 5191 opcode = opcode_map_0f_38[ctxt->b]; 5192 } 5193 } 5194 ctxt->d = opcode.flags; 5195 5196 if (ctxt->d & ModRM) 5197 ctxt->modrm = insn_fetch(u8, ctxt); 5198 5199 /* vex-prefix instructions are not implemented */ 5200 if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) && 5201 (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) { 5202 ctxt->d = NotImpl; 5203 } 5204 5205 while (ctxt->d & GroupMask) { 5206 switch (ctxt->d & GroupMask) { 5207 case Group: 5208 goffset = (ctxt->modrm >> 3) & 7; 5209 opcode = opcode.u.group[goffset]; 5210 break; 5211 case GroupDual: 5212 goffset = (ctxt->modrm >> 3) & 7; 5213 if ((ctxt->modrm >> 6) == 3) 5214 opcode = opcode.u.gdual->mod3[goffset]; 5215 else 5216 opcode = opcode.u.gdual->mod012[goffset]; 5217 break; 5218 case RMExt: 5219 goffset = ctxt->modrm & 7; 5220 opcode = opcode.u.group[goffset]; 5221 break; 5222 case Prefix: 5223 if (ctxt->rep_prefix && op_prefix) 5224 return EMULATION_FAILED; 5225 simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix; 5226 switch (simd_prefix) { 5227 case 0x00: opcode = opcode.u.gprefix->pfx_no; break; 5228 case 0x66: opcode = opcode.u.gprefix->pfx_66; break; 5229 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break; 5230 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break; 5231 } 5232 break; 5233 case Escape: 5234 if (ctxt->modrm > 0xbf) { 5235 size_t size = ARRAY_SIZE(opcode.u.esc->high); 5236 u32 index = array_index_nospec( 5237 ctxt->modrm - 0xc0, size); 5238 5239 opcode = opcode.u.esc->high[index]; 5240 } else { 5241 opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7]; 5242 } 5243 break; 5244 case InstrDual: 5245 if ((ctxt->modrm >> 6) == 3) 5246 opcode = opcode.u.idual->mod3; 5247 else 5248 opcode = opcode.u.idual->mod012; 5249 break; 5250 case ModeDual: 5251 if (ctxt->mode == X86EMUL_MODE_PROT64) 5252 opcode = opcode.u.mdual->mode64; 5253 else 5254 opcode = opcode.u.mdual->mode32; 5255 break; 5256 default: 5257 return EMULATION_FAILED; 5258 } 5259 5260 ctxt->d &= ~(u64)GroupMask; 5261 ctxt->d |= opcode.flags; 5262 } 5263 5264 ctxt->is_branch = opcode.flags & IsBranch; 5265 5266 /* Unrecognised? */ 5267 if (ctxt->d == 0) 5268 return EMULATION_FAILED; 5269 5270 ctxt->execute = opcode.u.execute; 5271 5272 if (unlikely(emulation_type & EMULTYPE_TRAP_UD) && 5273 likely(!(ctxt->d & EmulateOnUD))) 5274 return EMULATION_FAILED; 5275 5276 if (unlikely(ctxt->d & 5277 (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch| 5278 No16))) { 5279 /* 5280 * These are copied unconditionally here, and checked unconditionally 5281 * in x86_emulate_insn. 5282 */ 5283 ctxt->check_perm = opcode.check_perm; 5284 ctxt->intercept = opcode.intercept; 5285 5286 if (ctxt->d & NotImpl) 5287 return EMULATION_FAILED; 5288 5289 if (mode == X86EMUL_MODE_PROT64) { 5290 if (ctxt->op_bytes == 4 && (ctxt->d & Stack)) 5291 ctxt->op_bytes = 8; 5292 else if (ctxt->d & NearBranch) 5293 ctxt->op_bytes = 8; 5294 } 5295 5296 if (ctxt->d & Op3264) { 5297 if (mode == X86EMUL_MODE_PROT64) 5298 ctxt->op_bytes = 8; 5299 else 5300 ctxt->op_bytes = 4; 5301 } 5302 5303 if ((ctxt->d & No16) && ctxt->op_bytes == 2) 5304 ctxt->op_bytes = 4; 5305 5306 if (ctxt->d & Sse) 5307 ctxt->op_bytes = 16; 5308 else if (ctxt->d & Mmx) 5309 ctxt->op_bytes = 8; 5310 } 5311 5312 /* ModRM and SIB bytes. */ 5313 if (ctxt->d & ModRM) { 5314 rc = decode_modrm(ctxt, &ctxt->memop); 5315 if (!has_seg_override) { 5316 has_seg_override = true; 5317 ctxt->seg_override = ctxt->modrm_seg; 5318 } 5319 } else if (ctxt->d & MemAbs) 5320 rc = decode_abs(ctxt, &ctxt->memop); 5321 if (rc != X86EMUL_CONTINUE) 5322 goto done; 5323 5324 if (!has_seg_override) 5325 ctxt->seg_override = VCPU_SREG_DS; 5326 5327 ctxt->memop.addr.mem.seg = ctxt->seg_override; 5328 5329 /* 5330 * Decode and fetch the source operand: register, memory 5331 * or immediate. 5332 */ 5333 rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask); 5334 if (rc != X86EMUL_CONTINUE) 5335 goto done; 5336 5337 /* 5338 * Decode and fetch the second source operand: register, memory 5339 * or immediate. 5340 */ 5341 rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask); 5342 if (rc != X86EMUL_CONTINUE) 5343 goto done; 5344 5345 /* Decode and fetch the destination operand: register or memory. */ 5346 rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask); 5347 5348 if (ctxt->rip_relative && likely(ctxt->memopp)) 5349 ctxt->memopp->addr.mem.ea = address_mask(ctxt, 5350 ctxt->memopp->addr.mem.ea + ctxt->_eip); 5351 5352 done: 5353 if (rc == X86EMUL_PROPAGATE_FAULT) 5354 ctxt->have_exception = true; 5355 return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK; 5356 } 5357 5358 bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt) 5359 { 5360 return ctxt->d & PageTable; 5361 } 5362 5363 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt) 5364 { 5365 /* The second termination condition only applies for REPE 5366 * and REPNE. Test if the repeat string operation prefix is 5367 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the 5368 * corresponding termination condition according to: 5369 * - if REPE/REPZ and ZF = 0 then done 5370 * - if REPNE/REPNZ and ZF = 1 then done 5371 */ 5372 if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) || 5373 (ctxt->b == 0xae) || (ctxt->b == 0xaf)) 5374 && (((ctxt->rep_prefix == REPE_PREFIX) && 5375 ((ctxt->eflags & X86_EFLAGS_ZF) == 0)) 5376 || ((ctxt->rep_prefix == REPNE_PREFIX) && 5377 ((ctxt->eflags & X86_EFLAGS_ZF) == X86_EFLAGS_ZF)))) 5378 return true; 5379 5380 return false; 5381 } 5382 5383 static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt) 5384 { 5385 int rc; 5386 5387 kvm_fpu_get(); 5388 rc = asm_safe("fwait"); 5389 kvm_fpu_put(); 5390 5391 if (unlikely(rc != X86EMUL_CONTINUE)) 5392 return emulate_exception(ctxt, MF_VECTOR, 0, false); 5393 5394 return X86EMUL_CONTINUE; 5395 } 5396 5397 static void fetch_possible_mmx_operand(struct operand *op) 5398 { 5399 if (op->type == OP_MM) 5400 kvm_read_mmx_reg(op->addr.mm, &op->mm_val); 5401 } 5402 5403 static int fastop(struct x86_emulate_ctxt *ctxt, fastop_t fop) 5404 { 5405 ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF; 5406 5407 if (!(ctxt->d & ByteOp)) 5408 fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE; 5409 5410 asm("push %[flags]; popf; " CALL_NOSPEC " ; pushf; pop %[flags]\n" 5411 : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags), 5412 [thunk_target]"+S"(fop), ASM_CALL_CONSTRAINT 5413 : "c"(ctxt->src2.val)); 5414 5415 ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK); 5416 if (!fop) /* exception is returned in fop variable */ 5417 return emulate_de(ctxt); 5418 return X86EMUL_CONTINUE; 5419 } 5420 5421 void init_decode_cache(struct x86_emulate_ctxt *ctxt) 5422 { 5423 /* Clear fields that are set conditionally but read without a guard. */ 5424 ctxt->rip_relative = false; 5425 ctxt->rex_prefix = 0; 5426 ctxt->lock_prefix = 0; 5427 ctxt->rep_prefix = 0; 5428 ctxt->regs_valid = 0; 5429 ctxt->regs_dirty = 0; 5430 5431 ctxt->io_read.pos = 0; 5432 ctxt->io_read.end = 0; 5433 ctxt->mem_read.end = 0; 5434 } 5435 5436 int x86_emulate_insn(struct x86_emulate_ctxt *ctxt) 5437 { 5438 const struct x86_emulate_ops *ops = ctxt->ops; 5439 int rc = X86EMUL_CONTINUE; 5440 int saved_dst_type = ctxt->dst.type; 5441 unsigned emul_flags; 5442 5443 ctxt->mem_read.pos = 0; 5444 5445 /* LOCK prefix is allowed only with some instructions */ 5446 if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) { 5447 rc = emulate_ud(ctxt); 5448 goto done; 5449 } 5450 5451 if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) { 5452 rc = emulate_ud(ctxt); 5453 goto done; 5454 } 5455 5456 emul_flags = ctxt->ops->get_hflags(ctxt); 5457 if (unlikely(ctxt->d & 5458 (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) { 5459 if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) || 5460 (ctxt->d & Undefined)) { 5461 rc = emulate_ud(ctxt); 5462 goto done; 5463 } 5464 5465 if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM))) 5466 || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) { 5467 rc = emulate_ud(ctxt); 5468 goto done; 5469 } 5470 5471 if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) { 5472 rc = emulate_nm(ctxt); 5473 goto done; 5474 } 5475 5476 if (ctxt->d & Mmx) { 5477 rc = flush_pending_x87_faults(ctxt); 5478 if (rc != X86EMUL_CONTINUE) 5479 goto done; 5480 /* 5481 * Now that we know the fpu is exception safe, we can fetch 5482 * operands from it. 5483 */ 5484 fetch_possible_mmx_operand(&ctxt->src); 5485 fetch_possible_mmx_operand(&ctxt->src2); 5486 if (!(ctxt->d & Mov)) 5487 fetch_possible_mmx_operand(&ctxt->dst); 5488 } 5489 5490 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && ctxt->intercept) { 5491 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5492 X86_ICPT_PRE_EXCEPT); 5493 if (rc != X86EMUL_CONTINUE) 5494 goto done; 5495 } 5496 5497 /* Instruction can only be executed in protected mode */ 5498 if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) { 5499 rc = emulate_ud(ctxt); 5500 goto done; 5501 } 5502 5503 /* Privileged instruction can be executed only in CPL=0 */ 5504 if ((ctxt->d & Priv) && ops->cpl(ctxt)) { 5505 if (ctxt->d & PrivUD) 5506 rc = emulate_ud(ctxt); 5507 else 5508 rc = emulate_gp(ctxt, 0); 5509 goto done; 5510 } 5511 5512 /* Do instruction specific permission checks */ 5513 if (ctxt->d & CheckPerm) { 5514 rc = ctxt->check_perm(ctxt); 5515 if (rc != X86EMUL_CONTINUE) 5516 goto done; 5517 } 5518 5519 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) { 5520 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5521 X86_ICPT_POST_EXCEPT); 5522 if (rc != X86EMUL_CONTINUE) 5523 goto done; 5524 } 5525 5526 if (ctxt->rep_prefix && (ctxt->d & String)) { 5527 /* All REP prefixes have the same first termination condition */ 5528 if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) { 5529 string_registers_quirk(ctxt); 5530 ctxt->eip = ctxt->_eip; 5531 ctxt->eflags &= ~X86_EFLAGS_RF; 5532 goto done; 5533 } 5534 } 5535 } 5536 5537 if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) { 5538 rc = segmented_read(ctxt, ctxt->src.addr.mem, 5539 ctxt->src.valptr, ctxt->src.bytes); 5540 if (rc != X86EMUL_CONTINUE) 5541 goto done; 5542 ctxt->src.orig_val64 = ctxt->src.val64; 5543 } 5544 5545 if (ctxt->src2.type == OP_MEM) { 5546 rc = segmented_read(ctxt, ctxt->src2.addr.mem, 5547 &ctxt->src2.val, ctxt->src2.bytes); 5548 if (rc != X86EMUL_CONTINUE) 5549 goto done; 5550 } 5551 5552 if ((ctxt->d & DstMask) == ImplicitOps) 5553 goto special_insn; 5554 5555 5556 if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) { 5557 /* optimisation - avoid slow emulated read if Mov */ 5558 rc = segmented_read(ctxt, ctxt->dst.addr.mem, 5559 &ctxt->dst.val, ctxt->dst.bytes); 5560 if (rc != X86EMUL_CONTINUE) { 5561 if (!(ctxt->d & NoWrite) && 5562 rc == X86EMUL_PROPAGATE_FAULT && 5563 ctxt->exception.vector == PF_VECTOR) 5564 ctxt->exception.error_code |= PFERR_WRITE_MASK; 5565 goto done; 5566 } 5567 } 5568 /* Copy full 64-bit value for CMPXCHG8B. */ 5569 ctxt->dst.orig_val64 = ctxt->dst.val64; 5570 5571 special_insn: 5572 5573 if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) { 5574 rc = emulator_check_intercept(ctxt, ctxt->intercept, 5575 X86_ICPT_POST_MEMACCESS); 5576 if (rc != X86EMUL_CONTINUE) 5577 goto done; 5578 } 5579 5580 if (ctxt->rep_prefix && (ctxt->d & String)) 5581 ctxt->eflags |= X86_EFLAGS_RF; 5582 else 5583 ctxt->eflags &= ~X86_EFLAGS_RF; 5584 5585 if (ctxt->execute) { 5586 if (ctxt->d & Fastop) 5587 rc = fastop(ctxt, ctxt->fop); 5588 else 5589 rc = ctxt->execute(ctxt); 5590 if (rc != X86EMUL_CONTINUE) 5591 goto done; 5592 goto writeback; 5593 } 5594 5595 if (ctxt->opcode_len == 2) 5596 goto twobyte_insn; 5597 else if (ctxt->opcode_len == 3) 5598 goto threebyte_insn; 5599 5600 switch (ctxt->b) { 5601 case 0x70 ... 0x7f: /* jcc (short) */ 5602 if (test_cc(ctxt->b, ctxt->eflags)) 5603 rc = jmp_rel(ctxt, ctxt->src.val); 5604 break; 5605 case 0x8d: /* lea r16/r32, m */ 5606 ctxt->dst.val = ctxt->src.addr.mem.ea; 5607 break; 5608 case 0x90 ... 0x97: /* nop / xchg reg, rax */ 5609 if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX)) 5610 ctxt->dst.type = OP_NONE; 5611 else 5612 rc = em_xchg(ctxt); 5613 break; 5614 case 0x98: /* cbw/cwde/cdqe */ 5615 switch (ctxt->op_bytes) { 5616 case 2: ctxt->dst.val = (s8)ctxt->dst.val; break; 5617 case 4: ctxt->dst.val = (s16)ctxt->dst.val; break; 5618 case 8: ctxt->dst.val = (s32)ctxt->dst.val; break; 5619 } 5620 break; 5621 case 0xcc: /* int3 */ 5622 rc = emulate_int(ctxt, 3); 5623 break; 5624 case 0xcd: /* int n */ 5625 rc = emulate_int(ctxt, ctxt->src.val); 5626 break; 5627 case 0xce: /* into */ 5628 if (ctxt->eflags & X86_EFLAGS_OF) 5629 rc = emulate_int(ctxt, 4); 5630 break; 5631 case 0xe9: /* jmp rel */ 5632 case 0xeb: /* jmp rel short */ 5633 rc = jmp_rel(ctxt, ctxt->src.val); 5634 ctxt->dst.type = OP_NONE; /* Disable writeback. */ 5635 break; 5636 case 0xf4: /* hlt */ 5637 ctxt->ops->halt(ctxt); 5638 break; 5639 case 0xf5: /* cmc */ 5640 /* complement carry flag from eflags reg */ 5641 ctxt->eflags ^= X86_EFLAGS_CF; 5642 break; 5643 case 0xf8: /* clc */ 5644 ctxt->eflags &= ~X86_EFLAGS_CF; 5645 break; 5646 case 0xf9: /* stc */ 5647 ctxt->eflags |= X86_EFLAGS_CF; 5648 break; 5649 case 0xfc: /* cld */ 5650 ctxt->eflags &= ~X86_EFLAGS_DF; 5651 break; 5652 case 0xfd: /* std */ 5653 ctxt->eflags |= X86_EFLAGS_DF; 5654 break; 5655 default: 5656 goto cannot_emulate; 5657 } 5658 5659 if (rc != X86EMUL_CONTINUE) 5660 goto done; 5661 5662 writeback: 5663 if (ctxt->d & SrcWrite) { 5664 BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR); 5665 rc = writeback(ctxt, &ctxt->src); 5666 if (rc != X86EMUL_CONTINUE) 5667 goto done; 5668 } 5669 if (!(ctxt->d & NoWrite)) { 5670 rc = writeback(ctxt, &ctxt->dst); 5671 if (rc != X86EMUL_CONTINUE) 5672 goto done; 5673 } 5674 5675 /* 5676 * restore dst type in case the decoding will be reused 5677 * (happens for string instruction ) 5678 */ 5679 ctxt->dst.type = saved_dst_type; 5680 5681 if ((ctxt->d & SrcMask) == SrcSI) 5682 string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src); 5683 5684 if ((ctxt->d & DstMask) == DstDI) 5685 string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst); 5686 5687 if (ctxt->rep_prefix && (ctxt->d & String)) { 5688 unsigned int count; 5689 struct read_cache *r = &ctxt->io_read; 5690 if ((ctxt->d & SrcMask) == SrcSI) 5691 count = ctxt->src.count; 5692 else 5693 count = ctxt->dst.count; 5694 register_address_increment(ctxt, VCPU_REGS_RCX, -count); 5695 5696 if (!string_insn_completed(ctxt)) { 5697 /* 5698 * Re-enter guest when pio read ahead buffer is empty 5699 * or, if it is not used, after each 1024 iteration. 5700 */ 5701 if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) && 5702 (r->end == 0 || r->end != r->pos)) { 5703 /* 5704 * Reset read cache. Usually happens before 5705 * decode, but since instruction is restarted 5706 * we have to do it here. 5707 */ 5708 ctxt->mem_read.end = 0; 5709 writeback_registers(ctxt); 5710 return EMULATION_RESTART; 5711 } 5712 goto done; /* skip rip writeback */ 5713 } 5714 ctxt->eflags &= ~X86_EFLAGS_RF; 5715 } 5716 5717 ctxt->eip = ctxt->_eip; 5718 if (ctxt->mode != X86EMUL_MODE_PROT64) 5719 ctxt->eip = (u32)ctxt->_eip; 5720 5721 done: 5722 if (rc == X86EMUL_PROPAGATE_FAULT) { 5723 WARN_ON(ctxt->exception.vector > 0x1f); 5724 ctxt->have_exception = true; 5725 } 5726 if (rc == X86EMUL_INTERCEPTED) 5727 return EMULATION_INTERCEPTED; 5728 5729 if (rc == X86EMUL_CONTINUE) 5730 writeback_registers(ctxt); 5731 5732 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK; 5733 5734 twobyte_insn: 5735 switch (ctxt->b) { 5736 case 0x09: /* wbinvd */ 5737 (ctxt->ops->wbinvd)(ctxt); 5738 break; 5739 case 0x08: /* invd */ 5740 case 0x0d: /* GrpP (prefetch) */ 5741 case 0x18: /* Grp16 (prefetch/nop) */ 5742 case 0x1f: /* nop */ 5743 break; 5744 case 0x20: /* mov cr, reg */ 5745 ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg); 5746 break; 5747 case 0x21: /* mov from dr to reg */ 5748 ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val); 5749 break; 5750 case 0x40 ... 0x4f: /* cmov */ 5751 if (test_cc(ctxt->b, ctxt->eflags)) 5752 ctxt->dst.val = ctxt->src.val; 5753 else if (ctxt->op_bytes != 4) 5754 ctxt->dst.type = OP_NONE; /* no writeback */ 5755 break; 5756 case 0x80 ... 0x8f: /* jnz rel, etc*/ 5757 if (test_cc(ctxt->b, ctxt->eflags)) 5758 rc = jmp_rel(ctxt, ctxt->src.val); 5759 break; 5760 case 0x90 ... 0x9f: /* setcc r/m8 */ 5761 ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags); 5762 break; 5763 case 0xb6 ... 0xb7: /* movzx */ 5764 ctxt->dst.bytes = ctxt->op_bytes; 5765 ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val 5766 : (u16) ctxt->src.val; 5767 break; 5768 case 0xbe ... 0xbf: /* movsx */ 5769 ctxt->dst.bytes = ctxt->op_bytes; 5770 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val : 5771 (s16) ctxt->src.val; 5772 break; 5773 default: 5774 goto cannot_emulate; 5775 } 5776 5777 threebyte_insn: 5778 5779 if (rc != X86EMUL_CONTINUE) 5780 goto done; 5781 5782 goto writeback; 5783 5784 cannot_emulate: 5785 return EMULATION_FAILED; 5786 } 5787 5788 void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt) 5789 { 5790 invalidate_registers(ctxt); 5791 } 5792 5793 void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt) 5794 { 5795 writeback_registers(ctxt); 5796 } 5797 5798 bool emulator_can_use_gpa(struct x86_emulate_ctxt *ctxt) 5799 { 5800 if (ctxt->rep_prefix && (ctxt->d & String)) 5801 return false; 5802 5803 if (ctxt->d & TwoMemOp) 5804 return false; 5805 5806 return true; 5807 } 5808