1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * cpuid support routines 5 * 6 * derived from arch/x86/kvm/x86.c 7 * 8 * Copyright 2011 Red Hat, Inc. and/or its affiliates. 9 * Copyright IBM Corporation, 2008 10 */ 11 12 #include <linux/kvm_host.h> 13 #include <linux/export.h> 14 #include <linux/vmalloc.h> 15 #include <linux/uaccess.h> 16 #include <linux/sched/stat.h> 17 18 #include <asm/processor.h> 19 #include <asm/user.h> 20 #include <asm/fpu/xstate.h> 21 #include "cpuid.h" 22 #include "lapic.h" 23 #include "mmu.h" 24 #include "trace.h" 25 #include "pmu.h" 26 27 /* 28 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be 29 * aligned to sizeof(unsigned long) because it's not accessed via bitops. 30 */ 31 u32 kvm_cpu_caps[NCAPINTS] __read_mostly; 32 EXPORT_SYMBOL_GPL(kvm_cpu_caps); 33 34 static u32 xstate_required_size(u64 xstate_bv, bool compacted) 35 { 36 int feature_bit = 0; 37 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 38 39 xstate_bv &= XFEATURE_MASK_EXTEND; 40 while (xstate_bv) { 41 if (xstate_bv & 0x1) { 42 u32 eax, ebx, ecx, edx, offset; 43 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx); 44 offset = compacted ? ret : ebx; 45 ret = max(ret, offset + eax); 46 } 47 48 xstate_bv >>= 1; 49 feature_bit++; 50 } 51 52 return ret; 53 } 54 55 #define F feature_bit 56 57 static inline struct kvm_cpuid_entry2 *cpuid_entry2_find( 58 struct kvm_cpuid_entry2 *entries, int nent, u32 function, u32 index) 59 { 60 struct kvm_cpuid_entry2 *e; 61 int i; 62 63 for (i = 0; i < nent; i++) { 64 e = &entries[i]; 65 66 if (e->function == function && (e->index == index || 67 !(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX))) 68 return e; 69 } 70 71 return NULL; 72 } 73 74 static int kvm_check_cpuid(struct kvm_cpuid_entry2 *entries, int nent) 75 { 76 struct kvm_cpuid_entry2 *best; 77 78 /* 79 * The existing code assumes virtual address is 48-bit or 57-bit in the 80 * canonical address checks; exit if it is ever changed. 81 */ 82 best = cpuid_entry2_find(entries, nent, 0x80000008, 0); 83 if (best) { 84 int vaddr_bits = (best->eax & 0xff00) >> 8; 85 86 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) 87 return -EINVAL; 88 } 89 90 return 0; 91 } 92 93 void kvm_update_pv_runtime(struct kvm_vcpu *vcpu) 94 { 95 struct kvm_cpuid_entry2 *best; 96 97 best = kvm_find_cpuid_entry(vcpu, KVM_CPUID_FEATURES, 0); 98 99 /* 100 * save the feature bitmap to avoid cpuid lookup for every PV 101 * operation 102 */ 103 if (best) 104 vcpu->arch.pv_cpuid.features = best->eax; 105 } 106 107 void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu) 108 { 109 struct kvm_cpuid_entry2 *best; 110 111 best = kvm_find_cpuid_entry(vcpu, 1, 0); 112 if (best) { 113 /* Update OSXSAVE bit */ 114 if (boot_cpu_has(X86_FEATURE_XSAVE)) 115 cpuid_entry_change(best, X86_FEATURE_OSXSAVE, 116 kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)); 117 118 cpuid_entry_change(best, X86_FEATURE_APIC, 119 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE); 120 } 121 122 best = kvm_find_cpuid_entry(vcpu, 7, 0); 123 if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7) 124 cpuid_entry_change(best, X86_FEATURE_OSPKE, 125 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)); 126 127 best = kvm_find_cpuid_entry(vcpu, 0xD, 0); 128 if (best) 129 best->ebx = xstate_required_size(vcpu->arch.xcr0, false); 130 131 best = kvm_find_cpuid_entry(vcpu, 0xD, 1); 132 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) || 133 cpuid_entry_has(best, X86_FEATURE_XSAVEC))) 134 best->ebx = xstate_required_size(vcpu->arch.xcr0, true); 135 136 best = kvm_find_cpuid_entry(vcpu, KVM_CPUID_FEATURES, 0); 137 if (kvm_hlt_in_guest(vcpu->kvm) && best && 138 (best->eax & (1 << KVM_FEATURE_PV_UNHALT))) 139 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT); 140 141 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) { 142 best = kvm_find_cpuid_entry(vcpu, 0x1, 0); 143 if (best) 144 cpuid_entry_change(best, X86_FEATURE_MWAIT, 145 vcpu->arch.ia32_misc_enable_msr & 146 MSR_IA32_MISC_ENABLE_MWAIT); 147 } 148 } 149 150 static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) 151 { 152 struct kvm_lapic *apic = vcpu->arch.apic; 153 struct kvm_cpuid_entry2 *best; 154 155 best = kvm_find_cpuid_entry(vcpu, 1, 0); 156 if (best && apic) { 157 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER)) 158 apic->lapic_timer.timer_mode_mask = 3 << 17; 159 else 160 apic->lapic_timer.timer_mode_mask = 1 << 17; 161 162 kvm_apic_set_version(vcpu); 163 } 164 165 best = kvm_find_cpuid_entry(vcpu, 0xD, 0); 166 if (!best) 167 vcpu->arch.guest_supported_xcr0 = 0; 168 else 169 vcpu->arch.guest_supported_xcr0 = 170 (best->eax | ((u64)best->edx << 32)) & supported_xcr0; 171 172 kvm_update_pv_runtime(vcpu); 173 174 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 175 kvm_mmu_reset_context(vcpu); 176 177 kvm_pmu_refresh(vcpu); 178 vcpu->arch.cr4_guest_rsvd_bits = 179 __cr4_reserved_bits(guest_cpuid_has, vcpu); 180 181 /* Invoke the vendor callback only after the above state is updated. */ 182 kvm_x86_ops.vcpu_after_set_cpuid(vcpu); 183 } 184 185 static int is_efer_nx(void) 186 { 187 return host_efer & EFER_NX; 188 } 189 190 static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu) 191 { 192 int i; 193 struct kvm_cpuid_entry2 *e, *entry; 194 195 entry = NULL; 196 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { 197 e = &vcpu->arch.cpuid_entries[i]; 198 if (e->function == 0x80000001) { 199 entry = e; 200 break; 201 } 202 } 203 if (entry && cpuid_entry_has(entry, X86_FEATURE_NX) && !is_efer_nx()) { 204 cpuid_entry_clear(entry, X86_FEATURE_NX); 205 printk(KERN_INFO "kvm: guest NX capability removed\n"); 206 } 207 } 208 209 int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu) 210 { 211 struct kvm_cpuid_entry2 *best; 212 213 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0); 214 if (!best || best->eax < 0x80000008) 215 goto not_found; 216 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0); 217 if (best) 218 return best->eax & 0xff; 219 not_found: 220 return 36; 221 } 222 223 /* when an old userspace process fills a new kernel module */ 224 int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, 225 struct kvm_cpuid *cpuid, 226 struct kvm_cpuid_entry __user *entries) 227 { 228 int r, i; 229 struct kvm_cpuid_entry *e = NULL; 230 struct kvm_cpuid_entry2 *e2 = NULL; 231 232 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 233 return -E2BIG; 234 235 if (cpuid->nent) { 236 e = vmemdup_user(entries, array_size(sizeof(*e), cpuid->nent)); 237 if (IS_ERR(e)) 238 return PTR_ERR(e); 239 240 e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT); 241 if (!e2) { 242 r = -ENOMEM; 243 goto out_free_cpuid; 244 } 245 } 246 for (i = 0; i < cpuid->nent; i++) { 247 e2[i].function = e[i].function; 248 e2[i].eax = e[i].eax; 249 e2[i].ebx = e[i].ebx; 250 e2[i].ecx = e[i].ecx; 251 e2[i].edx = e[i].edx; 252 e2[i].index = 0; 253 e2[i].flags = 0; 254 e2[i].padding[0] = 0; 255 e2[i].padding[1] = 0; 256 e2[i].padding[2] = 0; 257 } 258 259 r = kvm_check_cpuid(e2, cpuid->nent); 260 if (r) { 261 kvfree(e2); 262 goto out_free_cpuid; 263 } 264 265 kvfree(vcpu->arch.cpuid_entries); 266 vcpu->arch.cpuid_entries = e2; 267 vcpu->arch.cpuid_nent = cpuid->nent; 268 269 cpuid_fix_nx_cap(vcpu); 270 kvm_update_cpuid_runtime(vcpu); 271 kvm_vcpu_after_set_cpuid(vcpu); 272 273 out_free_cpuid: 274 kvfree(e); 275 276 return r; 277 } 278 279 int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, 280 struct kvm_cpuid2 *cpuid, 281 struct kvm_cpuid_entry2 __user *entries) 282 { 283 struct kvm_cpuid_entry2 *e2 = NULL; 284 int r; 285 286 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 287 return -E2BIG; 288 289 if (cpuid->nent) { 290 e2 = vmemdup_user(entries, array_size(sizeof(*e2), cpuid->nent)); 291 if (IS_ERR(e2)) 292 return PTR_ERR(e2); 293 } 294 295 r = kvm_check_cpuid(e2, cpuid->nent); 296 if (r) { 297 kvfree(e2); 298 return r; 299 } 300 301 kvfree(vcpu->arch.cpuid_entries); 302 vcpu->arch.cpuid_entries = e2; 303 vcpu->arch.cpuid_nent = cpuid->nent; 304 305 kvm_update_cpuid_runtime(vcpu); 306 kvm_vcpu_after_set_cpuid(vcpu); 307 308 return 0; 309 } 310 311 int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, 312 struct kvm_cpuid2 *cpuid, 313 struct kvm_cpuid_entry2 __user *entries) 314 { 315 int r; 316 317 r = -E2BIG; 318 if (cpuid->nent < vcpu->arch.cpuid_nent) 319 goto out; 320 r = -EFAULT; 321 if (copy_to_user(entries, &vcpu->arch.cpuid_entries, 322 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) 323 goto out; 324 return 0; 325 326 out: 327 cpuid->nent = vcpu->arch.cpuid_nent; 328 return r; 329 } 330 331 static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask) 332 { 333 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32); 334 struct kvm_cpuid_entry2 entry; 335 336 reverse_cpuid_check(leaf); 337 kvm_cpu_caps[leaf] &= mask; 338 339 cpuid_count(cpuid.function, cpuid.index, 340 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx); 341 342 kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg); 343 } 344 345 void kvm_set_cpu_caps(void) 346 { 347 unsigned int f_nx = is_efer_nx() ? F(NX) : 0; 348 #ifdef CONFIG_X86_64 349 unsigned int f_gbpages = F(GBPAGES); 350 unsigned int f_lm = F(LM); 351 #else 352 unsigned int f_gbpages = 0; 353 unsigned int f_lm = 0; 354 #endif 355 356 BUILD_BUG_ON(sizeof(kvm_cpu_caps) > 357 sizeof(boot_cpu_data.x86_capability)); 358 359 memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability, 360 sizeof(kvm_cpu_caps)); 361 362 kvm_cpu_cap_mask(CPUID_1_ECX, 363 /* 364 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not* 365 * advertised to guests via CPUID! 366 */ 367 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ | 368 0 /* DS-CPL, VMX, SMX, EST */ | 369 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | 370 F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) | 371 F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) | 372 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | 373 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) | 374 F(F16C) | F(RDRAND) 375 ); 376 /* KVM emulates x2apic in software irrespective of host support. */ 377 kvm_cpu_cap_set(X86_FEATURE_X2APIC); 378 379 kvm_cpu_cap_mask(CPUID_1_EDX, 380 F(FPU) | F(VME) | F(DE) | F(PSE) | 381 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 382 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | 383 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 384 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) | 385 0 /* Reserved, DS, ACPI */ | F(MMX) | 386 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | 387 0 /* HTT, TM, Reserved, PBE */ 388 ); 389 390 kvm_cpu_cap_mask(CPUID_7_0_EBX, 391 F(FSGSBASE) | F(BMI1) | F(HLE) | F(AVX2) | F(SMEP) | 392 F(BMI2) | F(ERMS) | 0 /*INVPCID*/ | F(RTM) | 0 /*MPX*/ | F(RDSEED) | 393 F(ADX) | F(SMAP) | F(AVX512IFMA) | F(AVX512F) | F(AVX512PF) | 394 F(AVX512ER) | F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(AVX512DQ) | 395 F(SHA_NI) | F(AVX512BW) | F(AVX512VL) | 0 /*INTEL_PT*/ 396 ); 397 398 kvm_cpu_cap_mask(CPUID_7_ECX, 399 F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) | 400 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) | 401 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) | 402 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ 403 ); 404 /* Set LA57 based on hardware capability. */ 405 if (cpuid_ecx(7) & F(LA57)) 406 kvm_cpu_cap_set(X86_FEATURE_LA57); 407 408 /* 409 * PKU not yet implemented for shadow paging and requires OSPKE 410 * to be set on the host. Clear it if that is not the case 411 */ 412 if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE)) 413 kvm_cpu_cap_clear(X86_FEATURE_PKU); 414 415 kvm_cpu_cap_mask(CPUID_7_EDX, 416 F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | 417 F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | 418 F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | 419 F(SERIALIZE) | F(TSXLDTRK) 420 ); 421 422 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ 423 kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST); 424 kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES); 425 426 if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS)) 427 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL); 428 if (boot_cpu_has(X86_FEATURE_STIBP)) 429 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); 430 if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) 431 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); 432 433 kvm_cpu_cap_mask(CPUID_7_1_EAX, 434 F(AVX512_BF16) 435 ); 436 437 kvm_cpu_cap_mask(CPUID_D_1_EAX, 438 F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) 439 ); 440 441 kvm_cpu_cap_mask(CPUID_8000_0001_ECX, 442 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ | 443 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | 444 F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) | 445 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) | 446 F(TOPOEXT) | F(PERFCTR_CORE) 447 ); 448 449 kvm_cpu_cap_mask(CPUID_8000_0001_EDX, 450 F(FPU) | F(VME) | F(DE) | F(PSE) | 451 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 452 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | 453 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 454 F(PAT) | F(PSE36) | 0 /* Reserved */ | 455 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | 456 F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) | 457 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW) 458 ); 459 460 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64)) 461 kvm_cpu_cap_set(X86_FEATURE_GBPAGES); 462 463 kvm_cpu_cap_mask(CPUID_8000_0008_EBX, 464 F(CLZERO) | F(XSAVEERPTR) | 465 F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | 466 F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) 467 ); 468 469 /* 470 * AMD has separate bits for each SPEC_CTRL bit. 471 * arch/x86/kernel/cpu/bugs.c is kind enough to 472 * record that in cpufeatures so use them. 473 */ 474 if (boot_cpu_has(X86_FEATURE_IBPB)) 475 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB); 476 if (boot_cpu_has(X86_FEATURE_IBRS)) 477 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS); 478 if (boot_cpu_has(X86_FEATURE_STIBP)) 479 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP); 480 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) 481 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD); 482 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 483 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO); 484 /* 485 * The preference is to use SPEC CTRL MSR instead of the 486 * VIRT_SPEC MSR. 487 */ 488 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) && 489 !boot_cpu_has(X86_FEATURE_AMD_SSBD)) 490 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); 491 492 /* 493 * Hide all SVM features by default, SVM will set the cap bits for 494 * features it emulates and/or exposes for L1. 495 */ 496 kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0); 497 498 kvm_cpu_cap_mask(CPUID_C000_0001_EDX, 499 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | 500 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | 501 F(PMM) | F(PMM_EN) 502 ); 503 } 504 EXPORT_SYMBOL_GPL(kvm_set_cpu_caps); 505 506 struct kvm_cpuid_array { 507 struct kvm_cpuid_entry2 *entries; 508 int maxnent; 509 int nent; 510 }; 511 512 static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array, 513 u32 function, u32 index) 514 { 515 struct kvm_cpuid_entry2 *entry; 516 517 if (array->nent >= array->maxnent) 518 return NULL; 519 520 entry = &array->entries[array->nent++]; 521 522 entry->function = function; 523 entry->index = index; 524 entry->flags = 0; 525 526 cpuid_count(entry->function, entry->index, 527 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); 528 529 switch (function) { 530 case 4: 531 case 7: 532 case 0xb: 533 case 0xd: 534 case 0xf: 535 case 0x10: 536 case 0x12: 537 case 0x14: 538 case 0x17: 539 case 0x18: 540 case 0x1f: 541 case 0x8000001d: 542 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 543 break; 544 } 545 546 return entry; 547 } 548 549 static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func) 550 { 551 struct kvm_cpuid_entry2 *entry; 552 553 if (array->nent >= array->maxnent) 554 return -E2BIG; 555 556 entry = &array->entries[array->nent]; 557 entry->function = func; 558 entry->index = 0; 559 entry->flags = 0; 560 561 switch (func) { 562 case 0: 563 entry->eax = 7; 564 ++array->nent; 565 break; 566 case 1: 567 entry->ecx = F(MOVBE); 568 ++array->nent; 569 break; 570 case 7: 571 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 572 entry->eax = 0; 573 entry->ecx = F(RDPID); 574 ++array->nent; 575 default: 576 break; 577 } 578 579 return 0; 580 } 581 582 static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) 583 { 584 struct kvm_cpuid_entry2 *entry; 585 int r, i, max_idx; 586 587 /* all calls to cpuid_count() should be made on the same cpu */ 588 get_cpu(); 589 590 r = -E2BIG; 591 592 entry = do_host_cpuid(array, function, 0); 593 if (!entry) 594 goto out; 595 596 switch (function) { 597 case 0: 598 /* Limited to the highest leaf implemented in KVM. */ 599 entry->eax = min(entry->eax, 0x1fU); 600 break; 601 case 1: 602 cpuid_entry_override(entry, CPUID_1_EDX); 603 cpuid_entry_override(entry, CPUID_1_ECX); 604 break; 605 case 2: 606 /* 607 * On ancient CPUs, function 2 entries are STATEFUL. That is, 608 * CPUID(function=2, index=0) may return different results each 609 * time, with the least-significant byte in EAX enumerating the 610 * number of times software should do CPUID(2, 0). 611 * 612 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less 613 * idiotic. Intel's SDM states that EAX & 0xff "will always 614 * return 01H. Software should ignore this value and not 615 * interpret it as an informational descriptor", while AMD's 616 * APM states that CPUID(2) is reserved. 617 * 618 * WARN if a frankenstein CPU that supports virtualization and 619 * a stateful CPUID.0x2 is encountered. 620 */ 621 WARN_ON_ONCE((entry->eax & 0xff) > 1); 622 break; 623 /* functions 4 and 0x8000001d have additional index. */ 624 case 4: 625 case 0x8000001d: 626 /* 627 * Read entries until the cache type in the previous entry is 628 * zero, i.e. indicates an invalid entry. 629 */ 630 for (i = 1; entry->eax & 0x1f; ++i) { 631 entry = do_host_cpuid(array, function, i); 632 if (!entry) 633 goto out; 634 } 635 break; 636 case 6: /* Thermal management */ 637 entry->eax = 0x4; /* allow ARAT */ 638 entry->ebx = 0; 639 entry->ecx = 0; 640 entry->edx = 0; 641 break; 642 /* function 7 has additional index. */ 643 case 7: 644 entry->eax = min(entry->eax, 1u); 645 cpuid_entry_override(entry, CPUID_7_0_EBX); 646 cpuid_entry_override(entry, CPUID_7_ECX); 647 cpuid_entry_override(entry, CPUID_7_EDX); 648 649 /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */ 650 if (entry->eax == 1) { 651 entry = do_host_cpuid(array, function, 1); 652 if (!entry) 653 goto out; 654 655 cpuid_entry_override(entry, CPUID_7_1_EAX); 656 entry->ebx = 0; 657 entry->ecx = 0; 658 entry->edx = 0; 659 } 660 break; 661 case 9: 662 break; 663 case 0xa: { /* Architectural Performance Monitoring */ 664 struct x86_pmu_capability cap; 665 union cpuid10_eax eax; 666 union cpuid10_edx edx; 667 668 perf_get_x86_pmu_capability(&cap); 669 670 /* 671 * Only support guest architectural pmu on a host 672 * with architectural pmu. 673 */ 674 if (!cap.version) 675 memset(&cap, 0, sizeof(cap)); 676 677 eax.split.version_id = min(cap.version, 2); 678 eax.split.num_counters = cap.num_counters_gp; 679 eax.split.bit_width = cap.bit_width_gp; 680 eax.split.mask_length = cap.events_mask_len; 681 682 edx.split.num_counters_fixed = min(cap.num_counters_fixed, MAX_FIXED_COUNTERS); 683 edx.split.bit_width_fixed = cap.bit_width_fixed; 684 edx.split.reserved = 0; 685 686 entry->eax = eax.full; 687 entry->ebx = cap.events_mask; 688 entry->ecx = 0; 689 entry->edx = edx.full; 690 break; 691 } 692 /* 693 * Per Intel's SDM, the 0x1f is a superset of 0xb, 694 * thus they can be handled by common code. 695 */ 696 case 0x1f: 697 case 0xb: 698 /* 699 * Populate entries until the level type (ECX[15:8]) of the 700 * previous entry is zero. Note, CPUID EAX.{0x1f,0xb}.0 is 701 * the starting entry, filled by the primary do_host_cpuid(). 702 */ 703 for (i = 1; entry->ecx & 0xff00; ++i) { 704 entry = do_host_cpuid(array, function, i); 705 if (!entry) 706 goto out; 707 } 708 break; 709 case 0xd: 710 entry->eax &= supported_xcr0; 711 entry->ebx = xstate_required_size(supported_xcr0, false); 712 entry->ecx = entry->ebx; 713 entry->edx &= supported_xcr0 >> 32; 714 if (!supported_xcr0) 715 break; 716 717 entry = do_host_cpuid(array, function, 1); 718 if (!entry) 719 goto out; 720 721 cpuid_entry_override(entry, CPUID_D_1_EAX); 722 if (entry->eax & (F(XSAVES)|F(XSAVEC))) 723 entry->ebx = xstate_required_size(supported_xcr0 | supported_xss, 724 true); 725 else { 726 WARN_ON_ONCE(supported_xss != 0); 727 entry->ebx = 0; 728 } 729 entry->ecx &= supported_xss; 730 entry->edx &= supported_xss >> 32; 731 732 for (i = 2; i < 64; ++i) { 733 bool s_state; 734 if (supported_xcr0 & BIT_ULL(i)) 735 s_state = false; 736 else if (supported_xss & BIT_ULL(i)) 737 s_state = true; 738 else 739 continue; 740 741 entry = do_host_cpuid(array, function, i); 742 if (!entry) 743 goto out; 744 745 /* 746 * The supported check above should have filtered out 747 * invalid sub-leafs. Only valid sub-leafs should 748 * reach this point, and they should have a non-zero 749 * save state size. Furthermore, check whether the 750 * processor agrees with supported_xcr0/supported_xss 751 * on whether this is an XCR0- or IA32_XSS-managed area. 752 */ 753 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) { 754 --array->nent; 755 continue; 756 } 757 entry->edx = 0; 758 } 759 break; 760 /* Intel PT */ 761 case 0x14: 762 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) { 763 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 764 break; 765 } 766 767 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 768 if (!do_host_cpuid(array, function, i)) 769 goto out; 770 } 771 break; 772 case KVM_CPUID_SIGNATURE: { 773 static const char signature[12] = "KVMKVMKVM\0\0"; 774 const u32 *sigptr = (const u32 *)signature; 775 entry->eax = KVM_CPUID_FEATURES; 776 entry->ebx = sigptr[0]; 777 entry->ecx = sigptr[1]; 778 entry->edx = sigptr[2]; 779 break; 780 } 781 case KVM_CPUID_FEATURES: 782 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | 783 (1 << KVM_FEATURE_NOP_IO_DELAY) | 784 (1 << KVM_FEATURE_CLOCKSOURCE2) | 785 (1 << KVM_FEATURE_ASYNC_PF) | 786 (1 << KVM_FEATURE_PV_EOI) | 787 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) | 788 (1 << KVM_FEATURE_PV_UNHALT) | 789 (1 << KVM_FEATURE_PV_TLB_FLUSH) | 790 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) | 791 (1 << KVM_FEATURE_PV_SEND_IPI) | 792 (1 << KVM_FEATURE_POLL_CONTROL) | 793 (1 << KVM_FEATURE_PV_SCHED_YIELD) | 794 (1 << KVM_FEATURE_ASYNC_PF_INT); 795 796 if (sched_info_on()) 797 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME); 798 799 entry->ebx = 0; 800 entry->ecx = 0; 801 entry->edx = 0; 802 break; 803 case 0x80000000: 804 entry->eax = min(entry->eax, 0x8000001f); 805 break; 806 case 0x80000001: 807 cpuid_entry_override(entry, CPUID_8000_0001_EDX); 808 cpuid_entry_override(entry, CPUID_8000_0001_ECX); 809 break; 810 case 0x80000006: 811 /* L2 cache and TLB: pass through host info. */ 812 break; 813 case 0x80000007: /* Advanced power management */ 814 /* invariant TSC is CPUID.80000007H:EDX[8] */ 815 entry->edx &= (1 << 8); 816 /* mask against host */ 817 entry->edx &= boot_cpu_data.x86_power; 818 entry->eax = entry->ebx = entry->ecx = 0; 819 break; 820 case 0x80000008: { 821 unsigned g_phys_as = (entry->eax >> 16) & 0xff; 822 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U); 823 unsigned phys_as = entry->eax & 0xff; 824 825 if (!g_phys_as) 826 g_phys_as = phys_as; 827 entry->eax = g_phys_as | (virt_as << 8); 828 entry->edx = 0; 829 cpuid_entry_override(entry, CPUID_8000_0008_EBX); 830 break; 831 } 832 case 0x8000000A: 833 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) { 834 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 835 break; 836 } 837 entry->eax = 1; /* SVM revision 1 */ 838 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper 839 ASID emulation to nested SVM */ 840 entry->ecx = 0; /* Reserved */ 841 cpuid_entry_override(entry, CPUID_8000_000A_EDX); 842 break; 843 case 0x80000019: 844 entry->ecx = entry->edx = 0; 845 break; 846 case 0x8000001a: 847 case 0x8000001e: 848 break; 849 /* Support memory encryption cpuid if host supports it */ 850 case 0x8000001F: 851 if (!boot_cpu_has(X86_FEATURE_SEV)) 852 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 853 break; 854 /*Add support for Centaur's CPUID instruction*/ 855 case 0xC0000000: 856 /*Just support up to 0xC0000004 now*/ 857 entry->eax = min(entry->eax, 0xC0000004); 858 break; 859 case 0xC0000001: 860 cpuid_entry_override(entry, CPUID_C000_0001_EDX); 861 break; 862 case 3: /* Processor serial number */ 863 case 5: /* MONITOR/MWAIT */ 864 case 0xC0000002: 865 case 0xC0000003: 866 case 0xC0000004: 867 default: 868 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 869 break; 870 } 871 872 r = 0; 873 874 out: 875 put_cpu(); 876 877 return r; 878 } 879 880 static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func, 881 unsigned int type) 882 { 883 if (type == KVM_GET_EMULATED_CPUID) 884 return __do_cpuid_func_emulated(array, func); 885 886 return __do_cpuid_func(array, func); 887 } 888 889 #define CENTAUR_CPUID_SIGNATURE 0xC0000000 890 891 static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func, 892 unsigned int type) 893 { 894 u32 limit; 895 int r; 896 897 if (func == CENTAUR_CPUID_SIGNATURE && 898 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR) 899 return 0; 900 901 r = do_cpuid_func(array, func, type); 902 if (r) 903 return r; 904 905 limit = array->entries[array->nent - 1].eax; 906 for (func = func + 1; func <= limit; ++func) { 907 r = do_cpuid_func(array, func, type); 908 if (r) 909 break; 910 } 911 912 return r; 913 } 914 915 static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries, 916 __u32 num_entries, unsigned int ioctl_type) 917 { 918 int i; 919 __u32 pad[3]; 920 921 if (ioctl_type != KVM_GET_EMULATED_CPUID) 922 return false; 923 924 /* 925 * We want to make sure that ->padding is being passed clean from 926 * userspace in case we want to use it for something in the future. 927 * 928 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we 929 * have to give ourselves satisfied only with the emulated side. /me 930 * sheds a tear. 931 */ 932 for (i = 0; i < num_entries; i++) { 933 if (copy_from_user(pad, entries[i].padding, sizeof(pad))) 934 return true; 935 936 if (pad[0] || pad[1] || pad[2]) 937 return true; 938 } 939 return false; 940 } 941 942 int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid, 943 struct kvm_cpuid_entry2 __user *entries, 944 unsigned int type) 945 { 946 static const u32 funcs[] = { 947 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE, 948 }; 949 950 struct kvm_cpuid_array array = { 951 .nent = 0, 952 }; 953 int r, i; 954 955 if (cpuid->nent < 1) 956 return -E2BIG; 957 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 958 cpuid->nent = KVM_MAX_CPUID_ENTRIES; 959 960 if (sanity_check_entries(entries, cpuid->nent, type)) 961 return -EINVAL; 962 963 array.entries = vzalloc(array_size(sizeof(struct kvm_cpuid_entry2), 964 cpuid->nent)); 965 if (!array.entries) 966 return -ENOMEM; 967 968 array.maxnent = cpuid->nent; 969 970 for (i = 0; i < ARRAY_SIZE(funcs); i++) { 971 r = get_cpuid_func(&array, funcs[i], type); 972 if (r) 973 goto out_free; 974 } 975 cpuid->nent = array.nent; 976 977 if (copy_to_user(entries, array.entries, 978 array.nent * sizeof(struct kvm_cpuid_entry2))) 979 r = -EFAULT; 980 981 out_free: 982 vfree(array.entries); 983 return r; 984 } 985 986 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, 987 u32 function, u32 index) 988 { 989 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent, 990 function, index); 991 } 992 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); 993 994 /* 995 * Intel CPUID semantics treats any query for an out-of-range leaf as if the 996 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics 997 * returns all zeroes for any undefined leaf, whether or not the leaf is in 998 * range. Centaur/VIA follows Intel semantics. 999 * 1000 * A leaf is considered out-of-range if its function is higher than the maximum 1001 * supported leaf of its associated class or if its associated class does not 1002 * exist. 1003 * 1004 * There are three primary classes to be considered, with their respective 1005 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary 1006 * class exists if a guest CPUID entry for its <base> leaf exists. For a given 1007 * class, CPUID.<base>.EAX contains the max supported leaf for the class. 1008 * 1009 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff 1010 * - Hypervisor: 0x40000000 - 0x4fffffff 1011 * - Extended: 0x80000000 - 0xbfffffff 1012 * - Centaur: 0xc0000000 - 0xcfffffff 1013 * 1014 * The Hypervisor class is further subdivided into sub-classes that each act as 1015 * their own indepdent class associated with a 0x100 byte range. E.g. if Qemu 1016 * is advertising support for both HyperV and KVM, the resulting Hypervisor 1017 * CPUID sub-classes are: 1018 * 1019 * - HyperV: 0x40000000 - 0x400000ff 1020 * - KVM: 0x40000100 - 0x400001ff 1021 */ 1022 static struct kvm_cpuid_entry2 * 1023 get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index) 1024 { 1025 struct kvm_cpuid_entry2 *basic, *class; 1026 u32 function = *fn_ptr; 1027 1028 basic = kvm_find_cpuid_entry(vcpu, 0, 0); 1029 if (!basic) 1030 return NULL; 1031 1032 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) || 1033 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx)) 1034 return NULL; 1035 1036 if (function >= 0x40000000 && function <= 0x4fffffff) 1037 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00, 0); 1038 else if (function >= 0xc0000000) 1039 class = kvm_find_cpuid_entry(vcpu, 0xc0000000, 0); 1040 else 1041 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0); 1042 1043 if (class && function <= class->eax) 1044 return NULL; 1045 1046 /* 1047 * Leaf specific adjustments are also applied when redirecting to the 1048 * max basic entry, e.g. if the max basic leaf is 0xb but there is no 1049 * entry for CPUID.0xb.index (see below), then the output value for EDX 1050 * needs to be pulled from CPUID.0xb.1. 1051 */ 1052 *fn_ptr = basic->eax; 1053 1054 /* 1055 * The class does not exist or the requested function is out of range; 1056 * the effective CPUID entry is the max basic leaf. Note, the index of 1057 * the original requested leaf is observed! 1058 */ 1059 return kvm_find_cpuid_entry(vcpu, basic->eax, index); 1060 } 1061 1062 bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx, 1063 u32 *ecx, u32 *edx, bool exact_only) 1064 { 1065 u32 orig_function = *eax, function = *eax, index = *ecx; 1066 struct kvm_cpuid_entry2 *entry; 1067 bool exact, used_max_basic = false; 1068 1069 entry = kvm_find_cpuid_entry(vcpu, function, index); 1070 exact = !!entry; 1071 1072 if (!entry && !exact_only) { 1073 entry = get_out_of_range_cpuid_entry(vcpu, &function, index); 1074 used_max_basic = !!entry; 1075 } 1076 1077 if (entry) { 1078 *eax = entry->eax; 1079 *ebx = entry->ebx; 1080 *ecx = entry->ecx; 1081 *edx = entry->edx; 1082 if (function == 7 && index == 0) { 1083 u64 data; 1084 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) && 1085 (data & TSX_CTRL_CPUID_CLEAR)) 1086 *ebx &= ~(F(RTM) | F(HLE)); 1087 } 1088 } else { 1089 *eax = *ebx = *ecx = *edx = 0; 1090 /* 1091 * When leaf 0BH or 1FH is defined, CL is pass-through 1092 * and EDX is always the x2APIC ID, even for undefined 1093 * subleaves. Index 1 will exist iff the leaf is 1094 * implemented, so we pass through CL iff leaf 1 1095 * exists. EDX can be copied from any existing index. 1096 */ 1097 if (function == 0xb || function == 0x1f) { 1098 entry = kvm_find_cpuid_entry(vcpu, function, 1); 1099 if (entry) { 1100 *ecx = index & 0xff; 1101 *edx = entry->edx; 1102 } 1103 } 1104 } 1105 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact, 1106 used_max_basic); 1107 return exact; 1108 } 1109 EXPORT_SYMBOL_GPL(kvm_cpuid); 1110 1111 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu) 1112 { 1113 u32 eax, ebx, ecx, edx; 1114 1115 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0)) 1116 return 1; 1117 1118 eax = kvm_rax_read(vcpu); 1119 ecx = kvm_rcx_read(vcpu); 1120 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false); 1121 kvm_rax_write(vcpu, eax); 1122 kvm_rbx_write(vcpu, ebx); 1123 kvm_rcx_write(vcpu, ecx); 1124 kvm_rdx_write(vcpu, edx); 1125 return kvm_skip_emulated_instruction(vcpu); 1126 } 1127 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); 1128