1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * cpuid support routines 5 * 6 * derived from arch/x86/kvm/x86.c 7 * 8 * Copyright 2011 Red Hat, Inc. and/or its affiliates. 9 * Copyright IBM Corporation, 2008 10 */ 11 12 #include <linux/kvm_host.h> 13 #include <linux/export.h> 14 #include <linux/vmalloc.h> 15 #include <linux/uaccess.h> 16 #include <linux/sched/stat.h> 17 18 #include <asm/processor.h> 19 #include <asm/user.h> 20 #include <asm/fpu/xstate.h> 21 #include "cpuid.h" 22 #include "lapic.h" 23 #include "mmu.h" 24 #include "trace.h" 25 #include "pmu.h" 26 27 /* 28 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be 29 * aligned to sizeof(unsigned long) because it's not accessed via bitops. 30 */ 31 u32 kvm_cpu_caps[NCAPINTS] __read_mostly; 32 EXPORT_SYMBOL_GPL(kvm_cpu_caps); 33 34 static u32 xstate_required_size(u64 xstate_bv, bool compacted) 35 { 36 int feature_bit = 0; 37 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 38 39 xstate_bv &= XFEATURE_MASK_EXTEND; 40 while (xstate_bv) { 41 if (xstate_bv & 0x1) { 42 u32 eax, ebx, ecx, edx, offset; 43 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx); 44 offset = compacted ? ret : ebx; 45 ret = max(ret, offset + eax); 46 } 47 48 xstate_bv >>= 1; 49 feature_bit++; 50 } 51 52 return ret; 53 } 54 55 #define F feature_bit 56 57 int kvm_update_cpuid(struct kvm_vcpu *vcpu) 58 { 59 struct kvm_cpuid_entry2 *best; 60 struct kvm_lapic *apic = vcpu->arch.apic; 61 62 best = kvm_find_cpuid_entry(vcpu, 1, 0); 63 if (!best) 64 return 0; 65 66 /* Update OSXSAVE bit */ 67 if (boot_cpu_has(X86_FEATURE_XSAVE) && best->function == 0x1) 68 cpuid_entry_change(best, X86_FEATURE_OSXSAVE, 69 kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)); 70 71 cpuid_entry_change(best, X86_FEATURE_APIC, 72 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE); 73 74 if (apic) { 75 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER)) 76 apic->lapic_timer.timer_mode_mask = 3 << 17; 77 else 78 apic->lapic_timer.timer_mode_mask = 1 << 17; 79 } 80 81 best = kvm_find_cpuid_entry(vcpu, 7, 0); 82 if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7) 83 cpuid_entry_change(best, X86_FEATURE_OSPKE, 84 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)); 85 86 best = kvm_find_cpuid_entry(vcpu, 0xD, 0); 87 if (!best) { 88 vcpu->arch.guest_supported_xcr0 = 0; 89 } else { 90 vcpu->arch.guest_supported_xcr0 = 91 (best->eax | ((u64)best->edx << 32)) & supported_xcr0; 92 best->ebx = xstate_required_size(vcpu->arch.xcr0, false); 93 } 94 95 best = kvm_find_cpuid_entry(vcpu, 0xD, 1); 96 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) || 97 cpuid_entry_has(best, X86_FEATURE_XSAVEC))) 98 best->ebx = xstate_required_size(vcpu->arch.xcr0, true); 99 100 /* 101 * The existing code assumes virtual address is 48-bit or 57-bit in the 102 * canonical address checks; exit if it is ever changed. 103 */ 104 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0); 105 if (best) { 106 int vaddr_bits = (best->eax & 0xff00) >> 8; 107 108 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) 109 return -EINVAL; 110 } 111 112 best = kvm_find_cpuid_entry(vcpu, KVM_CPUID_FEATURES, 0); 113 if (kvm_hlt_in_guest(vcpu->kvm) && best && 114 (best->eax & (1 << KVM_FEATURE_PV_UNHALT))) 115 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT); 116 117 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) { 118 best = kvm_find_cpuid_entry(vcpu, 0x1, 0); 119 if (best) 120 cpuid_entry_change(best, X86_FEATURE_MWAIT, 121 vcpu->arch.ia32_misc_enable_msr & 122 MSR_IA32_MISC_ENABLE_MWAIT); 123 } 124 125 /* Note, maxphyaddr must be updated before tdp_level. */ 126 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 127 vcpu->arch.tdp_level = kvm_x86_ops.get_tdp_level(vcpu); 128 kvm_mmu_reset_context(vcpu); 129 130 kvm_pmu_refresh(vcpu); 131 return 0; 132 } 133 134 static int is_efer_nx(void) 135 { 136 return host_efer & EFER_NX; 137 } 138 139 static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu) 140 { 141 int i; 142 struct kvm_cpuid_entry2 *e, *entry; 143 144 entry = NULL; 145 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { 146 e = &vcpu->arch.cpuid_entries[i]; 147 if (e->function == 0x80000001) { 148 entry = e; 149 break; 150 } 151 } 152 if (entry && cpuid_entry_has(entry, X86_FEATURE_NX) && !is_efer_nx()) { 153 cpuid_entry_clear(entry, X86_FEATURE_NX); 154 printk(KERN_INFO "kvm: guest NX capability removed\n"); 155 } 156 } 157 158 int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu) 159 { 160 struct kvm_cpuid_entry2 *best; 161 162 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0); 163 if (!best || best->eax < 0x80000008) 164 goto not_found; 165 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0); 166 if (best) 167 return best->eax & 0xff; 168 not_found: 169 return 36; 170 } 171 EXPORT_SYMBOL_GPL(cpuid_query_maxphyaddr); 172 173 /* when an old userspace process fills a new kernel module */ 174 int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, 175 struct kvm_cpuid *cpuid, 176 struct kvm_cpuid_entry __user *entries) 177 { 178 int r, i; 179 struct kvm_cpuid_entry *cpuid_entries = NULL; 180 181 r = -E2BIG; 182 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 183 goto out; 184 r = -ENOMEM; 185 if (cpuid->nent) { 186 cpuid_entries = 187 vmalloc(array_size(sizeof(struct kvm_cpuid_entry), 188 cpuid->nent)); 189 if (!cpuid_entries) 190 goto out; 191 r = -EFAULT; 192 if (copy_from_user(cpuid_entries, entries, 193 cpuid->nent * sizeof(struct kvm_cpuid_entry))) 194 goto out; 195 } 196 for (i = 0; i < cpuid->nent; i++) { 197 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function; 198 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax; 199 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx; 200 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx; 201 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx; 202 vcpu->arch.cpuid_entries[i].index = 0; 203 vcpu->arch.cpuid_entries[i].flags = 0; 204 vcpu->arch.cpuid_entries[i].padding[0] = 0; 205 vcpu->arch.cpuid_entries[i].padding[1] = 0; 206 vcpu->arch.cpuid_entries[i].padding[2] = 0; 207 } 208 vcpu->arch.cpuid_nent = cpuid->nent; 209 cpuid_fix_nx_cap(vcpu); 210 kvm_apic_set_version(vcpu); 211 kvm_x86_ops.cpuid_update(vcpu); 212 r = kvm_update_cpuid(vcpu); 213 214 out: 215 vfree(cpuid_entries); 216 return r; 217 } 218 219 int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, 220 struct kvm_cpuid2 *cpuid, 221 struct kvm_cpuid_entry2 __user *entries) 222 { 223 int r; 224 225 r = -E2BIG; 226 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 227 goto out; 228 r = -EFAULT; 229 if (copy_from_user(&vcpu->arch.cpuid_entries, entries, 230 cpuid->nent * sizeof(struct kvm_cpuid_entry2))) 231 goto out; 232 vcpu->arch.cpuid_nent = cpuid->nent; 233 kvm_apic_set_version(vcpu); 234 kvm_x86_ops.cpuid_update(vcpu); 235 r = kvm_update_cpuid(vcpu); 236 out: 237 return r; 238 } 239 240 int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, 241 struct kvm_cpuid2 *cpuid, 242 struct kvm_cpuid_entry2 __user *entries) 243 { 244 int r; 245 246 r = -E2BIG; 247 if (cpuid->nent < vcpu->arch.cpuid_nent) 248 goto out; 249 r = -EFAULT; 250 if (copy_to_user(entries, &vcpu->arch.cpuid_entries, 251 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) 252 goto out; 253 return 0; 254 255 out: 256 cpuid->nent = vcpu->arch.cpuid_nent; 257 return r; 258 } 259 260 static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask) 261 { 262 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32); 263 struct kvm_cpuid_entry2 entry; 264 265 reverse_cpuid_check(leaf); 266 kvm_cpu_caps[leaf] &= mask; 267 268 cpuid_count(cpuid.function, cpuid.index, 269 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx); 270 271 kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg); 272 } 273 274 void kvm_set_cpu_caps(void) 275 { 276 unsigned int f_nx = is_efer_nx() ? F(NX) : 0; 277 #ifdef CONFIG_X86_64 278 unsigned int f_gbpages = F(GBPAGES); 279 unsigned int f_lm = F(LM); 280 #else 281 unsigned int f_gbpages = 0; 282 unsigned int f_lm = 0; 283 #endif 284 285 BUILD_BUG_ON(sizeof(kvm_cpu_caps) > 286 sizeof(boot_cpu_data.x86_capability)); 287 288 memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability, 289 sizeof(kvm_cpu_caps)); 290 291 kvm_cpu_cap_mask(CPUID_1_ECX, 292 /* 293 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not* 294 * advertised to guests via CPUID! 295 */ 296 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ | 297 0 /* DS-CPL, VMX, SMX, EST */ | 298 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | 299 F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) | 300 F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) | 301 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | 302 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) | 303 F(F16C) | F(RDRAND) 304 ); 305 /* KVM emulates x2apic in software irrespective of host support. */ 306 kvm_cpu_cap_set(X86_FEATURE_X2APIC); 307 308 kvm_cpu_cap_mask(CPUID_1_EDX, 309 F(FPU) | F(VME) | F(DE) | F(PSE) | 310 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 311 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | 312 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 313 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) | 314 0 /* Reserved, DS, ACPI */ | F(MMX) | 315 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | 316 0 /* HTT, TM, Reserved, PBE */ 317 ); 318 319 kvm_cpu_cap_mask(CPUID_7_0_EBX, 320 F(FSGSBASE) | F(BMI1) | F(HLE) | F(AVX2) | F(SMEP) | 321 F(BMI2) | F(ERMS) | 0 /*INVPCID*/ | F(RTM) | 0 /*MPX*/ | F(RDSEED) | 322 F(ADX) | F(SMAP) | F(AVX512IFMA) | F(AVX512F) | F(AVX512PF) | 323 F(AVX512ER) | F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(AVX512DQ) | 324 F(SHA_NI) | F(AVX512BW) | F(AVX512VL) | 0 /*INTEL_PT*/ 325 ); 326 327 kvm_cpu_cap_mask(CPUID_7_ECX, 328 F(AVX512VBMI) | F(LA57) | 0 /*PKU*/ | 0 /*OSPKE*/ | F(RDPID) | 329 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) | 330 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) | 331 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ 332 ); 333 /* Set LA57 based on hardware capability. */ 334 if (cpuid_ecx(7) & F(LA57)) 335 kvm_cpu_cap_set(X86_FEATURE_LA57); 336 337 kvm_cpu_cap_mask(CPUID_7_EDX, 338 F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | 339 F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | 340 F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) 341 ); 342 343 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ 344 kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST); 345 kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES); 346 347 if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS)) 348 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL); 349 if (boot_cpu_has(X86_FEATURE_STIBP)) 350 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); 351 if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) 352 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); 353 354 kvm_cpu_cap_mask(CPUID_7_1_EAX, 355 F(AVX512_BF16) 356 ); 357 358 kvm_cpu_cap_mask(CPUID_D_1_EAX, 359 F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) 360 ); 361 362 kvm_cpu_cap_mask(CPUID_8000_0001_ECX, 363 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ | 364 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | 365 F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) | 366 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) | 367 F(TOPOEXT) | F(PERFCTR_CORE) 368 ); 369 370 kvm_cpu_cap_mask(CPUID_8000_0001_EDX, 371 F(FPU) | F(VME) | F(DE) | F(PSE) | 372 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 373 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | 374 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 375 F(PAT) | F(PSE36) | 0 /* Reserved */ | 376 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | 377 F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) | 378 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW) 379 ); 380 381 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64)) 382 kvm_cpu_cap_set(X86_FEATURE_GBPAGES); 383 384 kvm_cpu_cap_mask(CPUID_8000_0008_EBX, 385 F(CLZERO) | F(XSAVEERPTR) | 386 F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | 387 F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) 388 ); 389 390 /* 391 * AMD has separate bits for each SPEC_CTRL bit. 392 * arch/x86/kernel/cpu/bugs.c is kind enough to 393 * record that in cpufeatures so use them. 394 */ 395 if (boot_cpu_has(X86_FEATURE_IBPB)) 396 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB); 397 if (boot_cpu_has(X86_FEATURE_IBRS)) 398 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS); 399 if (boot_cpu_has(X86_FEATURE_STIBP)) 400 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP); 401 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) 402 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD); 403 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 404 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO); 405 /* 406 * The preference is to use SPEC CTRL MSR instead of the 407 * VIRT_SPEC MSR. 408 */ 409 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) && 410 !boot_cpu_has(X86_FEATURE_AMD_SSBD)) 411 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); 412 413 /* 414 * Hide all SVM features by default, SVM will set the cap bits for 415 * features it emulates and/or exposes for L1. 416 */ 417 kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0); 418 419 kvm_cpu_cap_mask(CPUID_C000_0001_EDX, 420 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | 421 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | 422 F(PMM) | F(PMM_EN) 423 ); 424 } 425 EXPORT_SYMBOL_GPL(kvm_set_cpu_caps); 426 427 struct kvm_cpuid_array { 428 struct kvm_cpuid_entry2 *entries; 429 const int maxnent; 430 int nent; 431 }; 432 433 static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array, 434 u32 function, u32 index) 435 { 436 struct kvm_cpuid_entry2 *entry; 437 438 if (array->nent >= array->maxnent) 439 return NULL; 440 441 entry = &array->entries[array->nent++]; 442 443 entry->function = function; 444 entry->index = index; 445 entry->flags = 0; 446 447 cpuid_count(entry->function, entry->index, 448 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); 449 450 switch (function) { 451 case 4: 452 case 7: 453 case 0xb: 454 case 0xd: 455 case 0xf: 456 case 0x10: 457 case 0x12: 458 case 0x14: 459 case 0x17: 460 case 0x18: 461 case 0x1f: 462 case 0x8000001d: 463 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 464 break; 465 } 466 467 return entry; 468 } 469 470 static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func) 471 { 472 struct kvm_cpuid_entry2 *entry; 473 474 if (array->nent >= array->maxnent) 475 return -E2BIG; 476 477 entry = &array->entries[array->nent]; 478 entry->function = func; 479 entry->index = 0; 480 entry->flags = 0; 481 482 switch (func) { 483 case 0: 484 entry->eax = 7; 485 ++array->nent; 486 break; 487 case 1: 488 entry->ecx = F(MOVBE); 489 ++array->nent; 490 break; 491 case 7: 492 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 493 entry->eax = 0; 494 entry->ecx = F(RDPID); 495 ++array->nent; 496 default: 497 break; 498 } 499 500 return 0; 501 } 502 503 static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) 504 { 505 struct kvm_cpuid_entry2 *entry; 506 int r, i, max_idx; 507 508 /* all calls to cpuid_count() should be made on the same cpu */ 509 get_cpu(); 510 511 r = -E2BIG; 512 513 entry = do_host_cpuid(array, function, 0); 514 if (!entry) 515 goto out; 516 517 switch (function) { 518 case 0: 519 /* Limited to the highest leaf implemented in KVM. */ 520 entry->eax = min(entry->eax, 0x1fU); 521 break; 522 case 1: 523 cpuid_entry_override(entry, CPUID_1_EDX); 524 cpuid_entry_override(entry, CPUID_1_ECX); 525 break; 526 case 2: 527 /* 528 * On ancient CPUs, function 2 entries are STATEFUL. That is, 529 * CPUID(function=2, index=0) may return different results each 530 * time, with the least-significant byte in EAX enumerating the 531 * number of times software should do CPUID(2, 0). 532 * 533 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less 534 * idiotic. Intel's SDM states that EAX & 0xff "will always 535 * return 01H. Software should ignore this value and not 536 * interpret it as an informational descriptor", while AMD's 537 * APM states that CPUID(2) is reserved. 538 * 539 * WARN if a frankenstein CPU that supports virtualization and 540 * a stateful CPUID.0x2 is encountered. 541 */ 542 WARN_ON_ONCE((entry->eax & 0xff) > 1); 543 break; 544 /* functions 4 and 0x8000001d have additional index. */ 545 case 4: 546 case 0x8000001d: 547 /* 548 * Read entries until the cache type in the previous entry is 549 * zero, i.e. indicates an invalid entry. 550 */ 551 for (i = 1; entry->eax & 0x1f; ++i) { 552 entry = do_host_cpuid(array, function, i); 553 if (!entry) 554 goto out; 555 } 556 break; 557 case 6: /* Thermal management */ 558 entry->eax = 0x4; /* allow ARAT */ 559 entry->ebx = 0; 560 entry->ecx = 0; 561 entry->edx = 0; 562 break; 563 /* function 7 has additional index. */ 564 case 7: 565 entry->eax = min(entry->eax, 1u); 566 cpuid_entry_override(entry, CPUID_7_0_EBX); 567 cpuid_entry_override(entry, CPUID_7_ECX); 568 cpuid_entry_override(entry, CPUID_7_EDX); 569 570 /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */ 571 if (entry->eax == 1) { 572 entry = do_host_cpuid(array, function, 1); 573 if (!entry) 574 goto out; 575 576 cpuid_entry_override(entry, CPUID_7_1_EAX); 577 entry->ebx = 0; 578 entry->ecx = 0; 579 entry->edx = 0; 580 } 581 break; 582 case 9: 583 break; 584 case 0xa: { /* Architectural Performance Monitoring */ 585 struct x86_pmu_capability cap; 586 union cpuid10_eax eax; 587 union cpuid10_edx edx; 588 589 perf_get_x86_pmu_capability(&cap); 590 591 /* 592 * Only support guest architectural pmu on a host 593 * with architectural pmu. 594 */ 595 if (!cap.version) 596 memset(&cap, 0, sizeof(cap)); 597 598 eax.split.version_id = min(cap.version, 2); 599 eax.split.num_counters = cap.num_counters_gp; 600 eax.split.bit_width = cap.bit_width_gp; 601 eax.split.mask_length = cap.events_mask_len; 602 603 edx.split.num_counters_fixed = cap.num_counters_fixed; 604 edx.split.bit_width_fixed = cap.bit_width_fixed; 605 edx.split.reserved = 0; 606 607 entry->eax = eax.full; 608 entry->ebx = cap.events_mask; 609 entry->ecx = 0; 610 entry->edx = edx.full; 611 break; 612 } 613 /* 614 * Per Intel's SDM, the 0x1f is a superset of 0xb, 615 * thus they can be handled by common code. 616 */ 617 case 0x1f: 618 case 0xb: 619 /* 620 * Populate entries until the level type (ECX[15:8]) of the 621 * previous entry is zero. Note, CPUID EAX.{0x1f,0xb}.0 is 622 * the starting entry, filled by the primary do_host_cpuid(). 623 */ 624 for (i = 1; entry->ecx & 0xff00; ++i) { 625 entry = do_host_cpuid(array, function, i); 626 if (!entry) 627 goto out; 628 } 629 break; 630 case 0xd: 631 entry->eax &= supported_xcr0; 632 entry->ebx = xstate_required_size(supported_xcr0, false); 633 entry->ecx = entry->ebx; 634 entry->edx &= supported_xcr0 >> 32; 635 if (!supported_xcr0) 636 break; 637 638 entry = do_host_cpuid(array, function, 1); 639 if (!entry) 640 goto out; 641 642 cpuid_entry_override(entry, CPUID_D_1_EAX); 643 if (entry->eax & (F(XSAVES)|F(XSAVEC))) 644 entry->ebx = xstate_required_size(supported_xcr0 | supported_xss, 645 true); 646 else { 647 WARN_ON_ONCE(supported_xss != 0); 648 entry->ebx = 0; 649 } 650 entry->ecx &= supported_xss; 651 entry->edx &= supported_xss >> 32; 652 653 for (i = 2; i < 64; ++i) { 654 bool s_state; 655 if (supported_xcr0 & BIT_ULL(i)) 656 s_state = false; 657 else if (supported_xss & BIT_ULL(i)) 658 s_state = true; 659 else 660 continue; 661 662 entry = do_host_cpuid(array, function, i); 663 if (!entry) 664 goto out; 665 666 /* 667 * The supported check above should have filtered out 668 * invalid sub-leafs. Only valid sub-leafs should 669 * reach this point, and they should have a non-zero 670 * save state size. Furthermore, check whether the 671 * processor agrees with supported_xcr0/supported_xss 672 * on whether this is an XCR0- or IA32_XSS-managed area. 673 */ 674 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) { 675 --array->nent; 676 continue; 677 } 678 entry->edx = 0; 679 } 680 break; 681 /* Intel PT */ 682 case 0x14: 683 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) { 684 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 685 break; 686 } 687 688 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 689 if (!do_host_cpuid(array, function, i)) 690 goto out; 691 } 692 break; 693 case KVM_CPUID_SIGNATURE: { 694 static const char signature[12] = "KVMKVMKVM\0\0"; 695 const u32 *sigptr = (const u32 *)signature; 696 entry->eax = KVM_CPUID_FEATURES; 697 entry->ebx = sigptr[0]; 698 entry->ecx = sigptr[1]; 699 entry->edx = sigptr[2]; 700 break; 701 } 702 case KVM_CPUID_FEATURES: 703 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | 704 (1 << KVM_FEATURE_NOP_IO_DELAY) | 705 (1 << KVM_FEATURE_CLOCKSOURCE2) | 706 (1 << KVM_FEATURE_ASYNC_PF) | 707 (1 << KVM_FEATURE_PV_EOI) | 708 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) | 709 (1 << KVM_FEATURE_PV_UNHALT) | 710 (1 << KVM_FEATURE_PV_TLB_FLUSH) | 711 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) | 712 (1 << KVM_FEATURE_PV_SEND_IPI) | 713 (1 << KVM_FEATURE_POLL_CONTROL) | 714 (1 << KVM_FEATURE_PV_SCHED_YIELD) | 715 (1 << KVM_FEATURE_ASYNC_PF_INT); 716 717 if (sched_info_on()) 718 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME); 719 720 entry->ebx = 0; 721 entry->ecx = 0; 722 entry->edx = 0; 723 break; 724 case 0x80000000: 725 entry->eax = min(entry->eax, 0x8000001f); 726 break; 727 case 0x80000001: 728 cpuid_entry_override(entry, CPUID_8000_0001_EDX); 729 cpuid_entry_override(entry, CPUID_8000_0001_ECX); 730 break; 731 case 0x80000006: 732 /* L2 cache and TLB: pass through host info. */ 733 break; 734 case 0x80000007: /* Advanced power management */ 735 /* invariant TSC is CPUID.80000007H:EDX[8] */ 736 entry->edx &= (1 << 8); 737 /* mask against host */ 738 entry->edx &= boot_cpu_data.x86_power; 739 entry->eax = entry->ebx = entry->ecx = 0; 740 break; 741 case 0x80000008: { 742 unsigned g_phys_as = (entry->eax >> 16) & 0xff; 743 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U); 744 unsigned phys_as = entry->eax & 0xff; 745 746 if (!g_phys_as) 747 g_phys_as = phys_as; 748 entry->eax = g_phys_as | (virt_as << 8); 749 entry->edx = 0; 750 cpuid_entry_override(entry, CPUID_8000_0008_EBX); 751 break; 752 } 753 case 0x8000000A: 754 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) { 755 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 756 break; 757 } 758 entry->eax = 1; /* SVM revision 1 */ 759 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper 760 ASID emulation to nested SVM */ 761 entry->ecx = 0; /* Reserved */ 762 cpuid_entry_override(entry, CPUID_8000_000A_EDX); 763 break; 764 case 0x80000019: 765 entry->ecx = entry->edx = 0; 766 break; 767 case 0x8000001a: 768 case 0x8000001e: 769 break; 770 /* Support memory encryption cpuid if host supports it */ 771 case 0x8000001F: 772 if (!boot_cpu_has(X86_FEATURE_SEV)) 773 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 774 break; 775 /*Add support for Centaur's CPUID instruction*/ 776 case 0xC0000000: 777 /*Just support up to 0xC0000004 now*/ 778 entry->eax = min(entry->eax, 0xC0000004); 779 break; 780 case 0xC0000001: 781 cpuid_entry_override(entry, CPUID_C000_0001_EDX); 782 break; 783 case 3: /* Processor serial number */ 784 case 5: /* MONITOR/MWAIT */ 785 case 0xC0000002: 786 case 0xC0000003: 787 case 0xC0000004: 788 default: 789 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 790 break; 791 } 792 793 r = 0; 794 795 out: 796 put_cpu(); 797 798 return r; 799 } 800 801 static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func, 802 unsigned int type) 803 { 804 if (type == KVM_GET_EMULATED_CPUID) 805 return __do_cpuid_func_emulated(array, func); 806 807 return __do_cpuid_func(array, func); 808 } 809 810 #define CENTAUR_CPUID_SIGNATURE 0xC0000000 811 812 static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func, 813 unsigned int type) 814 { 815 u32 limit; 816 int r; 817 818 if (func == CENTAUR_CPUID_SIGNATURE && 819 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR) 820 return 0; 821 822 r = do_cpuid_func(array, func, type); 823 if (r) 824 return r; 825 826 limit = array->entries[array->nent - 1].eax; 827 for (func = func + 1; func <= limit; ++func) { 828 r = do_cpuid_func(array, func, type); 829 if (r) 830 break; 831 } 832 833 return r; 834 } 835 836 static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries, 837 __u32 num_entries, unsigned int ioctl_type) 838 { 839 int i; 840 __u32 pad[3]; 841 842 if (ioctl_type != KVM_GET_EMULATED_CPUID) 843 return false; 844 845 /* 846 * We want to make sure that ->padding is being passed clean from 847 * userspace in case we want to use it for something in the future. 848 * 849 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we 850 * have to give ourselves satisfied only with the emulated side. /me 851 * sheds a tear. 852 */ 853 for (i = 0; i < num_entries; i++) { 854 if (copy_from_user(pad, entries[i].padding, sizeof(pad))) 855 return true; 856 857 if (pad[0] || pad[1] || pad[2]) 858 return true; 859 } 860 return false; 861 } 862 863 int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid, 864 struct kvm_cpuid_entry2 __user *entries, 865 unsigned int type) 866 { 867 static const u32 funcs[] = { 868 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE, 869 }; 870 871 struct kvm_cpuid_array array = { 872 .nent = 0, 873 .maxnent = cpuid->nent, 874 }; 875 int r, i; 876 877 if (cpuid->nent < 1) 878 return -E2BIG; 879 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 880 cpuid->nent = KVM_MAX_CPUID_ENTRIES; 881 882 if (sanity_check_entries(entries, cpuid->nent, type)) 883 return -EINVAL; 884 885 array.entries = vzalloc(array_size(sizeof(struct kvm_cpuid_entry2), 886 cpuid->nent)); 887 if (!array.entries) 888 return -ENOMEM; 889 890 for (i = 0; i < ARRAY_SIZE(funcs); i++) { 891 r = get_cpuid_func(&array, funcs[i], type); 892 if (r) 893 goto out_free; 894 } 895 cpuid->nent = array.nent; 896 897 if (copy_to_user(entries, array.entries, 898 array.nent * sizeof(struct kvm_cpuid_entry2))) 899 r = -EFAULT; 900 901 out_free: 902 vfree(array.entries); 903 return r; 904 } 905 906 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, 907 u32 function, u32 index) 908 { 909 struct kvm_cpuid_entry2 *e; 910 int i; 911 912 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { 913 e = &vcpu->arch.cpuid_entries[i]; 914 915 if (e->function == function && (e->index == index || 916 !(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX))) 917 return e; 918 } 919 return NULL; 920 } 921 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); 922 923 /* 924 * Intel CPUID semantics treats any query for an out-of-range leaf as if the 925 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics 926 * returns all zeroes for any undefined leaf, whether or not the leaf is in 927 * range. Centaur/VIA follows Intel semantics. 928 * 929 * A leaf is considered out-of-range if its function is higher than the maximum 930 * supported leaf of its associated class or if its associated class does not 931 * exist. 932 * 933 * There are three primary classes to be considered, with their respective 934 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary 935 * class exists if a guest CPUID entry for its <base> leaf exists. For a given 936 * class, CPUID.<base>.EAX contains the max supported leaf for the class. 937 * 938 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff 939 * - Hypervisor: 0x40000000 - 0x4fffffff 940 * - Extended: 0x80000000 - 0xbfffffff 941 * - Centaur: 0xc0000000 - 0xcfffffff 942 * 943 * The Hypervisor class is further subdivided into sub-classes that each act as 944 * their own indepdent class associated with a 0x100 byte range. E.g. if Qemu 945 * is advertising support for both HyperV and KVM, the resulting Hypervisor 946 * CPUID sub-classes are: 947 * 948 * - HyperV: 0x40000000 - 0x400000ff 949 * - KVM: 0x40000100 - 0x400001ff 950 */ 951 static struct kvm_cpuid_entry2 * 952 get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index) 953 { 954 struct kvm_cpuid_entry2 *basic, *class; 955 u32 function = *fn_ptr; 956 957 basic = kvm_find_cpuid_entry(vcpu, 0, 0); 958 if (!basic) 959 return NULL; 960 961 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) || 962 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx)) 963 return NULL; 964 965 if (function >= 0x40000000 && function <= 0x4fffffff) 966 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00, 0); 967 else if (function >= 0xc0000000) 968 class = kvm_find_cpuid_entry(vcpu, 0xc0000000, 0); 969 else 970 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0); 971 972 if (class && function <= class->eax) 973 return NULL; 974 975 /* 976 * Leaf specific adjustments are also applied when redirecting to the 977 * max basic entry, e.g. if the max basic leaf is 0xb but there is no 978 * entry for CPUID.0xb.index (see below), then the output value for EDX 979 * needs to be pulled from CPUID.0xb.1. 980 */ 981 *fn_ptr = basic->eax; 982 983 /* 984 * The class does not exist or the requested function is out of range; 985 * the effective CPUID entry is the max basic leaf. Note, the index of 986 * the original requested leaf is observed! 987 */ 988 return kvm_find_cpuid_entry(vcpu, basic->eax, index); 989 } 990 991 bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx, 992 u32 *ecx, u32 *edx, bool exact_only) 993 { 994 u32 orig_function = *eax, function = *eax, index = *ecx; 995 struct kvm_cpuid_entry2 *entry; 996 bool exact, used_max_basic = false; 997 998 entry = kvm_find_cpuid_entry(vcpu, function, index); 999 exact = !!entry; 1000 1001 if (!entry && !exact_only) { 1002 entry = get_out_of_range_cpuid_entry(vcpu, &function, index); 1003 used_max_basic = !!entry; 1004 } 1005 1006 if (entry) { 1007 *eax = entry->eax; 1008 *ebx = entry->ebx; 1009 *ecx = entry->ecx; 1010 *edx = entry->edx; 1011 if (function == 7 && index == 0) { 1012 u64 data; 1013 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) && 1014 (data & TSX_CTRL_CPUID_CLEAR)) 1015 *ebx &= ~(F(RTM) | F(HLE)); 1016 } 1017 } else { 1018 *eax = *ebx = *ecx = *edx = 0; 1019 /* 1020 * When leaf 0BH or 1FH is defined, CL is pass-through 1021 * and EDX is always the x2APIC ID, even for undefined 1022 * subleaves. Index 1 will exist iff the leaf is 1023 * implemented, so we pass through CL iff leaf 1 1024 * exists. EDX can be copied from any existing index. 1025 */ 1026 if (function == 0xb || function == 0x1f) { 1027 entry = kvm_find_cpuid_entry(vcpu, function, 1); 1028 if (entry) { 1029 *ecx = index & 0xff; 1030 *edx = entry->edx; 1031 } 1032 } 1033 } 1034 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact, 1035 used_max_basic); 1036 return exact; 1037 } 1038 EXPORT_SYMBOL_GPL(kvm_cpuid); 1039 1040 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu) 1041 { 1042 u32 eax, ebx, ecx, edx; 1043 1044 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0)) 1045 return 1; 1046 1047 eax = kvm_rax_read(vcpu); 1048 ecx = kvm_rcx_read(vcpu); 1049 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false); 1050 kvm_rax_write(vcpu, eax); 1051 kvm_rbx_write(vcpu, ebx); 1052 kvm_rcx_write(vcpu, ecx); 1053 kvm_rdx_write(vcpu, edx); 1054 return kvm_skip_emulated_instruction(vcpu); 1055 } 1056 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); 1057