1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * cpuid support routines 5 * 6 * derived from arch/x86/kvm/x86.c 7 * 8 * Copyright 2011 Red Hat, Inc. and/or its affiliates. 9 * Copyright IBM Corporation, 2008 10 */ 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13 #include <linux/kvm_host.h> 14 #include <linux/export.h> 15 #include <linux/vmalloc.h> 16 #include <linux/uaccess.h> 17 #include <linux/sched/stat.h> 18 19 #include <asm/processor.h> 20 #include <asm/user.h> 21 #include <asm/fpu/xstate.h> 22 #include <asm/sgx.h> 23 #include <asm/cpuid.h> 24 #include "cpuid.h" 25 #include "lapic.h" 26 #include "mmu.h" 27 #include "trace.h" 28 #include "pmu.h" 29 #include "xen.h" 30 31 /* 32 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be 33 * aligned to sizeof(unsigned long) because it's not accessed via bitops. 34 */ 35 u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly; 36 EXPORT_SYMBOL_GPL(kvm_cpu_caps); 37 38 u32 xstate_required_size(u64 xstate_bv, bool compacted) 39 { 40 int feature_bit = 0; 41 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 42 43 xstate_bv &= XFEATURE_MASK_EXTEND; 44 while (xstate_bv) { 45 if (xstate_bv & 0x1) { 46 u32 eax, ebx, ecx, edx, offset; 47 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx); 48 /* ECX[1]: 64B alignment in compacted form */ 49 if (compacted) 50 offset = (ecx & 0x2) ? ALIGN(ret, 64) : ret; 51 else 52 offset = ebx; 53 ret = max(ret, offset + eax); 54 } 55 56 xstate_bv >>= 1; 57 feature_bit++; 58 } 59 60 return ret; 61 } 62 63 #define F feature_bit 64 65 /* Scattered Flag - For features that are scattered by cpufeatures.h. */ 66 #define SF(name) \ 67 ({ \ 68 BUILD_BUG_ON(X86_FEATURE_##name >= MAX_CPU_FEATURES); \ 69 (boot_cpu_has(X86_FEATURE_##name) ? F(name) : 0); \ 70 }) 71 72 /* 73 * Magic value used by KVM when querying userspace-provided CPUID entries and 74 * doesn't care about the CPIUD index because the index of the function in 75 * question is not significant. Note, this magic value must have at least one 76 * bit set in bits[63:32] and must be consumed as a u64 by cpuid_entry2_find() 77 * to avoid false positives when processing guest CPUID input. 78 */ 79 #define KVM_CPUID_INDEX_NOT_SIGNIFICANT -1ull 80 81 static inline struct kvm_cpuid_entry2 *cpuid_entry2_find( 82 struct kvm_cpuid_entry2 *entries, int nent, u32 function, u64 index) 83 { 84 struct kvm_cpuid_entry2 *e; 85 int i; 86 87 for (i = 0; i < nent; i++) { 88 e = &entries[i]; 89 90 if (e->function != function) 91 continue; 92 93 /* 94 * If the index isn't significant, use the first entry with a 95 * matching function. It's userspace's responsibilty to not 96 * provide "duplicate" entries in all cases. 97 */ 98 if (!(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) || e->index == index) 99 return e; 100 101 102 /* 103 * Similarly, use the first matching entry if KVM is doing a 104 * lookup (as opposed to emulating CPUID) for a function that's 105 * architecturally defined as not having a significant index. 106 */ 107 if (index == KVM_CPUID_INDEX_NOT_SIGNIFICANT) { 108 /* 109 * Direct lookups from KVM should not diverge from what 110 * KVM defines internally (the architectural behavior). 111 */ 112 WARN_ON_ONCE(cpuid_function_is_indexed(function)); 113 return e; 114 } 115 } 116 117 return NULL; 118 } 119 120 static int kvm_check_cpuid(struct kvm_vcpu *vcpu, 121 struct kvm_cpuid_entry2 *entries, 122 int nent) 123 { 124 struct kvm_cpuid_entry2 *best; 125 u64 xfeatures; 126 127 /* 128 * The existing code assumes virtual address is 48-bit or 57-bit in the 129 * canonical address checks; exit if it is ever changed. 130 */ 131 best = cpuid_entry2_find(entries, nent, 0x80000008, 132 KVM_CPUID_INDEX_NOT_SIGNIFICANT); 133 if (best) { 134 int vaddr_bits = (best->eax & 0xff00) >> 8; 135 136 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) 137 return -EINVAL; 138 } 139 140 /* 141 * Exposing dynamic xfeatures to the guest requires additional 142 * enabling in the FPU, e.g. to expand the guest XSAVE state size. 143 */ 144 best = cpuid_entry2_find(entries, nent, 0xd, 0); 145 if (!best) 146 return 0; 147 148 xfeatures = best->eax | ((u64)best->edx << 32); 149 xfeatures &= XFEATURE_MASK_USER_DYNAMIC; 150 if (!xfeatures) 151 return 0; 152 153 return fpu_enable_guest_xfd_features(&vcpu->arch.guest_fpu, xfeatures); 154 } 155 156 /* Check whether the supplied CPUID data is equal to what is already set for the vCPU. */ 157 static int kvm_cpuid_check_equal(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2, 158 int nent) 159 { 160 struct kvm_cpuid_entry2 *orig; 161 int i; 162 163 if (nent != vcpu->arch.cpuid_nent) 164 return -EINVAL; 165 166 for (i = 0; i < nent; i++) { 167 orig = &vcpu->arch.cpuid_entries[i]; 168 if (e2[i].function != orig->function || 169 e2[i].index != orig->index || 170 e2[i].flags != orig->flags || 171 e2[i].eax != orig->eax || e2[i].ebx != orig->ebx || 172 e2[i].ecx != orig->ecx || e2[i].edx != orig->edx) 173 return -EINVAL; 174 } 175 176 return 0; 177 } 178 179 static struct kvm_hypervisor_cpuid kvm_get_hypervisor_cpuid(struct kvm_vcpu *vcpu, 180 const char *sig) 181 { 182 struct kvm_hypervisor_cpuid cpuid = {}; 183 struct kvm_cpuid_entry2 *entry; 184 u32 base; 185 186 for_each_possible_hypervisor_cpuid_base(base) { 187 entry = kvm_find_cpuid_entry(vcpu, base); 188 189 if (entry) { 190 u32 signature[3]; 191 192 signature[0] = entry->ebx; 193 signature[1] = entry->ecx; 194 signature[2] = entry->edx; 195 196 if (!memcmp(signature, sig, sizeof(signature))) { 197 cpuid.base = base; 198 cpuid.limit = entry->eax; 199 break; 200 } 201 } 202 } 203 204 return cpuid; 205 } 206 207 static struct kvm_cpuid_entry2 *__kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu, 208 struct kvm_cpuid_entry2 *entries, int nent) 209 { 210 u32 base = vcpu->arch.kvm_cpuid.base; 211 212 if (!base) 213 return NULL; 214 215 return cpuid_entry2_find(entries, nent, base | KVM_CPUID_FEATURES, 216 KVM_CPUID_INDEX_NOT_SIGNIFICANT); 217 } 218 219 static struct kvm_cpuid_entry2 *kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu) 220 { 221 return __kvm_find_kvm_cpuid_features(vcpu, vcpu->arch.cpuid_entries, 222 vcpu->arch.cpuid_nent); 223 } 224 225 void kvm_update_pv_runtime(struct kvm_vcpu *vcpu) 226 { 227 struct kvm_cpuid_entry2 *best = kvm_find_kvm_cpuid_features(vcpu); 228 229 /* 230 * save the feature bitmap to avoid cpuid lookup for every PV 231 * operation 232 */ 233 if (best) 234 vcpu->arch.pv_cpuid.features = best->eax; 235 } 236 237 /* 238 * Calculate guest's supported XCR0 taking into account guest CPUID data and 239 * KVM's supported XCR0 (comprised of host's XCR0 and KVM_SUPPORTED_XCR0). 240 */ 241 static u64 cpuid_get_supported_xcr0(struct kvm_cpuid_entry2 *entries, int nent) 242 { 243 struct kvm_cpuid_entry2 *best; 244 245 best = cpuid_entry2_find(entries, nent, 0xd, 0); 246 if (!best) 247 return 0; 248 249 return (best->eax | ((u64)best->edx << 32)) & kvm_caps.supported_xcr0; 250 } 251 252 static void __kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *entries, 253 int nent) 254 { 255 struct kvm_cpuid_entry2 *best; 256 u64 guest_supported_xcr0 = cpuid_get_supported_xcr0(entries, nent); 257 258 best = cpuid_entry2_find(entries, nent, 1, KVM_CPUID_INDEX_NOT_SIGNIFICANT); 259 if (best) { 260 /* Update OSXSAVE bit */ 261 if (boot_cpu_has(X86_FEATURE_XSAVE)) 262 cpuid_entry_change(best, X86_FEATURE_OSXSAVE, 263 kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)); 264 265 cpuid_entry_change(best, X86_FEATURE_APIC, 266 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE); 267 } 268 269 best = cpuid_entry2_find(entries, nent, 7, 0); 270 if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7) 271 cpuid_entry_change(best, X86_FEATURE_OSPKE, 272 kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE)); 273 274 best = cpuid_entry2_find(entries, nent, 0xD, 0); 275 if (best) 276 best->ebx = xstate_required_size(vcpu->arch.xcr0, false); 277 278 best = cpuid_entry2_find(entries, nent, 0xD, 1); 279 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) || 280 cpuid_entry_has(best, X86_FEATURE_XSAVEC))) 281 best->ebx = xstate_required_size(vcpu->arch.xcr0, true); 282 283 best = __kvm_find_kvm_cpuid_features(vcpu, entries, nent); 284 if (kvm_hlt_in_guest(vcpu->kvm) && best && 285 (best->eax & (1 << KVM_FEATURE_PV_UNHALT))) 286 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT); 287 288 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) { 289 best = cpuid_entry2_find(entries, nent, 0x1, KVM_CPUID_INDEX_NOT_SIGNIFICANT); 290 if (best) 291 cpuid_entry_change(best, X86_FEATURE_MWAIT, 292 vcpu->arch.ia32_misc_enable_msr & 293 MSR_IA32_MISC_ENABLE_MWAIT); 294 } 295 296 /* 297 * Bits 127:0 of the allowed SECS.ATTRIBUTES (CPUID.0x12.0x1) enumerate 298 * the supported XSAVE Feature Request Mask (XFRM), i.e. the enclave's 299 * requested XCR0 value. The enclave's XFRM must be a subset of XCRO 300 * at the time of EENTER, thus adjust the allowed XFRM by the guest's 301 * supported XCR0. Similar to XCR0 handling, FP and SSE are forced to 302 * '1' even on CPUs that don't support XSAVE. 303 */ 304 best = cpuid_entry2_find(entries, nent, 0x12, 0x1); 305 if (best) { 306 best->ecx &= guest_supported_xcr0 & 0xffffffff; 307 best->edx &= guest_supported_xcr0 >> 32; 308 best->ecx |= XFEATURE_MASK_FPSSE; 309 } 310 } 311 312 void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu) 313 { 314 __kvm_update_cpuid_runtime(vcpu, vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent); 315 } 316 EXPORT_SYMBOL_GPL(kvm_update_cpuid_runtime); 317 318 static bool kvm_cpuid_has_hyperv(struct kvm_cpuid_entry2 *entries, int nent) 319 { 320 struct kvm_cpuid_entry2 *entry; 321 322 entry = cpuid_entry2_find(entries, nent, HYPERV_CPUID_INTERFACE, 323 KVM_CPUID_INDEX_NOT_SIGNIFICANT); 324 return entry && entry->eax == HYPERV_CPUID_SIGNATURE_EAX; 325 } 326 327 static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) 328 { 329 struct kvm_lapic *apic = vcpu->arch.apic; 330 struct kvm_cpuid_entry2 *best; 331 332 best = kvm_find_cpuid_entry(vcpu, 1); 333 if (best && apic) { 334 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER)) 335 apic->lapic_timer.timer_mode_mask = 3 << 17; 336 else 337 apic->lapic_timer.timer_mode_mask = 1 << 17; 338 339 kvm_apic_set_version(vcpu); 340 } 341 342 vcpu->arch.guest_supported_xcr0 = 343 cpuid_get_supported_xcr0(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent); 344 345 /* 346 * FP+SSE can always be saved/restored via KVM_{G,S}ET_XSAVE, even if 347 * XSAVE/XCRO are not exposed to the guest, and even if XSAVE isn't 348 * supported by the host. 349 */ 350 vcpu->arch.guest_fpu.fpstate->user_xfeatures = vcpu->arch.guest_supported_xcr0 | 351 XFEATURE_MASK_FPSSE; 352 353 kvm_update_pv_runtime(vcpu); 354 355 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 356 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 357 358 kvm_pmu_refresh(vcpu); 359 vcpu->arch.cr4_guest_rsvd_bits = 360 __cr4_reserved_bits(guest_cpuid_has, vcpu); 361 362 kvm_hv_set_cpuid(vcpu, kvm_cpuid_has_hyperv(vcpu->arch.cpuid_entries, 363 vcpu->arch.cpuid_nent)); 364 365 /* Invoke the vendor callback only after the above state is updated. */ 366 static_call(kvm_x86_vcpu_after_set_cpuid)(vcpu); 367 368 /* 369 * Except for the MMU, which needs to do its thing any vendor specific 370 * adjustments to the reserved GPA bits. 371 */ 372 kvm_mmu_after_set_cpuid(vcpu); 373 } 374 375 int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu) 376 { 377 struct kvm_cpuid_entry2 *best; 378 379 best = kvm_find_cpuid_entry(vcpu, 0x80000000); 380 if (!best || best->eax < 0x80000008) 381 goto not_found; 382 best = kvm_find_cpuid_entry(vcpu, 0x80000008); 383 if (best) 384 return best->eax & 0xff; 385 not_found: 386 return 36; 387 } 388 389 /* 390 * This "raw" version returns the reserved GPA bits without any adjustments for 391 * encryption technologies that usurp bits. The raw mask should be used if and 392 * only if hardware does _not_ strip the usurped bits, e.g. in virtual MTRRs. 393 */ 394 u64 kvm_vcpu_reserved_gpa_bits_raw(struct kvm_vcpu *vcpu) 395 { 396 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63); 397 } 398 399 static int kvm_set_cpuid(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2, 400 int nent) 401 { 402 int r; 403 404 __kvm_update_cpuid_runtime(vcpu, e2, nent); 405 406 /* 407 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as 408 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't 409 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page 410 * faults due to reusing SPs/SPTEs. In practice no sane VMM mucks with 411 * the core vCPU model on the fly. It would've been better to forbid any 412 * KVM_SET_CPUID{,2} calls after KVM_RUN altogether but unfortunately 413 * some VMMs (e.g. QEMU) reuse vCPU fds for CPU hotplug/unplug and do 414 * KVM_SET_CPUID{,2} again. To support this legacy behavior, check 415 * whether the supplied CPUID data is equal to what's already set. 416 */ 417 if (kvm_vcpu_has_run(vcpu)) { 418 r = kvm_cpuid_check_equal(vcpu, e2, nent); 419 if (r) 420 return r; 421 422 kvfree(e2); 423 return 0; 424 } 425 426 if (kvm_cpuid_has_hyperv(e2, nent)) { 427 r = kvm_hv_vcpu_init(vcpu); 428 if (r) 429 return r; 430 } 431 432 r = kvm_check_cpuid(vcpu, e2, nent); 433 if (r) 434 return r; 435 436 kvfree(vcpu->arch.cpuid_entries); 437 vcpu->arch.cpuid_entries = e2; 438 vcpu->arch.cpuid_nent = nent; 439 440 vcpu->arch.kvm_cpuid = kvm_get_hypervisor_cpuid(vcpu, KVM_SIGNATURE); 441 vcpu->arch.xen.cpuid = kvm_get_hypervisor_cpuid(vcpu, XEN_SIGNATURE); 442 kvm_vcpu_after_set_cpuid(vcpu); 443 444 return 0; 445 } 446 447 /* when an old userspace process fills a new kernel module */ 448 int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, 449 struct kvm_cpuid *cpuid, 450 struct kvm_cpuid_entry __user *entries) 451 { 452 int r, i; 453 struct kvm_cpuid_entry *e = NULL; 454 struct kvm_cpuid_entry2 *e2 = NULL; 455 456 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 457 return -E2BIG; 458 459 if (cpuid->nent) { 460 e = vmemdup_user(entries, array_size(sizeof(*e), cpuid->nent)); 461 if (IS_ERR(e)) 462 return PTR_ERR(e); 463 464 e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT); 465 if (!e2) { 466 r = -ENOMEM; 467 goto out_free_cpuid; 468 } 469 } 470 for (i = 0; i < cpuid->nent; i++) { 471 e2[i].function = e[i].function; 472 e2[i].eax = e[i].eax; 473 e2[i].ebx = e[i].ebx; 474 e2[i].ecx = e[i].ecx; 475 e2[i].edx = e[i].edx; 476 e2[i].index = 0; 477 e2[i].flags = 0; 478 e2[i].padding[0] = 0; 479 e2[i].padding[1] = 0; 480 e2[i].padding[2] = 0; 481 } 482 483 r = kvm_set_cpuid(vcpu, e2, cpuid->nent); 484 if (r) 485 kvfree(e2); 486 487 out_free_cpuid: 488 kvfree(e); 489 490 return r; 491 } 492 493 int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, 494 struct kvm_cpuid2 *cpuid, 495 struct kvm_cpuid_entry2 __user *entries) 496 { 497 struct kvm_cpuid_entry2 *e2 = NULL; 498 int r; 499 500 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 501 return -E2BIG; 502 503 if (cpuid->nent) { 504 e2 = vmemdup_user(entries, array_size(sizeof(*e2), cpuid->nent)); 505 if (IS_ERR(e2)) 506 return PTR_ERR(e2); 507 } 508 509 r = kvm_set_cpuid(vcpu, e2, cpuid->nent); 510 if (r) 511 kvfree(e2); 512 513 return r; 514 } 515 516 int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, 517 struct kvm_cpuid2 *cpuid, 518 struct kvm_cpuid_entry2 __user *entries) 519 { 520 int r; 521 522 r = -E2BIG; 523 if (cpuid->nent < vcpu->arch.cpuid_nent) 524 goto out; 525 r = -EFAULT; 526 if (copy_to_user(entries, vcpu->arch.cpuid_entries, 527 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) 528 goto out; 529 return 0; 530 531 out: 532 cpuid->nent = vcpu->arch.cpuid_nent; 533 return r; 534 } 535 536 /* Mask kvm_cpu_caps for @leaf with the raw CPUID capabilities of this CPU. */ 537 static __always_inline void __kvm_cpu_cap_mask(unsigned int leaf) 538 { 539 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32); 540 struct kvm_cpuid_entry2 entry; 541 542 reverse_cpuid_check(leaf); 543 544 cpuid_count(cpuid.function, cpuid.index, 545 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx); 546 547 kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg); 548 } 549 550 static __always_inline 551 void kvm_cpu_cap_init_kvm_defined(enum kvm_only_cpuid_leafs leaf, u32 mask) 552 { 553 /* Use kvm_cpu_cap_mask for leafs that aren't KVM-only. */ 554 BUILD_BUG_ON(leaf < NCAPINTS); 555 556 kvm_cpu_caps[leaf] = mask; 557 558 __kvm_cpu_cap_mask(leaf); 559 } 560 561 static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask) 562 { 563 /* Use kvm_cpu_cap_init_kvm_defined for KVM-only leafs. */ 564 BUILD_BUG_ON(leaf >= NCAPINTS); 565 566 kvm_cpu_caps[leaf] &= mask; 567 568 __kvm_cpu_cap_mask(leaf); 569 } 570 571 void kvm_set_cpu_caps(void) 572 { 573 #ifdef CONFIG_X86_64 574 unsigned int f_gbpages = F(GBPAGES); 575 unsigned int f_lm = F(LM); 576 unsigned int f_xfd = F(XFD); 577 #else 578 unsigned int f_gbpages = 0; 579 unsigned int f_lm = 0; 580 unsigned int f_xfd = 0; 581 #endif 582 memset(kvm_cpu_caps, 0, sizeof(kvm_cpu_caps)); 583 584 BUILD_BUG_ON(sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)) > 585 sizeof(boot_cpu_data.x86_capability)); 586 587 memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability, 588 sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps))); 589 590 kvm_cpu_cap_mask(CPUID_1_ECX, 591 /* 592 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not* 593 * advertised to guests via CPUID! 594 */ 595 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ | 596 0 /* DS-CPL, VMX, SMX, EST */ | 597 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | 598 F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) | 599 F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) | 600 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | 601 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) | 602 F(F16C) | F(RDRAND) 603 ); 604 /* KVM emulates x2apic in software irrespective of host support. */ 605 kvm_cpu_cap_set(X86_FEATURE_X2APIC); 606 607 kvm_cpu_cap_mask(CPUID_1_EDX, 608 F(FPU) | F(VME) | F(DE) | F(PSE) | 609 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 610 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | 611 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 612 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) | 613 0 /* Reserved, DS, ACPI */ | F(MMX) | 614 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | 615 0 /* HTT, TM, Reserved, PBE */ 616 ); 617 618 kvm_cpu_cap_mask(CPUID_7_0_EBX, 619 F(FSGSBASE) | F(SGX) | F(BMI1) | F(HLE) | F(AVX2) | 620 F(FDP_EXCPTN_ONLY) | F(SMEP) | F(BMI2) | F(ERMS) | F(INVPCID) | 621 F(RTM) | F(ZERO_FCS_FDS) | 0 /*MPX*/ | F(AVX512F) | 622 F(AVX512DQ) | F(RDSEED) | F(ADX) | F(SMAP) | F(AVX512IFMA) | 623 F(CLFLUSHOPT) | F(CLWB) | 0 /*INTEL_PT*/ | F(AVX512PF) | 624 F(AVX512ER) | F(AVX512CD) | F(SHA_NI) | F(AVX512BW) | 625 F(AVX512VL)); 626 627 kvm_cpu_cap_mask(CPUID_7_ECX, 628 F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) | 629 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) | 630 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) | 631 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ | 632 F(SGX_LC) | F(BUS_LOCK_DETECT) 633 ); 634 /* Set LA57 based on hardware capability. */ 635 if (cpuid_ecx(7) & F(LA57)) 636 kvm_cpu_cap_set(X86_FEATURE_LA57); 637 638 /* 639 * PKU not yet implemented for shadow paging and requires OSPKE 640 * to be set on the host. Clear it if that is not the case 641 */ 642 if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE)) 643 kvm_cpu_cap_clear(X86_FEATURE_PKU); 644 645 kvm_cpu_cap_mask(CPUID_7_EDX, 646 F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | 647 F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | 648 F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | 649 F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) | 650 F(AMX_TILE) | F(AMX_INT8) | F(AMX_BF16) | F(FLUSH_L1D) 651 ); 652 653 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ 654 kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST); 655 kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES); 656 657 if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS)) 658 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL); 659 if (boot_cpu_has(X86_FEATURE_STIBP)) 660 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); 661 if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) 662 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); 663 664 kvm_cpu_cap_mask(CPUID_7_1_EAX, 665 F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) | 666 F(FZRM) | F(FSRS) | F(FSRC) | 667 F(AMX_FP16) | F(AVX_IFMA) 668 ); 669 670 kvm_cpu_cap_init_kvm_defined(CPUID_7_1_EDX, 671 F(AVX_VNNI_INT8) | F(AVX_NE_CONVERT) | F(PREFETCHITI) 672 ); 673 674 kvm_cpu_cap_mask(CPUID_D_1_EAX, 675 F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | f_xfd 676 ); 677 678 kvm_cpu_cap_init_kvm_defined(CPUID_12_EAX, 679 SF(SGX1) | SF(SGX2) | SF(SGX_EDECCSSA) 680 ); 681 682 kvm_cpu_cap_mask(CPUID_8000_0001_ECX, 683 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ | 684 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | 685 F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) | 686 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) | 687 F(TOPOEXT) | 0 /* PERFCTR_CORE */ 688 ); 689 690 kvm_cpu_cap_mask(CPUID_8000_0001_EDX, 691 F(FPU) | F(VME) | F(DE) | F(PSE) | 692 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 693 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | 694 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 695 F(PAT) | F(PSE36) | 0 /* Reserved */ | 696 F(NX) | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | 697 F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) | 698 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW) 699 ); 700 701 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64)) 702 kvm_cpu_cap_set(X86_FEATURE_GBPAGES); 703 704 kvm_cpu_cap_init_kvm_defined(CPUID_8000_0007_EDX, 705 SF(CONSTANT_TSC) 706 ); 707 708 kvm_cpu_cap_mask(CPUID_8000_0008_EBX, 709 F(CLZERO) | F(XSAVEERPTR) | 710 F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | 711 F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) | 712 F(AMD_PSFD) 713 ); 714 715 /* 716 * AMD has separate bits for each SPEC_CTRL bit. 717 * arch/x86/kernel/cpu/bugs.c is kind enough to 718 * record that in cpufeatures so use them. 719 */ 720 if (boot_cpu_has(X86_FEATURE_IBPB)) 721 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB); 722 if (boot_cpu_has(X86_FEATURE_IBRS)) 723 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS); 724 if (boot_cpu_has(X86_FEATURE_STIBP)) 725 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP); 726 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) 727 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD); 728 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 729 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO); 730 /* 731 * The preference is to use SPEC CTRL MSR instead of the 732 * VIRT_SPEC MSR. 733 */ 734 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) && 735 !boot_cpu_has(X86_FEATURE_AMD_SSBD)) 736 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); 737 738 /* 739 * Hide all SVM features by default, SVM will set the cap bits for 740 * features it emulates and/or exposes for L1. 741 */ 742 kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0); 743 744 kvm_cpu_cap_mask(CPUID_8000_001F_EAX, 745 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) | 746 F(SME_COHERENT)); 747 748 kvm_cpu_cap_mask(CPUID_8000_0021_EAX, 749 F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ | 750 F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | 0 /* PrefetchCtlMsr */ 751 ); 752 753 /* 754 * Synthesize "LFENCE is serializing" into the AMD-defined entry in 755 * KVM's supported CPUID if the feature is reported as supported by the 756 * kernel. LFENCE_RDTSC was a Linux-defined synthetic feature long 757 * before AMD joined the bandwagon, e.g. LFENCE is serializing on most 758 * CPUs that support SSE2. On CPUs that don't support AMD's leaf, 759 * kvm_cpu_cap_mask() will unfortunately drop the flag due to ANDing 760 * the mask with the raw host CPUID, and reporting support in AMD's 761 * leaf can make it easier for userspace to detect the feature. 762 */ 763 if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC)) 764 kvm_cpu_cap_set(X86_FEATURE_LFENCE_RDTSC); 765 if (!static_cpu_has_bug(X86_BUG_NULL_SEG)) 766 kvm_cpu_cap_set(X86_FEATURE_NULL_SEL_CLR_BASE); 767 kvm_cpu_cap_set(X86_FEATURE_NO_SMM_CTL_MSR); 768 769 kvm_cpu_cap_mask(CPUID_C000_0001_EDX, 770 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | 771 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | 772 F(PMM) | F(PMM_EN) 773 ); 774 775 /* 776 * Hide RDTSCP and RDPID if either feature is reported as supported but 777 * probing MSR_TSC_AUX failed. This is purely a sanity check and 778 * should never happen, but the guest will likely crash if RDTSCP or 779 * RDPID is misreported, and KVM has botched MSR_TSC_AUX emulation in 780 * the past. For example, the sanity check may fire if this instance of 781 * KVM is running as L1 on top of an older, broken KVM. 782 */ 783 if (WARN_ON((kvm_cpu_cap_has(X86_FEATURE_RDTSCP) || 784 kvm_cpu_cap_has(X86_FEATURE_RDPID)) && 785 !kvm_is_supported_user_return_msr(MSR_TSC_AUX))) { 786 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP); 787 kvm_cpu_cap_clear(X86_FEATURE_RDPID); 788 } 789 } 790 EXPORT_SYMBOL_GPL(kvm_set_cpu_caps); 791 792 struct kvm_cpuid_array { 793 struct kvm_cpuid_entry2 *entries; 794 int maxnent; 795 int nent; 796 }; 797 798 static struct kvm_cpuid_entry2 *get_next_cpuid(struct kvm_cpuid_array *array) 799 { 800 if (array->nent >= array->maxnent) 801 return NULL; 802 803 return &array->entries[array->nent++]; 804 } 805 806 static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array, 807 u32 function, u32 index) 808 { 809 struct kvm_cpuid_entry2 *entry = get_next_cpuid(array); 810 811 if (!entry) 812 return NULL; 813 814 memset(entry, 0, sizeof(*entry)); 815 entry->function = function; 816 entry->index = index; 817 switch (function & 0xC0000000) { 818 case 0x40000000: 819 /* Hypervisor leaves are always synthesized by __do_cpuid_func. */ 820 return entry; 821 822 case 0x80000000: 823 /* 824 * 0x80000021 is sometimes synthesized by __do_cpuid_func, which 825 * would result in out-of-bounds calls to do_host_cpuid. 826 */ 827 { 828 static int max_cpuid_80000000; 829 if (!READ_ONCE(max_cpuid_80000000)) 830 WRITE_ONCE(max_cpuid_80000000, cpuid_eax(0x80000000)); 831 if (function > READ_ONCE(max_cpuid_80000000)) 832 return entry; 833 } 834 break; 835 836 default: 837 break; 838 } 839 840 cpuid_count(entry->function, entry->index, 841 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); 842 843 if (cpuid_function_is_indexed(function)) 844 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 845 846 return entry; 847 } 848 849 static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func) 850 { 851 struct kvm_cpuid_entry2 *entry; 852 853 if (array->nent >= array->maxnent) 854 return -E2BIG; 855 856 entry = &array->entries[array->nent]; 857 entry->function = func; 858 entry->index = 0; 859 entry->flags = 0; 860 861 switch (func) { 862 case 0: 863 entry->eax = 7; 864 ++array->nent; 865 break; 866 case 1: 867 entry->ecx = F(MOVBE); 868 ++array->nent; 869 break; 870 case 7: 871 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 872 entry->eax = 0; 873 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) 874 entry->ecx = F(RDPID); 875 ++array->nent; 876 break; 877 default: 878 break; 879 } 880 881 return 0; 882 } 883 884 static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) 885 { 886 struct kvm_cpuid_entry2 *entry; 887 int r, i, max_idx; 888 889 /* all calls to cpuid_count() should be made on the same cpu */ 890 get_cpu(); 891 892 r = -E2BIG; 893 894 entry = do_host_cpuid(array, function, 0); 895 if (!entry) 896 goto out; 897 898 switch (function) { 899 case 0: 900 /* Limited to the highest leaf implemented in KVM. */ 901 entry->eax = min(entry->eax, 0x1fU); 902 break; 903 case 1: 904 cpuid_entry_override(entry, CPUID_1_EDX); 905 cpuid_entry_override(entry, CPUID_1_ECX); 906 break; 907 case 2: 908 /* 909 * On ancient CPUs, function 2 entries are STATEFUL. That is, 910 * CPUID(function=2, index=0) may return different results each 911 * time, with the least-significant byte in EAX enumerating the 912 * number of times software should do CPUID(2, 0). 913 * 914 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less 915 * idiotic. Intel's SDM states that EAX & 0xff "will always 916 * return 01H. Software should ignore this value and not 917 * interpret it as an informational descriptor", while AMD's 918 * APM states that CPUID(2) is reserved. 919 * 920 * WARN if a frankenstein CPU that supports virtualization and 921 * a stateful CPUID.0x2 is encountered. 922 */ 923 WARN_ON_ONCE((entry->eax & 0xff) > 1); 924 break; 925 /* functions 4 and 0x8000001d have additional index. */ 926 case 4: 927 case 0x8000001d: 928 /* 929 * Read entries until the cache type in the previous entry is 930 * zero, i.e. indicates an invalid entry. 931 */ 932 for (i = 1; entry->eax & 0x1f; ++i) { 933 entry = do_host_cpuid(array, function, i); 934 if (!entry) 935 goto out; 936 } 937 break; 938 case 6: /* Thermal management */ 939 entry->eax = 0x4; /* allow ARAT */ 940 entry->ebx = 0; 941 entry->ecx = 0; 942 entry->edx = 0; 943 break; 944 /* function 7 has additional index. */ 945 case 7: 946 entry->eax = min(entry->eax, 1u); 947 cpuid_entry_override(entry, CPUID_7_0_EBX); 948 cpuid_entry_override(entry, CPUID_7_ECX); 949 cpuid_entry_override(entry, CPUID_7_EDX); 950 951 /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */ 952 if (entry->eax == 1) { 953 entry = do_host_cpuid(array, function, 1); 954 if (!entry) 955 goto out; 956 957 cpuid_entry_override(entry, CPUID_7_1_EAX); 958 cpuid_entry_override(entry, CPUID_7_1_EDX); 959 entry->ebx = 0; 960 entry->ecx = 0; 961 } 962 break; 963 case 0xa: { /* Architectural Performance Monitoring */ 964 union cpuid10_eax eax; 965 union cpuid10_edx edx; 966 967 if (!static_cpu_has(X86_FEATURE_ARCH_PERFMON)) { 968 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 969 break; 970 } 971 972 eax.split.version_id = kvm_pmu_cap.version; 973 eax.split.num_counters = kvm_pmu_cap.num_counters_gp; 974 eax.split.bit_width = kvm_pmu_cap.bit_width_gp; 975 eax.split.mask_length = kvm_pmu_cap.events_mask_len; 976 edx.split.num_counters_fixed = kvm_pmu_cap.num_counters_fixed; 977 edx.split.bit_width_fixed = kvm_pmu_cap.bit_width_fixed; 978 979 if (kvm_pmu_cap.version) 980 edx.split.anythread_deprecated = 1; 981 edx.split.reserved1 = 0; 982 edx.split.reserved2 = 0; 983 984 entry->eax = eax.full; 985 entry->ebx = kvm_pmu_cap.events_mask; 986 entry->ecx = 0; 987 entry->edx = edx.full; 988 break; 989 } 990 case 0x1f: 991 case 0xb: 992 /* 993 * No topology; a valid topology is indicated by the presence 994 * of subleaf 1. 995 */ 996 entry->eax = entry->ebx = entry->ecx = 0; 997 break; 998 case 0xd: { 999 u64 permitted_xcr0 = kvm_get_filtered_xcr0(); 1000 u64 permitted_xss = kvm_caps.supported_xss; 1001 1002 entry->eax &= permitted_xcr0; 1003 entry->ebx = xstate_required_size(permitted_xcr0, false); 1004 entry->ecx = entry->ebx; 1005 entry->edx &= permitted_xcr0 >> 32; 1006 if (!permitted_xcr0) 1007 break; 1008 1009 entry = do_host_cpuid(array, function, 1); 1010 if (!entry) 1011 goto out; 1012 1013 cpuid_entry_override(entry, CPUID_D_1_EAX); 1014 if (entry->eax & (F(XSAVES)|F(XSAVEC))) 1015 entry->ebx = xstate_required_size(permitted_xcr0 | permitted_xss, 1016 true); 1017 else { 1018 WARN_ON_ONCE(permitted_xss != 0); 1019 entry->ebx = 0; 1020 } 1021 entry->ecx &= permitted_xss; 1022 entry->edx &= permitted_xss >> 32; 1023 1024 for (i = 2; i < 64; ++i) { 1025 bool s_state; 1026 if (permitted_xcr0 & BIT_ULL(i)) 1027 s_state = false; 1028 else if (permitted_xss & BIT_ULL(i)) 1029 s_state = true; 1030 else 1031 continue; 1032 1033 entry = do_host_cpuid(array, function, i); 1034 if (!entry) 1035 goto out; 1036 1037 /* 1038 * The supported check above should have filtered out 1039 * invalid sub-leafs. Only valid sub-leafs should 1040 * reach this point, and they should have a non-zero 1041 * save state size. Furthermore, check whether the 1042 * processor agrees with permitted_xcr0/permitted_xss 1043 * on whether this is an XCR0- or IA32_XSS-managed area. 1044 */ 1045 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) { 1046 --array->nent; 1047 continue; 1048 } 1049 1050 if (!kvm_cpu_cap_has(X86_FEATURE_XFD)) 1051 entry->ecx &= ~BIT_ULL(2); 1052 entry->edx = 0; 1053 } 1054 break; 1055 } 1056 case 0x12: 1057 /* Intel SGX */ 1058 if (!kvm_cpu_cap_has(X86_FEATURE_SGX)) { 1059 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1060 break; 1061 } 1062 1063 /* 1064 * Index 0: Sub-features, MISCSELECT (a.k.a extended features) 1065 * and max enclave sizes. The SGX sub-features and MISCSELECT 1066 * are restricted by kernel and KVM capabilities (like most 1067 * feature flags), while enclave size is unrestricted. 1068 */ 1069 cpuid_entry_override(entry, CPUID_12_EAX); 1070 entry->ebx &= SGX_MISC_EXINFO; 1071 1072 entry = do_host_cpuid(array, function, 1); 1073 if (!entry) 1074 goto out; 1075 1076 /* 1077 * Index 1: SECS.ATTRIBUTES. ATTRIBUTES are restricted a la 1078 * feature flags. Advertise all supported flags, including 1079 * privileged attributes that require explicit opt-in from 1080 * userspace. ATTRIBUTES.XFRM is not adjusted as userspace is 1081 * expected to derive it from supported XCR0. 1082 */ 1083 entry->eax &= SGX_ATTR_PRIV_MASK | SGX_ATTR_UNPRIV_MASK; 1084 entry->ebx &= 0; 1085 break; 1086 /* Intel PT */ 1087 case 0x14: 1088 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) { 1089 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1090 break; 1091 } 1092 1093 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 1094 if (!do_host_cpuid(array, function, i)) 1095 goto out; 1096 } 1097 break; 1098 /* Intel AMX TILE */ 1099 case 0x1d: 1100 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { 1101 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1102 break; 1103 } 1104 1105 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 1106 if (!do_host_cpuid(array, function, i)) 1107 goto out; 1108 } 1109 break; 1110 case 0x1e: /* TMUL information */ 1111 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { 1112 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1113 break; 1114 } 1115 break; 1116 case KVM_CPUID_SIGNATURE: { 1117 const u32 *sigptr = (const u32 *)KVM_SIGNATURE; 1118 entry->eax = KVM_CPUID_FEATURES; 1119 entry->ebx = sigptr[0]; 1120 entry->ecx = sigptr[1]; 1121 entry->edx = sigptr[2]; 1122 break; 1123 } 1124 case KVM_CPUID_FEATURES: 1125 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | 1126 (1 << KVM_FEATURE_NOP_IO_DELAY) | 1127 (1 << KVM_FEATURE_CLOCKSOURCE2) | 1128 (1 << KVM_FEATURE_ASYNC_PF) | 1129 (1 << KVM_FEATURE_PV_EOI) | 1130 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) | 1131 (1 << KVM_FEATURE_PV_UNHALT) | 1132 (1 << KVM_FEATURE_PV_TLB_FLUSH) | 1133 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) | 1134 (1 << KVM_FEATURE_PV_SEND_IPI) | 1135 (1 << KVM_FEATURE_POLL_CONTROL) | 1136 (1 << KVM_FEATURE_PV_SCHED_YIELD) | 1137 (1 << KVM_FEATURE_ASYNC_PF_INT); 1138 1139 if (sched_info_on()) 1140 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME); 1141 1142 entry->ebx = 0; 1143 entry->ecx = 0; 1144 entry->edx = 0; 1145 break; 1146 case 0x80000000: 1147 entry->eax = min(entry->eax, 0x80000021); 1148 /* 1149 * Serializing LFENCE is reported in a multitude of ways, and 1150 * NullSegClearsBase is not reported in CPUID on Zen2; help 1151 * userspace by providing the CPUID leaf ourselves. 1152 * 1153 * However, only do it if the host has CPUID leaf 0x8000001d. 1154 * QEMU thinks that it can query the host blindly for that 1155 * CPUID leaf if KVM reports that it supports 0x8000001d or 1156 * above. The processor merrily returns values from the 1157 * highest Intel leaf which QEMU tries to use as the guest's 1158 * 0x8000001d. Even worse, this can result in an infinite 1159 * loop if said highest leaf has no subleaves indexed by ECX. 1160 */ 1161 if (entry->eax >= 0x8000001d && 1162 (static_cpu_has(X86_FEATURE_LFENCE_RDTSC) 1163 || !static_cpu_has_bug(X86_BUG_NULL_SEG))) 1164 entry->eax = max(entry->eax, 0x80000021); 1165 break; 1166 case 0x80000001: 1167 entry->ebx &= ~GENMASK(27, 16); 1168 cpuid_entry_override(entry, CPUID_8000_0001_EDX); 1169 cpuid_entry_override(entry, CPUID_8000_0001_ECX); 1170 break; 1171 case 0x80000006: 1172 /* Drop reserved bits, pass host L2 cache and TLB info. */ 1173 entry->edx &= ~GENMASK(17, 16); 1174 break; 1175 case 0x80000007: /* Advanced power management */ 1176 cpuid_entry_override(entry, CPUID_8000_0007_EDX); 1177 1178 /* mask against host */ 1179 entry->edx &= boot_cpu_data.x86_power; 1180 entry->eax = entry->ebx = entry->ecx = 0; 1181 break; 1182 case 0x80000008: { 1183 unsigned g_phys_as = (entry->eax >> 16) & 0xff; 1184 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U); 1185 unsigned phys_as = entry->eax & 0xff; 1186 1187 /* 1188 * If TDP (NPT) is disabled use the adjusted host MAXPHYADDR as 1189 * the guest operates in the same PA space as the host, i.e. 1190 * reductions in MAXPHYADDR for memory encryption affect shadow 1191 * paging, too. 1192 * 1193 * If TDP is enabled but an explicit guest MAXPHYADDR is not 1194 * provided, use the raw bare metal MAXPHYADDR as reductions to 1195 * the HPAs do not affect GPAs. 1196 */ 1197 if (!tdp_enabled) 1198 g_phys_as = boot_cpu_data.x86_phys_bits; 1199 else if (!g_phys_as) 1200 g_phys_as = phys_as; 1201 1202 entry->eax = g_phys_as | (virt_as << 8); 1203 entry->ecx &= ~(GENMASK(31, 16) | GENMASK(11, 8)); 1204 entry->edx = 0; 1205 cpuid_entry_override(entry, CPUID_8000_0008_EBX); 1206 break; 1207 } 1208 case 0x8000000A: 1209 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) { 1210 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1211 break; 1212 } 1213 entry->eax = 1; /* SVM revision 1 */ 1214 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper 1215 ASID emulation to nested SVM */ 1216 entry->ecx = 0; /* Reserved */ 1217 cpuid_entry_override(entry, CPUID_8000_000A_EDX); 1218 break; 1219 case 0x80000019: 1220 entry->ecx = entry->edx = 0; 1221 break; 1222 case 0x8000001a: 1223 entry->eax &= GENMASK(2, 0); 1224 entry->ebx = entry->ecx = entry->edx = 0; 1225 break; 1226 case 0x8000001e: 1227 /* Do not return host topology information. */ 1228 entry->eax = entry->ebx = entry->ecx = 0; 1229 entry->edx = 0; /* reserved */ 1230 break; 1231 case 0x8000001F: 1232 if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) { 1233 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1234 } else { 1235 cpuid_entry_override(entry, CPUID_8000_001F_EAX); 1236 /* Clear NumVMPL since KVM does not support VMPL. */ 1237 entry->ebx &= ~GENMASK(31, 12); 1238 /* 1239 * Enumerate '0' for "PA bits reduction", the adjusted 1240 * MAXPHYADDR is enumerated directly (see 0x80000008). 1241 */ 1242 entry->ebx &= ~GENMASK(11, 6); 1243 } 1244 break; 1245 case 0x80000020: 1246 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1247 break; 1248 case 0x80000021: 1249 entry->ebx = entry->ecx = entry->edx = 0; 1250 cpuid_entry_override(entry, CPUID_8000_0021_EAX); 1251 break; 1252 /*Add support for Centaur's CPUID instruction*/ 1253 case 0xC0000000: 1254 /*Just support up to 0xC0000004 now*/ 1255 entry->eax = min(entry->eax, 0xC0000004); 1256 break; 1257 case 0xC0000001: 1258 cpuid_entry_override(entry, CPUID_C000_0001_EDX); 1259 break; 1260 case 3: /* Processor serial number */ 1261 case 5: /* MONITOR/MWAIT */ 1262 case 0xC0000002: 1263 case 0xC0000003: 1264 case 0xC0000004: 1265 default: 1266 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1267 break; 1268 } 1269 1270 r = 0; 1271 1272 out: 1273 put_cpu(); 1274 1275 return r; 1276 } 1277 1278 static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func, 1279 unsigned int type) 1280 { 1281 if (type == KVM_GET_EMULATED_CPUID) 1282 return __do_cpuid_func_emulated(array, func); 1283 1284 return __do_cpuid_func(array, func); 1285 } 1286 1287 #define CENTAUR_CPUID_SIGNATURE 0xC0000000 1288 1289 static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func, 1290 unsigned int type) 1291 { 1292 u32 limit; 1293 int r; 1294 1295 if (func == CENTAUR_CPUID_SIGNATURE && 1296 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR) 1297 return 0; 1298 1299 r = do_cpuid_func(array, func, type); 1300 if (r) 1301 return r; 1302 1303 limit = array->entries[array->nent - 1].eax; 1304 for (func = func + 1; func <= limit; ++func) { 1305 r = do_cpuid_func(array, func, type); 1306 if (r) 1307 break; 1308 } 1309 1310 return r; 1311 } 1312 1313 static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries, 1314 __u32 num_entries, unsigned int ioctl_type) 1315 { 1316 int i; 1317 __u32 pad[3]; 1318 1319 if (ioctl_type != KVM_GET_EMULATED_CPUID) 1320 return false; 1321 1322 /* 1323 * We want to make sure that ->padding is being passed clean from 1324 * userspace in case we want to use it for something in the future. 1325 * 1326 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we 1327 * have to give ourselves satisfied only with the emulated side. /me 1328 * sheds a tear. 1329 */ 1330 for (i = 0; i < num_entries; i++) { 1331 if (copy_from_user(pad, entries[i].padding, sizeof(pad))) 1332 return true; 1333 1334 if (pad[0] || pad[1] || pad[2]) 1335 return true; 1336 } 1337 return false; 1338 } 1339 1340 int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid, 1341 struct kvm_cpuid_entry2 __user *entries, 1342 unsigned int type) 1343 { 1344 static const u32 funcs[] = { 1345 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE, 1346 }; 1347 1348 struct kvm_cpuid_array array = { 1349 .nent = 0, 1350 }; 1351 int r, i; 1352 1353 if (cpuid->nent < 1) 1354 return -E2BIG; 1355 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 1356 cpuid->nent = KVM_MAX_CPUID_ENTRIES; 1357 1358 if (sanity_check_entries(entries, cpuid->nent, type)) 1359 return -EINVAL; 1360 1361 array.entries = kvcalloc(cpuid->nent, sizeof(struct kvm_cpuid_entry2), GFP_KERNEL); 1362 if (!array.entries) 1363 return -ENOMEM; 1364 1365 array.maxnent = cpuid->nent; 1366 1367 for (i = 0; i < ARRAY_SIZE(funcs); i++) { 1368 r = get_cpuid_func(&array, funcs[i], type); 1369 if (r) 1370 goto out_free; 1371 } 1372 cpuid->nent = array.nent; 1373 1374 if (copy_to_user(entries, array.entries, 1375 array.nent * sizeof(struct kvm_cpuid_entry2))) 1376 r = -EFAULT; 1377 1378 out_free: 1379 kvfree(array.entries); 1380 return r; 1381 } 1382 1383 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry_index(struct kvm_vcpu *vcpu, 1384 u32 function, u32 index) 1385 { 1386 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent, 1387 function, index); 1388 } 1389 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry_index); 1390 1391 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, 1392 u32 function) 1393 { 1394 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent, 1395 function, KVM_CPUID_INDEX_NOT_SIGNIFICANT); 1396 } 1397 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); 1398 1399 /* 1400 * Intel CPUID semantics treats any query for an out-of-range leaf as if the 1401 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics 1402 * returns all zeroes for any undefined leaf, whether or not the leaf is in 1403 * range. Centaur/VIA follows Intel semantics. 1404 * 1405 * A leaf is considered out-of-range if its function is higher than the maximum 1406 * supported leaf of its associated class or if its associated class does not 1407 * exist. 1408 * 1409 * There are three primary classes to be considered, with their respective 1410 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary 1411 * class exists if a guest CPUID entry for its <base> leaf exists. For a given 1412 * class, CPUID.<base>.EAX contains the max supported leaf for the class. 1413 * 1414 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff 1415 * - Hypervisor: 0x40000000 - 0x4fffffff 1416 * - Extended: 0x80000000 - 0xbfffffff 1417 * - Centaur: 0xc0000000 - 0xcfffffff 1418 * 1419 * The Hypervisor class is further subdivided into sub-classes that each act as 1420 * their own independent class associated with a 0x100 byte range. E.g. if Qemu 1421 * is advertising support for both HyperV and KVM, the resulting Hypervisor 1422 * CPUID sub-classes are: 1423 * 1424 * - HyperV: 0x40000000 - 0x400000ff 1425 * - KVM: 0x40000100 - 0x400001ff 1426 */ 1427 static struct kvm_cpuid_entry2 * 1428 get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index) 1429 { 1430 struct kvm_cpuid_entry2 *basic, *class; 1431 u32 function = *fn_ptr; 1432 1433 basic = kvm_find_cpuid_entry(vcpu, 0); 1434 if (!basic) 1435 return NULL; 1436 1437 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) || 1438 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx)) 1439 return NULL; 1440 1441 if (function >= 0x40000000 && function <= 0x4fffffff) 1442 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00); 1443 else if (function >= 0xc0000000) 1444 class = kvm_find_cpuid_entry(vcpu, 0xc0000000); 1445 else 1446 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000); 1447 1448 if (class && function <= class->eax) 1449 return NULL; 1450 1451 /* 1452 * Leaf specific adjustments are also applied when redirecting to the 1453 * max basic entry, e.g. if the max basic leaf is 0xb but there is no 1454 * entry for CPUID.0xb.index (see below), then the output value for EDX 1455 * needs to be pulled from CPUID.0xb.1. 1456 */ 1457 *fn_ptr = basic->eax; 1458 1459 /* 1460 * The class does not exist or the requested function is out of range; 1461 * the effective CPUID entry is the max basic leaf. Note, the index of 1462 * the original requested leaf is observed! 1463 */ 1464 return kvm_find_cpuid_entry_index(vcpu, basic->eax, index); 1465 } 1466 1467 bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx, 1468 u32 *ecx, u32 *edx, bool exact_only) 1469 { 1470 u32 orig_function = *eax, function = *eax, index = *ecx; 1471 struct kvm_cpuid_entry2 *entry; 1472 bool exact, used_max_basic = false; 1473 1474 entry = kvm_find_cpuid_entry_index(vcpu, function, index); 1475 exact = !!entry; 1476 1477 if (!entry && !exact_only) { 1478 entry = get_out_of_range_cpuid_entry(vcpu, &function, index); 1479 used_max_basic = !!entry; 1480 } 1481 1482 if (entry) { 1483 *eax = entry->eax; 1484 *ebx = entry->ebx; 1485 *ecx = entry->ecx; 1486 *edx = entry->edx; 1487 if (function == 7 && index == 0) { 1488 u64 data; 1489 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) && 1490 (data & TSX_CTRL_CPUID_CLEAR)) 1491 *ebx &= ~(F(RTM) | F(HLE)); 1492 } else if (function == 0x80000007) { 1493 if (kvm_hv_invtsc_suppressed(vcpu)) 1494 *edx &= ~SF(CONSTANT_TSC); 1495 } 1496 } else { 1497 *eax = *ebx = *ecx = *edx = 0; 1498 /* 1499 * When leaf 0BH or 1FH is defined, CL is pass-through 1500 * and EDX is always the x2APIC ID, even for undefined 1501 * subleaves. Index 1 will exist iff the leaf is 1502 * implemented, so we pass through CL iff leaf 1 1503 * exists. EDX can be copied from any existing index. 1504 */ 1505 if (function == 0xb || function == 0x1f) { 1506 entry = kvm_find_cpuid_entry_index(vcpu, function, 1); 1507 if (entry) { 1508 *ecx = index & 0xff; 1509 *edx = entry->edx; 1510 } 1511 } 1512 } 1513 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact, 1514 used_max_basic); 1515 return exact; 1516 } 1517 EXPORT_SYMBOL_GPL(kvm_cpuid); 1518 1519 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu) 1520 { 1521 u32 eax, ebx, ecx, edx; 1522 1523 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0)) 1524 return 1; 1525 1526 eax = kvm_rax_read(vcpu); 1527 ecx = kvm_rcx_read(vcpu); 1528 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false); 1529 kvm_rax_write(vcpu, eax); 1530 kvm_rbx_write(vcpu, ebx); 1531 kvm_rcx_write(vcpu, ecx); 1532 kvm_rdx_write(vcpu, edx); 1533 return kvm_skip_emulated_instruction(vcpu); 1534 } 1535 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); 1536