1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * cpuid support routines 5 * 6 * derived from arch/x86/kvm/x86.c 7 * 8 * Copyright 2011 Red Hat, Inc. and/or its affiliates. 9 * Copyright IBM Corporation, 2008 10 */ 11 12 #include <linux/kvm_host.h> 13 #include <linux/export.h> 14 #include <linux/vmalloc.h> 15 #include <linux/uaccess.h> 16 #include <linux/sched/stat.h> 17 18 #include <asm/processor.h> 19 #include <asm/user.h> 20 #include <asm/fpu/xstate.h> 21 #include <asm/sgx.h> 22 #include <asm/cpuid.h> 23 #include "cpuid.h" 24 #include "lapic.h" 25 #include "mmu.h" 26 #include "trace.h" 27 #include "pmu.h" 28 29 /* 30 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be 31 * aligned to sizeof(unsigned long) because it's not accessed via bitops. 32 */ 33 u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly; 34 EXPORT_SYMBOL_GPL(kvm_cpu_caps); 35 36 u32 xstate_required_size(u64 xstate_bv, bool compacted) 37 { 38 int feature_bit = 0; 39 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 40 41 xstate_bv &= XFEATURE_MASK_EXTEND; 42 while (xstate_bv) { 43 if (xstate_bv & 0x1) { 44 u32 eax, ebx, ecx, edx, offset; 45 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx); 46 /* ECX[1]: 64B alignment in compacted form */ 47 if (compacted) 48 offset = (ecx & 0x2) ? ALIGN(ret, 64) : ret; 49 else 50 offset = ebx; 51 ret = max(ret, offset + eax); 52 } 53 54 xstate_bv >>= 1; 55 feature_bit++; 56 } 57 58 return ret; 59 } 60 61 /* 62 * This one is tied to SSB in the user API, and not 63 * visible in /proc/cpuinfo. 64 */ 65 #define KVM_X86_FEATURE_PSFD (13*32+28) /* Predictive Store Forwarding Disable */ 66 67 #define F feature_bit 68 #define SF(name) (boot_cpu_has(X86_FEATURE_##name) ? F(name) : 0) 69 70 /* 71 * Magic value used by KVM when querying userspace-provided CPUID entries and 72 * doesn't care about the CPIUD index because the index of the function in 73 * question is not significant. Note, this magic value must have at least one 74 * bit set in bits[63:32] and must be consumed as a u64 by cpuid_entry2_find() 75 * to avoid false positives when processing guest CPUID input. 76 */ 77 #define KVM_CPUID_INDEX_NOT_SIGNIFICANT -1ull 78 79 static inline struct kvm_cpuid_entry2 *cpuid_entry2_find( 80 struct kvm_cpuid_entry2 *entries, int nent, u32 function, u64 index) 81 { 82 struct kvm_cpuid_entry2 *e; 83 int i; 84 85 for (i = 0; i < nent; i++) { 86 e = &entries[i]; 87 88 if (e->function != function) 89 continue; 90 91 /* 92 * If the index isn't significant, use the first entry with a 93 * matching function. It's userspace's responsibilty to not 94 * provide "duplicate" entries in all cases. 95 */ 96 if (!(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) || e->index == index) 97 return e; 98 99 100 /* 101 * Similarly, use the first matching entry if KVM is doing a 102 * lookup (as opposed to emulating CPUID) for a function that's 103 * architecturally defined as not having a significant index. 104 */ 105 if (index == KVM_CPUID_INDEX_NOT_SIGNIFICANT) { 106 /* 107 * Direct lookups from KVM should not diverge from what 108 * KVM defines internally (the architectural behavior). 109 */ 110 WARN_ON_ONCE(cpuid_function_is_indexed(function)); 111 return e; 112 } 113 } 114 115 return NULL; 116 } 117 118 static int kvm_check_cpuid(struct kvm_vcpu *vcpu, 119 struct kvm_cpuid_entry2 *entries, 120 int nent) 121 { 122 struct kvm_cpuid_entry2 *best; 123 u64 xfeatures; 124 125 /* 126 * The existing code assumes virtual address is 48-bit or 57-bit in the 127 * canonical address checks; exit if it is ever changed. 128 */ 129 best = cpuid_entry2_find(entries, nent, 0x80000008, 130 KVM_CPUID_INDEX_NOT_SIGNIFICANT); 131 if (best) { 132 int vaddr_bits = (best->eax & 0xff00) >> 8; 133 134 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) 135 return -EINVAL; 136 } 137 138 /* 139 * Exposing dynamic xfeatures to the guest requires additional 140 * enabling in the FPU, e.g. to expand the guest XSAVE state size. 141 */ 142 best = cpuid_entry2_find(entries, nent, 0xd, 0); 143 if (!best) 144 return 0; 145 146 xfeatures = best->eax | ((u64)best->edx << 32); 147 xfeatures &= XFEATURE_MASK_USER_DYNAMIC; 148 if (!xfeatures) 149 return 0; 150 151 return fpu_enable_guest_xfd_features(&vcpu->arch.guest_fpu, xfeatures); 152 } 153 154 /* Check whether the supplied CPUID data is equal to what is already set for the vCPU. */ 155 static int kvm_cpuid_check_equal(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2, 156 int nent) 157 { 158 struct kvm_cpuid_entry2 *orig; 159 int i; 160 161 if (nent != vcpu->arch.cpuid_nent) 162 return -EINVAL; 163 164 for (i = 0; i < nent; i++) { 165 orig = &vcpu->arch.cpuid_entries[i]; 166 if (e2[i].function != orig->function || 167 e2[i].index != orig->index || 168 e2[i].flags != orig->flags || 169 e2[i].eax != orig->eax || e2[i].ebx != orig->ebx || 170 e2[i].ecx != orig->ecx || e2[i].edx != orig->edx) 171 return -EINVAL; 172 } 173 174 return 0; 175 } 176 177 static void kvm_update_kvm_cpuid_base(struct kvm_vcpu *vcpu) 178 { 179 u32 function; 180 struct kvm_cpuid_entry2 *entry; 181 182 vcpu->arch.kvm_cpuid_base = 0; 183 184 for_each_possible_hypervisor_cpuid_base(function) { 185 entry = kvm_find_cpuid_entry(vcpu, function); 186 187 if (entry) { 188 u32 signature[3]; 189 190 signature[0] = entry->ebx; 191 signature[1] = entry->ecx; 192 signature[2] = entry->edx; 193 194 BUILD_BUG_ON(sizeof(signature) > sizeof(KVM_SIGNATURE)); 195 if (!memcmp(signature, KVM_SIGNATURE, sizeof(signature))) { 196 vcpu->arch.kvm_cpuid_base = function; 197 break; 198 } 199 } 200 } 201 } 202 203 static struct kvm_cpuid_entry2 *__kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu, 204 struct kvm_cpuid_entry2 *entries, int nent) 205 { 206 u32 base = vcpu->arch.kvm_cpuid_base; 207 208 if (!base) 209 return NULL; 210 211 return cpuid_entry2_find(entries, nent, base | KVM_CPUID_FEATURES, 212 KVM_CPUID_INDEX_NOT_SIGNIFICANT); 213 } 214 215 static struct kvm_cpuid_entry2 *kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu) 216 { 217 return __kvm_find_kvm_cpuid_features(vcpu, vcpu->arch.cpuid_entries, 218 vcpu->arch.cpuid_nent); 219 } 220 221 void kvm_update_pv_runtime(struct kvm_vcpu *vcpu) 222 { 223 struct kvm_cpuid_entry2 *best = kvm_find_kvm_cpuid_features(vcpu); 224 225 /* 226 * save the feature bitmap to avoid cpuid lookup for every PV 227 * operation 228 */ 229 if (best) 230 vcpu->arch.pv_cpuid.features = best->eax; 231 } 232 233 /* 234 * Calculate guest's supported XCR0 taking into account guest CPUID data and 235 * KVM's supported XCR0 (comprised of host's XCR0 and KVM_SUPPORTED_XCR0). 236 */ 237 static u64 cpuid_get_supported_xcr0(struct kvm_cpuid_entry2 *entries, int nent) 238 { 239 struct kvm_cpuid_entry2 *best; 240 241 best = cpuid_entry2_find(entries, nent, 0xd, 0); 242 if (!best) 243 return 0; 244 245 return (best->eax | ((u64)best->edx << 32)) & kvm_caps.supported_xcr0; 246 } 247 248 static void __kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *entries, 249 int nent) 250 { 251 struct kvm_cpuid_entry2 *best; 252 u64 guest_supported_xcr0 = cpuid_get_supported_xcr0(entries, nent); 253 254 best = cpuid_entry2_find(entries, nent, 1, KVM_CPUID_INDEX_NOT_SIGNIFICANT); 255 if (best) { 256 /* Update OSXSAVE bit */ 257 if (boot_cpu_has(X86_FEATURE_XSAVE)) 258 cpuid_entry_change(best, X86_FEATURE_OSXSAVE, 259 kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)); 260 261 cpuid_entry_change(best, X86_FEATURE_APIC, 262 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE); 263 } 264 265 best = cpuid_entry2_find(entries, nent, 7, 0); 266 if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7) 267 cpuid_entry_change(best, X86_FEATURE_OSPKE, 268 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)); 269 270 best = cpuid_entry2_find(entries, nent, 0xD, 0); 271 if (best) 272 best->ebx = xstate_required_size(vcpu->arch.xcr0, false); 273 274 best = cpuid_entry2_find(entries, nent, 0xD, 1); 275 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) || 276 cpuid_entry_has(best, X86_FEATURE_XSAVEC))) 277 best->ebx = xstate_required_size(vcpu->arch.xcr0, true); 278 279 best = __kvm_find_kvm_cpuid_features(vcpu, entries, nent); 280 if (kvm_hlt_in_guest(vcpu->kvm) && best && 281 (best->eax & (1 << KVM_FEATURE_PV_UNHALT))) 282 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT); 283 284 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) { 285 best = cpuid_entry2_find(entries, nent, 0x1, KVM_CPUID_INDEX_NOT_SIGNIFICANT); 286 if (best) 287 cpuid_entry_change(best, X86_FEATURE_MWAIT, 288 vcpu->arch.ia32_misc_enable_msr & 289 MSR_IA32_MISC_ENABLE_MWAIT); 290 } 291 292 /* 293 * Bits 127:0 of the allowed SECS.ATTRIBUTES (CPUID.0x12.0x1) enumerate 294 * the supported XSAVE Feature Request Mask (XFRM), i.e. the enclave's 295 * requested XCR0 value. The enclave's XFRM must be a subset of XCRO 296 * at the time of EENTER, thus adjust the allowed XFRM by the guest's 297 * supported XCR0. Similar to XCR0 handling, FP and SSE are forced to 298 * '1' even on CPUs that don't support XSAVE. 299 */ 300 best = cpuid_entry2_find(entries, nent, 0x12, 0x1); 301 if (best) { 302 best->ecx &= guest_supported_xcr0 & 0xffffffff; 303 best->edx &= guest_supported_xcr0 >> 32; 304 best->ecx |= XFEATURE_MASK_FPSSE; 305 } 306 } 307 308 void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu) 309 { 310 __kvm_update_cpuid_runtime(vcpu, vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent); 311 } 312 EXPORT_SYMBOL_GPL(kvm_update_cpuid_runtime); 313 314 static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) 315 { 316 struct kvm_lapic *apic = vcpu->arch.apic; 317 struct kvm_cpuid_entry2 *best; 318 319 best = kvm_find_cpuid_entry(vcpu, 1); 320 if (best && apic) { 321 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER)) 322 apic->lapic_timer.timer_mode_mask = 3 << 17; 323 else 324 apic->lapic_timer.timer_mode_mask = 1 << 17; 325 326 kvm_apic_set_version(vcpu); 327 } 328 329 vcpu->arch.guest_supported_xcr0 = 330 cpuid_get_supported_xcr0(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent); 331 332 /* 333 * FP+SSE can always be saved/restored via KVM_{G,S}ET_XSAVE, even if 334 * XSAVE/XCRO are not exposed to the guest, and even if XSAVE isn't 335 * supported by the host. 336 */ 337 vcpu->arch.guest_fpu.fpstate->user_xfeatures = vcpu->arch.guest_supported_xcr0 | 338 XFEATURE_MASK_FPSSE; 339 340 kvm_update_pv_runtime(vcpu); 341 342 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 343 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 344 345 kvm_pmu_refresh(vcpu); 346 vcpu->arch.cr4_guest_rsvd_bits = 347 __cr4_reserved_bits(guest_cpuid_has, vcpu); 348 349 kvm_hv_set_cpuid(vcpu); 350 351 /* Invoke the vendor callback only after the above state is updated. */ 352 static_call(kvm_x86_vcpu_after_set_cpuid)(vcpu); 353 354 /* 355 * Except for the MMU, which needs to do its thing any vendor specific 356 * adjustments to the reserved GPA bits. 357 */ 358 kvm_mmu_after_set_cpuid(vcpu); 359 } 360 361 int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu) 362 { 363 struct kvm_cpuid_entry2 *best; 364 365 best = kvm_find_cpuid_entry(vcpu, 0x80000000); 366 if (!best || best->eax < 0x80000008) 367 goto not_found; 368 best = kvm_find_cpuid_entry(vcpu, 0x80000008); 369 if (best) 370 return best->eax & 0xff; 371 not_found: 372 return 36; 373 } 374 375 /* 376 * This "raw" version returns the reserved GPA bits without any adjustments for 377 * encryption technologies that usurp bits. The raw mask should be used if and 378 * only if hardware does _not_ strip the usurped bits, e.g. in virtual MTRRs. 379 */ 380 u64 kvm_vcpu_reserved_gpa_bits_raw(struct kvm_vcpu *vcpu) 381 { 382 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63); 383 } 384 385 static int kvm_set_cpuid(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2, 386 int nent) 387 { 388 int r; 389 390 __kvm_update_cpuid_runtime(vcpu, e2, nent); 391 392 /* 393 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as 394 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't 395 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page 396 * faults due to reusing SPs/SPTEs. In practice no sane VMM mucks with 397 * the core vCPU model on the fly. It would've been better to forbid any 398 * KVM_SET_CPUID{,2} calls after KVM_RUN altogether but unfortunately 399 * some VMMs (e.g. QEMU) reuse vCPU fds for CPU hotplug/unplug and do 400 * KVM_SET_CPUID{,2} again. To support this legacy behavior, check 401 * whether the supplied CPUID data is equal to what's already set. 402 */ 403 if (vcpu->arch.last_vmentry_cpu != -1) { 404 r = kvm_cpuid_check_equal(vcpu, e2, nent); 405 if (r) 406 return r; 407 408 kvfree(e2); 409 return 0; 410 } 411 412 r = kvm_check_cpuid(vcpu, e2, nent); 413 if (r) 414 return r; 415 416 kvfree(vcpu->arch.cpuid_entries); 417 vcpu->arch.cpuid_entries = e2; 418 vcpu->arch.cpuid_nent = nent; 419 420 kvm_update_kvm_cpuid_base(vcpu); 421 kvm_vcpu_after_set_cpuid(vcpu); 422 423 return 0; 424 } 425 426 /* when an old userspace process fills a new kernel module */ 427 int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, 428 struct kvm_cpuid *cpuid, 429 struct kvm_cpuid_entry __user *entries) 430 { 431 int r, i; 432 struct kvm_cpuid_entry *e = NULL; 433 struct kvm_cpuid_entry2 *e2 = NULL; 434 435 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 436 return -E2BIG; 437 438 if (cpuid->nent) { 439 e = vmemdup_user(entries, array_size(sizeof(*e), cpuid->nent)); 440 if (IS_ERR(e)) 441 return PTR_ERR(e); 442 443 e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT); 444 if (!e2) { 445 r = -ENOMEM; 446 goto out_free_cpuid; 447 } 448 } 449 for (i = 0; i < cpuid->nent; i++) { 450 e2[i].function = e[i].function; 451 e2[i].eax = e[i].eax; 452 e2[i].ebx = e[i].ebx; 453 e2[i].ecx = e[i].ecx; 454 e2[i].edx = e[i].edx; 455 e2[i].index = 0; 456 e2[i].flags = 0; 457 e2[i].padding[0] = 0; 458 e2[i].padding[1] = 0; 459 e2[i].padding[2] = 0; 460 } 461 462 r = kvm_set_cpuid(vcpu, e2, cpuid->nent); 463 if (r) 464 kvfree(e2); 465 466 out_free_cpuid: 467 kvfree(e); 468 469 return r; 470 } 471 472 int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, 473 struct kvm_cpuid2 *cpuid, 474 struct kvm_cpuid_entry2 __user *entries) 475 { 476 struct kvm_cpuid_entry2 *e2 = NULL; 477 int r; 478 479 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 480 return -E2BIG; 481 482 if (cpuid->nent) { 483 e2 = vmemdup_user(entries, array_size(sizeof(*e2), cpuid->nent)); 484 if (IS_ERR(e2)) 485 return PTR_ERR(e2); 486 } 487 488 r = kvm_set_cpuid(vcpu, e2, cpuid->nent); 489 if (r) 490 kvfree(e2); 491 492 return r; 493 } 494 495 int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, 496 struct kvm_cpuid2 *cpuid, 497 struct kvm_cpuid_entry2 __user *entries) 498 { 499 int r; 500 501 r = -E2BIG; 502 if (cpuid->nent < vcpu->arch.cpuid_nent) 503 goto out; 504 r = -EFAULT; 505 if (copy_to_user(entries, vcpu->arch.cpuid_entries, 506 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) 507 goto out; 508 return 0; 509 510 out: 511 cpuid->nent = vcpu->arch.cpuid_nent; 512 return r; 513 } 514 515 /* Mask kvm_cpu_caps for @leaf with the raw CPUID capabilities of this CPU. */ 516 static __always_inline void __kvm_cpu_cap_mask(unsigned int leaf) 517 { 518 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32); 519 struct kvm_cpuid_entry2 entry; 520 521 reverse_cpuid_check(leaf); 522 523 cpuid_count(cpuid.function, cpuid.index, 524 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx); 525 526 kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg); 527 } 528 529 static __always_inline 530 void kvm_cpu_cap_init_scattered(enum kvm_only_cpuid_leafs leaf, u32 mask) 531 { 532 /* Use kvm_cpu_cap_mask for non-scattered leafs. */ 533 BUILD_BUG_ON(leaf < NCAPINTS); 534 535 kvm_cpu_caps[leaf] = mask; 536 537 __kvm_cpu_cap_mask(leaf); 538 } 539 540 static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask) 541 { 542 /* Use kvm_cpu_cap_init_scattered for scattered leafs. */ 543 BUILD_BUG_ON(leaf >= NCAPINTS); 544 545 kvm_cpu_caps[leaf] &= mask; 546 547 __kvm_cpu_cap_mask(leaf); 548 } 549 550 void kvm_set_cpu_caps(void) 551 { 552 #ifdef CONFIG_X86_64 553 unsigned int f_gbpages = F(GBPAGES); 554 unsigned int f_lm = F(LM); 555 unsigned int f_xfd = F(XFD); 556 #else 557 unsigned int f_gbpages = 0; 558 unsigned int f_lm = 0; 559 unsigned int f_xfd = 0; 560 #endif 561 memset(kvm_cpu_caps, 0, sizeof(kvm_cpu_caps)); 562 563 BUILD_BUG_ON(sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)) > 564 sizeof(boot_cpu_data.x86_capability)); 565 566 memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability, 567 sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps))); 568 569 kvm_cpu_cap_mask(CPUID_1_ECX, 570 /* 571 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not* 572 * advertised to guests via CPUID! 573 */ 574 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ | 575 0 /* DS-CPL, VMX, SMX, EST */ | 576 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | 577 F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) | 578 F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) | 579 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | 580 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) | 581 F(F16C) | F(RDRAND) 582 ); 583 /* KVM emulates x2apic in software irrespective of host support. */ 584 kvm_cpu_cap_set(X86_FEATURE_X2APIC); 585 586 kvm_cpu_cap_mask(CPUID_1_EDX, 587 F(FPU) | F(VME) | F(DE) | F(PSE) | 588 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 589 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | 590 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 591 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) | 592 0 /* Reserved, DS, ACPI */ | F(MMX) | 593 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | 594 0 /* HTT, TM, Reserved, PBE */ 595 ); 596 597 kvm_cpu_cap_mask(CPUID_7_0_EBX, 598 F(FSGSBASE) | F(SGX) | F(BMI1) | F(HLE) | F(AVX2) | 599 F(FDP_EXCPTN_ONLY) | F(SMEP) | F(BMI2) | F(ERMS) | F(INVPCID) | 600 F(RTM) | F(ZERO_FCS_FDS) | 0 /*MPX*/ | F(AVX512F) | 601 F(AVX512DQ) | F(RDSEED) | F(ADX) | F(SMAP) | F(AVX512IFMA) | 602 F(CLFLUSHOPT) | F(CLWB) | 0 /*INTEL_PT*/ | F(AVX512PF) | 603 F(AVX512ER) | F(AVX512CD) | F(SHA_NI) | F(AVX512BW) | 604 F(AVX512VL)); 605 606 kvm_cpu_cap_mask(CPUID_7_ECX, 607 F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) | 608 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) | 609 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) | 610 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ | 611 F(SGX_LC) | F(BUS_LOCK_DETECT) 612 ); 613 /* Set LA57 based on hardware capability. */ 614 if (cpuid_ecx(7) & F(LA57)) 615 kvm_cpu_cap_set(X86_FEATURE_LA57); 616 617 /* 618 * PKU not yet implemented for shadow paging and requires OSPKE 619 * to be set on the host. Clear it if that is not the case 620 */ 621 if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE)) 622 kvm_cpu_cap_clear(X86_FEATURE_PKU); 623 624 kvm_cpu_cap_mask(CPUID_7_EDX, 625 F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | 626 F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | 627 F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | 628 F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) | 629 F(AMX_TILE) | F(AMX_INT8) | F(AMX_BF16) 630 ); 631 632 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ 633 kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST); 634 kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES); 635 636 if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS)) 637 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL); 638 if (boot_cpu_has(X86_FEATURE_STIBP)) 639 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); 640 if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) 641 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); 642 643 kvm_cpu_cap_mask(CPUID_7_1_EAX, 644 F(AVX_VNNI) | F(AVX512_BF16) 645 ); 646 647 kvm_cpu_cap_mask(CPUID_D_1_EAX, 648 F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | f_xfd 649 ); 650 651 kvm_cpu_cap_init_scattered(CPUID_12_EAX, 652 SF(SGX1) | SF(SGX2) 653 ); 654 655 kvm_cpu_cap_mask(CPUID_8000_0001_ECX, 656 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ | 657 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | 658 F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) | 659 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) | 660 F(TOPOEXT) | 0 /* PERFCTR_CORE */ 661 ); 662 663 kvm_cpu_cap_mask(CPUID_8000_0001_EDX, 664 F(FPU) | F(VME) | F(DE) | F(PSE) | 665 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 666 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | 667 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 668 F(PAT) | F(PSE36) | 0 /* Reserved */ | 669 F(NX) | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | 670 F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) | 671 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW) 672 ); 673 674 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64)) 675 kvm_cpu_cap_set(X86_FEATURE_GBPAGES); 676 677 kvm_cpu_cap_mask(CPUID_8000_0008_EBX, 678 F(CLZERO) | F(XSAVEERPTR) | 679 F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | 680 F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) | 681 __feature_bit(KVM_X86_FEATURE_PSFD) 682 ); 683 684 /* 685 * AMD has separate bits for each SPEC_CTRL bit. 686 * arch/x86/kernel/cpu/bugs.c is kind enough to 687 * record that in cpufeatures so use them. 688 */ 689 if (boot_cpu_has(X86_FEATURE_IBPB)) 690 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB); 691 if (boot_cpu_has(X86_FEATURE_IBRS)) 692 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS); 693 if (boot_cpu_has(X86_FEATURE_STIBP)) 694 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP); 695 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) 696 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD); 697 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 698 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO); 699 /* 700 * The preference is to use SPEC CTRL MSR instead of the 701 * VIRT_SPEC MSR. 702 */ 703 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) && 704 !boot_cpu_has(X86_FEATURE_AMD_SSBD)) 705 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); 706 707 /* 708 * Hide all SVM features by default, SVM will set the cap bits for 709 * features it emulates and/or exposes for L1. 710 */ 711 kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0); 712 713 kvm_cpu_cap_mask(CPUID_8000_001F_EAX, 714 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) | 715 F(SME_COHERENT)); 716 717 kvm_cpu_cap_mask(CPUID_C000_0001_EDX, 718 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | 719 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | 720 F(PMM) | F(PMM_EN) 721 ); 722 723 /* 724 * Hide RDTSCP and RDPID if either feature is reported as supported but 725 * probing MSR_TSC_AUX failed. This is purely a sanity check and 726 * should never happen, but the guest will likely crash if RDTSCP or 727 * RDPID is misreported, and KVM has botched MSR_TSC_AUX emulation in 728 * the past. For example, the sanity check may fire if this instance of 729 * KVM is running as L1 on top of an older, broken KVM. 730 */ 731 if (WARN_ON((kvm_cpu_cap_has(X86_FEATURE_RDTSCP) || 732 kvm_cpu_cap_has(X86_FEATURE_RDPID)) && 733 !kvm_is_supported_user_return_msr(MSR_TSC_AUX))) { 734 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP); 735 kvm_cpu_cap_clear(X86_FEATURE_RDPID); 736 } 737 } 738 EXPORT_SYMBOL_GPL(kvm_set_cpu_caps); 739 740 struct kvm_cpuid_array { 741 struct kvm_cpuid_entry2 *entries; 742 int maxnent; 743 int nent; 744 }; 745 746 static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array, 747 u32 function, u32 index) 748 { 749 struct kvm_cpuid_entry2 *entry; 750 751 if (array->nent >= array->maxnent) 752 return NULL; 753 754 entry = &array->entries[array->nent++]; 755 756 memset(entry, 0, sizeof(*entry)); 757 entry->function = function; 758 entry->index = index; 759 switch (function & 0xC0000000) { 760 case 0x40000000: 761 /* Hypervisor leaves are always synthesized by __do_cpuid_func. */ 762 return entry; 763 764 case 0x80000000: 765 /* 766 * 0x80000021 is sometimes synthesized by __do_cpuid_func, which 767 * would result in out-of-bounds calls to do_host_cpuid. 768 */ 769 { 770 static int max_cpuid_80000000; 771 if (!READ_ONCE(max_cpuid_80000000)) 772 WRITE_ONCE(max_cpuid_80000000, cpuid_eax(0x80000000)); 773 if (function > READ_ONCE(max_cpuid_80000000)) 774 return entry; 775 } 776 break; 777 778 default: 779 break; 780 } 781 782 cpuid_count(entry->function, entry->index, 783 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); 784 785 if (cpuid_function_is_indexed(function)) 786 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 787 788 return entry; 789 } 790 791 static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func) 792 { 793 struct kvm_cpuid_entry2 *entry; 794 795 if (array->nent >= array->maxnent) 796 return -E2BIG; 797 798 entry = &array->entries[array->nent]; 799 entry->function = func; 800 entry->index = 0; 801 entry->flags = 0; 802 803 switch (func) { 804 case 0: 805 entry->eax = 7; 806 ++array->nent; 807 break; 808 case 1: 809 entry->ecx = F(MOVBE); 810 ++array->nent; 811 break; 812 case 7: 813 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 814 entry->eax = 0; 815 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) 816 entry->ecx = F(RDPID); 817 ++array->nent; 818 break; 819 default: 820 break; 821 } 822 823 return 0; 824 } 825 826 static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) 827 { 828 struct kvm_cpuid_entry2 *entry; 829 int r, i, max_idx; 830 831 /* all calls to cpuid_count() should be made on the same cpu */ 832 get_cpu(); 833 834 r = -E2BIG; 835 836 entry = do_host_cpuid(array, function, 0); 837 if (!entry) 838 goto out; 839 840 switch (function) { 841 case 0: 842 /* Limited to the highest leaf implemented in KVM. */ 843 entry->eax = min(entry->eax, 0x1fU); 844 break; 845 case 1: 846 cpuid_entry_override(entry, CPUID_1_EDX); 847 cpuid_entry_override(entry, CPUID_1_ECX); 848 break; 849 case 2: 850 /* 851 * On ancient CPUs, function 2 entries are STATEFUL. That is, 852 * CPUID(function=2, index=0) may return different results each 853 * time, with the least-significant byte in EAX enumerating the 854 * number of times software should do CPUID(2, 0). 855 * 856 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less 857 * idiotic. Intel's SDM states that EAX & 0xff "will always 858 * return 01H. Software should ignore this value and not 859 * interpret it as an informational descriptor", while AMD's 860 * APM states that CPUID(2) is reserved. 861 * 862 * WARN if a frankenstein CPU that supports virtualization and 863 * a stateful CPUID.0x2 is encountered. 864 */ 865 WARN_ON_ONCE((entry->eax & 0xff) > 1); 866 break; 867 /* functions 4 and 0x8000001d have additional index. */ 868 case 4: 869 case 0x8000001d: 870 /* 871 * Read entries until the cache type in the previous entry is 872 * zero, i.e. indicates an invalid entry. 873 */ 874 for (i = 1; entry->eax & 0x1f; ++i) { 875 entry = do_host_cpuid(array, function, i); 876 if (!entry) 877 goto out; 878 } 879 break; 880 case 6: /* Thermal management */ 881 entry->eax = 0x4; /* allow ARAT */ 882 entry->ebx = 0; 883 entry->ecx = 0; 884 entry->edx = 0; 885 break; 886 /* function 7 has additional index. */ 887 case 7: 888 entry->eax = min(entry->eax, 1u); 889 cpuid_entry_override(entry, CPUID_7_0_EBX); 890 cpuid_entry_override(entry, CPUID_7_ECX); 891 cpuid_entry_override(entry, CPUID_7_EDX); 892 893 /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */ 894 if (entry->eax == 1) { 895 entry = do_host_cpuid(array, function, 1); 896 if (!entry) 897 goto out; 898 899 cpuid_entry_override(entry, CPUID_7_1_EAX); 900 entry->ebx = 0; 901 entry->ecx = 0; 902 entry->edx = 0; 903 } 904 break; 905 case 9: 906 break; 907 case 0xa: { /* Architectural Performance Monitoring */ 908 union cpuid10_eax eax; 909 union cpuid10_edx edx; 910 911 if (!static_cpu_has(X86_FEATURE_ARCH_PERFMON)) { 912 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 913 break; 914 } 915 916 eax.split.version_id = kvm_pmu_cap.version; 917 eax.split.num_counters = kvm_pmu_cap.num_counters_gp; 918 eax.split.bit_width = kvm_pmu_cap.bit_width_gp; 919 eax.split.mask_length = kvm_pmu_cap.events_mask_len; 920 edx.split.num_counters_fixed = kvm_pmu_cap.num_counters_fixed; 921 edx.split.bit_width_fixed = kvm_pmu_cap.bit_width_fixed; 922 923 if (kvm_pmu_cap.version) 924 edx.split.anythread_deprecated = 1; 925 edx.split.reserved1 = 0; 926 edx.split.reserved2 = 0; 927 928 entry->eax = eax.full; 929 entry->ebx = kvm_pmu_cap.events_mask; 930 entry->ecx = 0; 931 entry->edx = edx.full; 932 break; 933 } 934 /* 935 * Per Intel's SDM, the 0x1f is a superset of 0xb, 936 * thus they can be handled by common code. 937 */ 938 case 0x1f: 939 case 0xb: 940 /* 941 * Populate entries until the level type (ECX[15:8]) of the 942 * previous entry is zero. Note, CPUID EAX.{0x1f,0xb}.0 is 943 * the starting entry, filled by the primary do_host_cpuid(). 944 */ 945 for (i = 1; entry->ecx & 0xff00; ++i) { 946 entry = do_host_cpuid(array, function, i); 947 if (!entry) 948 goto out; 949 } 950 break; 951 case 0xd: { 952 u64 permitted_xcr0 = kvm_caps.supported_xcr0 & xstate_get_guest_group_perm(); 953 u64 permitted_xss = kvm_caps.supported_xss; 954 955 entry->eax &= permitted_xcr0; 956 entry->ebx = xstate_required_size(permitted_xcr0, false); 957 entry->ecx = entry->ebx; 958 entry->edx &= permitted_xcr0 >> 32; 959 if (!permitted_xcr0) 960 break; 961 962 entry = do_host_cpuid(array, function, 1); 963 if (!entry) 964 goto out; 965 966 cpuid_entry_override(entry, CPUID_D_1_EAX); 967 if (entry->eax & (F(XSAVES)|F(XSAVEC))) 968 entry->ebx = xstate_required_size(permitted_xcr0 | permitted_xss, 969 true); 970 else { 971 WARN_ON_ONCE(permitted_xss != 0); 972 entry->ebx = 0; 973 } 974 entry->ecx &= permitted_xss; 975 entry->edx &= permitted_xss >> 32; 976 977 for (i = 2; i < 64; ++i) { 978 bool s_state; 979 if (permitted_xcr0 & BIT_ULL(i)) 980 s_state = false; 981 else if (permitted_xss & BIT_ULL(i)) 982 s_state = true; 983 else 984 continue; 985 986 entry = do_host_cpuid(array, function, i); 987 if (!entry) 988 goto out; 989 990 /* 991 * The supported check above should have filtered out 992 * invalid sub-leafs. Only valid sub-leafs should 993 * reach this point, and they should have a non-zero 994 * save state size. Furthermore, check whether the 995 * processor agrees with permitted_xcr0/permitted_xss 996 * on whether this is an XCR0- or IA32_XSS-managed area. 997 */ 998 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) { 999 --array->nent; 1000 continue; 1001 } 1002 1003 if (!kvm_cpu_cap_has(X86_FEATURE_XFD)) 1004 entry->ecx &= ~BIT_ULL(2); 1005 entry->edx = 0; 1006 } 1007 break; 1008 } 1009 case 0x12: 1010 /* Intel SGX */ 1011 if (!kvm_cpu_cap_has(X86_FEATURE_SGX)) { 1012 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1013 break; 1014 } 1015 1016 /* 1017 * Index 0: Sub-features, MISCSELECT (a.k.a extended features) 1018 * and max enclave sizes. The SGX sub-features and MISCSELECT 1019 * are restricted by kernel and KVM capabilities (like most 1020 * feature flags), while enclave size is unrestricted. 1021 */ 1022 cpuid_entry_override(entry, CPUID_12_EAX); 1023 entry->ebx &= SGX_MISC_EXINFO; 1024 1025 entry = do_host_cpuid(array, function, 1); 1026 if (!entry) 1027 goto out; 1028 1029 /* 1030 * Index 1: SECS.ATTRIBUTES. ATTRIBUTES are restricted a la 1031 * feature flags. Advertise all supported flags, including 1032 * privileged attributes that require explicit opt-in from 1033 * userspace. ATTRIBUTES.XFRM is not adjusted as userspace is 1034 * expected to derive it from supported XCR0. 1035 */ 1036 entry->eax &= SGX_ATTR_DEBUG | SGX_ATTR_MODE64BIT | 1037 SGX_ATTR_PROVISIONKEY | SGX_ATTR_EINITTOKENKEY | 1038 SGX_ATTR_KSS; 1039 entry->ebx &= 0; 1040 break; 1041 /* Intel PT */ 1042 case 0x14: 1043 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) { 1044 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1045 break; 1046 } 1047 1048 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 1049 if (!do_host_cpuid(array, function, i)) 1050 goto out; 1051 } 1052 break; 1053 /* Intel AMX TILE */ 1054 case 0x1d: 1055 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { 1056 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1057 break; 1058 } 1059 1060 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 1061 if (!do_host_cpuid(array, function, i)) 1062 goto out; 1063 } 1064 break; 1065 case 0x1e: /* TMUL information */ 1066 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { 1067 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1068 break; 1069 } 1070 break; 1071 case KVM_CPUID_SIGNATURE: { 1072 const u32 *sigptr = (const u32 *)KVM_SIGNATURE; 1073 entry->eax = KVM_CPUID_FEATURES; 1074 entry->ebx = sigptr[0]; 1075 entry->ecx = sigptr[1]; 1076 entry->edx = sigptr[2]; 1077 break; 1078 } 1079 case KVM_CPUID_FEATURES: 1080 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | 1081 (1 << KVM_FEATURE_NOP_IO_DELAY) | 1082 (1 << KVM_FEATURE_CLOCKSOURCE2) | 1083 (1 << KVM_FEATURE_ASYNC_PF) | 1084 (1 << KVM_FEATURE_PV_EOI) | 1085 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) | 1086 (1 << KVM_FEATURE_PV_UNHALT) | 1087 (1 << KVM_FEATURE_PV_TLB_FLUSH) | 1088 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) | 1089 (1 << KVM_FEATURE_PV_SEND_IPI) | 1090 (1 << KVM_FEATURE_POLL_CONTROL) | 1091 (1 << KVM_FEATURE_PV_SCHED_YIELD) | 1092 (1 << KVM_FEATURE_ASYNC_PF_INT); 1093 1094 if (sched_info_on()) 1095 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME); 1096 1097 entry->ebx = 0; 1098 entry->ecx = 0; 1099 entry->edx = 0; 1100 break; 1101 case 0x80000000: 1102 entry->eax = min(entry->eax, 0x80000021); 1103 /* 1104 * Serializing LFENCE is reported in a multitude of ways, and 1105 * NullSegClearsBase is not reported in CPUID on Zen2; help 1106 * userspace by providing the CPUID leaf ourselves. 1107 * 1108 * However, only do it if the host has CPUID leaf 0x8000001d. 1109 * QEMU thinks that it can query the host blindly for that 1110 * CPUID leaf if KVM reports that it supports 0x8000001d or 1111 * above. The processor merrily returns values from the 1112 * highest Intel leaf which QEMU tries to use as the guest's 1113 * 0x8000001d. Even worse, this can result in an infinite 1114 * loop if said highest leaf has no subleaves indexed by ECX. 1115 */ 1116 if (entry->eax >= 0x8000001d && 1117 (static_cpu_has(X86_FEATURE_LFENCE_RDTSC) 1118 || !static_cpu_has_bug(X86_BUG_NULL_SEG))) 1119 entry->eax = max(entry->eax, 0x80000021); 1120 break; 1121 case 0x80000001: 1122 cpuid_entry_override(entry, CPUID_8000_0001_EDX); 1123 cpuid_entry_override(entry, CPUID_8000_0001_ECX); 1124 break; 1125 case 0x80000006: 1126 /* L2 cache and TLB: pass through host info. */ 1127 break; 1128 case 0x80000007: /* Advanced power management */ 1129 /* invariant TSC is CPUID.80000007H:EDX[8] */ 1130 entry->edx &= (1 << 8); 1131 /* mask against host */ 1132 entry->edx &= boot_cpu_data.x86_power; 1133 entry->eax = entry->ebx = entry->ecx = 0; 1134 break; 1135 case 0x80000008: { 1136 unsigned g_phys_as = (entry->eax >> 16) & 0xff; 1137 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U); 1138 unsigned phys_as = entry->eax & 0xff; 1139 1140 /* 1141 * If TDP (NPT) is disabled use the adjusted host MAXPHYADDR as 1142 * the guest operates in the same PA space as the host, i.e. 1143 * reductions in MAXPHYADDR for memory encryption affect shadow 1144 * paging, too. 1145 * 1146 * If TDP is enabled but an explicit guest MAXPHYADDR is not 1147 * provided, use the raw bare metal MAXPHYADDR as reductions to 1148 * the HPAs do not affect GPAs. 1149 */ 1150 if (!tdp_enabled) 1151 g_phys_as = boot_cpu_data.x86_phys_bits; 1152 else if (!g_phys_as) 1153 g_phys_as = phys_as; 1154 1155 entry->eax = g_phys_as | (virt_as << 8); 1156 entry->edx = 0; 1157 cpuid_entry_override(entry, CPUID_8000_0008_EBX); 1158 break; 1159 } 1160 case 0x8000000A: 1161 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) { 1162 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1163 break; 1164 } 1165 entry->eax = 1; /* SVM revision 1 */ 1166 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper 1167 ASID emulation to nested SVM */ 1168 entry->ecx = 0; /* Reserved */ 1169 cpuid_entry_override(entry, CPUID_8000_000A_EDX); 1170 break; 1171 case 0x80000019: 1172 entry->ecx = entry->edx = 0; 1173 break; 1174 case 0x8000001a: 1175 case 0x8000001e: 1176 break; 1177 case 0x8000001F: 1178 if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) { 1179 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1180 } else { 1181 cpuid_entry_override(entry, CPUID_8000_001F_EAX); 1182 1183 /* 1184 * Enumerate '0' for "PA bits reduction", the adjusted 1185 * MAXPHYADDR is enumerated directly (see 0x80000008). 1186 */ 1187 entry->ebx &= ~GENMASK(11, 6); 1188 } 1189 break; 1190 case 0x80000020: 1191 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1192 break; 1193 case 0x80000021: 1194 entry->ebx = entry->ecx = entry->edx = 0; 1195 /* 1196 * Pass down these bits: 1197 * EAX 0 NNDBP, Processor ignores nested data breakpoints 1198 * EAX 2 LAS, LFENCE always serializing 1199 * EAX 6 NSCB, Null selector clear base 1200 * 1201 * Other defined bits are for MSRs that KVM does not expose: 1202 * EAX 3 SPCL, SMM page configuration lock 1203 * EAX 13 PCMSR, Prefetch control MSR 1204 */ 1205 entry->eax &= BIT(0) | BIT(2) | BIT(6); 1206 if (static_cpu_has(X86_FEATURE_LFENCE_RDTSC)) 1207 entry->eax |= BIT(2); 1208 if (!static_cpu_has_bug(X86_BUG_NULL_SEG)) 1209 entry->eax |= BIT(6); 1210 break; 1211 /*Add support for Centaur's CPUID instruction*/ 1212 case 0xC0000000: 1213 /*Just support up to 0xC0000004 now*/ 1214 entry->eax = min(entry->eax, 0xC0000004); 1215 break; 1216 case 0xC0000001: 1217 cpuid_entry_override(entry, CPUID_C000_0001_EDX); 1218 break; 1219 case 3: /* Processor serial number */ 1220 case 5: /* MONITOR/MWAIT */ 1221 case 0xC0000002: 1222 case 0xC0000003: 1223 case 0xC0000004: 1224 default: 1225 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1226 break; 1227 } 1228 1229 r = 0; 1230 1231 out: 1232 put_cpu(); 1233 1234 return r; 1235 } 1236 1237 static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func, 1238 unsigned int type) 1239 { 1240 if (type == KVM_GET_EMULATED_CPUID) 1241 return __do_cpuid_func_emulated(array, func); 1242 1243 return __do_cpuid_func(array, func); 1244 } 1245 1246 #define CENTAUR_CPUID_SIGNATURE 0xC0000000 1247 1248 static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func, 1249 unsigned int type) 1250 { 1251 u32 limit; 1252 int r; 1253 1254 if (func == CENTAUR_CPUID_SIGNATURE && 1255 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR) 1256 return 0; 1257 1258 r = do_cpuid_func(array, func, type); 1259 if (r) 1260 return r; 1261 1262 limit = array->entries[array->nent - 1].eax; 1263 for (func = func + 1; func <= limit; ++func) { 1264 r = do_cpuid_func(array, func, type); 1265 if (r) 1266 break; 1267 } 1268 1269 return r; 1270 } 1271 1272 static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries, 1273 __u32 num_entries, unsigned int ioctl_type) 1274 { 1275 int i; 1276 __u32 pad[3]; 1277 1278 if (ioctl_type != KVM_GET_EMULATED_CPUID) 1279 return false; 1280 1281 /* 1282 * We want to make sure that ->padding is being passed clean from 1283 * userspace in case we want to use it for something in the future. 1284 * 1285 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we 1286 * have to give ourselves satisfied only with the emulated side. /me 1287 * sheds a tear. 1288 */ 1289 for (i = 0; i < num_entries; i++) { 1290 if (copy_from_user(pad, entries[i].padding, sizeof(pad))) 1291 return true; 1292 1293 if (pad[0] || pad[1] || pad[2]) 1294 return true; 1295 } 1296 return false; 1297 } 1298 1299 int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid, 1300 struct kvm_cpuid_entry2 __user *entries, 1301 unsigned int type) 1302 { 1303 static const u32 funcs[] = { 1304 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE, 1305 }; 1306 1307 struct kvm_cpuid_array array = { 1308 .nent = 0, 1309 }; 1310 int r, i; 1311 1312 if (cpuid->nent < 1) 1313 return -E2BIG; 1314 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 1315 cpuid->nent = KVM_MAX_CPUID_ENTRIES; 1316 1317 if (sanity_check_entries(entries, cpuid->nent, type)) 1318 return -EINVAL; 1319 1320 array.entries = kvcalloc(sizeof(struct kvm_cpuid_entry2), cpuid->nent, GFP_KERNEL); 1321 if (!array.entries) 1322 return -ENOMEM; 1323 1324 array.maxnent = cpuid->nent; 1325 1326 for (i = 0; i < ARRAY_SIZE(funcs); i++) { 1327 r = get_cpuid_func(&array, funcs[i], type); 1328 if (r) 1329 goto out_free; 1330 } 1331 cpuid->nent = array.nent; 1332 1333 if (copy_to_user(entries, array.entries, 1334 array.nent * sizeof(struct kvm_cpuid_entry2))) 1335 r = -EFAULT; 1336 1337 out_free: 1338 kvfree(array.entries); 1339 return r; 1340 } 1341 1342 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry_index(struct kvm_vcpu *vcpu, 1343 u32 function, u32 index) 1344 { 1345 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent, 1346 function, index); 1347 } 1348 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry_index); 1349 1350 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, 1351 u32 function) 1352 { 1353 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent, 1354 function, KVM_CPUID_INDEX_NOT_SIGNIFICANT); 1355 } 1356 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); 1357 1358 /* 1359 * Intel CPUID semantics treats any query for an out-of-range leaf as if the 1360 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics 1361 * returns all zeroes for any undefined leaf, whether or not the leaf is in 1362 * range. Centaur/VIA follows Intel semantics. 1363 * 1364 * A leaf is considered out-of-range if its function is higher than the maximum 1365 * supported leaf of its associated class or if its associated class does not 1366 * exist. 1367 * 1368 * There are three primary classes to be considered, with their respective 1369 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary 1370 * class exists if a guest CPUID entry for its <base> leaf exists. For a given 1371 * class, CPUID.<base>.EAX contains the max supported leaf for the class. 1372 * 1373 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff 1374 * - Hypervisor: 0x40000000 - 0x4fffffff 1375 * - Extended: 0x80000000 - 0xbfffffff 1376 * - Centaur: 0xc0000000 - 0xcfffffff 1377 * 1378 * The Hypervisor class is further subdivided into sub-classes that each act as 1379 * their own independent class associated with a 0x100 byte range. E.g. if Qemu 1380 * is advertising support for both HyperV and KVM, the resulting Hypervisor 1381 * CPUID sub-classes are: 1382 * 1383 * - HyperV: 0x40000000 - 0x400000ff 1384 * - KVM: 0x40000100 - 0x400001ff 1385 */ 1386 static struct kvm_cpuid_entry2 * 1387 get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index) 1388 { 1389 struct kvm_cpuid_entry2 *basic, *class; 1390 u32 function = *fn_ptr; 1391 1392 basic = kvm_find_cpuid_entry(vcpu, 0); 1393 if (!basic) 1394 return NULL; 1395 1396 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) || 1397 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx)) 1398 return NULL; 1399 1400 if (function >= 0x40000000 && function <= 0x4fffffff) 1401 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00); 1402 else if (function >= 0xc0000000) 1403 class = kvm_find_cpuid_entry(vcpu, 0xc0000000); 1404 else 1405 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000); 1406 1407 if (class && function <= class->eax) 1408 return NULL; 1409 1410 /* 1411 * Leaf specific adjustments are also applied when redirecting to the 1412 * max basic entry, e.g. if the max basic leaf is 0xb but there is no 1413 * entry for CPUID.0xb.index (see below), then the output value for EDX 1414 * needs to be pulled from CPUID.0xb.1. 1415 */ 1416 *fn_ptr = basic->eax; 1417 1418 /* 1419 * The class does not exist or the requested function is out of range; 1420 * the effective CPUID entry is the max basic leaf. Note, the index of 1421 * the original requested leaf is observed! 1422 */ 1423 return kvm_find_cpuid_entry_index(vcpu, basic->eax, index); 1424 } 1425 1426 bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx, 1427 u32 *ecx, u32 *edx, bool exact_only) 1428 { 1429 u32 orig_function = *eax, function = *eax, index = *ecx; 1430 struct kvm_cpuid_entry2 *entry; 1431 bool exact, used_max_basic = false; 1432 1433 entry = kvm_find_cpuid_entry_index(vcpu, function, index); 1434 exact = !!entry; 1435 1436 if (!entry && !exact_only) { 1437 entry = get_out_of_range_cpuid_entry(vcpu, &function, index); 1438 used_max_basic = !!entry; 1439 } 1440 1441 if (entry) { 1442 *eax = entry->eax; 1443 *ebx = entry->ebx; 1444 *ecx = entry->ecx; 1445 *edx = entry->edx; 1446 if (function == 7 && index == 0) { 1447 u64 data; 1448 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) && 1449 (data & TSX_CTRL_CPUID_CLEAR)) 1450 *ebx &= ~(F(RTM) | F(HLE)); 1451 } 1452 } else { 1453 *eax = *ebx = *ecx = *edx = 0; 1454 /* 1455 * When leaf 0BH or 1FH is defined, CL is pass-through 1456 * and EDX is always the x2APIC ID, even for undefined 1457 * subleaves. Index 1 will exist iff the leaf is 1458 * implemented, so we pass through CL iff leaf 1 1459 * exists. EDX can be copied from any existing index. 1460 */ 1461 if (function == 0xb || function == 0x1f) { 1462 entry = kvm_find_cpuid_entry_index(vcpu, function, 1); 1463 if (entry) { 1464 *ecx = index & 0xff; 1465 *edx = entry->edx; 1466 } 1467 } 1468 } 1469 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact, 1470 used_max_basic); 1471 return exact; 1472 } 1473 EXPORT_SYMBOL_GPL(kvm_cpuid); 1474 1475 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu) 1476 { 1477 u32 eax, ebx, ecx, edx; 1478 1479 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0)) 1480 return 1; 1481 1482 eax = kvm_rax_read(vcpu); 1483 ecx = kvm_rcx_read(vcpu); 1484 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false); 1485 kvm_rax_write(vcpu, eax); 1486 kvm_rbx_write(vcpu, ebx); 1487 kvm_rcx_write(vcpu, ecx); 1488 kvm_rdx_write(vcpu, edx); 1489 return kvm_skip_emulated_instruction(vcpu); 1490 } 1491 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); 1492