1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * cpuid support routines 5 * 6 * derived from arch/x86/kvm/x86.c 7 * 8 * Copyright 2011 Red Hat, Inc. and/or its affiliates. 9 * Copyright IBM Corporation, 2008 10 */ 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13 #include <linux/kvm_host.h> 14 #include "linux/lockdep.h" 15 #include <linux/export.h> 16 #include <linux/vmalloc.h> 17 #include <linux/uaccess.h> 18 #include <linux/sched/stat.h> 19 20 #include <asm/processor.h> 21 #include <asm/user.h> 22 #include <asm/fpu/xstate.h> 23 #include <asm/sgx.h> 24 #include <asm/cpuid.h> 25 #include "cpuid.h" 26 #include "lapic.h" 27 #include "mmu.h" 28 #include "trace.h" 29 #include "pmu.h" 30 #include "xen.h" 31 32 /* 33 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be 34 * aligned to sizeof(unsigned long) because it's not accessed via bitops. 35 */ 36 u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly; 37 EXPORT_SYMBOL_GPL(kvm_cpu_caps); 38 39 struct cpuid_xstate_sizes { 40 u32 eax; 41 u32 ebx; 42 u32 ecx; 43 }; 44 45 static struct cpuid_xstate_sizes xstate_sizes[XFEATURE_MAX] __ro_after_init; 46 47 void __init kvm_init_xstate_sizes(void) 48 { 49 u32 ign; 50 int i; 51 52 for (i = XFEATURE_YMM; i < ARRAY_SIZE(xstate_sizes); i++) { 53 struct cpuid_xstate_sizes *xs = &xstate_sizes[i]; 54 55 cpuid_count(0xD, i, &xs->eax, &xs->ebx, &xs->ecx, &ign); 56 } 57 } 58 59 u32 xstate_required_size(u64 xstate_bv, bool compacted) 60 { 61 int feature_bit = 0; 62 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 63 64 xstate_bv &= XFEATURE_MASK_EXTEND; 65 while (xstate_bv) { 66 if (xstate_bv & 0x1) { 67 struct cpuid_xstate_sizes *xs = &xstate_sizes[feature_bit]; 68 u32 offset; 69 70 /* ECX[1]: 64B alignment in compacted form */ 71 if (compacted) 72 offset = (xs->ecx & 0x2) ? ALIGN(ret, 64) : ret; 73 else 74 offset = xs->ebx; 75 ret = max(ret, offset + xs->eax); 76 } 77 78 xstate_bv >>= 1; 79 feature_bit++; 80 } 81 82 return ret; 83 } 84 85 /* 86 * Magic value used by KVM when querying userspace-provided CPUID entries and 87 * doesn't care about the CPIUD index because the index of the function in 88 * question is not significant. Note, this magic value must have at least one 89 * bit set in bits[63:32] and must be consumed as a u64 by cpuid_entry2_find() 90 * to avoid false positives when processing guest CPUID input. 91 */ 92 #define KVM_CPUID_INDEX_NOT_SIGNIFICANT -1ull 93 94 static struct kvm_cpuid_entry2 *cpuid_entry2_find(struct kvm_vcpu *vcpu, 95 u32 function, u64 index) 96 { 97 struct kvm_cpuid_entry2 *e; 98 int i; 99 100 /* 101 * KVM has a semi-arbitrary rule that querying the guest's CPUID model 102 * with IRQs disabled is disallowed. The CPUID model can legitimately 103 * have over one hundred entries, i.e. the lookup is slow, and IRQs are 104 * typically disabled in KVM only when KVM is in a performance critical 105 * path, e.g. the core VM-Enter/VM-Exit run loop. Nothing will break 106 * if this rule is violated, this assertion is purely to flag potential 107 * performance issues. If this fires, consider moving the lookup out 108 * of the hotpath, e.g. by caching information during CPUID updates. 109 */ 110 lockdep_assert_irqs_enabled(); 111 112 for (i = 0; i < vcpu->arch.cpuid_nent; i++) { 113 e = &vcpu->arch.cpuid_entries[i]; 114 115 if (e->function != function) 116 continue; 117 118 /* 119 * If the index isn't significant, use the first entry with a 120 * matching function. It's userspace's responsibility to not 121 * provide "duplicate" entries in all cases. 122 */ 123 if (!(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) || e->index == index) 124 return e; 125 126 127 /* 128 * Similarly, use the first matching entry if KVM is doing a 129 * lookup (as opposed to emulating CPUID) for a function that's 130 * architecturally defined as not having a significant index. 131 */ 132 if (index == KVM_CPUID_INDEX_NOT_SIGNIFICANT) { 133 /* 134 * Direct lookups from KVM should not diverge from what 135 * KVM defines internally (the architectural behavior). 136 */ 137 WARN_ON_ONCE(cpuid_function_is_indexed(function)); 138 return e; 139 } 140 } 141 142 return NULL; 143 } 144 145 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry_index(struct kvm_vcpu *vcpu, 146 u32 function, u32 index) 147 { 148 return cpuid_entry2_find(vcpu, function, index); 149 } 150 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry_index); 151 152 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, 153 u32 function) 154 { 155 return cpuid_entry2_find(vcpu, function, KVM_CPUID_INDEX_NOT_SIGNIFICANT); 156 } 157 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); 158 159 /* 160 * cpuid_entry2_find() and KVM_CPUID_INDEX_NOT_SIGNIFICANT should never be used 161 * directly outside of kvm_find_cpuid_entry() and kvm_find_cpuid_entry_index(). 162 */ 163 #undef KVM_CPUID_INDEX_NOT_SIGNIFICANT 164 165 static int kvm_check_cpuid(struct kvm_vcpu *vcpu) 166 { 167 struct kvm_cpuid_entry2 *best; 168 u64 xfeatures; 169 170 /* 171 * The existing code assumes virtual address is 48-bit or 57-bit in the 172 * canonical address checks; exit if it is ever changed. 173 */ 174 best = kvm_find_cpuid_entry(vcpu, 0x80000008); 175 if (best) { 176 int vaddr_bits = (best->eax & 0xff00) >> 8; 177 178 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) 179 return -EINVAL; 180 } 181 182 /* 183 * Exposing dynamic xfeatures to the guest requires additional 184 * enabling in the FPU, e.g. to expand the guest XSAVE state size. 185 */ 186 best = kvm_find_cpuid_entry_index(vcpu, 0xd, 0); 187 if (!best) 188 return 0; 189 190 xfeatures = best->eax | ((u64)best->edx << 32); 191 xfeatures &= XFEATURE_MASK_USER_DYNAMIC; 192 if (!xfeatures) 193 return 0; 194 195 return fpu_enable_guest_xfd_features(&vcpu->arch.guest_fpu, xfeatures); 196 } 197 198 static u32 kvm_apply_cpuid_pv_features_quirk(struct kvm_vcpu *vcpu); 199 200 /* Check whether the supplied CPUID data is equal to what is already set for the vCPU. */ 201 static int kvm_cpuid_check_equal(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2, 202 int nent) 203 { 204 struct kvm_cpuid_entry2 *orig; 205 int i; 206 207 /* 208 * Apply runtime CPUID updates to the incoming CPUID entries to avoid 209 * false positives due mismatches on KVM-owned feature flags. 210 * 211 * Note! @e2 and @nent track the _old_ CPUID entries! 212 */ 213 kvm_update_cpuid_runtime(vcpu); 214 kvm_apply_cpuid_pv_features_quirk(vcpu); 215 216 if (nent != vcpu->arch.cpuid_nent) 217 return -EINVAL; 218 219 for (i = 0; i < nent; i++) { 220 orig = &vcpu->arch.cpuid_entries[i]; 221 if (e2[i].function != orig->function || 222 e2[i].index != orig->index || 223 e2[i].flags != orig->flags || 224 e2[i].eax != orig->eax || e2[i].ebx != orig->ebx || 225 e2[i].ecx != orig->ecx || e2[i].edx != orig->edx) 226 return -EINVAL; 227 } 228 229 return 0; 230 } 231 232 static struct kvm_hypervisor_cpuid kvm_get_hypervisor_cpuid(struct kvm_vcpu *vcpu, 233 const char *sig) 234 { 235 struct kvm_hypervisor_cpuid cpuid = {}; 236 struct kvm_cpuid_entry2 *entry; 237 u32 base; 238 239 for_each_possible_hypervisor_cpuid_base(base) { 240 entry = kvm_find_cpuid_entry(vcpu, base); 241 242 if (entry) { 243 u32 signature[3]; 244 245 signature[0] = entry->ebx; 246 signature[1] = entry->ecx; 247 signature[2] = entry->edx; 248 249 if (!memcmp(signature, sig, sizeof(signature))) { 250 cpuid.base = base; 251 cpuid.limit = entry->eax; 252 break; 253 } 254 } 255 } 256 257 return cpuid; 258 } 259 260 static u32 kvm_apply_cpuid_pv_features_quirk(struct kvm_vcpu *vcpu) 261 { 262 struct kvm_hypervisor_cpuid kvm_cpuid; 263 struct kvm_cpuid_entry2 *best; 264 265 kvm_cpuid = kvm_get_hypervisor_cpuid(vcpu, KVM_SIGNATURE); 266 if (!kvm_cpuid.base) 267 return 0; 268 269 best = kvm_find_cpuid_entry(vcpu, kvm_cpuid.base | KVM_CPUID_FEATURES); 270 if (!best) 271 return 0; 272 273 if (kvm_hlt_in_guest(vcpu->kvm)) 274 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT); 275 276 return best->eax; 277 } 278 279 /* 280 * Calculate guest's supported XCR0 taking into account guest CPUID data and 281 * KVM's supported XCR0 (comprised of host's XCR0 and KVM_SUPPORTED_XCR0). 282 */ 283 static u64 cpuid_get_supported_xcr0(struct kvm_vcpu *vcpu) 284 { 285 struct kvm_cpuid_entry2 *best; 286 287 best = kvm_find_cpuid_entry_index(vcpu, 0xd, 0); 288 if (!best) 289 return 0; 290 291 return (best->eax | ((u64)best->edx << 32)) & kvm_caps.supported_xcr0; 292 } 293 294 static __always_inline void kvm_update_feature_runtime(struct kvm_vcpu *vcpu, 295 struct kvm_cpuid_entry2 *entry, 296 unsigned int x86_feature, 297 bool has_feature) 298 { 299 cpuid_entry_change(entry, x86_feature, has_feature); 300 guest_cpu_cap_change(vcpu, x86_feature, has_feature); 301 } 302 303 void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu) 304 { 305 struct kvm_cpuid_entry2 *best; 306 307 best = kvm_find_cpuid_entry(vcpu, 1); 308 if (best) { 309 kvm_update_feature_runtime(vcpu, best, X86_FEATURE_OSXSAVE, 310 kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)); 311 312 kvm_update_feature_runtime(vcpu, best, X86_FEATURE_APIC, 313 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE); 314 315 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) 316 kvm_update_feature_runtime(vcpu, best, X86_FEATURE_MWAIT, 317 vcpu->arch.ia32_misc_enable_msr & 318 MSR_IA32_MISC_ENABLE_MWAIT); 319 } 320 321 best = kvm_find_cpuid_entry_index(vcpu, 7, 0); 322 if (best) 323 kvm_update_feature_runtime(vcpu, best, X86_FEATURE_OSPKE, 324 kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE)); 325 326 327 best = kvm_find_cpuid_entry_index(vcpu, 0xD, 0); 328 if (best) 329 best->ebx = xstate_required_size(vcpu->arch.xcr0, false); 330 331 best = kvm_find_cpuid_entry_index(vcpu, 0xD, 1); 332 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) || 333 cpuid_entry_has(best, X86_FEATURE_XSAVEC))) 334 best->ebx = xstate_required_size(vcpu->arch.xcr0, true); 335 } 336 EXPORT_SYMBOL_GPL(kvm_update_cpuid_runtime); 337 338 static bool kvm_cpuid_has_hyperv(struct kvm_vcpu *vcpu) 339 { 340 #ifdef CONFIG_KVM_HYPERV 341 struct kvm_cpuid_entry2 *entry; 342 343 entry = kvm_find_cpuid_entry(vcpu, HYPERV_CPUID_INTERFACE); 344 return entry && entry->eax == HYPERV_CPUID_SIGNATURE_EAX; 345 #else 346 return false; 347 #endif 348 } 349 350 static bool guest_cpuid_is_amd_or_hygon(struct kvm_vcpu *vcpu) 351 { 352 struct kvm_cpuid_entry2 *entry; 353 354 entry = kvm_find_cpuid_entry(vcpu, 0); 355 if (!entry) 356 return false; 357 358 return is_guest_vendor_amd(entry->ebx, entry->ecx, entry->edx) || 359 is_guest_vendor_hygon(entry->ebx, entry->ecx, entry->edx); 360 } 361 362 /* 363 * This isn't truly "unsafe", but except for the cpu_caps initialization code, 364 * all register lookups should use __cpuid_entry_get_reg(), which provides 365 * compile-time validation of the input. 366 */ 367 static u32 cpuid_get_reg_unsafe(struct kvm_cpuid_entry2 *entry, u32 reg) 368 { 369 switch (reg) { 370 case CPUID_EAX: 371 return entry->eax; 372 case CPUID_EBX: 373 return entry->ebx; 374 case CPUID_ECX: 375 return entry->ecx; 376 case CPUID_EDX: 377 return entry->edx; 378 default: 379 WARN_ON_ONCE(1); 380 return 0; 381 } 382 } 383 384 static int cpuid_func_emulated(struct kvm_cpuid_entry2 *entry, u32 func, 385 bool include_partially_emulated); 386 387 void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) 388 { 389 struct kvm_lapic *apic = vcpu->arch.apic; 390 struct kvm_cpuid_entry2 *best; 391 struct kvm_cpuid_entry2 *entry; 392 bool allow_gbpages; 393 int i; 394 395 memset(vcpu->arch.cpu_caps, 0, sizeof(vcpu->arch.cpu_caps)); 396 BUILD_BUG_ON(ARRAY_SIZE(reverse_cpuid) != NR_KVM_CPU_CAPS); 397 398 /* 399 * Reset guest capabilities to userspace's guest CPUID definition, i.e. 400 * honor userspace's definition for features that don't require KVM or 401 * hardware management/support (or that KVM simply doesn't care about). 402 */ 403 for (i = 0; i < NR_KVM_CPU_CAPS; i++) { 404 const struct cpuid_reg cpuid = reverse_cpuid[i]; 405 struct kvm_cpuid_entry2 emulated; 406 407 if (!cpuid.function) 408 continue; 409 410 entry = kvm_find_cpuid_entry_index(vcpu, cpuid.function, cpuid.index); 411 if (!entry) 412 continue; 413 414 cpuid_func_emulated(&emulated, cpuid.function, true); 415 416 /* 417 * A vCPU has a feature if it's supported by KVM and is enabled 418 * in guest CPUID. Note, this includes features that are 419 * supported by KVM but aren't advertised to userspace! 420 */ 421 vcpu->arch.cpu_caps[i] = kvm_cpu_caps[i] | 422 cpuid_get_reg_unsafe(&emulated, cpuid.reg); 423 vcpu->arch.cpu_caps[i] &= cpuid_get_reg_unsafe(entry, cpuid.reg); 424 } 425 426 kvm_update_cpuid_runtime(vcpu); 427 428 /* 429 * If TDP is enabled, let the guest use GBPAGES if they're supported in 430 * hardware. The hardware page walker doesn't let KVM disable GBPAGES, 431 * i.e. won't treat them as reserved, and KVM doesn't redo the GVA->GPA 432 * walk for performance and complexity reasons. Not to mention KVM 433 * _can't_ solve the problem because GVA->GPA walks aren't visible to 434 * KVM once a TDP translation is installed. Mimic hardware behavior so 435 * that KVM's is at least consistent, i.e. doesn't randomly inject #PF. 436 * If TDP is disabled, honor *only* guest CPUID as KVM has full control 437 * and can install smaller shadow pages if the host lacks 1GiB support. 438 */ 439 allow_gbpages = tdp_enabled ? boot_cpu_has(X86_FEATURE_GBPAGES) : 440 guest_cpu_cap_has(vcpu, X86_FEATURE_GBPAGES); 441 guest_cpu_cap_change(vcpu, X86_FEATURE_GBPAGES, allow_gbpages); 442 443 best = kvm_find_cpuid_entry(vcpu, 1); 444 if (best && apic) { 445 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER)) 446 apic->lapic_timer.timer_mode_mask = 3 << 17; 447 else 448 apic->lapic_timer.timer_mode_mask = 1 << 17; 449 450 kvm_apic_set_version(vcpu); 451 } 452 453 vcpu->arch.guest_supported_xcr0 = cpuid_get_supported_xcr0(vcpu); 454 455 vcpu->arch.pv_cpuid.features = kvm_apply_cpuid_pv_features_quirk(vcpu); 456 457 vcpu->arch.is_amd_compatible = guest_cpuid_is_amd_or_hygon(vcpu); 458 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 459 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 460 461 kvm_pmu_refresh(vcpu); 462 463 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f) 464 vcpu->arch.cr4_guest_rsvd_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_) | 465 __cr4_reserved_bits(guest_cpu_cap_has, vcpu); 466 #undef __kvm_cpu_cap_has 467 468 kvm_hv_set_cpuid(vcpu, kvm_cpuid_has_hyperv(vcpu)); 469 470 /* Invoke the vendor callback only after the above state is updated. */ 471 kvm_x86_call(vcpu_after_set_cpuid)(vcpu); 472 473 /* 474 * Except for the MMU, which needs to do its thing any vendor specific 475 * adjustments to the reserved GPA bits. 476 */ 477 kvm_mmu_after_set_cpuid(vcpu); 478 } 479 480 int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu) 481 { 482 struct kvm_cpuid_entry2 *best; 483 484 best = kvm_find_cpuid_entry(vcpu, 0x80000000); 485 if (!best || best->eax < 0x80000008) 486 goto not_found; 487 best = kvm_find_cpuid_entry(vcpu, 0x80000008); 488 if (best) 489 return best->eax & 0xff; 490 not_found: 491 return 36; 492 } 493 494 /* 495 * This "raw" version returns the reserved GPA bits without any adjustments for 496 * encryption technologies that usurp bits. The raw mask should be used if and 497 * only if hardware does _not_ strip the usurped bits, e.g. in virtual MTRRs. 498 */ 499 u64 kvm_vcpu_reserved_gpa_bits_raw(struct kvm_vcpu *vcpu) 500 { 501 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63); 502 } 503 504 static int kvm_set_cpuid(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2, 505 int nent) 506 { 507 u32 vcpu_caps[NR_KVM_CPU_CAPS]; 508 int r; 509 510 /* 511 * Swap the existing (old) entries with the incoming (new) entries in 512 * order to massage the new entries, e.g. to account for dynamic bits 513 * that KVM controls, without clobbering the current guest CPUID, which 514 * KVM needs to preserve in order to unwind on failure. 515 * 516 * Similarly, save the vCPU's current cpu_caps so that the capabilities 517 * can be updated alongside the CPUID entries when performing runtime 518 * updates. Full initialization is done if and only if the vCPU hasn't 519 * run, i.e. only if userspace is potentially changing CPUID features. 520 */ 521 swap(vcpu->arch.cpuid_entries, e2); 522 swap(vcpu->arch.cpuid_nent, nent); 523 524 memcpy(vcpu_caps, vcpu->arch.cpu_caps, sizeof(vcpu_caps)); 525 BUILD_BUG_ON(sizeof(vcpu_caps) != sizeof(vcpu->arch.cpu_caps)); 526 527 /* 528 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as 529 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't 530 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page 531 * faults due to reusing SPs/SPTEs. In practice no sane VMM mucks with 532 * the core vCPU model on the fly. It would've been better to forbid any 533 * KVM_SET_CPUID{,2} calls after KVM_RUN altogether but unfortunately 534 * some VMMs (e.g. QEMU) reuse vCPU fds for CPU hotplug/unplug and do 535 * KVM_SET_CPUID{,2} again. To support this legacy behavior, check 536 * whether the supplied CPUID data is equal to what's already set. 537 */ 538 if (kvm_vcpu_has_run(vcpu)) { 539 r = kvm_cpuid_check_equal(vcpu, e2, nent); 540 if (r) 541 goto err; 542 goto success; 543 } 544 545 #ifdef CONFIG_KVM_HYPERV 546 if (kvm_cpuid_has_hyperv(vcpu)) { 547 r = kvm_hv_vcpu_init(vcpu); 548 if (r) 549 goto err; 550 } 551 #endif 552 553 r = kvm_check_cpuid(vcpu); 554 if (r) 555 goto err; 556 557 #ifdef CONFIG_KVM_XEN 558 vcpu->arch.xen.cpuid = kvm_get_hypervisor_cpuid(vcpu, XEN_SIGNATURE); 559 #endif 560 kvm_vcpu_after_set_cpuid(vcpu); 561 562 success: 563 kvfree(e2); 564 return 0; 565 566 err: 567 memcpy(vcpu->arch.cpu_caps, vcpu_caps, sizeof(vcpu_caps)); 568 swap(vcpu->arch.cpuid_entries, e2); 569 swap(vcpu->arch.cpuid_nent, nent); 570 return r; 571 } 572 573 /* when an old userspace process fills a new kernel module */ 574 int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, 575 struct kvm_cpuid *cpuid, 576 struct kvm_cpuid_entry __user *entries) 577 { 578 int r, i; 579 struct kvm_cpuid_entry *e = NULL; 580 struct kvm_cpuid_entry2 *e2 = NULL; 581 582 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 583 return -E2BIG; 584 585 if (cpuid->nent) { 586 e = vmemdup_array_user(entries, cpuid->nent, sizeof(*e)); 587 if (IS_ERR(e)) 588 return PTR_ERR(e); 589 590 e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT); 591 if (!e2) { 592 r = -ENOMEM; 593 goto out_free_cpuid; 594 } 595 } 596 for (i = 0; i < cpuid->nent; i++) { 597 e2[i].function = e[i].function; 598 e2[i].eax = e[i].eax; 599 e2[i].ebx = e[i].ebx; 600 e2[i].ecx = e[i].ecx; 601 e2[i].edx = e[i].edx; 602 e2[i].index = 0; 603 e2[i].flags = 0; 604 e2[i].padding[0] = 0; 605 e2[i].padding[1] = 0; 606 e2[i].padding[2] = 0; 607 } 608 609 r = kvm_set_cpuid(vcpu, e2, cpuid->nent); 610 if (r) 611 kvfree(e2); 612 613 out_free_cpuid: 614 kvfree(e); 615 616 return r; 617 } 618 619 int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, 620 struct kvm_cpuid2 *cpuid, 621 struct kvm_cpuid_entry2 __user *entries) 622 { 623 struct kvm_cpuid_entry2 *e2 = NULL; 624 int r; 625 626 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 627 return -E2BIG; 628 629 if (cpuid->nent) { 630 e2 = vmemdup_array_user(entries, cpuid->nent, sizeof(*e2)); 631 if (IS_ERR(e2)) 632 return PTR_ERR(e2); 633 } 634 635 r = kvm_set_cpuid(vcpu, e2, cpuid->nent); 636 if (r) 637 kvfree(e2); 638 639 return r; 640 } 641 642 int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, 643 struct kvm_cpuid2 *cpuid, 644 struct kvm_cpuid_entry2 __user *entries) 645 { 646 if (cpuid->nent < vcpu->arch.cpuid_nent) 647 return -E2BIG; 648 649 if (copy_to_user(entries, vcpu->arch.cpuid_entries, 650 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) 651 return -EFAULT; 652 653 cpuid->nent = vcpu->arch.cpuid_nent; 654 return 0; 655 } 656 657 static __always_inline u32 raw_cpuid_get(struct cpuid_reg cpuid) 658 { 659 struct kvm_cpuid_entry2 entry; 660 u32 base; 661 662 /* 663 * KVM only supports features defined by Intel (0x0), AMD (0x80000000), 664 * and Centaur (0xc0000000). WARN if a feature for new vendor base is 665 * defined, as this and other code would need to be updated. 666 */ 667 base = cpuid.function & 0xffff0000; 668 if (WARN_ON_ONCE(base && base != 0x80000000 && base != 0xc0000000)) 669 return 0; 670 671 if (cpuid_eax(base) < cpuid.function) 672 return 0; 673 674 cpuid_count(cpuid.function, cpuid.index, 675 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx); 676 677 return *__cpuid_entry_get_reg(&entry, cpuid.reg); 678 } 679 680 /* 681 * For kernel-defined leafs, mask KVM's supported feature set with the kernel's 682 * capabilities as well as raw CPUID. For KVM-defined leafs, consult only raw 683 * CPUID, as KVM is the one and only authority (in the kernel). 684 */ 685 #define kvm_cpu_cap_init(leaf, feature_initializers...) \ 686 do { \ 687 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32); \ 688 const u32 __maybe_unused kvm_cpu_cap_init_in_progress = leaf; \ 689 const u32 *kernel_cpu_caps = boot_cpu_data.x86_capability; \ 690 u32 kvm_cpu_cap_passthrough = 0; \ 691 u32 kvm_cpu_cap_synthesized = 0; \ 692 u32 kvm_cpu_cap_emulated = 0; \ 693 u32 kvm_cpu_cap_features = 0; \ 694 \ 695 feature_initializers \ 696 \ 697 kvm_cpu_caps[leaf] = kvm_cpu_cap_features; \ 698 \ 699 if (leaf < NCAPINTS) \ 700 kvm_cpu_caps[leaf] &= kernel_cpu_caps[leaf]; \ 701 \ 702 kvm_cpu_caps[leaf] |= kvm_cpu_cap_passthrough; \ 703 kvm_cpu_caps[leaf] &= (raw_cpuid_get(cpuid) | \ 704 kvm_cpu_cap_synthesized); \ 705 kvm_cpu_caps[leaf] |= kvm_cpu_cap_emulated; \ 706 } while (0) 707 708 /* 709 * Assert that the feature bit being declared, e.g. via F(), is in the CPUID 710 * word that's being initialized. Exempt 0x8000_0001.EDX usage of 0x1.EDX 711 * features, as AMD duplicated many 0x1.EDX features into 0x8000_0001.EDX. 712 */ 713 #define KVM_VALIDATE_CPU_CAP_USAGE(name) \ 714 do { \ 715 u32 __leaf = __feature_leaf(X86_FEATURE_##name); \ 716 \ 717 BUILD_BUG_ON(__leaf != kvm_cpu_cap_init_in_progress); \ 718 } while (0) 719 720 #define F(name) \ 721 ({ \ 722 KVM_VALIDATE_CPU_CAP_USAGE(name); \ 723 kvm_cpu_cap_features |= feature_bit(name); \ 724 }) 725 726 /* Scattered Flag - For features that are scattered by cpufeatures.h. */ 727 #define SCATTERED_F(name) \ 728 ({ \ 729 BUILD_BUG_ON(X86_FEATURE_##name >= MAX_CPU_FEATURES); \ 730 KVM_VALIDATE_CPU_CAP_USAGE(name); \ 731 if (boot_cpu_has(X86_FEATURE_##name)) \ 732 F(name); \ 733 }) 734 735 /* Features that KVM supports only on 64-bit kernels. */ 736 #define X86_64_F(name) \ 737 ({ \ 738 KVM_VALIDATE_CPU_CAP_USAGE(name); \ 739 if (IS_ENABLED(CONFIG_X86_64)) \ 740 F(name); \ 741 }) 742 743 /* 744 * Emulated Feature - For features that KVM emulates in software irrespective 745 * of host CPU/kernel support. 746 */ 747 #define EMULATED_F(name) \ 748 ({ \ 749 kvm_cpu_cap_emulated |= feature_bit(name); \ 750 F(name); \ 751 }) 752 753 /* 754 * Synthesized Feature - For features that are synthesized into boot_cpu_data, 755 * i.e. may not be present in the raw CPUID, but can still be advertised to 756 * userspace. Primarily used for mitigation related feature flags. 757 */ 758 #define SYNTHESIZED_F(name) \ 759 ({ \ 760 kvm_cpu_cap_synthesized |= feature_bit(name); \ 761 F(name); \ 762 }) 763 764 /* 765 * Passthrough Feature - For features that KVM supports based purely on raw 766 * hardware CPUID, i.e. that KVM virtualizes even if the host kernel doesn't 767 * use the feature. Simply force set the feature in KVM's capabilities, raw 768 * CPUID support will be factored in by kvm_cpu_cap_mask(). 769 */ 770 #define PASSTHROUGH_F(name) \ 771 ({ \ 772 kvm_cpu_cap_passthrough |= feature_bit(name); \ 773 F(name); \ 774 }) 775 776 /* 777 * Aliased Features - For features in 0x8000_0001.EDX that are duplicates of 778 * identical 0x1.EDX features, and thus are aliased from 0x1 to 0x8000_0001. 779 */ 780 #define ALIASED_1_EDX_F(name) \ 781 ({ \ 782 BUILD_BUG_ON(__feature_leaf(X86_FEATURE_##name) != CPUID_1_EDX); \ 783 BUILD_BUG_ON(kvm_cpu_cap_init_in_progress != CPUID_8000_0001_EDX); \ 784 kvm_cpu_cap_features |= feature_bit(name); \ 785 }) 786 787 /* 788 * Vendor Features - For features that KVM supports, but are added in later 789 * because they require additional vendor enabling. 790 */ 791 #define VENDOR_F(name) \ 792 ({ \ 793 KVM_VALIDATE_CPU_CAP_USAGE(name); \ 794 }) 795 796 /* 797 * Runtime Features - For features that KVM dynamically sets/clears at runtime, 798 * e.g. when CR4 changes, but which are never advertised to userspace. 799 */ 800 #define RUNTIME_F(name) \ 801 ({ \ 802 KVM_VALIDATE_CPU_CAP_USAGE(name); \ 803 }) 804 805 /* 806 * Undefine the MSR bit macro to avoid token concatenation issues when 807 * processing X86_FEATURE_SPEC_CTRL_SSBD. 808 */ 809 #undef SPEC_CTRL_SSBD 810 811 /* DS is defined by ptrace-abi.h on 32-bit builds. */ 812 #undef DS 813 814 void kvm_set_cpu_caps(void) 815 { 816 memset(kvm_cpu_caps, 0, sizeof(kvm_cpu_caps)); 817 818 BUILD_BUG_ON(sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)) > 819 sizeof(boot_cpu_data.x86_capability)); 820 821 kvm_cpu_cap_init(CPUID_1_ECX, 822 F(XMM3), 823 F(PCLMULQDQ), 824 VENDOR_F(DTES64), 825 /* 826 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not* 827 * advertised to guests via CPUID! MWAIT is also technically a 828 * runtime flag thanks to IA32_MISC_ENABLES; mark it as such so 829 * that KVM is aware that it's a known, unadvertised flag. 830 */ 831 RUNTIME_F(MWAIT), 832 /* DS-CPL */ 833 VENDOR_F(VMX), 834 /* SMX, EST */ 835 /* TM2 */ 836 F(SSSE3), 837 /* CNXT-ID */ 838 /* Reserved */ 839 F(FMA), 840 F(CX16), 841 /* xTPR Update */ 842 F(PDCM), 843 F(PCID), 844 /* Reserved, DCA */ 845 F(XMM4_1), 846 F(XMM4_2), 847 EMULATED_F(X2APIC), 848 F(MOVBE), 849 F(POPCNT), 850 EMULATED_F(TSC_DEADLINE_TIMER), 851 F(AES), 852 F(XSAVE), 853 RUNTIME_F(OSXSAVE), 854 F(AVX), 855 F(F16C), 856 F(RDRAND), 857 EMULATED_F(HYPERVISOR), 858 ); 859 860 kvm_cpu_cap_init(CPUID_1_EDX, 861 F(FPU), 862 F(VME), 863 F(DE), 864 F(PSE), 865 F(TSC), 866 F(MSR), 867 F(PAE), 868 F(MCE), 869 F(CX8), 870 F(APIC), 871 /* Reserved */ 872 F(SEP), 873 F(MTRR), 874 F(PGE), 875 F(MCA), 876 F(CMOV), 877 F(PAT), 878 F(PSE36), 879 /* PSN */ 880 F(CLFLUSH), 881 /* Reserved */ 882 VENDOR_F(DS), 883 /* ACPI */ 884 F(MMX), 885 F(FXSR), 886 F(XMM), 887 F(XMM2), 888 F(SELFSNOOP), 889 /* HTT, TM, Reserved, PBE */ 890 ); 891 892 kvm_cpu_cap_init(CPUID_7_0_EBX, 893 F(FSGSBASE), 894 EMULATED_F(TSC_ADJUST), 895 F(SGX), 896 F(BMI1), 897 F(HLE), 898 F(AVX2), 899 F(FDP_EXCPTN_ONLY), 900 F(SMEP), 901 F(BMI2), 902 F(ERMS), 903 F(INVPCID), 904 F(RTM), 905 F(ZERO_FCS_FDS), 906 VENDOR_F(MPX), 907 F(AVX512F), 908 F(AVX512DQ), 909 F(RDSEED), 910 F(ADX), 911 F(SMAP), 912 F(AVX512IFMA), 913 F(CLFLUSHOPT), 914 F(CLWB), 915 VENDOR_F(INTEL_PT), 916 F(AVX512PF), 917 F(AVX512ER), 918 F(AVX512CD), 919 F(SHA_NI), 920 F(AVX512BW), 921 F(AVX512VL), 922 ); 923 924 kvm_cpu_cap_init(CPUID_7_ECX, 925 F(AVX512VBMI), 926 PASSTHROUGH_F(LA57), 927 F(PKU), 928 RUNTIME_F(OSPKE), 929 F(RDPID), 930 F(AVX512_VPOPCNTDQ), 931 F(UMIP), 932 F(AVX512_VBMI2), 933 F(GFNI), 934 F(VAES), 935 F(VPCLMULQDQ), 936 F(AVX512_VNNI), 937 F(AVX512_BITALG), 938 F(CLDEMOTE), 939 F(MOVDIRI), 940 F(MOVDIR64B), 941 VENDOR_F(WAITPKG), 942 F(SGX_LC), 943 F(BUS_LOCK_DETECT), 944 ); 945 946 /* 947 * PKU not yet implemented for shadow paging and requires OSPKE 948 * to be set on the host. Clear it if that is not the case 949 */ 950 if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE)) 951 kvm_cpu_cap_clear(X86_FEATURE_PKU); 952 953 kvm_cpu_cap_init(CPUID_7_EDX, 954 F(AVX512_4VNNIW), 955 F(AVX512_4FMAPS), 956 F(SPEC_CTRL), 957 F(SPEC_CTRL_SSBD), 958 EMULATED_F(ARCH_CAPABILITIES), 959 F(INTEL_STIBP), 960 F(MD_CLEAR), 961 F(AVX512_VP2INTERSECT), 962 F(FSRM), 963 F(SERIALIZE), 964 F(TSXLDTRK), 965 F(AVX512_FP16), 966 F(AMX_TILE), 967 F(AMX_INT8), 968 F(AMX_BF16), 969 F(FLUSH_L1D), 970 ); 971 972 if (boot_cpu_has(X86_FEATURE_AMD_IBPB_RET) && 973 boot_cpu_has(X86_FEATURE_AMD_IBPB) && 974 boot_cpu_has(X86_FEATURE_AMD_IBRS)) 975 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL); 976 if (boot_cpu_has(X86_FEATURE_STIBP)) 977 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); 978 if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) 979 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); 980 981 kvm_cpu_cap_init(CPUID_7_1_EAX, 982 F(SHA512), 983 F(SM3), 984 F(SM4), 985 F(AVX_VNNI), 986 F(AVX512_BF16), 987 F(CMPCCXADD), 988 F(FZRM), 989 F(FSRS), 990 F(FSRC), 991 F(AMX_FP16), 992 F(AVX_IFMA), 993 F(LAM), 994 ); 995 996 kvm_cpu_cap_init(CPUID_7_1_EDX, 997 F(AVX_VNNI_INT8), 998 F(AVX_NE_CONVERT), 999 F(AMX_COMPLEX), 1000 F(AVX_VNNI_INT16), 1001 F(PREFETCHITI), 1002 F(AVX10), 1003 ); 1004 1005 kvm_cpu_cap_init(CPUID_7_2_EDX, 1006 F(INTEL_PSFD), 1007 F(IPRED_CTRL), 1008 F(RRSBA_CTRL), 1009 F(DDPD_U), 1010 F(BHI_CTRL), 1011 F(MCDT_NO), 1012 ); 1013 1014 kvm_cpu_cap_init(CPUID_D_1_EAX, 1015 F(XSAVEOPT), 1016 F(XSAVEC), 1017 F(XGETBV1), 1018 F(XSAVES), 1019 X86_64_F(XFD), 1020 ); 1021 1022 kvm_cpu_cap_init(CPUID_12_EAX, 1023 SCATTERED_F(SGX1), 1024 SCATTERED_F(SGX2), 1025 SCATTERED_F(SGX_EDECCSSA), 1026 ); 1027 1028 kvm_cpu_cap_init(CPUID_24_0_EBX, 1029 F(AVX10_128), 1030 F(AVX10_256), 1031 F(AVX10_512), 1032 ); 1033 1034 kvm_cpu_cap_init(CPUID_8000_0001_ECX, 1035 F(LAHF_LM), 1036 F(CMP_LEGACY), 1037 VENDOR_F(SVM), 1038 /* ExtApicSpace */ 1039 F(CR8_LEGACY), 1040 F(ABM), 1041 F(SSE4A), 1042 F(MISALIGNSSE), 1043 F(3DNOWPREFETCH), 1044 F(OSVW), 1045 /* IBS */ 1046 F(XOP), 1047 /* SKINIT, WDT, LWP */ 1048 F(FMA4), 1049 F(TBM), 1050 F(TOPOEXT), 1051 VENDOR_F(PERFCTR_CORE), 1052 ); 1053 1054 kvm_cpu_cap_init(CPUID_8000_0001_EDX, 1055 ALIASED_1_EDX_F(FPU), 1056 ALIASED_1_EDX_F(VME), 1057 ALIASED_1_EDX_F(DE), 1058 ALIASED_1_EDX_F(PSE), 1059 ALIASED_1_EDX_F(TSC), 1060 ALIASED_1_EDX_F(MSR), 1061 ALIASED_1_EDX_F(PAE), 1062 ALIASED_1_EDX_F(MCE), 1063 ALIASED_1_EDX_F(CX8), 1064 ALIASED_1_EDX_F(APIC), 1065 /* Reserved */ 1066 F(SYSCALL), 1067 ALIASED_1_EDX_F(MTRR), 1068 ALIASED_1_EDX_F(PGE), 1069 ALIASED_1_EDX_F(MCA), 1070 ALIASED_1_EDX_F(CMOV), 1071 ALIASED_1_EDX_F(PAT), 1072 ALIASED_1_EDX_F(PSE36), 1073 /* Reserved */ 1074 F(NX), 1075 /* Reserved */ 1076 F(MMXEXT), 1077 ALIASED_1_EDX_F(MMX), 1078 ALIASED_1_EDX_F(FXSR), 1079 F(FXSR_OPT), 1080 X86_64_F(GBPAGES), 1081 F(RDTSCP), 1082 /* Reserved */ 1083 X86_64_F(LM), 1084 F(3DNOWEXT), 1085 F(3DNOW), 1086 ); 1087 1088 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64)) 1089 kvm_cpu_cap_set(X86_FEATURE_GBPAGES); 1090 1091 kvm_cpu_cap_init(CPUID_8000_0007_EDX, 1092 SCATTERED_F(CONSTANT_TSC), 1093 ); 1094 1095 kvm_cpu_cap_init(CPUID_8000_0008_EBX, 1096 F(CLZERO), 1097 F(XSAVEERPTR), 1098 F(WBNOINVD), 1099 F(AMD_IBPB), 1100 F(AMD_IBRS), 1101 F(AMD_SSBD), 1102 F(VIRT_SSBD), 1103 F(AMD_SSB_NO), 1104 F(AMD_STIBP), 1105 F(AMD_STIBP_ALWAYS_ON), 1106 F(AMD_PSFD), 1107 F(AMD_IBPB_RET), 1108 ); 1109 1110 /* 1111 * AMD has separate bits for each SPEC_CTRL bit. 1112 * arch/x86/kernel/cpu/bugs.c is kind enough to 1113 * record that in cpufeatures so use them. 1114 */ 1115 if (boot_cpu_has(X86_FEATURE_IBPB)) { 1116 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB); 1117 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL) && 1118 !boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) 1119 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB_RET); 1120 } 1121 if (boot_cpu_has(X86_FEATURE_IBRS)) 1122 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS); 1123 if (boot_cpu_has(X86_FEATURE_STIBP)) 1124 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP); 1125 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) 1126 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD); 1127 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 1128 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO); 1129 /* 1130 * The preference is to use SPEC CTRL MSR instead of the 1131 * VIRT_SPEC MSR. 1132 */ 1133 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) && 1134 !boot_cpu_has(X86_FEATURE_AMD_SSBD)) 1135 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); 1136 1137 /* All SVM features required additional vendor module enabling. */ 1138 kvm_cpu_cap_init(CPUID_8000_000A_EDX, 1139 VENDOR_F(NPT), 1140 VENDOR_F(VMCBCLEAN), 1141 VENDOR_F(FLUSHBYASID), 1142 VENDOR_F(NRIPS), 1143 VENDOR_F(TSCRATEMSR), 1144 VENDOR_F(V_VMSAVE_VMLOAD), 1145 VENDOR_F(LBRV), 1146 VENDOR_F(PAUSEFILTER), 1147 VENDOR_F(PFTHRESHOLD), 1148 VENDOR_F(VGIF), 1149 VENDOR_F(VNMI), 1150 VENDOR_F(SVME_ADDR_CHK), 1151 ); 1152 1153 kvm_cpu_cap_init(CPUID_8000_001F_EAX, 1154 VENDOR_F(SME), 1155 VENDOR_F(SEV), 1156 /* VM_PAGE_FLUSH */ 1157 VENDOR_F(SEV_ES), 1158 F(SME_COHERENT), 1159 ); 1160 1161 kvm_cpu_cap_init(CPUID_8000_0021_EAX, 1162 F(NO_NESTED_DATA_BP), 1163 /* 1164 * Synthesize "LFENCE is serializing" into the AMD-defined entry 1165 * in KVM's supported CPUID, i.e. if the feature is reported as 1166 * supported by the kernel. LFENCE_RDTSC was a Linux-defined 1167 * synthetic feature long before AMD joined the bandwagon, e.g. 1168 * LFENCE is serializing on most CPUs that support SSE2. On 1169 * CPUs that don't support AMD's leaf, ANDing with the raw host 1170 * CPUID will drop the flags, and reporting support in AMD's 1171 * leaf can make it easier for userspace to detect the feature. 1172 */ 1173 SYNTHESIZED_F(LFENCE_RDTSC), 1174 /* SmmPgCfgLock */ 1175 F(NULL_SEL_CLR_BASE), 1176 F(AUTOIBRS), 1177 EMULATED_F(NO_SMM_CTL_MSR), 1178 /* PrefetchCtlMsr */ 1179 F(WRMSR_XX_BASE_NS), 1180 SYNTHESIZED_F(SBPB), 1181 SYNTHESIZED_F(IBPB_BRTYPE), 1182 SYNTHESIZED_F(SRSO_NO), 1183 F(SRSO_USER_KERNEL_NO), 1184 ); 1185 1186 kvm_cpu_cap_init(CPUID_8000_0022_EAX, 1187 F(PERFMON_V2), 1188 ); 1189 1190 if (!static_cpu_has_bug(X86_BUG_NULL_SEG)) 1191 kvm_cpu_cap_set(X86_FEATURE_NULL_SEL_CLR_BASE); 1192 1193 kvm_cpu_cap_init(CPUID_C000_0001_EDX, 1194 F(XSTORE), 1195 F(XSTORE_EN), 1196 F(XCRYPT), 1197 F(XCRYPT_EN), 1198 F(ACE2), 1199 F(ACE2_EN), 1200 F(PHE), 1201 F(PHE_EN), 1202 F(PMM), 1203 F(PMM_EN), 1204 ); 1205 1206 /* 1207 * Hide RDTSCP and RDPID if either feature is reported as supported but 1208 * probing MSR_TSC_AUX failed. This is purely a sanity check and 1209 * should never happen, but the guest will likely crash if RDTSCP or 1210 * RDPID is misreported, and KVM has botched MSR_TSC_AUX emulation in 1211 * the past. For example, the sanity check may fire if this instance of 1212 * KVM is running as L1 on top of an older, broken KVM. 1213 */ 1214 if (WARN_ON((kvm_cpu_cap_has(X86_FEATURE_RDTSCP) || 1215 kvm_cpu_cap_has(X86_FEATURE_RDPID)) && 1216 !kvm_is_supported_user_return_msr(MSR_TSC_AUX))) { 1217 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP); 1218 kvm_cpu_cap_clear(X86_FEATURE_RDPID); 1219 } 1220 } 1221 EXPORT_SYMBOL_GPL(kvm_set_cpu_caps); 1222 1223 #undef F 1224 #undef SCATTERED_F 1225 #undef X86_64_F 1226 #undef EMULATED_F 1227 #undef SYNTHESIZED_F 1228 #undef PASSTHROUGH_F 1229 #undef ALIASED_1_EDX_F 1230 #undef VENDOR_F 1231 #undef RUNTIME_F 1232 1233 struct kvm_cpuid_array { 1234 struct kvm_cpuid_entry2 *entries; 1235 int maxnent; 1236 int nent; 1237 }; 1238 1239 static struct kvm_cpuid_entry2 *get_next_cpuid(struct kvm_cpuid_array *array) 1240 { 1241 if (array->nent >= array->maxnent) 1242 return NULL; 1243 1244 return &array->entries[array->nent++]; 1245 } 1246 1247 static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array, 1248 u32 function, u32 index) 1249 { 1250 struct kvm_cpuid_entry2 *entry = get_next_cpuid(array); 1251 1252 if (!entry) 1253 return NULL; 1254 1255 memset(entry, 0, sizeof(*entry)); 1256 entry->function = function; 1257 entry->index = index; 1258 switch (function & 0xC0000000) { 1259 case 0x40000000: 1260 /* Hypervisor leaves are always synthesized by __do_cpuid_func. */ 1261 return entry; 1262 1263 case 0x80000000: 1264 /* 1265 * 0x80000021 is sometimes synthesized by __do_cpuid_func, which 1266 * would result in out-of-bounds calls to do_host_cpuid. 1267 */ 1268 { 1269 static int max_cpuid_80000000; 1270 if (!READ_ONCE(max_cpuid_80000000)) 1271 WRITE_ONCE(max_cpuid_80000000, cpuid_eax(0x80000000)); 1272 if (function > READ_ONCE(max_cpuid_80000000)) 1273 return entry; 1274 } 1275 break; 1276 1277 default: 1278 break; 1279 } 1280 1281 cpuid_count(entry->function, entry->index, 1282 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); 1283 1284 if (cpuid_function_is_indexed(function)) 1285 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 1286 1287 return entry; 1288 } 1289 1290 static int cpuid_func_emulated(struct kvm_cpuid_entry2 *entry, u32 func, 1291 bool include_partially_emulated) 1292 { 1293 memset(entry, 0, sizeof(*entry)); 1294 1295 entry->function = func; 1296 entry->index = 0; 1297 entry->flags = 0; 1298 1299 switch (func) { 1300 case 0: 1301 entry->eax = 7; 1302 return 1; 1303 case 1: 1304 entry->ecx = feature_bit(MOVBE); 1305 /* 1306 * KVM allows userspace to enumerate MONITOR+MWAIT support to 1307 * the guest, but the MWAIT feature flag is never advertised 1308 * to userspace because MONITOR+MWAIT aren't virtualized by 1309 * hardware, can't be faithfully emulated in software (KVM 1310 * emulates them as NOPs), and allowing the guest to execute 1311 * them natively requires enabling a per-VM capability. 1312 */ 1313 if (include_partially_emulated) 1314 entry->ecx |= feature_bit(MWAIT); 1315 return 1; 1316 case 7: 1317 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 1318 entry->eax = 0; 1319 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) 1320 entry->ecx = feature_bit(RDPID); 1321 return 1; 1322 default: 1323 return 0; 1324 } 1325 } 1326 1327 static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func) 1328 { 1329 if (array->nent >= array->maxnent) 1330 return -E2BIG; 1331 1332 array->nent += cpuid_func_emulated(&array->entries[array->nent], func, false); 1333 return 0; 1334 } 1335 1336 static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) 1337 { 1338 struct kvm_cpuid_entry2 *entry; 1339 int r, i, max_idx; 1340 1341 /* all calls to cpuid_count() should be made on the same cpu */ 1342 get_cpu(); 1343 1344 r = -E2BIG; 1345 1346 entry = do_host_cpuid(array, function, 0); 1347 if (!entry) 1348 goto out; 1349 1350 switch (function) { 1351 case 0: 1352 /* Limited to the highest leaf implemented in KVM. */ 1353 entry->eax = min(entry->eax, 0x24U); 1354 break; 1355 case 1: 1356 cpuid_entry_override(entry, CPUID_1_EDX); 1357 cpuid_entry_override(entry, CPUID_1_ECX); 1358 break; 1359 case 2: 1360 /* 1361 * On ancient CPUs, function 2 entries are STATEFUL. That is, 1362 * CPUID(function=2, index=0) may return different results each 1363 * time, with the least-significant byte in EAX enumerating the 1364 * number of times software should do CPUID(2, 0). 1365 * 1366 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less 1367 * idiotic. Intel's SDM states that EAX & 0xff "will always 1368 * return 01H. Software should ignore this value and not 1369 * interpret it as an informational descriptor", while AMD's 1370 * APM states that CPUID(2) is reserved. 1371 * 1372 * WARN if a frankenstein CPU that supports virtualization and 1373 * a stateful CPUID.0x2 is encountered. 1374 */ 1375 WARN_ON_ONCE((entry->eax & 0xff) > 1); 1376 break; 1377 /* functions 4 and 0x8000001d have additional index. */ 1378 case 4: 1379 case 0x8000001d: 1380 /* 1381 * Read entries until the cache type in the previous entry is 1382 * zero, i.e. indicates an invalid entry. 1383 */ 1384 for (i = 1; entry->eax & 0x1f; ++i) { 1385 entry = do_host_cpuid(array, function, i); 1386 if (!entry) 1387 goto out; 1388 } 1389 break; 1390 case 6: /* Thermal management */ 1391 entry->eax = 0x4; /* allow ARAT */ 1392 entry->ebx = 0; 1393 entry->ecx = 0; 1394 entry->edx = 0; 1395 break; 1396 /* function 7 has additional index. */ 1397 case 7: 1398 max_idx = entry->eax = min(entry->eax, 2u); 1399 cpuid_entry_override(entry, CPUID_7_0_EBX); 1400 cpuid_entry_override(entry, CPUID_7_ECX); 1401 cpuid_entry_override(entry, CPUID_7_EDX); 1402 1403 /* KVM only supports up to 0x7.2, capped above via min(). */ 1404 if (max_idx >= 1) { 1405 entry = do_host_cpuid(array, function, 1); 1406 if (!entry) 1407 goto out; 1408 1409 cpuid_entry_override(entry, CPUID_7_1_EAX); 1410 cpuid_entry_override(entry, CPUID_7_1_EDX); 1411 entry->ebx = 0; 1412 entry->ecx = 0; 1413 } 1414 if (max_idx >= 2) { 1415 entry = do_host_cpuid(array, function, 2); 1416 if (!entry) 1417 goto out; 1418 1419 cpuid_entry_override(entry, CPUID_7_2_EDX); 1420 entry->ecx = 0; 1421 entry->ebx = 0; 1422 entry->eax = 0; 1423 } 1424 break; 1425 case 0xa: { /* Architectural Performance Monitoring */ 1426 union cpuid10_eax eax; 1427 union cpuid10_edx edx; 1428 1429 if (!enable_pmu || !static_cpu_has(X86_FEATURE_ARCH_PERFMON)) { 1430 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1431 break; 1432 } 1433 1434 eax.split.version_id = kvm_pmu_cap.version; 1435 eax.split.num_counters = kvm_pmu_cap.num_counters_gp; 1436 eax.split.bit_width = kvm_pmu_cap.bit_width_gp; 1437 eax.split.mask_length = kvm_pmu_cap.events_mask_len; 1438 edx.split.num_counters_fixed = kvm_pmu_cap.num_counters_fixed; 1439 edx.split.bit_width_fixed = kvm_pmu_cap.bit_width_fixed; 1440 1441 if (kvm_pmu_cap.version) 1442 edx.split.anythread_deprecated = 1; 1443 edx.split.reserved1 = 0; 1444 edx.split.reserved2 = 0; 1445 1446 entry->eax = eax.full; 1447 entry->ebx = kvm_pmu_cap.events_mask; 1448 entry->ecx = 0; 1449 entry->edx = edx.full; 1450 break; 1451 } 1452 case 0x1f: 1453 case 0xb: 1454 /* 1455 * No topology; a valid topology is indicated by the presence 1456 * of subleaf 1. 1457 */ 1458 entry->eax = entry->ebx = entry->ecx = 0; 1459 break; 1460 case 0xd: { 1461 u64 permitted_xcr0 = kvm_get_filtered_xcr0(); 1462 u64 permitted_xss = kvm_caps.supported_xss; 1463 1464 entry->eax &= permitted_xcr0; 1465 entry->ebx = xstate_required_size(permitted_xcr0, false); 1466 entry->ecx = entry->ebx; 1467 entry->edx &= permitted_xcr0 >> 32; 1468 if (!permitted_xcr0) 1469 break; 1470 1471 entry = do_host_cpuid(array, function, 1); 1472 if (!entry) 1473 goto out; 1474 1475 cpuid_entry_override(entry, CPUID_D_1_EAX); 1476 if (entry->eax & (feature_bit(XSAVES) | feature_bit(XSAVEC))) 1477 entry->ebx = xstate_required_size(permitted_xcr0 | permitted_xss, 1478 true); 1479 else { 1480 WARN_ON_ONCE(permitted_xss != 0); 1481 entry->ebx = 0; 1482 } 1483 entry->ecx &= permitted_xss; 1484 entry->edx &= permitted_xss >> 32; 1485 1486 for (i = 2; i < 64; ++i) { 1487 bool s_state; 1488 if (permitted_xcr0 & BIT_ULL(i)) 1489 s_state = false; 1490 else if (permitted_xss & BIT_ULL(i)) 1491 s_state = true; 1492 else 1493 continue; 1494 1495 entry = do_host_cpuid(array, function, i); 1496 if (!entry) 1497 goto out; 1498 1499 /* 1500 * The supported check above should have filtered out 1501 * invalid sub-leafs. Only valid sub-leafs should 1502 * reach this point, and they should have a non-zero 1503 * save state size. Furthermore, check whether the 1504 * processor agrees with permitted_xcr0/permitted_xss 1505 * on whether this is an XCR0- or IA32_XSS-managed area. 1506 */ 1507 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) { 1508 --array->nent; 1509 continue; 1510 } 1511 1512 if (!kvm_cpu_cap_has(X86_FEATURE_XFD)) 1513 entry->ecx &= ~BIT_ULL(2); 1514 entry->edx = 0; 1515 } 1516 break; 1517 } 1518 case 0x12: 1519 /* Intel SGX */ 1520 if (!kvm_cpu_cap_has(X86_FEATURE_SGX)) { 1521 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1522 break; 1523 } 1524 1525 /* 1526 * Index 0: Sub-features, MISCSELECT (a.k.a extended features) 1527 * and max enclave sizes. The SGX sub-features and MISCSELECT 1528 * are restricted by kernel and KVM capabilities (like most 1529 * feature flags), while enclave size is unrestricted. 1530 */ 1531 cpuid_entry_override(entry, CPUID_12_EAX); 1532 entry->ebx &= SGX_MISC_EXINFO; 1533 1534 entry = do_host_cpuid(array, function, 1); 1535 if (!entry) 1536 goto out; 1537 1538 /* 1539 * Index 1: SECS.ATTRIBUTES. ATTRIBUTES are restricted a la 1540 * feature flags. Advertise all supported flags, including 1541 * privileged attributes that require explicit opt-in from 1542 * userspace. ATTRIBUTES.XFRM is not adjusted as userspace is 1543 * expected to derive it from supported XCR0. 1544 */ 1545 entry->eax &= SGX_ATTR_PRIV_MASK | SGX_ATTR_UNPRIV_MASK; 1546 entry->ebx &= 0; 1547 break; 1548 /* Intel PT */ 1549 case 0x14: 1550 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) { 1551 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1552 break; 1553 } 1554 1555 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 1556 if (!do_host_cpuid(array, function, i)) 1557 goto out; 1558 } 1559 break; 1560 /* Intel AMX TILE */ 1561 case 0x1d: 1562 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { 1563 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1564 break; 1565 } 1566 1567 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 1568 if (!do_host_cpuid(array, function, i)) 1569 goto out; 1570 } 1571 break; 1572 case 0x1e: /* TMUL information */ 1573 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { 1574 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1575 break; 1576 } 1577 break; 1578 case 0x24: { 1579 u8 avx10_version; 1580 1581 if (!kvm_cpu_cap_has(X86_FEATURE_AVX10)) { 1582 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1583 break; 1584 } 1585 1586 /* 1587 * The AVX10 version is encoded in EBX[7:0]. Note, the version 1588 * is guaranteed to be >=1 if AVX10 is supported. Note #2, the 1589 * version needs to be captured before overriding EBX features! 1590 */ 1591 avx10_version = min_t(u8, entry->ebx & 0xff, 1); 1592 cpuid_entry_override(entry, CPUID_24_0_EBX); 1593 entry->ebx |= avx10_version; 1594 1595 entry->eax = 0; 1596 entry->ecx = 0; 1597 entry->edx = 0; 1598 break; 1599 } 1600 case KVM_CPUID_SIGNATURE: { 1601 const u32 *sigptr = (const u32 *)KVM_SIGNATURE; 1602 entry->eax = KVM_CPUID_FEATURES; 1603 entry->ebx = sigptr[0]; 1604 entry->ecx = sigptr[1]; 1605 entry->edx = sigptr[2]; 1606 break; 1607 } 1608 case KVM_CPUID_FEATURES: 1609 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | 1610 (1 << KVM_FEATURE_NOP_IO_DELAY) | 1611 (1 << KVM_FEATURE_CLOCKSOURCE2) | 1612 (1 << KVM_FEATURE_ASYNC_PF) | 1613 (1 << KVM_FEATURE_PV_EOI) | 1614 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) | 1615 (1 << KVM_FEATURE_PV_UNHALT) | 1616 (1 << KVM_FEATURE_PV_TLB_FLUSH) | 1617 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) | 1618 (1 << KVM_FEATURE_PV_SEND_IPI) | 1619 (1 << KVM_FEATURE_POLL_CONTROL) | 1620 (1 << KVM_FEATURE_PV_SCHED_YIELD) | 1621 (1 << KVM_FEATURE_ASYNC_PF_INT); 1622 1623 if (sched_info_on()) 1624 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME); 1625 1626 entry->ebx = 0; 1627 entry->ecx = 0; 1628 entry->edx = 0; 1629 break; 1630 case 0x80000000: 1631 entry->eax = min(entry->eax, 0x80000022); 1632 /* 1633 * Serializing LFENCE is reported in a multitude of ways, and 1634 * NullSegClearsBase is not reported in CPUID on Zen2; help 1635 * userspace by providing the CPUID leaf ourselves. 1636 * 1637 * However, only do it if the host has CPUID leaf 0x8000001d. 1638 * QEMU thinks that it can query the host blindly for that 1639 * CPUID leaf if KVM reports that it supports 0x8000001d or 1640 * above. The processor merrily returns values from the 1641 * highest Intel leaf which QEMU tries to use as the guest's 1642 * 0x8000001d. Even worse, this can result in an infinite 1643 * loop if said highest leaf has no subleaves indexed by ECX. 1644 */ 1645 if (entry->eax >= 0x8000001d && 1646 (static_cpu_has(X86_FEATURE_LFENCE_RDTSC) 1647 || !static_cpu_has_bug(X86_BUG_NULL_SEG))) 1648 entry->eax = max(entry->eax, 0x80000021); 1649 break; 1650 case 0x80000001: 1651 entry->ebx &= ~GENMASK(27, 16); 1652 cpuid_entry_override(entry, CPUID_8000_0001_EDX); 1653 cpuid_entry_override(entry, CPUID_8000_0001_ECX); 1654 break; 1655 case 0x80000005: 1656 /* Pass host L1 cache and TLB info. */ 1657 break; 1658 case 0x80000006: 1659 /* Drop reserved bits, pass host L2 cache and TLB info. */ 1660 entry->edx &= ~GENMASK(17, 16); 1661 break; 1662 case 0x80000007: /* Advanced power management */ 1663 cpuid_entry_override(entry, CPUID_8000_0007_EDX); 1664 1665 /* mask against host */ 1666 entry->edx &= boot_cpu_data.x86_power; 1667 entry->eax = entry->ebx = entry->ecx = 0; 1668 break; 1669 case 0x80000008: { 1670 /* 1671 * GuestPhysAddrSize (EAX[23:16]) is intended for software 1672 * use. 1673 * 1674 * KVM's ABI is to report the effective MAXPHYADDR for the 1675 * guest in PhysAddrSize (phys_as), and the maximum 1676 * *addressable* GPA in GuestPhysAddrSize (g_phys_as). 1677 * 1678 * GuestPhysAddrSize is valid if and only if TDP is enabled, 1679 * in which case the max GPA that can be addressed by KVM may 1680 * be less than the max GPA that can be legally generated by 1681 * the guest, e.g. if MAXPHYADDR>48 but the CPU doesn't 1682 * support 5-level TDP. 1683 */ 1684 unsigned int virt_as = max((entry->eax >> 8) & 0xff, 48U); 1685 unsigned int phys_as, g_phys_as; 1686 1687 /* 1688 * If TDP (NPT) is disabled use the adjusted host MAXPHYADDR as 1689 * the guest operates in the same PA space as the host, i.e. 1690 * reductions in MAXPHYADDR for memory encryption affect shadow 1691 * paging, too. 1692 * 1693 * If TDP is enabled, use the raw bare metal MAXPHYADDR as 1694 * reductions to the HPAs do not affect GPAs. The max 1695 * addressable GPA is the same as the max effective GPA, except 1696 * that it's capped at 48 bits if 5-level TDP isn't supported 1697 * (hardware processes bits 51:48 only when walking the fifth 1698 * level page table). 1699 */ 1700 if (!tdp_enabled) { 1701 phys_as = boot_cpu_data.x86_phys_bits; 1702 g_phys_as = 0; 1703 } else { 1704 phys_as = entry->eax & 0xff; 1705 g_phys_as = phys_as; 1706 if (kvm_mmu_get_max_tdp_level() < 5) 1707 g_phys_as = min(g_phys_as, 48); 1708 } 1709 1710 entry->eax = phys_as | (virt_as << 8) | (g_phys_as << 16); 1711 entry->ecx &= ~(GENMASK(31, 16) | GENMASK(11, 8)); 1712 entry->edx = 0; 1713 cpuid_entry_override(entry, CPUID_8000_0008_EBX); 1714 break; 1715 } 1716 case 0x8000000A: 1717 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) { 1718 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1719 break; 1720 } 1721 entry->eax = 1; /* SVM revision 1 */ 1722 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper 1723 ASID emulation to nested SVM */ 1724 entry->ecx = 0; /* Reserved */ 1725 cpuid_entry_override(entry, CPUID_8000_000A_EDX); 1726 break; 1727 case 0x80000019: 1728 entry->ecx = entry->edx = 0; 1729 break; 1730 case 0x8000001a: 1731 entry->eax &= GENMASK(2, 0); 1732 entry->ebx = entry->ecx = entry->edx = 0; 1733 break; 1734 case 0x8000001e: 1735 /* Do not return host topology information. */ 1736 entry->eax = entry->ebx = entry->ecx = 0; 1737 entry->edx = 0; /* reserved */ 1738 break; 1739 case 0x8000001F: 1740 if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) { 1741 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1742 } else { 1743 cpuid_entry_override(entry, CPUID_8000_001F_EAX); 1744 /* Clear NumVMPL since KVM does not support VMPL. */ 1745 entry->ebx &= ~GENMASK(31, 12); 1746 /* 1747 * Enumerate '0' for "PA bits reduction", the adjusted 1748 * MAXPHYADDR is enumerated directly (see 0x80000008). 1749 */ 1750 entry->ebx &= ~GENMASK(11, 6); 1751 } 1752 break; 1753 case 0x80000020: 1754 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1755 break; 1756 case 0x80000021: 1757 entry->ebx = entry->ecx = entry->edx = 0; 1758 cpuid_entry_override(entry, CPUID_8000_0021_EAX); 1759 break; 1760 /* AMD Extended Performance Monitoring and Debug */ 1761 case 0x80000022: { 1762 union cpuid_0x80000022_ebx ebx; 1763 1764 entry->ecx = entry->edx = 0; 1765 if (!enable_pmu || !kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) { 1766 entry->eax = entry->ebx = 0; 1767 break; 1768 } 1769 1770 cpuid_entry_override(entry, CPUID_8000_0022_EAX); 1771 1772 if (kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) 1773 ebx.split.num_core_pmc = kvm_pmu_cap.num_counters_gp; 1774 else if (kvm_cpu_cap_has(X86_FEATURE_PERFCTR_CORE)) 1775 ebx.split.num_core_pmc = AMD64_NUM_COUNTERS_CORE; 1776 else 1777 ebx.split.num_core_pmc = AMD64_NUM_COUNTERS; 1778 1779 entry->ebx = ebx.full; 1780 break; 1781 } 1782 /*Add support for Centaur's CPUID instruction*/ 1783 case 0xC0000000: 1784 /*Just support up to 0xC0000004 now*/ 1785 entry->eax = min(entry->eax, 0xC0000004); 1786 break; 1787 case 0xC0000001: 1788 cpuid_entry_override(entry, CPUID_C000_0001_EDX); 1789 break; 1790 case 3: /* Processor serial number */ 1791 case 5: /* MONITOR/MWAIT */ 1792 case 0xC0000002: 1793 case 0xC0000003: 1794 case 0xC0000004: 1795 default: 1796 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1797 break; 1798 } 1799 1800 r = 0; 1801 1802 out: 1803 put_cpu(); 1804 1805 return r; 1806 } 1807 1808 static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func, 1809 unsigned int type) 1810 { 1811 if (type == KVM_GET_EMULATED_CPUID) 1812 return __do_cpuid_func_emulated(array, func); 1813 1814 return __do_cpuid_func(array, func); 1815 } 1816 1817 #define CENTAUR_CPUID_SIGNATURE 0xC0000000 1818 1819 static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func, 1820 unsigned int type) 1821 { 1822 u32 limit; 1823 int r; 1824 1825 if (func == CENTAUR_CPUID_SIGNATURE && 1826 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR) 1827 return 0; 1828 1829 r = do_cpuid_func(array, func, type); 1830 if (r) 1831 return r; 1832 1833 limit = array->entries[array->nent - 1].eax; 1834 for (func = func + 1; func <= limit; ++func) { 1835 r = do_cpuid_func(array, func, type); 1836 if (r) 1837 break; 1838 } 1839 1840 return r; 1841 } 1842 1843 static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries, 1844 __u32 num_entries, unsigned int ioctl_type) 1845 { 1846 int i; 1847 __u32 pad[3]; 1848 1849 if (ioctl_type != KVM_GET_EMULATED_CPUID) 1850 return false; 1851 1852 /* 1853 * We want to make sure that ->padding is being passed clean from 1854 * userspace in case we want to use it for something in the future. 1855 * 1856 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we 1857 * have to give ourselves satisfied only with the emulated side. /me 1858 * sheds a tear. 1859 */ 1860 for (i = 0; i < num_entries; i++) { 1861 if (copy_from_user(pad, entries[i].padding, sizeof(pad))) 1862 return true; 1863 1864 if (pad[0] || pad[1] || pad[2]) 1865 return true; 1866 } 1867 return false; 1868 } 1869 1870 int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid, 1871 struct kvm_cpuid_entry2 __user *entries, 1872 unsigned int type) 1873 { 1874 static const u32 funcs[] = { 1875 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE, 1876 }; 1877 1878 struct kvm_cpuid_array array = { 1879 .nent = 0, 1880 }; 1881 int r, i; 1882 1883 if (cpuid->nent < 1) 1884 return -E2BIG; 1885 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 1886 cpuid->nent = KVM_MAX_CPUID_ENTRIES; 1887 1888 if (sanity_check_entries(entries, cpuid->nent, type)) 1889 return -EINVAL; 1890 1891 array.entries = kvcalloc(cpuid->nent, sizeof(struct kvm_cpuid_entry2), GFP_KERNEL); 1892 if (!array.entries) 1893 return -ENOMEM; 1894 1895 array.maxnent = cpuid->nent; 1896 1897 for (i = 0; i < ARRAY_SIZE(funcs); i++) { 1898 r = get_cpuid_func(&array, funcs[i], type); 1899 if (r) 1900 goto out_free; 1901 } 1902 cpuid->nent = array.nent; 1903 1904 if (copy_to_user(entries, array.entries, 1905 array.nent * sizeof(struct kvm_cpuid_entry2))) 1906 r = -EFAULT; 1907 1908 out_free: 1909 kvfree(array.entries); 1910 return r; 1911 } 1912 1913 /* 1914 * Intel CPUID semantics treats any query for an out-of-range leaf as if the 1915 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics 1916 * returns all zeroes for any undefined leaf, whether or not the leaf is in 1917 * range. Centaur/VIA follows Intel semantics. 1918 * 1919 * A leaf is considered out-of-range if its function is higher than the maximum 1920 * supported leaf of its associated class or if its associated class does not 1921 * exist. 1922 * 1923 * There are three primary classes to be considered, with their respective 1924 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary 1925 * class exists if a guest CPUID entry for its <base> leaf exists. For a given 1926 * class, CPUID.<base>.EAX contains the max supported leaf for the class. 1927 * 1928 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff 1929 * - Hypervisor: 0x40000000 - 0x4fffffff 1930 * - Extended: 0x80000000 - 0xbfffffff 1931 * - Centaur: 0xc0000000 - 0xcfffffff 1932 * 1933 * The Hypervisor class is further subdivided into sub-classes that each act as 1934 * their own independent class associated with a 0x100 byte range. E.g. if Qemu 1935 * is advertising support for both HyperV and KVM, the resulting Hypervisor 1936 * CPUID sub-classes are: 1937 * 1938 * - HyperV: 0x40000000 - 0x400000ff 1939 * - KVM: 0x40000100 - 0x400001ff 1940 */ 1941 static struct kvm_cpuid_entry2 * 1942 get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index) 1943 { 1944 struct kvm_cpuid_entry2 *basic, *class; 1945 u32 function = *fn_ptr; 1946 1947 basic = kvm_find_cpuid_entry(vcpu, 0); 1948 if (!basic) 1949 return NULL; 1950 1951 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) || 1952 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx)) 1953 return NULL; 1954 1955 if (function >= 0x40000000 && function <= 0x4fffffff) 1956 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00); 1957 else if (function >= 0xc0000000) 1958 class = kvm_find_cpuid_entry(vcpu, 0xc0000000); 1959 else 1960 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000); 1961 1962 if (class && function <= class->eax) 1963 return NULL; 1964 1965 /* 1966 * Leaf specific adjustments are also applied when redirecting to the 1967 * max basic entry, e.g. if the max basic leaf is 0xb but there is no 1968 * entry for CPUID.0xb.index (see below), then the output value for EDX 1969 * needs to be pulled from CPUID.0xb.1. 1970 */ 1971 *fn_ptr = basic->eax; 1972 1973 /* 1974 * The class does not exist or the requested function is out of range; 1975 * the effective CPUID entry is the max basic leaf. Note, the index of 1976 * the original requested leaf is observed! 1977 */ 1978 return kvm_find_cpuid_entry_index(vcpu, basic->eax, index); 1979 } 1980 1981 bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx, 1982 u32 *ecx, u32 *edx, bool exact_only) 1983 { 1984 u32 orig_function = *eax, function = *eax, index = *ecx; 1985 struct kvm_cpuid_entry2 *entry; 1986 bool exact, used_max_basic = false; 1987 1988 entry = kvm_find_cpuid_entry_index(vcpu, function, index); 1989 exact = !!entry; 1990 1991 if (!entry && !exact_only) { 1992 entry = get_out_of_range_cpuid_entry(vcpu, &function, index); 1993 used_max_basic = !!entry; 1994 } 1995 1996 if (entry) { 1997 *eax = entry->eax; 1998 *ebx = entry->ebx; 1999 *ecx = entry->ecx; 2000 *edx = entry->edx; 2001 if (function == 7 && index == 0) { 2002 u64 data; 2003 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) && 2004 (data & TSX_CTRL_CPUID_CLEAR)) 2005 *ebx &= ~(feature_bit(RTM) | feature_bit(HLE)); 2006 } else if (function == 0x80000007) { 2007 if (kvm_hv_invtsc_suppressed(vcpu)) 2008 *edx &= ~feature_bit(CONSTANT_TSC); 2009 } 2010 } else { 2011 *eax = *ebx = *ecx = *edx = 0; 2012 /* 2013 * When leaf 0BH or 1FH is defined, CL is pass-through 2014 * and EDX is always the x2APIC ID, even for undefined 2015 * subleaves. Index 1 will exist iff the leaf is 2016 * implemented, so we pass through CL iff leaf 1 2017 * exists. EDX can be copied from any existing index. 2018 */ 2019 if (function == 0xb || function == 0x1f) { 2020 entry = kvm_find_cpuid_entry_index(vcpu, function, 1); 2021 if (entry) { 2022 *ecx = index & 0xff; 2023 *edx = entry->edx; 2024 } 2025 } 2026 } 2027 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact, 2028 used_max_basic); 2029 return exact; 2030 } 2031 EXPORT_SYMBOL_GPL(kvm_cpuid); 2032 2033 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu) 2034 { 2035 u32 eax, ebx, ecx, edx; 2036 2037 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0)) 2038 return 1; 2039 2040 eax = kvm_rax_read(vcpu); 2041 ecx = kvm_rcx_read(vcpu); 2042 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false); 2043 kvm_rax_write(vcpu, eax); 2044 kvm_rbx_write(vcpu, ebx); 2045 kvm_rcx_write(vcpu, ecx); 2046 kvm_rdx_write(vcpu, edx); 2047 return kvm_skip_emulated_instruction(vcpu); 2048 } 2049 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); 2050