1 /* 2 * Copyright (C) 2009 Thomas Gleixner <tglx@linutronix.de> 3 * 4 * For licencing details see kernel-base/COPYING 5 */ 6 #include <linux/init.h> 7 #include <linux/ioport.h> 8 #include <linux/export.h> 9 #include <linux/pci.h> 10 11 #include <asm/acpi.h> 12 #include <asm/bios_ebda.h> 13 #include <asm/paravirt.h> 14 #include <asm/pci_x86.h> 15 #include <asm/mpspec.h> 16 #include <asm/setup.h> 17 #include <asm/apic.h> 18 #include <asm/e820/api.h> 19 #include <asm/time.h> 20 #include <asm/irq.h> 21 #include <asm/io_apic.h> 22 #include <asm/hpet.h> 23 #include <asm/memtype.h> 24 #include <asm/tsc.h> 25 #include <asm/iommu.h> 26 #include <asm/mach_traps.h> 27 #include <asm/irqdomain.h> 28 #include <asm/realmode.h> 29 30 void x86_init_noop(void) { } 31 void __init x86_init_uint_noop(unsigned int unused) { } 32 static int __init iommu_init_noop(void) { return 0; } 33 static void iommu_shutdown_noop(void) { } 34 bool __init bool_x86_init_noop(void) { return false; } 35 void x86_op_int_noop(int cpu) { } 36 int set_rtc_noop(const struct timespec64 *now) { return -EINVAL; } 37 void get_rtc_noop(struct timespec64 *now) { } 38 39 static __initconst const struct of_device_id of_cmos_match[] = { 40 { .compatible = "motorola,mc146818" }, 41 {} 42 }; 43 44 /* 45 * Allow devicetree configured systems to disable the RTC by setting the 46 * corresponding DT node's status property to disabled. Code is optimized 47 * out for CONFIG_OF=n builds. 48 */ 49 static __init void x86_wallclock_init(void) 50 { 51 struct device_node *node = of_find_matching_node(NULL, of_cmos_match); 52 53 if (node && !of_device_is_available(node)) { 54 x86_platform.get_wallclock = get_rtc_noop; 55 x86_platform.set_wallclock = set_rtc_noop; 56 } 57 } 58 59 /* 60 * The platform setup functions are preset with the default functions 61 * for standard PC hardware. 62 */ 63 struct x86_init_ops x86_init __initdata = { 64 65 .resources = { 66 .probe_roms = probe_roms, 67 .reserve_resources = reserve_standard_io_resources, 68 .memory_setup = e820__memory_setup_default, 69 }, 70 71 .mpparse = { 72 .setup_ioapic_ids = x86_init_noop, 73 .find_mptable = mpparse_find_mptable, 74 .early_parse_smp_cfg = mpparse_parse_early_smp_config, 75 .parse_smp_cfg = mpparse_parse_smp_config, 76 }, 77 78 .irqs = { 79 .pre_vector_init = init_ISA_irqs, 80 .intr_init = native_init_IRQ, 81 .intr_mode_select = apic_intr_mode_select, 82 .intr_mode_init = apic_intr_mode_init, 83 .create_pci_msi_domain = native_create_pci_msi_domain, 84 }, 85 86 .oem = { 87 .arch_setup = x86_init_noop, 88 .banner = default_banner, 89 }, 90 91 .paging = { 92 .pagetable_init = native_pagetable_init, 93 }, 94 95 .timers = { 96 .setup_percpu_clockev = setup_boot_APIC_clock, 97 .timer_init = hpet_time_init, 98 .wallclock_init = x86_wallclock_init, 99 }, 100 101 .iommu = { 102 .iommu_init = iommu_init_noop, 103 }, 104 105 .pci = { 106 .init = x86_default_pci_init, 107 .init_irq = x86_default_pci_init_irq, 108 .fixup_irqs = x86_default_pci_fixup_irqs, 109 }, 110 111 .hyper = { 112 .init_platform = x86_init_noop, 113 .guest_late_init = x86_init_noop, 114 .x2apic_available = bool_x86_init_noop, 115 .msi_ext_dest_id = bool_x86_init_noop, 116 .init_mem_mapping = x86_init_noop, 117 .init_after_bootmem = x86_init_noop, 118 }, 119 120 .acpi = { 121 .set_root_pointer = x86_default_set_root_pointer, 122 .get_root_pointer = x86_default_get_root_pointer, 123 .reduced_hw_early_init = acpi_generic_reduced_hw_init, 124 }, 125 }; 126 127 struct x86_cpuinit_ops x86_cpuinit = { 128 .early_percpu_clock_init = x86_init_noop, 129 .setup_percpu_clockev = setup_secondary_APIC_clock, 130 .parallel_bringup = true, 131 }; 132 133 static void default_nmi_init(void) { }; 134 135 static bool enc_status_change_prepare_noop(unsigned long vaddr, int npages, bool enc) { return true; } 136 static bool enc_status_change_finish_noop(unsigned long vaddr, int npages, bool enc) { return true; } 137 static bool enc_tlb_flush_required_noop(bool enc) { return false; } 138 static bool enc_cache_flush_required_noop(void) { return false; } 139 static bool is_private_mmio_noop(u64 addr) {return false; } 140 141 struct x86_platform_ops x86_platform __ro_after_init = { 142 .calibrate_cpu = native_calibrate_cpu_early, 143 .calibrate_tsc = native_calibrate_tsc, 144 .get_wallclock = mach_get_cmos_time, 145 .set_wallclock = mach_set_cmos_time, 146 .iommu_shutdown = iommu_shutdown_noop, 147 .is_untracked_pat_range = is_ISA_range, 148 .nmi_init = default_nmi_init, 149 .get_nmi_reason = default_get_nmi_reason, 150 .save_sched_clock_state = tsc_save_sched_clock_state, 151 .restore_sched_clock_state = tsc_restore_sched_clock_state, 152 .realmode_reserve = reserve_real_mode, 153 .realmode_init = init_real_mode, 154 .hyper.pin_vcpu = x86_op_int_noop, 155 .hyper.is_private_mmio = is_private_mmio_noop, 156 157 .guest = { 158 .enc_status_change_prepare = enc_status_change_prepare_noop, 159 .enc_status_change_finish = enc_status_change_finish_noop, 160 .enc_tlb_flush_required = enc_tlb_flush_required_noop, 161 .enc_cache_flush_required = enc_cache_flush_required_noop, 162 }, 163 }; 164 165 EXPORT_SYMBOL_GPL(x86_platform); 166 167 struct x86_apic_ops x86_apic_ops __ro_after_init = { 168 .io_apic_read = native_io_apic_read, 169 .restore = native_restore_boot_irq_mode, 170 }; 171