1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * User-space Probes (UProbes) for x86 4 * 5 * Copyright (C) IBM Corporation, 2008-2011 6 * Authors: 7 * Srikar Dronamraju 8 * Jim Keniston 9 */ 10 #include <linux/kernel.h> 11 #include <linux/sched.h> 12 #include <linux/ptrace.h> 13 #include <linux/uprobes.h> 14 #include <linux/uaccess.h> 15 #include <linux/syscalls.h> 16 17 #include <linux/kdebug.h> 18 #include <asm/processor.h> 19 #include <asm/insn.h> 20 #include <asm/insn-eval.h> 21 #include <asm/mmu_context.h> 22 #include <asm/nops.h> 23 24 /* Post-execution fixups. */ 25 26 /* Adjust IP back to vicinity of actual insn */ 27 #define UPROBE_FIX_IP 0x01 28 29 /* Adjust the return address of a call insn */ 30 #define UPROBE_FIX_CALL 0x02 31 32 /* Instruction will modify TF, don't change it */ 33 #define UPROBE_FIX_SETF 0x04 34 35 #define UPROBE_FIX_RIP_SI 0x08 36 #define UPROBE_FIX_RIP_DI 0x10 37 #define UPROBE_FIX_RIP_BX 0x20 38 #define UPROBE_FIX_RIP_MASK \ 39 (UPROBE_FIX_RIP_SI | UPROBE_FIX_RIP_DI | UPROBE_FIX_RIP_BX) 40 41 #define UPROBE_TRAP_NR UINT_MAX 42 43 /* Adaptations for mhiramat x86 decoder v14. */ 44 #define OPCODE1(insn) ((insn)->opcode.bytes[0]) 45 #define OPCODE2(insn) ((insn)->opcode.bytes[1]) 46 #define OPCODE3(insn) ((insn)->opcode.bytes[2]) 47 #define MODRM_REG(insn) X86_MODRM_REG((insn)->modrm.value) 48 49 #define W(row, b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, ba, bb, bc, bd, be, bf)\ 50 (((b0##UL << 0x0)|(b1##UL << 0x1)|(b2##UL << 0x2)|(b3##UL << 0x3) | \ 51 (b4##UL << 0x4)|(b5##UL << 0x5)|(b6##UL << 0x6)|(b7##UL << 0x7) | \ 52 (b8##UL << 0x8)|(b9##UL << 0x9)|(ba##UL << 0xa)|(bb##UL << 0xb) | \ 53 (bc##UL << 0xc)|(bd##UL << 0xd)|(be##UL << 0xe)|(bf##UL << 0xf)) \ 54 << (row % 32)) 55 56 /* 57 * Good-instruction tables for 32-bit apps. This is non-const and volatile 58 * to keep gcc from statically optimizing it out, as variable_test_bit makes 59 * some versions of gcc to think only *(unsigned long*) is used. 60 * 61 * Opcodes we'll probably never support: 62 * 6c-6f - ins,outs. SEGVs if used in userspace 63 * e4-e7 - in,out imm. SEGVs if used in userspace 64 * ec-ef - in,out acc. SEGVs if used in userspace 65 * cc - int3. SIGTRAP if used in userspace 66 * ce - into. Not used in userspace - no kernel support to make it useful. SEGVs 67 * (why we support bound (62) then? it's similar, and similarly unused...) 68 * f1 - int1. SIGTRAP if used in userspace 69 * f4 - hlt. SEGVs if used in userspace 70 * fa - cli. SEGVs if used in userspace 71 * fb - sti. SEGVs if used in userspace 72 * 73 * Opcodes which need some work to be supported: 74 * 07,17,1f - pop es/ss/ds 75 * Normally not used in userspace, but would execute if used. 76 * Can cause GP or stack exception if tries to load wrong segment descriptor. 77 * We hesitate to run them under single step since kernel's handling 78 * of userspace single-stepping (TF flag) is fragile. 79 * We can easily refuse to support push es/cs/ss/ds (06/0e/16/1e) 80 * on the same grounds that they are never used. 81 * cd - int N. 82 * Used by userspace for "int 80" syscall entry. (Other "int N" 83 * cause GP -> SEGV since their IDT gates don't allow calls from CPL 3). 84 * Not supported since kernel's handling of userspace single-stepping 85 * (TF flag) is fragile. 86 * cf - iret. Normally not used in userspace. Doesn't SEGV unless arguments are bad 87 */ 88 #if defined(CONFIG_X86_32) || defined(CONFIG_IA32_EMULATION) 89 static volatile u32 good_insns_32[256 / 32] = { 90 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 91 /* ---------------------------------------------- */ 92 W(0x00, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1) | /* 00 */ 93 W(0x10, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 10 */ 94 W(0x20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */ 95 W(0x30, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 30 */ 96 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */ 97 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */ 98 W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */ 99 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */ 100 W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */ 101 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */ 102 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */ 103 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */ 104 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */ 105 W(0xd0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */ 106 W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* e0 */ 107 W(0xf0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */ 108 /* ---------------------------------------------- */ 109 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 110 }; 111 #else 112 #define good_insns_32 NULL 113 #endif 114 115 /* Good-instruction tables for 64-bit apps. 116 * 117 * Genuinely invalid opcodes: 118 * 06,07 - formerly push/pop es 119 * 0e - formerly push cs 120 * 16,17 - formerly push/pop ss 121 * 1e,1f - formerly push/pop ds 122 * 27,2f,37,3f - formerly daa/das/aaa/aas 123 * 60,61 - formerly pusha/popa 124 * 62 - formerly bound. EVEX prefix for AVX512 (not yet supported) 125 * 82 - formerly redundant encoding of Group1 126 * 9a - formerly call seg:ofs 127 * ce - formerly into 128 * d4,d5 - formerly aam/aad 129 * d6 - formerly undocumented salc 130 * ea - formerly jmp seg:ofs 131 * 132 * Opcodes we'll probably never support: 133 * 6c-6f - ins,outs. SEGVs if used in userspace 134 * e4-e7 - in,out imm. SEGVs if used in userspace 135 * ec-ef - in,out acc. SEGVs if used in userspace 136 * cc - int3. SIGTRAP if used in userspace 137 * f1 - int1. SIGTRAP if used in userspace 138 * f4 - hlt. SEGVs if used in userspace 139 * fa - cli. SEGVs if used in userspace 140 * fb - sti. SEGVs if used in userspace 141 * 142 * Opcodes which need some work to be supported: 143 * cd - int N. 144 * Used by userspace for "int 80" syscall entry. (Other "int N" 145 * cause GP -> SEGV since their IDT gates don't allow calls from CPL 3). 146 * Not supported since kernel's handling of userspace single-stepping 147 * (TF flag) is fragile. 148 * cf - iret. Normally not used in userspace. Doesn't SEGV unless arguments are bad 149 */ 150 #if defined(CONFIG_X86_64) 151 static volatile u32 good_insns_64[256 / 32] = { 152 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 153 /* ---------------------------------------------- */ 154 W(0x00, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1) | /* 00 */ 155 W(0x10, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) , /* 10 */ 156 W(0x20, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) | /* 20 */ 157 W(0x30, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 30 */ 158 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */ 159 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */ 160 W(0x60, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */ 161 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */ 162 W(0x80, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */ 163 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1) , /* 90 */ 164 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */ 165 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */ 166 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */ 167 W(0xd0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */ 168 W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0) | /* e0 */ 169 W(0xf0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */ 170 /* ---------------------------------------------- */ 171 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 172 }; 173 #else 174 #define good_insns_64 NULL 175 #endif 176 177 /* Using this for both 64-bit and 32-bit apps. 178 * Opcodes we don't support: 179 * 0f 00 - SLDT/STR/LLDT/LTR/VERR/VERW/-/- group. System insns 180 * 0f 01 - SGDT/SIDT/LGDT/LIDT/SMSW/-/LMSW/INVLPG group. 181 * Also encodes tons of other system insns if mod=11. 182 * Some are in fact non-system: xend, xtest, rdtscp, maybe more 183 * 0f 05 - syscall 184 * 0f 06 - clts (CPL0 insn) 185 * 0f 07 - sysret 186 * 0f 08 - invd (CPL0 insn) 187 * 0f 09 - wbinvd (CPL0 insn) 188 * 0f 0b - ud2 189 * 0f 30 - wrmsr (CPL0 insn) (then why rdmsr is allowed, it's also CPL0 insn?) 190 * 0f 34 - sysenter 191 * 0f 35 - sysexit 192 * 0f 37 - getsec 193 * 0f 78 - vmread (Intel VMX. CPL0 insn) 194 * 0f 79 - vmwrite (Intel VMX. CPL0 insn) 195 * Note: with prefixes, these two opcodes are 196 * extrq/insertq/AVX512 convert vector ops. 197 * 0f ae - group15: [f]xsave,[f]xrstor,[v]{ld,st}mxcsr,clflush[opt], 198 * {rd,wr}{fs,gs}base,{s,l,m}fence. 199 * Why? They are all user-executable. 200 */ 201 static volatile u32 good_2byte_insns[256 / 32] = { 202 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 203 /* ---------------------------------------------- */ 204 W(0x00, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1) | /* 00 */ 205 W(0x10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 10 */ 206 W(0x20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */ 207 W(0x30, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1) , /* 30 */ 208 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */ 209 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */ 210 W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 60 */ 211 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1) , /* 70 */ 212 W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */ 213 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */ 214 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1) | /* a0 */ 215 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */ 216 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* c0 */ 217 W(0xd0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */ 218 W(0xe0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* e0 */ 219 W(0xf0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) /* f0 */ 220 /* ---------------------------------------------- */ 221 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 222 }; 223 #undef W 224 225 /* 226 * opcodes we may need to refine support for: 227 * 228 * 0f - 2-byte instructions: For many of these instructions, the validity 229 * depends on the prefix and/or the reg field. On such instructions, we 230 * just consider the opcode combination valid if it corresponds to any 231 * valid instruction. 232 * 233 * 8f - Group 1 - only reg = 0 is OK 234 * c6-c7 - Group 11 - only reg = 0 is OK 235 * d9-df - fpu insns with some illegal encodings 236 * f2, f3 - repnz, repz prefixes. These are also the first byte for 237 * certain floating-point instructions, such as addsd. 238 * 239 * fe - Group 4 - only reg = 0 or 1 is OK 240 * ff - Group 5 - only reg = 0-6 is OK 241 * 242 * others -- Do we need to support these? 243 * 244 * 0f - (floating-point?) prefetch instructions 245 * 07, 17, 1f - pop es, pop ss, pop ds 246 * 26, 2e, 36, 3e - es:, cs:, ss:, ds: segment prefixes -- 247 * but 64 and 65 (fs: and gs:) seem to be used, so we support them 248 * 67 - addr16 prefix 249 * ce - into 250 * f0 - lock prefix 251 */ 252 253 /* 254 * TODO: 255 * - Where necessary, examine the modrm byte and allow only valid instructions 256 * in the different Groups and fpu instructions. 257 */ 258 259 static bool is_prefix_bad(struct insn *insn) 260 { 261 insn_byte_t p; 262 263 for_each_insn_prefix(insn, p) { 264 insn_attr_t attr; 265 266 attr = inat_get_opcode_attribute(p); 267 switch (attr) { 268 case INAT_MAKE_PREFIX(INAT_PFX_ES): 269 case INAT_MAKE_PREFIX(INAT_PFX_CS): 270 case INAT_MAKE_PREFIX(INAT_PFX_DS): 271 case INAT_MAKE_PREFIX(INAT_PFX_SS): 272 case INAT_MAKE_PREFIX(INAT_PFX_LOCK): 273 return true; 274 } 275 } 276 return false; 277 } 278 279 static int uprobe_init_insn(struct arch_uprobe *auprobe, struct insn *insn) 280 { 281 u32 volatile *good_insns; 282 283 if (is_prefix_bad(insn)) 284 return -ENOTSUPP; 285 286 /* We should not singlestep on the exception masking instructions */ 287 if (insn_masking_exception(insn)) 288 return -ENOTSUPP; 289 290 if (insn->x86_64) 291 good_insns = good_insns_64; 292 else 293 good_insns = good_insns_32; 294 295 if (test_bit(OPCODE1(insn), (unsigned long *)good_insns)) 296 return 0; 297 298 if (insn->opcode.nbytes == 2) { 299 if (test_bit(OPCODE2(insn), (unsigned long *)good_2byte_insns)) 300 return 0; 301 } 302 303 return -ENOTSUPP; 304 } 305 306 #ifdef CONFIG_X86_64 307 308 struct uretprobe_syscall_args { 309 unsigned long r11; 310 unsigned long cx; 311 unsigned long ax; 312 }; 313 314 asm ( 315 ".pushsection .rodata\n" 316 ".global uretprobe_trampoline_entry\n" 317 "uretprobe_trampoline_entry:\n" 318 "push %rax\n" 319 "push %rcx\n" 320 "push %r11\n" 321 "mov $" __stringify(__NR_uretprobe) ", %rax\n" 322 "syscall\n" 323 ".global uretprobe_syscall_check\n" 324 "uretprobe_syscall_check:\n" 325 "pop %r11\n" 326 "pop %rcx\n" 327 /* 328 * The uretprobe syscall replaces stored %rax value with final 329 * return address, so we don't restore %rax in here and just 330 * call ret. 331 */ 332 "ret\n" 333 "int3\n" 334 ".global uretprobe_trampoline_end\n" 335 "uretprobe_trampoline_end:\n" 336 ".popsection\n" 337 ); 338 339 extern u8 uretprobe_trampoline_entry[]; 340 extern u8 uretprobe_trampoline_end[]; 341 extern u8 uretprobe_syscall_check[]; 342 343 void *arch_uretprobe_trampoline(unsigned long *psize) 344 { 345 static uprobe_opcode_t insn = UPROBE_SWBP_INSN; 346 struct pt_regs *regs = task_pt_regs(current); 347 348 /* 349 * At the moment the uretprobe syscall trampoline is supported 350 * only for native 64-bit process, the compat process still uses 351 * standard breakpoint. 352 */ 353 if (user_64bit_mode(regs)) { 354 *psize = uretprobe_trampoline_end - uretprobe_trampoline_entry; 355 return uretprobe_trampoline_entry; 356 } 357 358 *psize = UPROBE_SWBP_INSN_SIZE; 359 return &insn; 360 } 361 362 static unsigned long trampoline_check_ip(unsigned long tramp) 363 { 364 return tramp + (uretprobe_syscall_check - uretprobe_trampoline_entry); 365 } 366 367 SYSCALL_DEFINE0(uretprobe) 368 { 369 struct pt_regs *regs = task_pt_regs(current); 370 struct uretprobe_syscall_args args; 371 unsigned long err, ip, sp, tramp; 372 373 /* If there's no trampoline, we are called from wrong place. */ 374 tramp = uprobe_get_trampoline_vaddr(); 375 if (unlikely(tramp == UPROBE_NO_TRAMPOLINE_VADDR)) 376 goto sigill; 377 378 /* Make sure the ip matches the only allowed sys_uretprobe caller. */ 379 if (unlikely(regs->ip != trampoline_check_ip(tramp))) 380 goto sigill; 381 382 err = copy_from_user(&args, (void __user *)regs->sp, sizeof(args)); 383 if (err) 384 goto sigill; 385 386 /* expose the "right" values of r11/cx/ax/sp to uprobe_consumer/s */ 387 regs->r11 = args.r11; 388 regs->cx = args.cx; 389 regs->ax = args.ax; 390 regs->sp += sizeof(args); 391 regs->orig_ax = -1; 392 393 ip = regs->ip; 394 sp = regs->sp; 395 396 uprobe_handle_trampoline(regs); 397 398 /* 399 * Some of the uprobe consumers has changed sp, we can do nothing, 400 * just return via iret. 401 * .. or shadow stack is enabled, in which case we need to skip 402 * return through the user space stack address. 403 */ 404 if (regs->sp != sp || shstk_is_enabled()) 405 return regs->ax; 406 regs->sp -= sizeof(args); 407 408 /* for the case uprobe_consumer has changed r11/cx */ 409 args.r11 = regs->r11; 410 args.cx = regs->cx; 411 412 /* 413 * ax register is passed through as return value, so we can use 414 * its space on stack for ip value and jump to it through the 415 * trampoline's ret instruction 416 */ 417 args.ax = regs->ip; 418 regs->ip = ip; 419 420 err = copy_to_user((void __user *)regs->sp, &args, sizeof(args)); 421 if (err) 422 goto sigill; 423 424 /* ensure sysret, see do_syscall_64() */ 425 regs->r11 = regs->flags; 426 regs->cx = regs->ip; 427 428 return regs->ax; 429 430 sigill: 431 force_sig(SIGILL); 432 return -1; 433 } 434 435 /* 436 * If arch_uprobe->insn doesn't use rip-relative addressing, return 437 * immediately. Otherwise, rewrite the instruction so that it accesses 438 * its memory operand indirectly through a scratch register. Set 439 * defparam->fixups accordingly. (The contents of the scratch register 440 * will be saved before we single-step the modified instruction, 441 * and restored afterward). 442 * 443 * We do this because a rip-relative instruction can access only a 444 * relatively small area (+/- 2 GB from the instruction), and the XOL 445 * area typically lies beyond that area. At least for instructions 446 * that store to memory, we can't execute the original instruction 447 * and "fix things up" later, because the misdirected store could be 448 * disastrous. 449 * 450 * Some useful facts about rip-relative instructions: 451 * 452 * - There's always a modrm byte with bit layout "00 reg 101". 453 * - There's never a SIB byte. 454 * - The displacement is always 4 bytes. 455 * - REX.B=1 bit in REX prefix, which normally extends r/m field, 456 * has no effect on rip-relative mode. It doesn't make modrm byte 457 * with r/m=101 refer to register 1101 = R13. 458 */ 459 static void riprel_analyze(struct arch_uprobe *auprobe, struct insn *insn) 460 { 461 u8 *cursor; 462 u8 reg; 463 u8 reg2; 464 465 if (!insn_rip_relative(insn)) 466 return; 467 468 /* 469 * insn_rip_relative() would have decoded rex_prefix, vex_prefix, modrm. 470 * Clear REX.b bit (extension of MODRM.rm field): 471 * we want to encode low numbered reg, not r8+. 472 */ 473 if (insn->rex_prefix.nbytes) { 474 cursor = auprobe->insn + insn_offset_rex_prefix(insn); 475 /* REX byte has 0100wrxb layout, clearing REX.b bit */ 476 *cursor &= 0xfe; 477 } 478 /* 479 * Similar treatment for VEX3/EVEX prefix. 480 * TODO: add XOP treatment when insn decoder supports them 481 */ 482 if (insn->vex_prefix.nbytes >= 3) { 483 /* 484 * vex2: c5 rvvvvLpp (has no b bit) 485 * vex3/xop: c4/8f rxbmmmmm wvvvvLpp 486 * evex: 62 rxbR00mm wvvvv1pp zllBVaaa 487 * Setting VEX3.b (setting because it has inverted meaning). 488 * Setting EVEX.x since (in non-SIB encoding) EVEX.x 489 * is the 4th bit of MODRM.rm, and needs the same treatment. 490 * For VEX3-encoded insns, VEX3.x value has no effect in 491 * non-SIB encoding, the change is superfluous but harmless. 492 */ 493 cursor = auprobe->insn + insn_offset_vex_prefix(insn) + 1; 494 *cursor |= 0x60; 495 } 496 497 /* 498 * Convert from rip-relative addressing to register-relative addressing 499 * via a scratch register. 500 * 501 * This is tricky since there are insns with modrm byte 502 * which also use registers not encoded in modrm byte: 503 * [i]div/[i]mul: implicitly use dx:ax 504 * shift ops: implicitly use cx 505 * cmpxchg: implicitly uses ax 506 * cmpxchg8/16b: implicitly uses dx:ax and bx:cx 507 * Encoding: 0f c7/1 modrm 508 * The code below thinks that reg=1 (cx), chooses si as scratch. 509 * mulx: implicitly uses dx: mulx r/m,r1,r2 does r1:r2 = dx * r/m. 510 * First appeared in Haswell (BMI2 insn). It is vex-encoded. 511 * Example where none of bx,cx,dx can be used as scratch reg: 512 * c4 e2 63 f6 0d disp32 mulx disp32(%rip),%ebx,%ecx 513 * [v]pcmpistri: implicitly uses cx, xmm0 514 * [v]pcmpistrm: implicitly uses xmm0 515 * [v]pcmpestri: implicitly uses ax, dx, cx, xmm0 516 * [v]pcmpestrm: implicitly uses ax, dx, xmm0 517 * Evil SSE4.2 string comparison ops from hell. 518 * maskmovq/[v]maskmovdqu: implicitly uses (ds:rdi) as destination. 519 * Encoding: 0f f7 modrm, 66 0f f7 modrm, vex-encoded: c5 f9 f7 modrm. 520 * Store op1, byte-masked by op2 msb's in each byte, to (ds:rdi). 521 * AMD says it has no 3-operand form (vex.vvvv must be 1111) 522 * and that it can have only register operands, not mem 523 * (its modrm byte must have mode=11). 524 * If these restrictions will ever be lifted, 525 * we'll need code to prevent selection of di as scratch reg! 526 * 527 * Summary: I don't know any insns with modrm byte which 528 * use SI register implicitly. DI register is used only 529 * by one insn (maskmovq) and BX register is used 530 * only by one too (cmpxchg8b). 531 * BP is stack-segment based (may be a problem?). 532 * AX, DX, CX are off-limits (many implicit users). 533 * SP is unusable (it's stack pointer - think about "pop mem"; 534 * also, rsp+disp32 needs sib encoding -> insn length change). 535 */ 536 537 reg = MODRM_REG(insn); /* Fetch modrm.reg */ 538 reg2 = 0xff; /* Fetch vex.vvvv */ 539 if (insn->vex_prefix.nbytes) 540 reg2 = insn->vex_prefix.bytes[2]; 541 /* 542 * TODO: add XOP vvvv reading. 543 * 544 * vex.vvvv field is in bits 6-3, bits are inverted. 545 * But in 32-bit mode, high-order bit may be ignored. 546 * Therefore, let's consider only 3 low-order bits. 547 */ 548 reg2 = ((reg2 >> 3) & 0x7) ^ 0x7; 549 /* 550 * Register numbering is ax,cx,dx,bx, sp,bp,si,di, r8..r15. 551 * 552 * Choose scratch reg. Order is important: must not select bx 553 * if we can use si (cmpxchg8b case!) 554 */ 555 if (reg != 6 && reg2 != 6) { 556 reg2 = 6; 557 auprobe->defparam.fixups |= UPROBE_FIX_RIP_SI; 558 } else if (reg != 7 && reg2 != 7) { 559 reg2 = 7; 560 auprobe->defparam.fixups |= UPROBE_FIX_RIP_DI; 561 /* TODO (paranoia): force maskmovq to not use di */ 562 } else { 563 reg2 = 3; 564 auprobe->defparam.fixups |= UPROBE_FIX_RIP_BX; 565 } 566 /* 567 * Point cursor at the modrm byte. The next 4 bytes are the 568 * displacement. Beyond the displacement, for some instructions, 569 * is the immediate operand. 570 */ 571 cursor = auprobe->insn + insn_offset_modrm(insn); 572 /* 573 * Change modrm from "00 reg 101" to "10 reg reg2". Example: 574 * 89 05 disp32 mov %eax,disp32(%rip) becomes 575 * 89 86 disp32 mov %eax,disp32(%rsi) 576 */ 577 *cursor = 0x80 | (reg << 3) | reg2; 578 } 579 580 static inline unsigned long * 581 scratch_reg(struct arch_uprobe *auprobe, struct pt_regs *regs) 582 { 583 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_SI) 584 return ®s->si; 585 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_DI) 586 return ®s->di; 587 return ®s->bx; 588 } 589 590 /* 591 * If we're emulating a rip-relative instruction, save the contents 592 * of the scratch register and store the target address in that register. 593 */ 594 static void riprel_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) 595 { 596 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_MASK) { 597 struct uprobe_task *utask = current->utask; 598 unsigned long *sr = scratch_reg(auprobe, regs); 599 600 utask->autask.saved_scratch_register = *sr; 601 *sr = utask->vaddr + auprobe->defparam.ilen; 602 } 603 } 604 605 static void riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) 606 { 607 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_MASK) { 608 struct uprobe_task *utask = current->utask; 609 unsigned long *sr = scratch_reg(auprobe, regs); 610 611 *sr = utask->autask.saved_scratch_register; 612 } 613 } 614 615 static int tramp_mremap(const struct vm_special_mapping *sm, struct vm_area_struct *new_vma) 616 { 617 return -EPERM; 618 } 619 620 static struct page *tramp_mapping_pages[2] __ro_after_init; 621 622 static struct vm_special_mapping tramp_mapping = { 623 .name = "[uprobes-trampoline]", 624 .mremap = tramp_mremap, 625 .pages = tramp_mapping_pages, 626 }; 627 628 629 #define LEA_INSN_SIZE 5 630 #define OPT_INSN_SIZE (LEA_INSN_SIZE + CALL_INSN_SIZE) 631 #define REDZONE_SIZE 0x80 632 633 static const u8 lea_rsp[] = { 0x48, 0x8d, 0x64, 0x24, 0x80 }; 634 635 static bool is_opt_insns(const uprobe_opcode_t *insn) 636 { 637 return !memcmp(insn, lea_rsp, LEA_INSN_SIZE) && 638 insn[LEA_INSN_SIZE] == CALL_INSN_OPCODE; 639 } 640 641 static bool is_swbp_opt_insns(uprobe_opcode_t *insn) 642 { 643 return is_swbp_insn(&insn[0]) && 644 !memcmp(&insn[1], &lea_rsp[1], LEA_INSN_SIZE - 1) && 645 insn[LEA_INSN_SIZE] == CALL_INSN_OPCODE; 646 } 647 648 static bool is_reachable_by_call(unsigned long vtramp, unsigned long vaddr) 649 { 650 long delta = (long)(vaddr + OPT_INSN_SIZE - vtramp); 651 652 return delta >= INT_MIN && delta <= INT_MAX; 653 } 654 655 static unsigned long find_nearest_trampoline(unsigned long vaddr) 656 { 657 struct vm_unmapped_area_info info = { 658 .length = PAGE_SIZE, 659 .align_mask = ~PAGE_MASK, 660 }; 661 unsigned long low_limit, high_limit; 662 unsigned long low_tramp, high_tramp; 663 unsigned long call_end = vaddr + OPT_INSN_SIZE; 664 665 if (check_add_overflow(call_end, INT_MIN, &low_limit)) 666 low_limit = PAGE_SIZE; 667 668 high_limit = call_end + INT_MAX; 669 670 /* Search up from the caller address. */ 671 info.low_limit = call_end; 672 info.high_limit = min(high_limit, TASK_SIZE); 673 high_tramp = vm_unmapped_area(&info); 674 675 /* Search down from the caller address. */ 676 info.low_limit = max(low_limit, PAGE_SIZE); 677 info.high_limit = call_end; 678 info.flags = VM_UNMAPPED_AREA_TOPDOWN; 679 low_tramp = vm_unmapped_area(&info); 680 681 if (IS_ERR_VALUE(high_tramp) && IS_ERR_VALUE(low_tramp)) 682 return -ENOMEM; 683 if (IS_ERR_VALUE(high_tramp)) 684 return low_tramp; 685 if (IS_ERR_VALUE(low_tramp)) 686 return high_tramp; 687 688 /* Return address that's closest to the caller address. */ 689 if (call_end - low_tramp < high_tramp - call_end) 690 return low_tramp; 691 return high_tramp; 692 } 693 694 static struct vm_area_struct *get_uprobe_trampoline(struct mm_struct *mm, unsigned long vaddr, 695 bool *new_mapping) 696 { 697 VMA_ITERATOR(vmi, mm, 0); 698 struct vm_area_struct *vma; 699 700 *new_mapping = false; 701 702 if (vaddr > TASK_SIZE || vaddr < PAGE_SIZE) 703 return ERR_PTR(-EINVAL); 704 705 for_each_vma(vmi, vma) { 706 if (!vma_is_special_mapping(vma, &tramp_mapping)) 707 continue; 708 if (is_reachable_by_call(vma->vm_start, vaddr)) 709 return vma; 710 } 711 712 vaddr = find_nearest_trampoline(vaddr); 713 if (IS_ERR_VALUE(vaddr)) 714 return ERR_PTR(vaddr); 715 716 *new_mapping = true; 717 return _install_special_mapping(mm, vaddr, PAGE_SIZE, 718 VM_READ|VM_EXEC|VM_MAYEXEC|VM_MAYREAD|VM_IO, 719 &tramp_mapping); 720 } 721 722 static bool __in_uprobe_trampoline(struct mm_struct *mm, unsigned long ip) 723 { 724 struct vm_area_struct *vma = vma_lookup(mm, ip); 725 726 return vma && vma_is_special_mapping(vma, &tramp_mapping); 727 } 728 729 static bool in_uprobe_trampoline(unsigned long ip) 730 { 731 struct mm_struct *mm = current->mm; 732 bool found, retry = true; 733 unsigned int seq; 734 735 rcu_read_lock(); 736 if (mmap_lock_speculate_try_begin(mm, &seq)) { 737 found = __in_uprobe_trampoline(mm, ip); 738 retry = mmap_lock_speculate_retry(mm, seq); 739 } 740 rcu_read_unlock(); 741 742 if (retry) { 743 mmap_read_lock(mm); 744 found = __in_uprobe_trampoline(mm, ip); 745 mmap_read_unlock(mm); 746 } 747 return found; 748 } 749 750 /* 751 * See uprobe syscall trampoline; the call to the trampoline will push 752 * the return address on the stack, the trampoline itself then pushes 753 * cx, r11 and ax. 754 */ 755 struct uprobe_syscall_args { 756 unsigned long ax; 757 unsigned long r11; 758 unsigned long cx; 759 unsigned long retaddr; 760 }; 761 762 SYSCALL_DEFINE0(uprobe) 763 { 764 struct pt_regs *regs = task_pt_regs(current); 765 struct uprobe_syscall_args args; 766 unsigned long ip, sp, sret; 767 int err; 768 769 /* Allow execution only from uprobe trampolines. */ 770 if (!in_uprobe_trampoline(regs->ip)) 771 return -EPROTO; 772 773 err = copy_from_user(&args, (void __user *)regs->sp, sizeof(args)); 774 if (err) 775 goto sigill; 776 777 ip = regs->ip; 778 779 /* 780 * expose the "right" values of ax/r11/cx/ip/sp to uprobe_consumer/s, plus: 781 * - adjust ip to the probe address, call saved next instruction address 782 * - adjust sp to the probe's stack frame (check trampoline code) 783 */ 784 regs->ax = args.ax; 785 regs->r11 = args.r11; 786 regs->cx = args.cx; 787 regs->ip = args.retaddr - OPT_INSN_SIZE; 788 regs->sp += sizeof(args) + REDZONE_SIZE; 789 regs->orig_ax = -1; 790 791 sp = regs->sp; 792 793 err = shstk_pop((u64 *)&sret); 794 if (err == -EFAULT || (!err && sret != args.retaddr)) 795 goto sigill; 796 797 handle_syscall_uprobe(regs, regs->ip); 798 799 /* 800 * Some of the uprobe consumers has changed sp, we can do nothing, 801 * just return via iret. 802 */ 803 if (regs->sp != sp) { 804 /* skip the trampoline call */ 805 if (args.retaddr - OPT_INSN_SIZE == regs->ip) 806 regs->ip += OPT_INSN_SIZE; 807 return regs->ax; 808 } 809 810 regs->sp -= sizeof(args) + REDZONE_SIZE; 811 812 /* for the case uprobe_consumer has changed ax/r11/cx */ 813 args.ax = regs->ax; 814 args.r11 = regs->r11; 815 args.cx = regs->cx; 816 817 /* keep return address unless we are instructed otherwise */ 818 if (args.retaddr - OPT_INSN_SIZE != regs->ip) 819 args.retaddr = regs->ip; 820 821 if (shstk_push(args.retaddr) == -EFAULT) 822 goto sigill; 823 824 regs->ip = ip; 825 826 err = copy_to_user((void __user *)regs->sp, &args, sizeof(args)); 827 if (err) 828 goto sigill; 829 830 /* ensure sysret, see do_syscall_64() */ 831 regs->r11 = regs->flags; 832 regs->cx = regs->ip; 833 return 0; 834 835 sigill: 836 force_sig(SIGILL); 837 return -1; 838 } 839 840 asm ( 841 ".pushsection .rodata\n" 842 ".balign " __stringify(PAGE_SIZE) "\n" 843 "uprobe_trampoline_entry:\n" 844 "push %rcx\n" 845 "push %r11\n" 846 "push %rax\n" 847 "mov $" __stringify(__NR_uprobe) ", %rax\n" 848 "syscall\n" 849 "pop %rax\n" 850 "pop %r11\n" 851 "pop %rcx\n" 852 "ret $" __stringify(REDZONE_SIZE) "\n" 853 "int3\n" 854 ".balign " __stringify(PAGE_SIZE) "\n" 855 ".popsection\n" 856 ); 857 858 extern u8 uprobe_trampoline_entry[]; 859 860 static int __init arch_uprobes_init(void) 861 { 862 tramp_mapping_pages[0] = virt_to_page(uprobe_trampoline_entry); 863 return 0; 864 } 865 866 late_initcall(arch_uprobes_init); 867 868 enum { 869 EXPECT_SWBP, 870 EXPECT_OPTIMIZED, 871 EXPECT_SWBP_OPTIMIZED, 872 }; 873 874 struct write_opcode_ctx { 875 unsigned long base; 876 int expect; 877 }; 878 879 /* 880 * Verification callback used by uprobe_write calls to make sure the underlying 881 * instruction is in the expected stage of the INT3 update sequence. 882 */ 883 static int verify_insn(struct page *page, unsigned long vaddr, uprobe_opcode_t *new_opcode, 884 int nbytes, void *data) 885 { 886 struct write_opcode_ctx *ctx = data; 887 uprobe_opcode_t old_opcode[OPT_INSN_SIZE]; 888 889 uprobe_copy_from_page(page, ctx->base, old_opcode, OPT_INSN_SIZE); 890 891 switch (ctx->expect) { 892 case EXPECT_SWBP: 893 if (is_swbp_insn(&old_opcode[0])) 894 return 1; 895 break; 896 case EXPECT_OPTIMIZED: 897 if (is_opt_insns(&old_opcode[0])) 898 return 1; 899 break; 900 case EXPECT_SWBP_OPTIMIZED: 901 if (is_swbp_opt_insns(&old_opcode[0])) 902 return 1; 903 break; 904 } 905 906 return -1; 907 } 908 909 /* 910 * Modify the optimized instruction by using INT3 breakpoints on SMP. 911 * We completely avoid using stop_machine() here, and achieve the 912 * synchronization using INT3 breakpoints and SMP cross-calls. 913 * (borrowed comment from smp_text_poke_batch_finish) 914 * 915 * For optimization (int3_update_optimize): 916 * 1) Start with the uprobe INT3 trap already installed 917 * 2) Update everything but the first byte 918 * 3) Replace the first INT3 by the first byte of the LEA instruction 919 * 920 * For unoptimization (int3_update_unoptimize): 921 * 1) Start with the optimized uprobe lea/call instructions 922 * 2) Add an INT3 trap to the address that will be patched 923 * 3) Restore the NOP bytes before the call opcode 924 * 4) Replace the first INT3 by the first byte of the NOP instruction 925 * 926 * Note that unoptimization deliberately keeps the call opcode and displacement 927 * in bytes 5..9. Those bytes become operands of the restored 10-byte NOP. 928 * 929 * Since there is only a single target uprobe-trampoline for the given nop10 930 * instruction address, the CALL instruction will not be changed across 931 * unoptimization/optimization cycles. 932 * Therefore, any task that is preempted at the CALL instruction is guaranteed 933 * to observe that CALL and not anything else. 934 */ 935 static int int3_update_optimize(struct arch_uprobe *auprobe, struct vm_area_struct *vma, 936 unsigned long vaddr, uprobe_opcode_t *insn) 937 { 938 struct write_opcode_ctx ctx = { 939 .base = vaddr, 940 }; 941 int err; 942 943 /* 944 * 1) Initial state after set_swbp() installed the uprobe: 945 * cc 2e 0f 1f 84 00 00 00 00 00 946 * 947 * After a previous unoptimization bytes 5..9 may still contain the 948 * old call instruction, which remains valid for threads already there. 949 */ 950 smp_text_poke_sync_each_cpu(); 951 952 /* 953 * 2) Rewrite the LEA tail and call displacement: 954 * cc [8d 64 24 80 e8 d0 d1 d2 d3] 955 */ 956 ctx.expect = EXPECT_SWBP; 957 err = uprobe_write(auprobe, vma, vaddr + 1, insn + 1, 958 OPT_INSN_SIZE - 1, verify_insn, 959 true /* is_register */, false /* do_update_ref_ctr */, 960 &ctx); 961 if (err) 962 return err; 963 964 smp_text_poke_sync_each_cpu(); 965 966 /* 967 * 3) Publish the first LEA byte: 968 * [48] 8d 64 24 80 e8 d0 d1 d2 d3 969 * 970 * From offset 0 this is: 971 * lea -0x80(%rsp), %rsp 972 * call <uprobe-trampoline> 973 */ 974 ctx.expect = EXPECT_SWBP_OPTIMIZED; 975 err = uprobe_write(auprobe, vma, vaddr, insn, 1, verify_insn, 976 true /* is_register */, false /* do_update_ref_ctr */, 977 &ctx); 978 if (err) 979 goto error; 980 981 smp_text_poke_sync_each_cpu(); 982 return 0; 983 984 error: 985 /* 986 * In all intermediate states byte 0 is INT3, so EXPECT_SWBP covers every 987 * case. Restore NOP bytes 1..4, but keep the valid CALL at bytes 5..9 988 * for a thread that had already executed the LEA before a previous 989 * unoptimization. 990 */ 991 ctx.expect = EXPECT_SWBP; 992 uprobe_write(auprobe, vma, vaddr + 1, auprobe->insn + 1, 993 LEA_INSN_SIZE - 1, verify_insn, true, false, &ctx); 994 smp_text_poke_sync_each_cpu(); 995 return err; 996 } 997 998 static int int3_update_unoptimize(struct arch_uprobe *auprobe, struct vm_area_struct *vma, 999 unsigned long vaddr, uprobe_opcode_t *insn) 1000 { 1001 uprobe_opcode_t int3 = UPROBE_SWBP_INSN; 1002 struct write_opcode_ctx ctx = { 1003 .base = vaddr, 1004 .expect = EXPECT_OPTIMIZED, 1005 }; 1006 int err; 1007 1008 /* 1009 * Note the first two uprobe_write calls use is_register=true, because they 1010 * are intermediate patching states while the probe is still active, so 1011 * we force the exclusive anonymous page for the update. 1012 * Also we use do_update_ref_ctr=false because refctr was already updated by 1013 * the initial int3 install. 1014 * 1015 * The last uprobe_write to nop10 instruction is called with is_register=false 1016 * and do_update_ref_ctr=true to trigger the refctr update and to instruct 1017 * uprobe_write to zap the anonymous page if it now matches the file page. 1018 * 1019 * 1) Initial optimized state: 1020 * 48 8d 64 24 80 e8 d0 d1 d2 d3 1021 * 1022 * 2) Trap new entries before restoring the NOP bytes: 1023 * [cc] 8d 64 24 80 e8 d0 d1 d2 d3 1024 */ 1025 err = uprobe_write(auprobe, vma, vaddr, &int3, 1, verify_insn, 1026 true /* is_register */, false /* do_update_ref_ctr */, 1027 &ctx); 1028 if (err) 1029 return err; 1030 1031 smp_text_poke_sync_each_cpu(); 1032 1033 /* 1034 * 3) Restore bytes 1..4 of the original NOP while keeping byte 0 trapped 1035 * and byte 5 as CALL: 1036 * cc [2e 0f 1f 84] e8 d0 d1 d2 d3 1037 */ 1038 ctx.expect = EXPECT_SWBP_OPTIMIZED; 1039 err = uprobe_write(auprobe, vma, vaddr + 1, insn + 1, 1040 LEA_INSN_SIZE - 1, verify_insn, 1041 true /* is_register */, false /* do_update_ref_ctr */, 1042 &ctx); 1043 if (err) 1044 return err; 1045 1046 smp_text_poke_sync_each_cpu(); 1047 1048 /* 1049 * 4) Publish the first byte of the original NOP: 1050 * [66] 2e 0f 1f 84 e8 d0 d1 d2 d3 1051 * 1052 * From offset 0 this is the restored 10-byte NOP; the CALL opcode and 1053 * displacement are now only NOP operands. Offset 5 still decodes as 1054 * CALL for a thread that was already there. 1055 */ 1056 ctx.expect = EXPECT_SWBP; 1057 err = uprobe_write(auprobe, vma, vaddr, insn, 1, verify_insn, 1058 false /* is_register */, true /* do_update_ref_ctr */, 1059 &ctx); 1060 if (err) 1061 return err; 1062 1063 smp_text_poke_sync_each_cpu(); 1064 return 0; 1065 } 1066 1067 static int swbp_optimize(struct arch_uprobe *auprobe, struct vm_area_struct *vma, 1068 unsigned long vaddr, unsigned long tramp) 1069 { 1070 u8 insn[OPT_INSN_SIZE], *call = &insn[LEA_INSN_SIZE]; 1071 1072 /* 1073 * We have nop10 instruction (with first byte overwritten to int3), 1074 * changing it to: 1075 * lea -0x80(%rsp), %rsp 1076 * call tramp 1077 */ 1078 memcpy(insn, lea_rsp, LEA_INSN_SIZE); 1079 __text_gen_insn(call, CALL_INSN_OPCODE, 1080 (const void *) (vaddr + LEA_INSN_SIZE), 1081 (const void *) tramp, CALL_INSN_SIZE); 1082 return int3_update_optimize(auprobe, vma, vaddr, insn); 1083 } 1084 1085 static int swbp_unoptimize(struct arch_uprobe *auprobe, struct vm_area_struct *vma, 1086 unsigned long vaddr) 1087 { 1088 return int3_update_unoptimize(auprobe, vma, vaddr, auprobe->insn); 1089 } 1090 1091 static int copy_from_vaddr(struct mm_struct *mm, unsigned long vaddr, void *dst, int len) 1092 { 1093 unsigned int gup_flags = FOLL_FORCE|FOLL_SPLIT_PMD; 1094 struct vm_area_struct *vma; 1095 struct page *page; 1096 1097 page = get_user_page_vma_remote(mm, vaddr, gup_flags, &vma); 1098 if (IS_ERR(page)) 1099 return PTR_ERR(page); 1100 uprobe_copy_from_page(page, vaddr, dst, len); 1101 put_page(page); 1102 return 0; 1103 } 1104 1105 static bool __is_optimized(struct mm_struct *mm, uprobe_opcode_t *insn, unsigned long vaddr) 1106 { 1107 struct __packed __arch_relative_insn { 1108 u8 op; 1109 s32 raddr; 1110 } *call = (struct __arch_relative_insn *)(insn + LEA_INSN_SIZE); 1111 1112 if (!is_opt_insns(insn)) 1113 return false; 1114 return __in_uprobe_trampoline(mm, vaddr + OPT_INSN_SIZE + call->raddr); 1115 } 1116 1117 static int is_optimized(struct mm_struct *mm, unsigned long vaddr) 1118 { 1119 uprobe_opcode_t insn[OPT_INSN_SIZE]; 1120 int err; 1121 1122 err = copy_from_vaddr(mm, vaddr, &insn, OPT_INSN_SIZE); 1123 if (err) 1124 return err; 1125 return __is_optimized(mm, (uprobe_opcode_t *)&insn, vaddr); 1126 } 1127 1128 static bool should_optimize(struct arch_uprobe *auprobe) 1129 { 1130 return !test_bit(ARCH_UPROBE_FLAG_OPTIMIZE_FAIL, &auprobe->flags) && 1131 test_bit(ARCH_UPROBE_FLAG_CAN_OPTIMIZE, &auprobe->flags); 1132 } 1133 1134 int set_swbp(struct arch_uprobe *auprobe, struct vm_area_struct *vma, 1135 unsigned long vaddr) 1136 { 1137 if (should_optimize(auprobe)) { 1138 /* 1139 * We could race with another thread that already optimized the probe, 1140 * so let's not overwrite it with int3 again in this case. 1141 */ 1142 int ret = is_optimized(vma->vm_mm, vaddr); 1143 if (ret < 0) 1144 return ret; 1145 if (ret) 1146 return 0; 1147 } 1148 return uprobe_write_opcode(auprobe, vma, vaddr, UPROBE_SWBP_INSN, 1149 true /* is_register */); 1150 } 1151 1152 int set_orig_insn(struct arch_uprobe *auprobe, struct vm_area_struct *vma, 1153 unsigned long vaddr) 1154 { 1155 if (test_bit(ARCH_UPROBE_FLAG_CAN_OPTIMIZE, &auprobe->flags)) { 1156 int ret = is_optimized(vma->vm_mm, vaddr); 1157 if (ret < 0) 1158 return ret; 1159 if (ret) { 1160 ret = swbp_unoptimize(auprobe, vma, vaddr); 1161 WARN_ON_ONCE(ret); 1162 return ret; 1163 } 1164 } 1165 return uprobe_write_opcode(auprobe, vma, vaddr, *(uprobe_opcode_t *)&auprobe->insn, 1166 false /* is_register */); 1167 } 1168 1169 static int __arch_uprobe_optimize(struct arch_uprobe *auprobe, struct mm_struct *mm, 1170 unsigned long vaddr) 1171 { 1172 struct pt_regs *regs = task_pt_regs(current); 1173 struct vm_area_struct *vma, *tramp; 1174 bool new_mapping; 1175 int ret; 1176 1177 if (!user_64bit_mode(regs)) 1178 return -EINVAL; 1179 vma = find_vma(mm, vaddr); 1180 if (!vma) 1181 return -EINVAL; 1182 tramp = get_uprobe_trampoline(mm, vaddr, &new_mapping); 1183 if (IS_ERR(tramp)) 1184 return PTR_ERR(tramp); 1185 ret = swbp_optimize(auprobe, vma, vaddr, tramp->vm_start); 1186 if (WARN_ON_ONCE(ret) && new_mapping) 1187 WARN_ON_ONCE(do_munmap(mm, tramp->vm_start, PAGE_SIZE, NULL)); 1188 return ret; 1189 } 1190 1191 void arch_uprobe_optimize(struct arch_uprobe *auprobe, unsigned long vaddr) 1192 { 1193 struct mm_struct *mm = current->mm; 1194 uprobe_opcode_t insn[OPT_INSN_SIZE]; 1195 1196 if (!should_optimize(auprobe)) 1197 return; 1198 1199 mmap_write_lock(mm); 1200 1201 /* 1202 * Check if some other thread already optimized the uprobe for us, 1203 * if it's the case just go away silently. 1204 */ 1205 if (copy_from_vaddr(mm, vaddr, &insn, OPT_INSN_SIZE)) 1206 goto unlock; 1207 if (!is_swbp_insn((uprobe_opcode_t*) &insn)) 1208 goto unlock; 1209 1210 /* 1211 * If we fail to optimize the uprobe we set the fail bit so the 1212 * above should_optimize will fail from now on. 1213 */ 1214 if (__arch_uprobe_optimize(auprobe, mm, vaddr)) 1215 set_bit(ARCH_UPROBE_FLAG_OPTIMIZE_FAIL, &auprobe->flags); 1216 1217 unlock: 1218 mmap_write_unlock(mm); 1219 } 1220 1221 static bool is_optimizable_nop10(struct insn *insn) 1222 { 1223 static const u8 nop10_prefix[] = { 1224 0x66, 0x2e, 0x0f, 0x1f, 0x84 1225 }; 1226 1227 /* 1228 * Restrict this to the 10-byte NOP form whose last 5 bytes are 1229 * SIB/displacement operands. Unoptimization keeps the call opcode and 1230 * displacement in those bytes, so other NOP encodings are not safe. 1231 */ 1232 return insn->length == OPT_INSN_SIZE && 1233 insn_is_nop(insn) && 1234 !memcmp(insn->kaddr, nop10_prefix, ARRAY_SIZE(nop10_prefix)); 1235 } 1236 1237 static bool can_optimize(struct insn *insn, unsigned long vaddr) 1238 { 1239 if (!insn->x86_64) 1240 return false; 1241 1242 if (!is_optimizable_nop10(insn)) 1243 return false; 1244 1245 /* We can't do cross page atomic writes yet. */ 1246 return PAGE_SIZE - (vaddr & ~PAGE_MASK) >= OPT_INSN_SIZE; 1247 } 1248 #else /* 32-bit: */ 1249 /* 1250 * No RIP-relative addressing on 32-bit 1251 */ 1252 static void riprel_analyze(struct arch_uprobe *auprobe, struct insn *insn) 1253 { 1254 } 1255 static void riprel_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) 1256 { 1257 } 1258 static void riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) 1259 { 1260 } 1261 static bool can_optimize(struct insn *insn, unsigned long vaddr) 1262 { 1263 return false; 1264 } 1265 #endif /* CONFIG_X86_64 */ 1266 1267 struct uprobe_xol_ops { 1268 bool (*emulate)(struct arch_uprobe *, struct pt_regs *); 1269 int (*pre_xol)(struct arch_uprobe *, struct pt_regs *); 1270 int (*post_xol)(struct arch_uprobe *, struct pt_regs *); 1271 void (*abort)(struct arch_uprobe *, struct pt_regs *); 1272 }; 1273 1274 static inline int sizeof_long(struct pt_regs *regs) 1275 { 1276 /* 1277 * Check registers for mode as in_xxx_syscall() does not apply here. 1278 */ 1279 return user_64bit_mode(regs) ? 8 : 4; 1280 } 1281 1282 static int default_pre_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs) 1283 { 1284 riprel_pre_xol(auprobe, regs); 1285 return 0; 1286 } 1287 1288 static int emulate_push_stack(struct pt_regs *regs, unsigned long val) 1289 { 1290 unsigned long new_sp = regs->sp - sizeof_long(regs); 1291 1292 if (copy_to_user((void __user *)new_sp, &val, sizeof_long(regs))) 1293 return -EFAULT; 1294 1295 regs->sp = new_sp; 1296 return 0; 1297 } 1298 1299 /* 1300 * We have to fix things up as follows: 1301 * 1302 * Typically, the new ip is relative to the copied instruction. We need 1303 * to make it relative to the original instruction (FIX_IP). Exceptions 1304 * are return instructions and absolute or indirect jump or call instructions. 1305 * 1306 * If the single-stepped instruction was a call, the return address that 1307 * is atop the stack is the address following the copied instruction. We 1308 * need to make it the address following the original instruction (FIX_CALL). 1309 * 1310 * If the original instruction was a rip-relative instruction such as 1311 * "movl %edx,0xnnnn(%rip)", we have instead executed an equivalent 1312 * instruction using a scratch register -- e.g., "movl %edx,0xnnnn(%rsi)". 1313 * We need to restore the contents of the scratch register 1314 * (FIX_RIP_reg). 1315 */ 1316 static int default_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs) 1317 { 1318 struct uprobe_task *utask = current->utask; 1319 1320 riprel_post_xol(auprobe, regs); 1321 if (auprobe->defparam.fixups & UPROBE_FIX_IP) { 1322 long correction = utask->vaddr - utask->xol_vaddr; 1323 regs->ip += correction; 1324 } else if (auprobe->defparam.fixups & UPROBE_FIX_CALL) { 1325 unsigned long retaddr = utask->vaddr + auprobe->defparam.ilen; 1326 int err; 1327 1328 regs->sp += sizeof_long(regs); /* Pop incorrect return address */ 1329 if (emulate_push_stack(regs, retaddr)) 1330 return -ERESTART; 1331 err = shstk_update_last_frame(retaddr); 1332 if (err) 1333 return err; 1334 } 1335 /* popf; tell the caller to not touch TF */ 1336 if (auprobe->defparam.fixups & UPROBE_FIX_SETF) 1337 utask->autask.saved_tf = true; 1338 1339 return 0; 1340 } 1341 1342 static void default_abort_op(struct arch_uprobe *auprobe, struct pt_regs *regs) 1343 { 1344 riprel_post_xol(auprobe, regs); 1345 } 1346 1347 static const struct uprobe_xol_ops default_xol_ops = { 1348 .pre_xol = default_pre_xol_op, 1349 .post_xol = default_post_xol_op, 1350 .abort = default_abort_op, 1351 }; 1352 1353 static bool branch_is_call(struct arch_uprobe *auprobe) 1354 { 1355 return auprobe->branch.opc1 == 0xe8; 1356 } 1357 1358 #define CASE_COND \ 1359 COND(70, 71, XF(OF)) \ 1360 COND(72, 73, XF(CF)) \ 1361 COND(74, 75, XF(ZF)) \ 1362 COND(78, 79, XF(SF)) \ 1363 COND(7a, 7b, XF(PF)) \ 1364 COND(76, 77, XF(CF) || XF(ZF)) \ 1365 COND(7c, 7d, XF(SF) != XF(OF)) \ 1366 COND(7e, 7f, XF(ZF) || XF(SF) != XF(OF)) 1367 1368 #define COND(op_y, op_n, expr) \ 1369 case 0x ## op_y: DO((expr) != 0) \ 1370 case 0x ## op_n: DO((expr) == 0) 1371 1372 #define XF(xf) (!!(flags & X86_EFLAGS_ ## xf)) 1373 1374 static bool is_cond_jmp_opcode(u8 opcode) 1375 { 1376 switch (opcode) { 1377 #define DO(expr) \ 1378 return true; 1379 CASE_COND 1380 #undef DO 1381 1382 default: 1383 return false; 1384 } 1385 } 1386 1387 static bool check_jmp_cond(struct arch_uprobe *auprobe, struct pt_regs *regs) 1388 { 1389 unsigned long flags = regs->flags; 1390 1391 switch (auprobe->branch.opc1) { 1392 #define DO(expr) \ 1393 return expr; 1394 CASE_COND 1395 #undef DO 1396 1397 default: /* not a conditional jmp */ 1398 return true; 1399 } 1400 } 1401 1402 #undef XF 1403 #undef COND 1404 #undef CASE_COND 1405 1406 static bool branch_emulate_op(struct arch_uprobe *auprobe, struct pt_regs *regs) 1407 { 1408 unsigned long new_ip = regs->ip += auprobe->branch.ilen; 1409 unsigned long offs = (long)auprobe->branch.offs; 1410 1411 if (branch_is_call(auprobe)) { 1412 /* 1413 * If it fails we execute this (mangled, see the comment in 1414 * branch_clear_offset) insn out-of-line. In the likely case 1415 * this should trigger the trap, and the probed application 1416 * should die or restart the same insn after it handles the 1417 * signal, arch_uprobe_post_xol() won't be even called. 1418 * 1419 * But there is corner case, see the comment in ->post_xol(). 1420 */ 1421 if (emulate_push_stack(regs, new_ip)) 1422 return false; 1423 if (shstk_push(new_ip) == -EFAULT) { 1424 regs->sp += sizeof_long(regs); 1425 return false; 1426 } 1427 } else if (!check_jmp_cond(auprobe, regs)) { 1428 offs = 0; 1429 } 1430 1431 regs->ip = new_ip + offs; 1432 return true; 1433 } 1434 1435 static bool push_emulate_op(struct arch_uprobe *auprobe, struct pt_regs *regs) 1436 { 1437 unsigned long *src_ptr = (void *)regs + auprobe->push.reg_offset; 1438 1439 if (emulate_push_stack(regs, *src_ptr)) 1440 return false; 1441 regs->ip += auprobe->push.ilen; 1442 return true; 1443 } 1444 1445 static int branch_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs) 1446 { 1447 BUG_ON(!branch_is_call(auprobe)); 1448 /* 1449 * We can only get here if branch_emulate_op() failed to push the ret 1450 * address _and_ another thread expanded our stack before the (mangled) 1451 * "call" insn was executed out-of-line. Just restore ->sp and restart. 1452 * We could also restore ->ip and try to call branch_emulate_op() again. 1453 */ 1454 regs->sp += sizeof_long(regs); 1455 return -ERESTART; 1456 } 1457 1458 static void branch_clear_offset(struct arch_uprobe *auprobe, struct insn *insn) 1459 { 1460 /* 1461 * Turn this insn into "call 1f; 1:", this is what we will execute 1462 * out-of-line if ->emulate() fails. We only need this to generate 1463 * a trap, so that the probed task receives the correct signal with 1464 * the properly filled siginfo. 1465 * 1466 * But see the comment in ->post_xol(), in the unlikely case it can 1467 * succeed. So we need to ensure that the new ->ip can not fall into 1468 * the non-canonical area and trigger #GP. 1469 * 1470 * We could turn it into (say) "pushf", but then we would need to 1471 * divorce ->insn[] and ->ixol[]. We need to preserve the 1st byte 1472 * of ->insn[] for set_orig_insn(). 1473 */ 1474 memset(auprobe->insn + insn_offset_immediate(insn), 1475 0, insn->immediate.nbytes); 1476 } 1477 1478 static const struct uprobe_xol_ops branch_xol_ops = { 1479 .emulate = branch_emulate_op, 1480 .post_xol = branch_post_xol_op, 1481 }; 1482 1483 static const struct uprobe_xol_ops push_xol_ops = { 1484 .emulate = push_emulate_op, 1485 }; 1486 1487 /* Returns -ENOSYS if branch_xol_ops doesn't handle this insn */ 1488 static int branch_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn) 1489 { 1490 u8 opc1 = OPCODE1(insn); 1491 insn_byte_t p; 1492 1493 if (insn_is_nop(insn)) 1494 goto setup; 1495 1496 switch (opc1) { 1497 case 0xeb: /* jmp 8 */ 1498 case 0xe9: /* jmp 32 */ 1499 break; 1500 1501 case 0xe8: /* call relative */ 1502 branch_clear_offset(auprobe, insn); 1503 break; 1504 1505 case 0x0f: 1506 if (insn->opcode.nbytes != 2) 1507 return -ENOSYS; 1508 /* 1509 * If it is a "near" conditional jmp, OPCODE2() - 0x10 matches 1510 * OPCODE1() of the "short" jmp which checks the same condition. 1511 */ 1512 opc1 = OPCODE2(insn) - 0x10; 1513 fallthrough; 1514 default: 1515 if (!is_cond_jmp_opcode(opc1)) 1516 return -ENOSYS; 1517 } 1518 1519 /* 1520 * 16-bit overrides such as CALLW (66 e8 nn nn) are not supported. 1521 * Intel and AMD behavior differ in 64-bit mode: Intel ignores 66 prefix. 1522 * No one uses these insns, reject any branch insns with such prefix. 1523 */ 1524 for_each_insn_prefix(insn, p) { 1525 if (p == 0x66) 1526 return -ENOTSUPP; 1527 } 1528 1529 setup: 1530 auprobe->branch.opc1 = opc1; 1531 auprobe->branch.ilen = insn->length; 1532 auprobe->branch.offs = insn->immediate.value; 1533 1534 auprobe->ops = &branch_xol_ops; 1535 return 0; 1536 } 1537 1538 /* Returns -ENOSYS if push_xol_ops doesn't handle this insn */ 1539 static int push_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn) 1540 { 1541 u8 opc1 = OPCODE1(insn), reg_offset = 0; 1542 1543 if (opc1 < 0x50 || opc1 > 0x57) 1544 return -ENOSYS; 1545 1546 if (insn->length > 2) 1547 return -ENOSYS; 1548 if (insn->length == 2) { 1549 /* only support rex_prefix 0x41 (x64 only) */ 1550 #ifdef CONFIG_X86_64 1551 if (insn->rex_prefix.nbytes != 1 || 1552 insn->rex_prefix.bytes[0] != 0x41) 1553 return -ENOSYS; 1554 1555 switch (opc1) { 1556 case 0x50: 1557 reg_offset = offsetof(struct pt_regs, r8); 1558 break; 1559 case 0x51: 1560 reg_offset = offsetof(struct pt_regs, r9); 1561 break; 1562 case 0x52: 1563 reg_offset = offsetof(struct pt_regs, r10); 1564 break; 1565 case 0x53: 1566 reg_offset = offsetof(struct pt_regs, r11); 1567 break; 1568 case 0x54: 1569 reg_offset = offsetof(struct pt_regs, r12); 1570 break; 1571 case 0x55: 1572 reg_offset = offsetof(struct pt_regs, r13); 1573 break; 1574 case 0x56: 1575 reg_offset = offsetof(struct pt_regs, r14); 1576 break; 1577 case 0x57: 1578 reg_offset = offsetof(struct pt_regs, r15); 1579 break; 1580 } 1581 #else 1582 return -ENOSYS; 1583 #endif 1584 } else { 1585 switch (opc1) { 1586 case 0x50: 1587 reg_offset = offsetof(struct pt_regs, ax); 1588 break; 1589 case 0x51: 1590 reg_offset = offsetof(struct pt_regs, cx); 1591 break; 1592 case 0x52: 1593 reg_offset = offsetof(struct pt_regs, dx); 1594 break; 1595 case 0x53: 1596 reg_offset = offsetof(struct pt_regs, bx); 1597 break; 1598 case 0x54: 1599 reg_offset = offsetof(struct pt_regs, sp); 1600 break; 1601 case 0x55: 1602 reg_offset = offsetof(struct pt_regs, bp); 1603 break; 1604 case 0x56: 1605 reg_offset = offsetof(struct pt_regs, si); 1606 break; 1607 case 0x57: 1608 reg_offset = offsetof(struct pt_regs, di); 1609 break; 1610 } 1611 } 1612 1613 auprobe->push.reg_offset = reg_offset; 1614 auprobe->push.ilen = insn->length; 1615 auprobe->ops = &push_xol_ops; 1616 return 0; 1617 } 1618 1619 /** 1620 * arch_uprobe_analyze_insn - instruction analysis including validity and fixups. 1621 * @auprobe: the probepoint information. 1622 * @mm: the probed address space. 1623 * @addr: virtual address at which to install the probepoint 1624 * Return 0 on success or a -ve number on error. 1625 */ 1626 int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, unsigned long addr) 1627 { 1628 enum insn_mode m = is_64bit_mm(mm) ? INSN_MODE_64 : INSN_MODE_32; 1629 u8 fix_ip_or_call = UPROBE_FIX_IP; 1630 struct insn insn; 1631 int ret; 1632 1633 ret = insn_decode(&insn, auprobe->insn, sizeof(auprobe->insn), m); 1634 if (ret < 0) 1635 return -ENOEXEC; 1636 1637 /* 1638 * No need to check instruction in uprobe_init_insn in case we 1639 * are on top of optimizable nop10. 1640 */ 1641 if (can_optimize(&insn, addr)) { 1642 set_bit(ARCH_UPROBE_FLAG_CAN_OPTIMIZE, &auprobe->flags); 1643 } else { 1644 ret = uprobe_init_insn(auprobe, &insn); 1645 if (ret) 1646 return ret; 1647 } 1648 1649 ret = branch_setup_xol_ops(auprobe, &insn); 1650 if (ret != -ENOSYS) 1651 return ret; 1652 1653 ret = push_setup_xol_ops(auprobe, &insn); 1654 if (ret != -ENOSYS) 1655 return ret; 1656 1657 /* 1658 * Figure out which fixups default_post_xol_op() will need to perform, 1659 * and annotate defparam->fixups accordingly. 1660 */ 1661 switch (OPCODE1(&insn)) { 1662 case 0x9d: /* popf */ 1663 auprobe->defparam.fixups |= UPROBE_FIX_SETF; 1664 break; 1665 case 0xc3: /* ret or lret -- ip is correct */ 1666 case 0xcb: 1667 case 0xc2: 1668 case 0xca: 1669 case 0xea: /* jmp absolute -- ip is correct */ 1670 fix_ip_or_call = 0; 1671 break; 1672 case 0x9a: /* call absolute - Fix return addr, not ip */ 1673 fix_ip_or_call = UPROBE_FIX_CALL; 1674 break; 1675 case 0xff: 1676 switch (MODRM_REG(&insn)) { 1677 case 2: case 3: /* call or lcall, indirect */ 1678 fix_ip_or_call = UPROBE_FIX_CALL; 1679 break; 1680 case 4: case 5: /* jmp or ljmp, indirect */ 1681 fix_ip_or_call = 0; 1682 break; 1683 } 1684 fallthrough; 1685 default: 1686 riprel_analyze(auprobe, &insn); 1687 } 1688 1689 auprobe->defparam.ilen = insn.length; 1690 auprobe->defparam.fixups |= fix_ip_or_call; 1691 1692 auprobe->ops = &default_xol_ops; 1693 return 0; 1694 } 1695 1696 /* 1697 * arch_uprobe_pre_xol - prepare to execute out of line. 1698 * @auprobe: the probepoint information. 1699 * @regs: reflects the saved user state of current task. 1700 */ 1701 int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) 1702 { 1703 struct uprobe_task *utask = current->utask; 1704 1705 if (auprobe->ops->pre_xol) { 1706 int err = auprobe->ops->pre_xol(auprobe, regs); 1707 if (err) 1708 return err; 1709 } 1710 1711 regs->ip = utask->xol_vaddr; 1712 utask->autask.saved_trap_nr = current->thread.trap_nr; 1713 current->thread.trap_nr = UPROBE_TRAP_NR; 1714 1715 utask->autask.saved_tf = !!(regs->flags & X86_EFLAGS_TF); 1716 regs->flags |= X86_EFLAGS_TF; 1717 if (test_tsk_thread_flag(current, TIF_BLOCKSTEP)) 1718 set_task_blockstep(current, false); 1719 1720 return 0; 1721 } 1722 1723 /* 1724 * If xol insn itself traps and generates a signal(Say, 1725 * SIGILL/SIGSEGV/etc), then detect the case where a singlestepped 1726 * instruction jumps back to its own address. It is assumed that anything 1727 * like do_page_fault/do_trap/etc sets thread.trap_nr != -1. 1728 * 1729 * arch_uprobe_pre_xol/arch_uprobe_post_xol save/restore thread.trap_nr, 1730 * arch_uprobe_xol_was_trapped() simply checks that ->trap_nr is not equal to 1731 * UPROBE_TRAP_NR == -1 set by arch_uprobe_pre_xol(). 1732 */ 1733 bool arch_uprobe_xol_was_trapped(struct task_struct *t) 1734 { 1735 if (t->thread.trap_nr != UPROBE_TRAP_NR) 1736 return true; 1737 1738 return false; 1739 } 1740 1741 /* 1742 * Called after single-stepping. To avoid the SMP problems that can 1743 * occur when we temporarily put back the original opcode to 1744 * single-step, we single-stepped a copy of the instruction. 1745 * 1746 * This function prepares to resume execution after the single-step. 1747 */ 1748 int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) 1749 { 1750 struct uprobe_task *utask = current->utask; 1751 bool send_sigtrap = utask->autask.saved_tf; 1752 int err = 0; 1753 1754 WARN_ON_ONCE(current->thread.trap_nr != UPROBE_TRAP_NR); 1755 current->thread.trap_nr = utask->autask.saved_trap_nr; 1756 1757 if (auprobe->ops->post_xol) { 1758 err = auprobe->ops->post_xol(auprobe, regs); 1759 if (err) { 1760 /* 1761 * Restore ->ip for restart or post mortem analysis. 1762 * ->post_xol() must not return -ERESTART unless this 1763 * is really possible. 1764 */ 1765 regs->ip = utask->vaddr; 1766 if (err == -ERESTART) 1767 err = 0; 1768 send_sigtrap = false; 1769 } 1770 } 1771 /* 1772 * arch_uprobe_pre_xol() doesn't save the state of TIF_BLOCKSTEP 1773 * so we can get an extra SIGTRAP if we do not clear TF. We need 1774 * to examine the opcode to make it right. 1775 */ 1776 if (send_sigtrap) 1777 send_sig(SIGTRAP, current, 0); 1778 1779 if (!utask->autask.saved_tf) 1780 regs->flags &= ~X86_EFLAGS_TF; 1781 1782 return err; 1783 } 1784 1785 /* callback routine for handling exceptions. */ 1786 int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, void *data) 1787 { 1788 struct die_args *args = data; 1789 struct pt_regs *regs = args->regs; 1790 int ret = NOTIFY_DONE; 1791 1792 /* We are only interested in userspace traps */ 1793 if (regs && !user_mode(regs)) 1794 return NOTIFY_DONE; 1795 1796 switch (val) { 1797 case DIE_INT3: 1798 if (uprobe_pre_sstep_notifier(regs)) 1799 ret = NOTIFY_STOP; 1800 1801 break; 1802 1803 case DIE_DEBUG: 1804 if (uprobe_post_sstep_notifier(regs)) 1805 ret = NOTIFY_STOP; 1806 1807 break; 1808 1809 default: 1810 break; 1811 } 1812 1813 return ret; 1814 } 1815 1816 /* 1817 * This function gets called when XOL instruction either gets trapped or 1818 * the thread has a fatal signal. Reset the instruction pointer to its 1819 * probed address for the potential restart or for post mortem analysis. 1820 */ 1821 void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) 1822 { 1823 struct uprobe_task *utask = current->utask; 1824 1825 if (auprobe->ops->abort) 1826 auprobe->ops->abort(auprobe, regs); 1827 1828 current->thread.trap_nr = utask->autask.saved_trap_nr; 1829 regs->ip = utask->vaddr; 1830 /* clear TF if it was set by us in arch_uprobe_pre_xol() */ 1831 if (!utask->autask.saved_tf) 1832 regs->flags &= ~X86_EFLAGS_TF; 1833 } 1834 1835 static bool __skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs) 1836 { 1837 if (auprobe->ops->emulate) 1838 return auprobe->ops->emulate(auprobe, regs); 1839 return false; 1840 } 1841 1842 bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs) 1843 { 1844 bool ret = __skip_sstep(auprobe, regs); 1845 if (ret && (regs->flags & X86_EFLAGS_TF)) 1846 send_sig(SIGTRAP, current, 0); 1847 return ret; 1848 } 1849 1850 unsigned long 1851 arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr, struct pt_regs *regs) 1852 { 1853 int rasize = sizeof_long(regs), nleft; 1854 unsigned long orig_ret_vaddr = 0; /* clear high bits for 32-bit apps */ 1855 1856 if (copy_from_user(&orig_ret_vaddr, (void __user *)regs->sp, rasize)) 1857 return -1; 1858 1859 /* check whether address has been already hijacked */ 1860 if (orig_ret_vaddr == trampoline_vaddr) 1861 return orig_ret_vaddr; 1862 1863 nleft = copy_to_user((void __user *)regs->sp, &trampoline_vaddr, rasize); 1864 if (likely(!nleft)) { 1865 if (shstk_update_last_frame(trampoline_vaddr)) { 1866 force_sig(SIGSEGV); 1867 return -1; 1868 } 1869 return orig_ret_vaddr; 1870 } 1871 1872 if (nleft != rasize) { 1873 pr_err("return address clobbered: pid=%d, %%sp=%#lx, %%ip=%#lx\n", 1874 current->pid, regs->sp, regs->ip); 1875 1876 force_sig(SIGSEGV); 1877 } 1878 1879 return -1; 1880 } 1881 1882 bool arch_uretprobe_is_alive(struct return_instance *ret, enum rp_check ctx, 1883 struct pt_regs *regs) 1884 { 1885 if (ctx == RP_CHECK_CALL) /* sp was just decremented by "call" insn */ 1886 return regs->sp < ret->stack; 1887 else 1888 return regs->sp <= ret->stack; 1889 } 1890 1891 /* 1892 * Heuristic-based check if uprobe is installed at the function entry. 1893 * 1894 * Under assumption of user code being compiled with frame pointers, 1895 * `push %rbp/%ebp` is a good indicator that we indeed are. 1896 * 1897 * Similarly, `endbr64` (assuming 64-bit mode) is also a common pattern. 1898 * If we get this wrong, captured stack trace might have one extra bogus 1899 * entry, but the rest of stack trace will still be meaningful. 1900 */ 1901 bool is_uprobe_at_func_entry(struct pt_regs *regs) 1902 { 1903 struct arch_uprobe *auprobe; 1904 1905 if (!current->utask) 1906 return false; 1907 1908 auprobe = current->utask->auprobe; 1909 if (!auprobe) 1910 return false; 1911 1912 /* push %rbp/%ebp */ 1913 if (auprobe->insn[0] == 0x55) 1914 return true; 1915 1916 /* endbr64 (64-bit only) */ 1917 if (user_64bit_mode(regs) && is_endbr((u32 *)auprobe->insn)) 1918 return true; 1919 1920 return false; 1921 } 1922 1923 #ifdef CONFIG_IA32_EMULATION 1924 unsigned long arch_uprobe_get_xol_area(void) 1925 { 1926 struct thread_info *ti = current_thread_info(); 1927 unsigned long vaddr; 1928 1929 /* 1930 * HACK: we are not in a syscall, but x86 get_unmapped_area() paths 1931 * ignore TIF_ADDR32 and rely on in_32bit_syscall() to calculate 1932 * vm_unmapped_area_info.high_limit. 1933 * 1934 * The #ifdef above doesn't cover the CONFIG_X86_X32_ABI=y case, 1935 * but in this case in_32bit_syscall() -> in_x32_syscall() always 1936 * (falsely) returns true because ->orig_ax == -1. 1937 */ 1938 if (test_thread_flag(TIF_ADDR32)) 1939 ti->status |= TS_COMPAT; 1940 vaddr = get_unmapped_area(NULL, TASK_SIZE - PAGE_SIZE, PAGE_SIZE, 0, 0); 1941 ti->status &= ~TS_COMPAT; 1942 1943 return vaddr; 1944 } 1945 #endif 1946