1 /* 2 * User-space Probes (UProbes) for x86 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 * 18 * Copyright (C) IBM Corporation, 2008-2011 19 * Authors: 20 * Srikar Dronamraju 21 * Jim Keniston 22 */ 23 #include <linux/kernel.h> 24 #include <linux/sched.h> 25 #include <linux/ptrace.h> 26 #include <linux/uprobes.h> 27 #include <linux/uaccess.h> 28 29 #include <linux/kdebug.h> 30 #include <asm/processor.h> 31 #include <asm/insn.h> 32 33 /* Post-execution fixups. */ 34 35 /* No fixup needed */ 36 #define UPROBE_FIX_NONE 0x0 37 38 /* Adjust IP back to vicinity of actual insn */ 39 #define UPROBE_FIX_IP 0x1 40 41 /* Adjust the return address of a call insn */ 42 #define UPROBE_FIX_CALL 0x2 43 44 /* Instruction will modify TF, don't change it */ 45 #define UPROBE_FIX_SETF 0x4 46 47 #define UPROBE_FIX_RIP_AX 0x8000 48 #define UPROBE_FIX_RIP_CX 0x4000 49 50 #define UPROBE_TRAP_NR UINT_MAX 51 52 /* Adaptations for mhiramat x86 decoder v14. */ 53 #define OPCODE1(insn) ((insn)->opcode.bytes[0]) 54 #define OPCODE2(insn) ((insn)->opcode.bytes[1]) 55 #define OPCODE3(insn) ((insn)->opcode.bytes[2]) 56 #define MODRM_REG(insn) X86_MODRM_REG((insn)->modrm.value) 57 58 #define W(row, b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, ba, bb, bc, bd, be, bf)\ 59 (((b0##UL << 0x0)|(b1##UL << 0x1)|(b2##UL << 0x2)|(b3##UL << 0x3) | \ 60 (b4##UL << 0x4)|(b5##UL << 0x5)|(b6##UL << 0x6)|(b7##UL << 0x7) | \ 61 (b8##UL << 0x8)|(b9##UL << 0x9)|(ba##UL << 0xa)|(bb##UL << 0xb) | \ 62 (bc##UL << 0xc)|(bd##UL << 0xd)|(be##UL << 0xe)|(bf##UL << 0xf)) \ 63 << (row % 32)) 64 65 /* 66 * Good-instruction tables for 32-bit apps. This is non-const and volatile 67 * to keep gcc from statically optimizing it out, as variable_test_bit makes 68 * some versions of gcc to think only *(unsigned long*) is used. 69 */ 70 static volatile u32 good_insns_32[256 / 32] = { 71 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 72 /* ---------------------------------------------- */ 73 W(0x00, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) | /* 00 */ 74 W(0x10, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 10 */ 75 W(0x20, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1) | /* 20 */ 76 W(0x30, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1) , /* 30 */ 77 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */ 78 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */ 79 W(0x60, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */ 80 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */ 81 W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */ 82 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */ 83 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */ 84 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */ 85 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */ 86 W(0xd0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */ 87 W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* e0 */ 88 W(0xf0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */ 89 /* ---------------------------------------------- */ 90 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 91 }; 92 93 /* Using this for both 64-bit and 32-bit apps */ 94 static volatile u32 good_2byte_insns[256 / 32] = { 95 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 96 /* ---------------------------------------------- */ 97 W(0x00, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1) | /* 00 */ 98 W(0x10, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1) , /* 10 */ 99 W(0x20, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */ 100 W(0x30, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) , /* 30 */ 101 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */ 102 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */ 103 W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 60 */ 104 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1) , /* 70 */ 105 W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */ 106 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */ 107 W(0xa0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1) | /* a0 */ 108 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1) , /* b0 */ 109 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* c0 */ 110 W(0xd0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */ 111 W(0xe0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* e0 */ 112 W(0xf0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0) /* f0 */ 113 /* ---------------------------------------------- */ 114 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 115 }; 116 117 #ifdef CONFIG_X86_64 118 /* Good-instruction tables for 64-bit apps */ 119 static volatile u32 good_insns_64[256 / 32] = { 120 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 121 /* ---------------------------------------------- */ 122 W(0x00, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) | /* 00 */ 123 W(0x10, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) , /* 10 */ 124 W(0x20, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) | /* 20 */ 125 W(0x30, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) , /* 30 */ 126 W(0x40, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) | /* 40 */ 127 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */ 128 W(0x60, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */ 129 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */ 130 W(0x80, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */ 131 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */ 132 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */ 133 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */ 134 W(0xc0, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */ 135 W(0xd0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */ 136 W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* e0 */ 137 W(0xf0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */ 138 /* ---------------------------------------------- */ 139 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 140 }; 141 #endif 142 #undef W 143 144 /* 145 * opcodes we'll probably never support: 146 * 147 * 6c-6d, e4-e5, ec-ed - in 148 * 6e-6f, e6-e7, ee-ef - out 149 * cc, cd - int3, int 150 * cf - iret 151 * d6 - illegal instruction 152 * f1 - int1/icebp 153 * f4 - hlt 154 * fa, fb - cli, sti 155 * 0f - lar, lsl, syscall, clts, sysret, sysenter, sysexit, invd, wbinvd, ud2 156 * 157 * invalid opcodes in 64-bit mode: 158 * 159 * 06, 0e, 16, 1e, 27, 2f, 37, 3f, 60-62, 82, c4-c5, d4-d5 160 * 63 - we support this opcode in x86_64 but not in i386. 161 * 162 * opcodes we may need to refine support for: 163 * 164 * 0f - 2-byte instructions: For many of these instructions, the validity 165 * depends on the prefix and/or the reg field. On such instructions, we 166 * just consider the opcode combination valid if it corresponds to any 167 * valid instruction. 168 * 169 * 8f - Group 1 - only reg = 0 is OK 170 * c6-c7 - Group 11 - only reg = 0 is OK 171 * d9-df - fpu insns with some illegal encodings 172 * f2, f3 - repnz, repz prefixes. These are also the first byte for 173 * certain floating-point instructions, such as addsd. 174 * 175 * fe - Group 4 - only reg = 0 or 1 is OK 176 * ff - Group 5 - only reg = 0-6 is OK 177 * 178 * others -- Do we need to support these? 179 * 180 * 0f - (floating-point?) prefetch instructions 181 * 07, 17, 1f - pop es, pop ss, pop ds 182 * 26, 2e, 36, 3e - es:, cs:, ss:, ds: segment prefixes -- 183 * but 64 and 65 (fs: and gs:) seem to be used, so we support them 184 * 67 - addr16 prefix 185 * ce - into 186 * f0 - lock prefix 187 */ 188 189 /* 190 * TODO: 191 * - Where necessary, examine the modrm byte and allow only valid instructions 192 * in the different Groups and fpu instructions. 193 */ 194 195 static bool is_prefix_bad(struct insn *insn) 196 { 197 int i; 198 199 for (i = 0; i < insn->prefixes.nbytes; i++) { 200 switch (insn->prefixes.bytes[i]) { 201 case 0x26: /* INAT_PFX_ES */ 202 case 0x2E: /* INAT_PFX_CS */ 203 case 0x36: /* INAT_PFX_DS */ 204 case 0x3E: /* INAT_PFX_SS */ 205 case 0xF0: /* INAT_PFX_LOCK */ 206 return true; 207 } 208 } 209 return false; 210 } 211 212 static int validate_insn_32bits(struct arch_uprobe *auprobe, struct insn *insn) 213 { 214 insn_init(insn, auprobe->insn, false); 215 216 /* Skip good instruction prefixes; reject "bad" ones. */ 217 insn_get_opcode(insn); 218 if (is_prefix_bad(insn)) 219 return -ENOTSUPP; 220 221 if (test_bit(OPCODE1(insn), (unsigned long *)good_insns_32)) 222 return 0; 223 224 if (insn->opcode.nbytes == 2) { 225 if (test_bit(OPCODE2(insn), (unsigned long *)good_2byte_insns)) 226 return 0; 227 } 228 229 return -ENOTSUPP; 230 } 231 232 #ifdef CONFIG_X86_64 233 /* 234 * If arch_uprobe->insn doesn't use rip-relative addressing, return 235 * immediately. Otherwise, rewrite the instruction so that it accesses 236 * its memory operand indirectly through a scratch register. Set 237 * arch_uprobe->fixups and arch_uprobe->rip_rela_target_address 238 * accordingly. (The contents of the scratch register will be saved 239 * before we single-step the modified instruction, and restored 240 * afterward.) 241 * 242 * We do this because a rip-relative instruction can access only a 243 * relatively small area (+/- 2 GB from the instruction), and the XOL 244 * area typically lies beyond that area. At least for instructions 245 * that store to memory, we can't execute the original instruction 246 * and "fix things up" later, because the misdirected store could be 247 * disastrous. 248 * 249 * Some useful facts about rip-relative instructions: 250 * 251 * - There's always a modrm byte. 252 * - There's never a SIB byte. 253 * - The displacement is always 4 bytes. 254 */ 255 static void 256 handle_riprel_insn(struct arch_uprobe *auprobe, struct insn *insn) 257 { 258 u8 *cursor; 259 u8 reg; 260 261 if (!insn_rip_relative(insn)) 262 return; 263 264 /* 265 * insn_rip_relative() would have decoded rex_prefix, modrm. 266 * Clear REX.b bit (extension of MODRM.rm field): 267 * we want to encode rax/rcx, not r8/r9. 268 */ 269 if (insn->rex_prefix.nbytes) { 270 cursor = auprobe->insn + insn_offset_rex_prefix(insn); 271 *cursor &= 0xfe; /* Clearing REX.B bit */ 272 } 273 274 /* 275 * Point cursor at the modrm byte. The next 4 bytes are the 276 * displacement. Beyond the displacement, for some instructions, 277 * is the immediate operand. 278 */ 279 cursor = auprobe->insn + insn_offset_modrm(insn); 280 insn_get_length(insn); 281 282 /* 283 * Convert from rip-relative addressing to indirect addressing 284 * via a scratch register. Change the r/m field from 0x5 (%rip) 285 * to 0x0 (%rax) or 0x1 (%rcx), and squeeze out the offset field. 286 */ 287 reg = MODRM_REG(insn); 288 if (reg == 0) { 289 /* 290 * The register operand (if any) is either the A register 291 * (%rax, %eax, etc.) or (if the 0x4 bit is set in the 292 * REX prefix) %r8. In any case, we know the C register 293 * is NOT the register operand, so we use %rcx (register 294 * #1) for the scratch register. 295 */ 296 auprobe->fixups = UPROBE_FIX_RIP_CX; 297 /* Change modrm from 00 000 101 to 00 000 001. */ 298 *cursor = 0x1; 299 } else { 300 /* Use %rax (register #0) for the scratch register. */ 301 auprobe->fixups = UPROBE_FIX_RIP_AX; 302 /* Change modrm from 00 xxx 101 to 00 xxx 000 */ 303 *cursor = (reg << 3); 304 } 305 306 /* Target address = address of next instruction + (signed) offset */ 307 auprobe->rip_rela_target_address = (long)insn->length + insn->displacement.value; 308 309 /* Displacement field is gone; slide immediate field (if any) over. */ 310 if (insn->immediate.nbytes) { 311 cursor++; 312 memmove(cursor, cursor + insn->displacement.nbytes, insn->immediate.nbytes); 313 } 314 } 315 316 /* 317 * If we're emulating a rip-relative instruction, save the contents 318 * of the scratch register and store the target address in that register. 319 */ 320 static void 321 pre_xol_rip_insn(struct arch_uprobe *auprobe, struct pt_regs *regs, 322 struct arch_uprobe_task *autask) 323 { 324 if (auprobe->fixups & UPROBE_FIX_RIP_AX) { 325 autask->saved_scratch_register = regs->ax; 326 regs->ax = current->utask->vaddr; 327 regs->ax += auprobe->rip_rela_target_address; 328 } else if (auprobe->fixups & UPROBE_FIX_RIP_CX) { 329 autask->saved_scratch_register = regs->cx; 330 regs->cx = current->utask->vaddr; 331 regs->cx += auprobe->rip_rela_target_address; 332 } 333 } 334 335 static void 336 handle_riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs, long *correction) 337 { 338 if (auprobe->fixups & (UPROBE_FIX_RIP_AX | UPROBE_FIX_RIP_CX)) { 339 struct arch_uprobe_task *autask; 340 341 autask = ¤t->utask->autask; 342 if (auprobe->fixups & UPROBE_FIX_RIP_AX) 343 regs->ax = autask->saved_scratch_register; 344 else 345 regs->cx = autask->saved_scratch_register; 346 347 /* 348 * The original instruction includes a displacement, and so 349 * is 4 bytes longer than what we've just single-stepped. 350 * Caller may need to apply other fixups to handle stuff 351 * like "jmpq *...(%rip)" and "callq *...(%rip)". 352 */ 353 if (correction) 354 *correction += 4; 355 } 356 } 357 358 static int validate_insn_64bits(struct arch_uprobe *auprobe, struct insn *insn) 359 { 360 insn_init(insn, auprobe->insn, true); 361 362 /* Skip good instruction prefixes; reject "bad" ones. */ 363 insn_get_opcode(insn); 364 if (is_prefix_bad(insn)) 365 return -ENOTSUPP; 366 367 if (test_bit(OPCODE1(insn), (unsigned long *)good_insns_64)) 368 return 0; 369 370 if (insn->opcode.nbytes == 2) { 371 if (test_bit(OPCODE2(insn), (unsigned long *)good_2byte_insns)) 372 return 0; 373 } 374 return -ENOTSUPP; 375 } 376 377 static int validate_insn_bits(struct arch_uprobe *auprobe, struct mm_struct *mm, struct insn *insn) 378 { 379 if (mm->context.ia32_compat) 380 return validate_insn_32bits(auprobe, insn); 381 return validate_insn_64bits(auprobe, insn); 382 } 383 #else /* 32-bit: */ 384 /* 385 * No RIP-relative addressing on 32-bit 386 */ 387 static void handle_riprel_insn(struct arch_uprobe *auprobe, struct insn *insn) 388 { 389 } 390 static void pre_xol_rip_insn(struct arch_uprobe *auprobe, struct pt_regs *regs, 391 struct arch_uprobe_task *autask) 392 { 393 } 394 static void handle_riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs, 395 long *correction) 396 { 397 } 398 399 static int validate_insn_bits(struct arch_uprobe *auprobe, struct mm_struct *mm, struct insn *insn) 400 { 401 return validate_insn_32bits(auprobe, insn); 402 } 403 #endif /* CONFIG_X86_64 */ 404 405 struct uprobe_xol_ops { 406 bool (*emulate)(struct arch_uprobe *, struct pt_regs *); 407 int (*pre_xol)(struct arch_uprobe *, struct pt_regs *); 408 int (*post_xol)(struct arch_uprobe *, struct pt_regs *); 409 }; 410 411 static inline int sizeof_long(void) 412 { 413 return is_ia32_task() ? 4 : 8; 414 } 415 416 static int default_pre_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs) 417 { 418 pre_xol_rip_insn(auprobe, regs, ¤t->utask->autask); 419 return 0; 420 } 421 422 /* 423 * Adjust the return address pushed by a call insn executed out of line. 424 */ 425 static int adjust_ret_addr(unsigned long sp, long correction) 426 { 427 int rasize = sizeof_long(); 428 long ra; 429 430 if (copy_from_user(&ra, (void __user *)sp, rasize)) 431 return -EFAULT; 432 433 ra += correction; 434 if (copy_to_user((void __user *)sp, &ra, rasize)) 435 return -EFAULT; 436 437 return 0; 438 } 439 440 static int default_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs) 441 { 442 struct uprobe_task *utask = current->utask; 443 long correction = (long)(utask->vaddr - utask->xol_vaddr); 444 445 handle_riprel_post_xol(auprobe, regs, &correction); 446 if (auprobe->fixups & UPROBE_FIX_IP) 447 regs->ip += correction; 448 449 if (auprobe->fixups & UPROBE_FIX_CALL) { 450 if (adjust_ret_addr(regs->sp, correction)) { 451 regs->sp += sizeof_long(); 452 return -ERESTART; 453 } 454 } 455 456 return 0; 457 } 458 459 static struct uprobe_xol_ops default_xol_ops = { 460 .pre_xol = default_pre_xol_op, 461 .post_xol = default_post_xol_op, 462 }; 463 464 static bool branch_is_call(struct arch_uprobe *auprobe) 465 { 466 return auprobe->branch.opc1 == 0xe8; 467 } 468 469 #define CASE_COND \ 470 COND(70, 71, XF(OF)) \ 471 COND(72, 73, XF(CF)) \ 472 COND(74, 75, XF(ZF)) \ 473 COND(78, 79, XF(SF)) \ 474 COND(7a, 7b, XF(PF)) \ 475 COND(76, 77, XF(CF) || XF(ZF)) \ 476 COND(7c, 7d, XF(SF) != XF(OF)) \ 477 COND(7e, 7f, XF(ZF) || XF(SF) != XF(OF)) 478 479 #define COND(op_y, op_n, expr) \ 480 case 0x ## op_y: DO((expr) != 0) \ 481 case 0x ## op_n: DO((expr) == 0) 482 483 #define XF(xf) (!!(flags & X86_EFLAGS_ ## xf)) 484 485 static bool is_cond_jmp_opcode(u8 opcode) 486 { 487 switch (opcode) { 488 #define DO(expr) \ 489 return true; 490 CASE_COND 491 #undef DO 492 493 default: 494 return false; 495 } 496 } 497 498 static bool check_jmp_cond(struct arch_uprobe *auprobe, struct pt_regs *regs) 499 { 500 unsigned long flags = regs->flags; 501 502 switch (auprobe->branch.opc1) { 503 #define DO(expr) \ 504 return expr; 505 CASE_COND 506 #undef DO 507 508 default: /* not a conditional jmp */ 509 return true; 510 } 511 } 512 513 #undef XF 514 #undef COND 515 #undef CASE_COND 516 517 static bool branch_emulate_op(struct arch_uprobe *auprobe, struct pt_regs *regs) 518 { 519 unsigned long new_ip = regs->ip += auprobe->branch.ilen; 520 unsigned long offs = (long)auprobe->branch.offs; 521 522 if (branch_is_call(auprobe)) { 523 unsigned long new_sp = regs->sp - sizeof_long(); 524 /* 525 * If it fails we execute this (mangled, see the comment in 526 * branch_clear_offset) insn out-of-line. In the likely case 527 * this should trigger the trap, and the probed application 528 * should die or restart the same insn after it handles the 529 * signal, arch_uprobe_post_xol() won't be even called. 530 * 531 * But there is corner case, see the comment in ->post_xol(). 532 */ 533 if (copy_to_user((void __user *)new_sp, &new_ip, sizeof_long())) 534 return false; 535 regs->sp = new_sp; 536 } else if (!check_jmp_cond(auprobe, regs)) { 537 offs = 0; 538 } 539 540 regs->ip = new_ip + offs; 541 return true; 542 } 543 544 static int branch_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs) 545 { 546 BUG_ON(!branch_is_call(auprobe)); 547 /* 548 * We can only get here if branch_emulate_op() failed to push the ret 549 * address _and_ another thread expanded our stack before the (mangled) 550 * "call" insn was executed out-of-line. Just restore ->sp and restart. 551 * We could also restore ->ip and try to call branch_emulate_op() again. 552 */ 553 regs->sp += sizeof_long(); 554 return -ERESTART; 555 } 556 557 static void branch_clear_offset(struct arch_uprobe *auprobe, struct insn *insn) 558 { 559 /* 560 * Turn this insn into "call 1f; 1:", this is what we will execute 561 * out-of-line if ->emulate() fails. We only need this to generate 562 * a trap, so that the probed task receives the correct signal with 563 * the properly filled siginfo. 564 * 565 * But see the comment in ->post_xol(), in the unlikely case it can 566 * succeed. So we need to ensure that the new ->ip can not fall into 567 * the non-canonical area and trigger #GP. 568 * 569 * We could turn it into (say) "pushf", but then we would need to 570 * divorce ->insn[] and ->ixol[]. We need to preserve the 1st byte 571 * of ->insn[] for set_orig_insn(). 572 */ 573 memset(auprobe->insn + insn_offset_immediate(insn), 574 0, insn->immediate.nbytes); 575 } 576 577 static struct uprobe_xol_ops branch_xol_ops = { 578 .emulate = branch_emulate_op, 579 .post_xol = branch_post_xol_op, 580 }; 581 582 /* Returns -ENOSYS if branch_xol_ops doesn't handle this insn */ 583 static int branch_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn) 584 { 585 u8 opc1 = OPCODE1(insn); 586 587 /* has the side-effect of processing the entire instruction */ 588 insn_get_length(insn); 589 if (WARN_ON_ONCE(!insn_complete(insn))) 590 return -ENOEXEC; 591 592 switch (opc1) { 593 case 0xeb: /* jmp 8 */ 594 case 0xe9: /* jmp 32 */ 595 case 0x90: /* prefix* + nop; same as jmp with .offs = 0 */ 596 break; 597 598 case 0xe8: /* call relative */ 599 branch_clear_offset(auprobe, insn); 600 break; 601 602 case 0x0f: 603 if (insn->opcode.nbytes != 2) 604 return -ENOSYS; 605 /* 606 * If it is a "near" conditional jmp, OPCODE2() - 0x10 matches 607 * OPCODE1() of the "short" jmp which checks the same condition. 608 */ 609 opc1 = OPCODE2(insn) - 0x10; 610 default: 611 if (!is_cond_jmp_opcode(opc1)) 612 return -ENOSYS; 613 } 614 615 auprobe->branch.opc1 = opc1; 616 auprobe->branch.ilen = insn->length; 617 auprobe->branch.offs = insn->immediate.value; 618 619 auprobe->ops = &branch_xol_ops; 620 return 0; 621 } 622 623 /** 624 * arch_uprobe_analyze_insn - instruction analysis including validity and fixups. 625 * @mm: the probed address space. 626 * @arch_uprobe: the probepoint information. 627 * @addr: virtual address at which to install the probepoint 628 * Return 0 on success or a -ve number on error. 629 */ 630 int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, unsigned long addr) 631 { 632 struct insn insn; 633 bool fix_ip = true, fix_call = false; 634 int ret; 635 636 ret = validate_insn_bits(auprobe, mm, &insn); 637 if (ret) 638 return ret; 639 640 ret = branch_setup_xol_ops(auprobe, &insn); 641 if (ret != -ENOSYS) 642 return ret; 643 644 /* 645 * Figure out which fixups arch_uprobe_post_xol() will need to perform, 646 * and annotate arch_uprobe->fixups accordingly. To start with, ->fixups 647 * is either zero or it reflects rip-related fixups. 648 */ 649 switch (OPCODE1(&insn)) { 650 case 0x9d: /* popf */ 651 auprobe->fixups |= UPROBE_FIX_SETF; 652 break; 653 case 0xc3: /* ret or lret -- ip is correct */ 654 case 0xcb: 655 case 0xc2: 656 case 0xca: 657 fix_ip = false; 658 break; 659 case 0x9a: /* call absolute - Fix return addr, not ip */ 660 fix_call = true; 661 fix_ip = false; 662 break; 663 case 0xea: /* jmp absolute -- ip is correct */ 664 fix_ip = false; 665 break; 666 case 0xff: 667 insn_get_modrm(&insn); 668 switch (MODRM_REG(&insn)) { 669 case 2: case 3: /* call or lcall, indirect */ 670 fix_call = true; 671 case 4: case 5: /* jmp or ljmp, indirect */ 672 fix_ip = false; 673 } 674 /* fall through */ 675 default: 676 handle_riprel_insn(auprobe, &insn); 677 } 678 679 if (fix_ip) 680 auprobe->fixups |= UPROBE_FIX_IP; 681 if (fix_call) 682 auprobe->fixups |= UPROBE_FIX_CALL; 683 684 auprobe->ops = &default_xol_ops; 685 return 0; 686 } 687 688 /* 689 * arch_uprobe_pre_xol - prepare to execute out of line. 690 * @auprobe: the probepoint information. 691 * @regs: reflects the saved user state of current task. 692 */ 693 int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) 694 { 695 struct uprobe_task *utask = current->utask; 696 697 regs->ip = utask->xol_vaddr; 698 utask->autask.saved_trap_nr = current->thread.trap_nr; 699 current->thread.trap_nr = UPROBE_TRAP_NR; 700 701 utask->autask.saved_tf = !!(regs->flags & X86_EFLAGS_TF); 702 regs->flags |= X86_EFLAGS_TF; 703 if (test_tsk_thread_flag(current, TIF_BLOCKSTEP)) 704 set_task_blockstep(current, false); 705 706 if (auprobe->ops->pre_xol) 707 return auprobe->ops->pre_xol(auprobe, regs); 708 return 0; 709 } 710 711 /* 712 * If xol insn itself traps and generates a signal(Say, 713 * SIGILL/SIGSEGV/etc), then detect the case where a singlestepped 714 * instruction jumps back to its own address. It is assumed that anything 715 * like do_page_fault/do_trap/etc sets thread.trap_nr != -1. 716 * 717 * arch_uprobe_pre_xol/arch_uprobe_post_xol save/restore thread.trap_nr, 718 * arch_uprobe_xol_was_trapped() simply checks that ->trap_nr is not equal to 719 * UPROBE_TRAP_NR == -1 set by arch_uprobe_pre_xol(). 720 */ 721 bool arch_uprobe_xol_was_trapped(struct task_struct *t) 722 { 723 if (t->thread.trap_nr != UPROBE_TRAP_NR) 724 return true; 725 726 return false; 727 } 728 729 /* 730 * Called after single-stepping. To avoid the SMP problems that can 731 * occur when we temporarily put back the original opcode to 732 * single-step, we single-stepped a copy of the instruction. 733 * 734 * This function prepares to resume execution after the single-step. 735 * We have to fix things up as follows: 736 * 737 * Typically, the new ip is relative to the copied instruction. We need 738 * to make it relative to the original instruction (FIX_IP). Exceptions 739 * are return instructions and absolute or indirect jump or call instructions. 740 * 741 * If the single-stepped instruction was a call, the return address that 742 * is atop the stack is the address following the copied instruction. We 743 * need to make it the address following the original instruction (FIX_CALL). 744 * 745 * If the original instruction was a rip-relative instruction such as 746 * "movl %edx,0xnnnn(%rip)", we have instead executed an equivalent 747 * instruction using a scratch register -- e.g., "movl %edx,(%rax)". 748 * We need to restore the contents of the scratch register and adjust 749 * the ip, keeping in mind that the instruction we executed is 4 bytes 750 * shorter than the original instruction (since we squeezed out the offset 751 * field). (FIX_RIP_AX or FIX_RIP_CX) 752 */ 753 int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) 754 { 755 struct uprobe_task *utask = current->utask; 756 757 WARN_ON_ONCE(current->thread.trap_nr != UPROBE_TRAP_NR); 758 759 if (auprobe->ops->post_xol) { 760 int err = auprobe->ops->post_xol(auprobe, regs); 761 if (err) { 762 arch_uprobe_abort_xol(auprobe, regs); 763 /* 764 * Restart the probed insn. ->post_xol() must ensure 765 * this is really possible if it returns -ERESTART. 766 */ 767 if (err == -ERESTART) 768 return 0; 769 return err; 770 } 771 } 772 773 current->thread.trap_nr = utask->autask.saved_trap_nr; 774 /* 775 * arch_uprobe_pre_xol() doesn't save the state of TIF_BLOCKSTEP 776 * so we can get an extra SIGTRAP if we do not clear TF. We need 777 * to examine the opcode to make it right. 778 */ 779 if (utask->autask.saved_tf) 780 send_sig(SIGTRAP, current, 0); 781 else if (!(auprobe->fixups & UPROBE_FIX_SETF)) 782 regs->flags &= ~X86_EFLAGS_TF; 783 784 return 0; 785 } 786 787 /* callback routine for handling exceptions. */ 788 int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, void *data) 789 { 790 struct die_args *args = data; 791 struct pt_regs *regs = args->regs; 792 int ret = NOTIFY_DONE; 793 794 /* We are only interested in userspace traps */ 795 if (regs && !user_mode_vm(regs)) 796 return NOTIFY_DONE; 797 798 switch (val) { 799 case DIE_INT3: 800 if (uprobe_pre_sstep_notifier(regs)) 801 ret = NOTIFY_STOP; 802 803 break; 804 805 case DIE_DEBUG: 806 if (uprobe_post_sstep_notifier(regs)) 807 ret = NOTIFY_STOP; 808 809 default: 810 break; 811 } 812 813 return ret; 814 } 815 816 /* 817 * This function gets called when XOL instruction either gets trapped or 818 * the thread has a fatal signal, or if arch_uprobe_post_xol() failed. 819 * Reset the instruction pointer to its probed address for the potential 820 * restart or for post mortem analysis. 821 */ 822 void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) 823 { 824 struct uprobe_task *utask = current->utask; 825 826 current->thread.trap_nr = utask->autask.saved_trap_nr; 827 handle_riprel_post_xol(auprobe, regs, NULL); 828 instruction_pointer_set(regs, utask->vaddr); 829 830 /* clear TF if it was set by us in arch_uprobe_pre_xol() */ 831 if (!utask->autask.saved_tf) 832 regs->flags &= ~X86_EFLAGS_TF; 833 } 834 835 static bool __skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs) 836 { 837 if (auprobe->ops->emulate) 838 return auprobe->ops->emulate(auprobe, regs); 839 return false; 840 } 841 842 bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs) 843 { 844 bool ret = __skip_sstep(auprobe, regs); 845 if (ret && (regs->flags & X86_EFLAGS_TF)) 846 send_sig(SIGTRAP, current, 0); 847 return ret; 848 } 849 850 unsigned long 851 arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr, struct pt_regs *regs) 852 { 853 int rasize = sizeof_long(), nleft; 854 unsigned long orig_ret_vaddr = 0; /* clear high bits for 32-bit apps */ 855 856 if (copy_from_user(&orig_ret_vaddr, (void __user *)regs->sp, rasize)) 857 return -1; 858 859 /* check whether address has been already hijacked */ 860 if (orig_ret_vaddr == trampoline_vaddr) 861 return orig_ret_vaddr; 862 863 nleft = copy_to_user((void __user *)regs->sp, &trampoline_vaddr, rasize); 864 if (likely(!nleft)) 865 return orig_ret_vaddr; 866 867 if (nleft != rasize) { 868 pr_err("uprobe: return address clobbered: pid=%d, %%sp=%#lx, " 869 "%%ip=%#lx\n", current->pid, regs->sp, regs->ip); 870 871 force_sig_info(SIGSEGV, SEND_SIG_FORCED, current); 872 } 873 874 return -1; 875 } 876