1 /* 2 * User-space Probes (UProbes) for x86 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 * 18 * Copyright (C) IBM Corporation, 2008-2011 19 * Authors: 20 * Srikar Dronamraju 21 * Jim Keniston 22 */ 23 #include <linux/kernel.h> 24 #include <linux/sched.h> 25 #include <linux/ptrace.h> 26 #include <linux/uprobes.h> 27 #include <linux/uaccess.h> 28 29 #include <linux/kdebug.h> 30 #include <asm/processor.h> 31 #include <asm/insn.h> 32 #include <asm/mmu_context.h> 33 34 /* Post-execution fixups. */ 35 36 /* Adjust IP back to vicinity of actual insn */ 37 #define UPROBE_FIX_IP 0x01 38 39 /* Adjust the return address of a call insn */ 40 #define UPROBE_FIX_CALL 0x02 41 42 /* Instruction will modify TF, don't change it */ 43 #define UPROBE_FIX_SETF 0x04 44 45 #define UPROBE_FIX_RIP_SI 0x08 46 #define UPROBE_FIX_RIP_DI 0x10 47 #define UPROBE_FIX_RIP_BX 0x20 48 #define UPROBE_FIX_RIP_MASK \ 49 (UPROBE_FIX_RIP_SI | UPROBE_FIX_RIP_DI | UPROBE_FIX_RIP_BX) 50 51 #define UPROBE_TRAP_NR UINT_MAX 52 53 /* Adaptations for mhiramat x86 decoder v14. */ 54 #define OPCODE1(insn) ((insn)->opcode.bytes[0]) 55 #define OPCODE2(insn) ((insn)->opcode.bytes[1]) 56 #define OPCODE3(insn) ((insn)->opcode.bytes[2]) 57 #define MODRM_REG(insn) X86_MODRM_REG((insn)->modrm.value) 58 59 #define W(row, b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, ba, bb, bc, bd, be, bf)\ 60 (((b0##UL << 0x0)|(b1##UL << 0x1)|(b2##UL << 0x2)|(b3##UL << 0x3) | \ 61 (b4##UL << 0x4)|(b5##UL << 0x5)|(b6##UL << 0x6)|(b7##UL << 0x7) | \ 62 (b8##UL << 0x8)|(b9##UL << 0x9)|(ba##UL << 0xa)|(bb##UL << 0xb) | \ 63 (bc##UL << 0xc)|(bd##UL << 0xd)|(be##UL << 0xe)|(bf##UL << 0xf)) \ 64 << (row % 32)) 65 66 /* 67 * Good-instruction tables for 32-bit apps. This is non-const and volatile 68 * to keep gcc from statically optimizing it out, as variable_test_bit makes 69 * some versions of gcc to think only *(unsigned long*) is used. 70 * 71 * Opcodes we'll probably never support: 72 * 6c-6f - ins,outs. SEGVs if used in userspace 73 * e4-e7 - in,out imm. SEGVs if used in userspace 74 * ec-ef - in,out acc. SEGVs if used in userspace 75 * cc - int3. SIGTRAP if used in userspace 76 * ce - into. Not used in userspace - no kernel support to make it useful. SEGVs 77 * (why we support bound (62) then? it's similar, and similarly unused...) 78 * f1 - int1. SIGTRAP if used in userspace 79 * f4 - hlt. SEGVs if used in userspace 80 * fa - cli. SEGVs if used in userspace 81 * fb - sti. SEGVs if used in userspace 82 * 83 * Opcodes which need some work to be supported: 84 * 07,17,1f - pop es/ss/ds 85 * Normally not used in userspace, but would execute if used. 86 * Can cause GP or stack exception if tries to load wrong segment descriptor. 87 * We hesitate to run them under single step since kernel's handling 88 * of userspace single-stepping (TF flag) is fragile. 89 * We can easily refuse to support push es/cs/ss/ds (06/0e/16/1e) 90 * on the same grounds that they are never used. 91 * cd - int N. 92 * Used by userspace for "int 80" syscall entry. (Other "int N" 93 * cause GP -> SEGV since their IDT gates don't allow calls from CPL 3). 94 * Not supported since kernel's handling of userspace single-stepping 95 * (TF flag) is fragile. 96 * cf - iret. Normally not used in userspace. Doesn't SEGV unless arguments are bad 97 */ 98 #if defined(CONFIG_X86_32) || defined(CONFIG_IA32_EMULATION) 99 static volatile u32 good_insns_32[256 / 32] = { 100 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 101 /* ---------------------------------------------- */ 102 W(0x00, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1) | /* 00 */ 103 W(0x10, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 10 */ 104 W(0x20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */ 105 W(0x30, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 30 */ 106 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */ 107 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */ 108 W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */ 109 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */ 110 W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */ 111 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */ 112 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */ 113 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */ 114 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */ 115 W(0xd0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */ 116 W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* e0 */ 117 W(0xf0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */ 118 /* ---------------------------------------------- */ 119 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 120 }; 121 #else 122 #define good_insns_32 NULL 123 #endif 124 125 /* Good-instruction tables for 64-bit apps. 126 * 127 * Genuinely invalid opcodes: 128 * 06,07 - formerly push/pop es 129 * 0e - formerly push cs 130 * 16,17 - formerly push/pop ss 131 * 1e,1f - formerly push/pop ds 132 * 27,2f,37,3f - formerly daa/das/aaa/aas 133 * 60,61 - formerly pusha/popa 134 * 62 - formerly bound. EVEX prefix for AVX512 (not yet supported) 135 * 82 - formerly redundant encoding of Group1 136 * 9a - formerly call seg:ofs 137 * ce - formerly into 138 * d4,d5 - formerly aam/aad 139 * d6 - formerly undocumented salc 140 * ea - formerly jmp seg:ofs 141 * 142 * Opcodes we'll probably never support: 143 * 6c-6f - ins,outs. SEGVs if used in userspace 144 * e4-e7 - in,out imm. SEGVs if used in userspace 145 * ec-ef - in,out acc. SEGVs if used in userspace 146 * cc - int3. SIGTRAP if used in userspace 147 * f1 - int1. SIGTRAP if used in userspace 148 * f4 - hlt. SEGVs if used in userspace 149 * fa - cli. SEGVs if used in userspace 150 * fb - sti. SEGVs if used in userspace 151 * 152 * Opcodes which need some work to be supported: 153 * cd - int N. 154 * Used by userspace for "int 80" syscall entry. (Other "int N" 155 * cause GP -> SEGV since their IDT gates don't allow calls from CPL 3). 156 * Not supported since kernel's handling of userspace single-stepping 157 * (TF flag) is fragile. 158 * cf - iret. Normally not used in userspace. Doesn't SEGV unless arguments are bad 159 */ 160 #if defined(CONFIG_X86_64) 161 static volatile u32 good_insns_64[256 / 32] = { 162 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 163 /* ---------------------------------------------- */ 164 W(0x00, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1) | /* 00 */ 165 W(0x10, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) , /* 10 */ 166 W(0x20, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) | /* 20 */ 167 W(0x30, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 30 */ 168 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */ 169 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */ 170 W(0x60, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */ 171 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */ 172 W(0x80, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */ 173 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1) , /* 90 */ 174 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */ 175 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */ 176 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */ 177 W(0xd0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */ 178 W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0) | /* e0 */ 179 W(0xf0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */ 180 /* ---------------------------------------------- */ 181 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 182 }; 183 #else 184 #define good_insns_64 NULL 185 #endif 186 187 /* Using this for both 64-bit and 32-bit apps. 188 * Opcodes we don't support: 189 * 0f 00 - SLDT/STR/LLDT/LTR/VERR/VERW/-/- group. System insns 190 * 0f 01 - SGDT/SIDT/LGDT/LIDT/SMSW/-/LMSW/INVLPG group. 191 * Also encodes tons of other system insns if mod=11. 192 * Some are in fact non-system: xend, xtest, rdtscp, maybe more 193 * 0f 05 - syscall 194 * 0f 06 - clts (CPL0 insn) 195 * 0f 07 - sysret 196 * 0f 08 - invd (CPL0 insn) 197 * 0f 09 - wbinvd (CPL0 insn) 198 * 0f 0b - ud2 199 * 0f 30 - wrmsr (CPL0 insn) (then why rdmsr is allowed, it's also CPL0 insn?) 200 * 0f 34 - sysenter 201 * 0f 35 - sysexit 202 * 0f 37 - getsec 203 * 0f 78 - vmread (Intel VMX. CPL0 insn) 204 * 0f 79 - vmwrite (Intel VMX. CPL0 insn) 205 * Note: with prefixes, these two opcodes are 206 * extrq/insertq/AVX512 convert vector ops. 207 * 0f ae - group15: [f]xsave,[f]xrstor,[v]{ld,st}mxcsr,clflush[opt], 208 * {rd,wr}{fs,gs}base,{s,l,m}fence. 209 * Why? They are all user-executable. 210 */ 211 static volatile u32 good_2byte_insns[256 / 32] = { 212 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 213 /* ---------------------------------------------- */ 214 W(0x00, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1) | /* 00 */ 215 W(0x10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 10 */ 216 W(0x20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */ 217 W(0x30, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1) , /* 30 */ 218 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */ 219 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */ 220 W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 60 */ 221 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1) , /* 70 */ 222 W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */ 223 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */ 224 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1) | /* a0 */ 225 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */ 226 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* c0 */ 227 W(0xd0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */ 228 W(0xe0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* e0 */ 229 W(0xf0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) /* f0 */ 230 /* ---------------------------------------------- */ 231 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 232 }; 233 #undef W 234 235 /* 236 * opcodes we may need to refine support for: 237 * 238 * 0f - 2-byte instructions: For many of these instructions, the validity 239 * depends on the prefix and/or the reg field. On such instructions, we 240 * just consider the opcode combination valid if it corresponds to any 241 * valid instruction. 242 * 243 * 8f - Group 1 - only reg = 0 is OK 244 * c6-c7 - Group 11 - only reg = 0 is OK 245 * d9-df - fpu insns with some illegal encodings 246 * f2, f3 - repnz, repz prefixes. These are also the first byte for 247 * certain floating-point instructions, such as addsd. 248 * 249 * fe - Group 4 - only reg = 0 or 1 is OK 250 * ff - Group 5 - only reg = 0-6 is OK 251 * 252 * others -- Do we need to support these? 253 * 254 * 0f - (floating-point?) prefetch instructions 255 * 07, 17, 1f - pop es, pop ss, pop ds 256 * 26, 2e, 36, 3e - es:, cs:, ss:, ds: segment prefixes -- 257 * but 64 and 65 (fs: and gs:) seem to be used, so we support them 258 * 67 - addr16 prefix 259 * ce - into 260 * f0 - lock prefix 261 */ 262 263 /* 264 * TODO: 265 * - Where necessary, examine the modrm byte and allow only valid instructions 266 * in the different Groups and fpu instructions. 267 */ 268 269 static bool is_prefix_bad(struct insn *insn) 270 { 271 int i; 272 273 for (i = 0; i < insn->prefixes.nbytes; i++) { 274 insn_attr_t attr; 275 276 attr = inat_get_opcode_attribute(insn->prefixes.bytes[i]); 277 switch (attr) { 278 case INAT_MAKE_PREFIX(INAT_PFX_ES): 279 case INAT_MAKE_PREFIX(INAT_PFX_CS): 280 case INAT_MAKE_PREFIX(INAT_PFX_DS): 281 case INAT_MAKE_PREFIX(INAT_PFX_SS): 282 case INAT_MAKE_PREFIX(INAT_PFX_LOCK): 283 return true; 284 } 285 } 286 return false; 287 } 288 289 static int uprobe_init_insn(struct arch_uprobe *auprobe, struct insn *insn, bool x86_64) 290 { 291 u32 volatile *good_insns; 292 293 insn_init(insn, auprobe->insn, sizeof(auprobe->insn), x86_64); 294 /* has the side-effect of processing the entire instruction */ 295 insn_get_length(insn); 296 if (!insn_complete(insn)) 297 return -ENOEXEC; 298 299 if (is_prefix_bad(insn)) 300 return -ENOTSUPP; 301 302 /* We should not singlestep on the exception masking instructions */ 303 if (insn_masking_exception(insn)) 304 return -ENOTSUPP; 305 306 if (x86_64) 307 good_insns = good_insns_64; 308 else 309 good_insns = good_insns_32; 310 311 if (test_bit(OPCODE1(insn), (unsigned long *)good_insns)) 312 return 0; 313 314 if (insn->opcode.nbytes == 2) { 315 if (test_bit(OPCODE2(insn), (unsigned long *)good_2byte_insns)) 316 return 0; 317 } 318 319 return -ENOTSUPP; 320 } 321 322 #ifdef CONFIG_X86_64 323 /* 324 * If arch_uprobe->insn doesn't use rip-relative addressing, return 325 * immediately. Otherwise, rewrite the instruction so that it accesses 326 * its memory operand indirectly through a scratch register. Set 327 * defparam->fixups accordingly. (The contents of the scratch register 328 * will be saved before we single-step the modified instruction, 329 * and restored afterward). 330 * 331 * We do this because a rip-relative instruction can access only a 332 * relatively small area (+/- 2 GB from the instruction), and the XOL 333 * area typically lies beyond that area. At least for instructions 334 * that store to memory, we can't execute the original instruction 335 * and "fix things up" later, because the misdirected store could be 336 * disastrous. 337 * 338 * Some useful facts about rip-relative instructions: 339 * 340 * - There's always a modrm byte with bit layout "00 reg 101". 341 * - There's never a SIB byte. 342 * - The displacement is always 4 bytes. 343 * - REX.B=1 bit in REX prefix, which normally extends r/m field, 344 * has no effect on rip-relative mode. It doesn't make modrm byte 345 * with r/m=101 refer to register 1101 = R13. 346 */ 347 static void riprel_analyze(struct arch_uprobe *auprobe, struct insn *insn) 348 { 349 u8 *cursor; 350 u8 reg; 351 u8 reg2; 352 353 if (!insn_rip_relative(insn)) 354 return; 355 356 /* 357 * insn_rip_relative() would have decoded rex_prefix, vex_prefix, modrm. 358 * Clear REX.b bit (extension of MODRM.rm field): 359 * we want to encode low numbered reg, not r8+. 360 */ 361 if (insn->rex_prefix.nbytes) { 362 cursor = auprobe->insn + insn_offset_rex_prefix(insn); 363 /* REX byte has 0100wrxb layout, clearing REX.b bit */ 364 *cursor &= 0xfe; 365 } 366 /* 367 * Similar treatment for VEX3/EVEX prefix. 368 * TODO: add XOP treatment when insn decoder supports them 369 */ 370 if (insn->vex_prefix.nbytes >= 3) { 371 /* 372 * vex2: c5 rvvvvLpp (has no b bit) 373 * vex3/xop: c4/8f rxbmmmmm wvvvvLpp 374 * evex: 62 rxbR00mm wvvvv1pp zllBVaaa 375 * Setting VEX3.b (setting because it has inverted meaning). 376 * Setting EVEX.x since (in non-SIB encoding) EVEX.x 377 * is the 4th bit of MODRM.rm, and needs the same treatment. 378 * For VEX3-encoded insns, VEX3.x value has no effect in 379 * non-SIB encoding, the change is superfluous but harmless. 380 */ 381 cursor = auprobe->insn + insn_offset_vex_prefix(insn) + 1; 382 *cursor |= 0x60; 383 } 384 385 /* 386 * Convert from rip-relative addressing to register-relative addressing 387 * via a scratch register. 388 * 389 * This is tricky since there are insns with modrm byte 390 * which also use registers not encoded in modrm byte: 391 * [i]div/[i]mul: implicitly use dx:ax 392 * shift ops: implicitly use cx 393 * cmpxchg: implicitly uses ax 394 * cmpxchg8/16b: implicitly uses dx:ax and bx:cx 395 * Encoding: 0f c7/1 modrm 396 * The code below thinks that reg=1 (cx), chooses si as scratch. 397 * mulx: implicitly uses dx: mulx r/m,r1,r2 does r1:r2 = dx * r/m. 398 * First appeared in Haswell (BMI2 insn). It is vex-encoded. 399 * Example where none of bx,cx,dx can be used as scratch reg: 400 * c4 e2 63 f6 0d disp32 mulx disp32(%rip),%ebx,%ecx 401 * [v]pcmpistri: implicitly uses cx, xmm0 402 * [v]pcmpistrm: implicitly uses xmm0 403 * [v]pcmpestri: implicitly uses ax, dx, cx, xmm0 404 * [v]pcmpestrm: implicitly uses ax, dx, xmm0 405 * Evil SSE4.2 string comparison ops from hell. 406 * maskmovq/[v]maskmovdqu: implicitly uses (ds:rdi) as destination. 407 * Encoding: 0f f7 modrm, 66 0f f7 modrm, vex-encoded: c5 f9 f7 modrm. 408 * Store op1, byte-masked by op2 msb's in each byte, to (ds:rdi). 409 * AMD says it has no 3-operand form (vex.vvvv must be 1111) 410 * and that it can have only register operands, not mem 411 * (its modrm byte must have mode=11). 412 * If these restrictions will ever be lifted, 413 * we'll need code to prevent selection of di as scratch reg! 414 * 415 * Summary: I don't know any insns with modrm byte which 416 * use SI register implicitly. DI register is used only 417 * by one insn (maskmovq) and BX register is used 418 * only by one too (cmpxchg8b). 419 * BP is stack-segment based (may be a problem?). 420 * AX, DX, CX are off-limits (many implicit users). 421 * SP is unusable (it's stack pointer - think about "pop mem"; 422 * also, rsp+disp32 needs sib encoding -> insn length change). 423 */ 424 425 reg = MODRM_REG(insn); /* Fetch modrm.reg */ 426 reg2 = 0xff; /* Fetch vex.vvvv */ 427 if (insn->vex_prefix.nbytes) 428 reg2 = insn->vex_prefix.bytes[2]; 429 /* 430 * TODO: add XOP vvvv reading. 431 * 432 * vex.vvvv field is in bits 6-3, bits are inverted. 433 * But in 32-bit mode, high-order bit may be ignored. 434 * Therefore, let's consider only 3 low-order bits. 435 */ 436 reg2 = ((reg2 >> 3) & 0x7) ^ 0x7; 437 /* 438 * Register numbering is ax,cx,dx,bx, sp,bp,si,di, r8..r15. 439 * 440 * Choose scratch reg. Order is important: must not select bx 441 * if we can use si (cmpxchg8b case!) 442 */ 443 if (reg != 6 && reg2 != 6) { 444 reg2 = 6; 445 auprobe->defparam.fixups |= UPROBE_FIX_RIP_SI; 446 } else if (reg != 7 && reg2 != 7) { 447 reg2 = 7; 448 auprobe->defparam.fixups |= UPROBE_FIX_RIP_DI; 449 /* TODO (paranoia): force maskmovq to not use di */ 450 } else { 451 reg2 = 3; 452 auprobe->defparam.fixups |= UPROBE_FIX_RIP_BX; 453 } 454 /* 455 * Point cursor at the modrm byte. The next 4 bytes are the 456 * displacement. Beyond the displacement, for some instructions, 457 * is the immediate operand. 458 */ 459 cursor = auprobe->insn + insn_offset_modrm(insn); 460 /* 461 * Change modrm from "00 reg 101" to "10 reg reg2". Example: 462 * 89 05 disp32 mov %eax,disp32(%rip) becomes 463 * 89 86 disp32 mov %eax,disp32(%rsi) 464 */ 465 *cursor = 0x80 | (reg << 3) | reg2; 466 } 467 468 static inline unsigned long * 469 scratch_reg(struct arch_uprobe *auprobe, struct pt_regs *regs) 470 { 471 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_SI) 472 return ®s->si; 473 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_DI) 474 return ®s->di; 475 return ®s->bx; 476 } 477 478 /* 479 * If we're emulating a rip-relative instruction, save the contents 480 * of the scratch register and store the target address in that register. 481 */ 482 static void riprel_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) 483 { 484 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_MASK) { 485 struct uprobe_task *utask = current->utask; 486 unsigned long *sr = scratch_reg(auprobe, regs); 487 488 utask->autask.saved_scratch_register = *sr; 489 *sr = utask->vaddr + auprobe->defparam.ilen; 490 } 491 } 492 493 static void riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) 494 { 495 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_MASK) { 496 struct uprobe_task *utask = current->utask; 497 unsigned long *sr = scratch_reg(auprobe, regs); 498 499 *sr = utask->autask.saved_scratch_register; 500 } 501 } 502 #else /* 32-bit: */ 503 /* 504 * No RIP-relative addressing on 32-bit 505 */ 506 static void riprel_analyze(struct arch_uprobe *auprobe, struct insn *insn) 507 { 508 } 509 static void riprel_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) 510 { 511 } 512 static void riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) 513 { 514 } 515 #endif /* CONFIG_X86_64 */ 516 517 struct uprobe_xol_ops { 518 bool (*emulate)(struct arch_uprobe *, struct pt_regs *); 519 int (*pre_xol)(struct arch_uprobe *, struct pt_regs *); 520 int (*post_xol)(struct arch_uprobe *, struct pt_regs *); 521 void (*abort)(struct arch_uprobe *, struct pt_regs *); 522 }; 523 524 static inline int sizeof_long(void) 525 { 526 return in_ia32_syscall() ? 4 : 8; 527 } 528 529 static int default_pre_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs) 530 { 531 riprel_pre_xol(auprobe, regs); 532 return 0; 533 } 534 535 static int emulate_push_stack(struct pt_regs *regs, unsigned long val) 536 { 537 unsigned long new_sp = regs->sp - sizeof_long(); 538 539 if (copy_to_user((void __user *)new_sp, &val, sizeof_long())) 540 return -EFAULT; 541 542 regs->sp = new_sp; 543 return 0; 544 } 545 546 /* 547 * We have to fix things up as follows: 548 * 549 * Typically, the new ip is relative to the copied instruction. We need 550 * to make it relative to the original instruction (FIX_IP). Exceptions 551 * are return instructions and absolute or indirect jump or call instructions. 552 * 553 * If the single-stepped instruction was a call, the return address that 554 * is atop the stack is the address following the copied instruction. We 555 * need to make it the address following the original instruction (FIX_CALL). 556 * 557 * If the original instruction was a rip-relative instruction such as 558 * "movl %edx,0xnnnn(%rip)", we have instead executed an equivalent 559 * instruction using a scratch register -- e.g., "movl %edx,0xnnnn(%rsi)". 560 * We need to restore the contents of the scratch register 561 * (FIX_RIP_reg). 562 */ 563 static int default_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs) 564 { 565 struct uprobe_task *utask = current->utask; 566 567 riprel_post_xol(auprobe, regs); 568 if (auprobe->defparam.fixups & UPROBE_FIX_IP) { 569 long correction = utask->vaddr - utask->xol_vaddr; 570 regs->ip += correction; 571 } else if (auprobe->defparam.fixups & UPROBE_FIX_CALL) { 572 regs->sp += sizeof_long(); /* Pop incorrect return address */ 573 if (emulate_push_stack(regs, utask->vaddr + auprobe->defparam.ilen)) 574 return -ERESTART; 575 } 576 /* popf; tell the caller to not touch TF */ 577 if (auprobe->defparam.fixups & UPROBE_FIX_SETF) 578 utask->autask.saved_tf = true; 579 580 return 0; 581 } 582 583 static void default_abort_op(struct arch_uprobe *auprobe, struct pt_regs *regs) 584 { 585 riprel_post_xol(auprobe, regs); 586 } 587 588 static const struct uprobe_xol_ops default_xol_ops = { 589 .pre_xol = default_pre_xol_op, 590 .post_xol = default_post_xol_op, 591 .abort = default_abort_op, 592 }; 593 594 static bool branch_is_call(struct arch_uprobe *auprobe) 595 { 596 return auprobe->branch.opc1 == 0xe8; 597 } 598 599 #define CASE_COND \ 600 COND(70, 71, XF(OF)) \ 601 COND(72, 73, XF(CF)) \ 602 COND(74, 75, XF(ZF)) \ 603 COND(78, 79, XF(SF)) \ 604 COND(7a, 7b, XF(PF)) \ 605 COND(76, 77, XF(CF) || XF(ZF)) \ 606 COND(7c, 7d, XF(SF) != XF(OF)) \ 607 COND(7e, 7f, XF(ZF) || XF(SF) != XF(OF)) 608 609 #define COND(op_y, op_n, expr) \ 610 case 0x ## op_y: DO((expr) != 0) \ 611 case 0x ## op_n: DO((expr) == 0) 612 613 #define XF(xf) (!!(flags & X86_EFLAGS_ ## xf)) 614 615 static bool is_cond_jmp_opcode(u8 opcode) 616 { 617 switch (opcode) { 618 #define DO(expr) \ 619 return true; 620 CASE_COND 621 #undef DO 622 623 default: 624 return false; 625 } 626 } 627 628 static bool check_jmp_cond(struct arch_uprobe *auprobe, struct pt_regs *regs) 629 { 630 unsigned long flags = regs->flags; 631 632 switch (auprobe->branch.opc1) { 633 #define DO(expr) \ 634 return expr; 635 CASE_COND 636 #undef DO 637 638 default: /* not a conditional jmp */ 639 return true; 640 } 641 } 642 643 #undef XF 644 #undef COND 645 #undef CASE_COND 646 647 static bool branch_emulate_op(struct arch_uprobe *auprobe, struct pt_regs *regs) 648 { 649 unsigned long new_ip = regs->ip += auprobe->branch.ilen; 650 unsigned long offs = (long)auprobe->branch.offs; 651 652 if (branch_is_call(auprobe)) { 653 /* 654 * If it fails we execute this (mangled, see the comment in 655 * branch_clear_offset) insn out-of-line. In the likely case 656 * this should trigger the trap, and the probed application 657 * should die or restart the same insn after it handles the 658 * signal, arch_uprobe_post_xol() won't be even called. 659 * 660 * But there is corner case, see the comment in ->post_xol(). 661 */ 662 if (emulate_push_stack(regs, new_ip)) 663 return false; 664 } else if (!check_jmp_cond(auprobe, regs)) { 665 offs = 0; 666 } 667 668 regs->ip = new_ip + offs; 669 return true; 670 } 671 672 static bool push_emulate_op(struct arch_uprobe *auprobe, struct pt_regs *regs) 673 { 674 unsigned long *src_ptr = (void *)regs + auprobe->push.reg_offset; 675 676 if (emulate_push_stack(regs, *src_ptr)) 677 return false; 678 regs->ip += auprobe->push.ilen; 679 return true; 680 } 681 682 static int branch_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs) 683 { 684 BUG_ON(!branch_is_call(auprobe)); 685 /* 686 * We can only get here if branch_emulate_op() failed to push the ret 687 * address _and_ another thread expanded our stack before the (mangled) 688 * "call" insn was executed out-of-line. Just restore ->sp and restart. 689 * We could also restore ->ip and try to call branch_emulate_op() again. 690 */ 691 regs->sp += sizeof_long(); 692 return -ERESTART; 693 } 694 695 static void branch_clear_offset(struct arch_uprobe *auprobe, struct insn *insn) 696 { 697 /* 698 * Turn this insn into "call 1f; 1:", this is what we will execute 699 * out-of-line if ->emulate() fails. We only need this to generate 700 * a trap, so that the probed task receives the correct signal with 701 * the properly filled siginfo. 702 * 703 * But see the comment in ->post_xol(), in the unlikely case it can 704 * succeed. So we need to ensure that the new ->ip can not fall into 705 * the non-canonical area and trigger #GP. 706 * 707 * We could turn it into (say) "pushf", but then we would need to 708 * divorce ->insn[] and ->ixol[]. We need to preserve the 1st byte 709 * of ->insn[] for set_orig_insn(). 710 */ 711 memset(auprobe->insn + insn_offset_immediate(insn), 712 0, insn->immediate.nbytes); 713 } 714 715 static const struct uprobe_xol_ops branch_xol_ops = { 716 .emulate = branch_emulate_op, 717 .post_xol = branch_post_xol_op, 718 }; 719 720 static const struct uprobe_xol_ops push_xol_ops = { 721 .emulate = push_emulate_op, 722 }; 723 724 /* Returns -ENOSYS if branch_xol_ops doesn't handle this insn */ 725 static int branch_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn) 726 { 727 u8 opc1 = OPCODE1(insn); 728 int i; 729 730 switch (opc1) { 731 case 0xeb: /* jmp 8 */ 732 case 0xe9: /* jmp 32 */ 733 case 0x90: /* prefix* + nop; same as jmp with .offs = 0 */ 734 break; 735 736 case 0xe8: /* call relative */ 737 branch_clear_offset(auprobe, insn); 738 break; 739 740 case 0x0f: 741 if (insn->opcode.nbytes != 2) 742 return -ENOSYS; 743 /* 744 * If it is a "near" conditional jmp, OPCODE2() - 0x10 matches 745 * OPCODE1() of the "short" jmp which checks the same condition. 746 */ 747 opc1 = OPCODE2(insn) - 0x10; 748 /* fall through */ 749 default: 750 if (!is_cond_jmp_opcode(opc1)) 751 return -ENOSYS; 752 } 753 754 /* 755 * 16-bit overrides such as CALLW (66 e8 nn nn) are not supported. 756 * Intel and AMD behavior differ in 64-bit mode: Intel ignores 66 prefix. 757 * No one uses these insns, reject any branch insns with such prefix. 758 */ 759 for (i = 0; i < insn->prefixes.nbytes; i++) { 760 if (insn->prefixes.bytes[i] == 0x66) 761 return -ENOTSUPP; 762 } 763 764 auprobe->branch.opc1 = opc1; 765 auprobe->branch.ilen = insn->length; 766 auprobe->branch.offs = insn->immediate.value; 767 768 auprobe->ops = &branch_xol_ops; 769 return 0; 770 } 771 772 /* Returns -ENOSYS if push_xol_ops doesn't handle this insn */ 773 static int push_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn) 774 { 775 u8 opc1 = OPCODE1(insn), reg_offset = 0; 776 777 if (opc1 < 0x50 || opc1 > 0x57) 778 return -ENOSYS; 779 780 if (insn->length > 2) 781 return -ENOSYS; 782 if (insn->length == 2) { 783 /* only support rex_prefix 0x41 (x64 only) */ 784 #ifdef CONFIG_X86_64 785 if (insn->rex_prefix.nbytes != 1 || 786 insn->rex_prefix.bytes[0] != 0x41) 787 return -ENOSYS; 788 789 switch (opc1) { 790 case 0x50: 791 reg_offset = offsetof(struct pt_regs, r8); 792 break; 793 case 0x51: 794 reg_offset = offsetof(struct pt_regs, r9); 795 break; 796 case 0x52: 797 reg_offset = offsetof(struct pt_regs, r10); 798 break; 799 case 0x53: 800 reg_offset = offsetof(struct pt_regs, r11); 801 break; 802 case 0x54: 803 reg_offset = offsetof(struct pt_regs, r12); 804 break; 805 case 0x55: 806 reg_offset = offsetof(struct pt_regs, r13); 807 break; 808 case 0x56: 809 reg_offset = offsetof(struct pt_regs, r14); 810 break; 811 case 0x57: 812 reg_offset = offsetof(struct pt_regs, r15); 813 break; 814 } 815 #else 816 return -ENOSYS; 817 #endif 818 } else { 819 switch (opc1) { 820 case 0x50: 821 reg_offset = offsetof(struct pt_regs, ax); 822 break; 823 case 0x51: 824 reg_offset = offsetof(struct pt_regs, cx); 825 break; 826 case 0x52: 827 reg_offset = offsetof(struct pt_regs, dx); 828 break; 829 case 0x53: 830 reg_offset = offsetof(struct pt_regs, bx); 831 break; 832 case 0x54: 833 reg_offset = offsetof(struct pt_regs, sp); 834 break; 835 case 0x55: 836 reg_offset = offsetof(struct pt_regs, bp); 837 break; 838 case 0x56: 839 reg_offset = offsetof(struct pt_regs, si); 840 break; 841 case 0x57: 842 reg_offset = offsetof(struct pt_regs, di); 843 break; 844 } 845 } 846 847 auprobe->push.reg_offset = reg_offset; 848 auprobe->push.ilen = insn->length; 849 auprobe->ops = &push_xol_ops; 850 return 0; 851 } 852 853 /** 854 * arch_uprobe_analyze_insn - instruction analysis including validity and fixups. 855 * @mm: the probed address space. 856 * @arch_uprobe: the probepoint information. 857 * @addr: virtual address at which to install the probepoint 858 * Return 0 on success or a -ve number on error. 859 */ 860 int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, unsigned long addr) 861 { 862 struct insn insn; 863 u8 fix_ip_or_call = UPROBE_FIX_IP; 864 int ret; 865 866 ret = uprobe_init_insn(auprobe, &insn, is_64bit_mm(mm)); 867 if (ret) 868 return ret; 869 870 ret = branch_setup_xol_ops(auprobe, &insn); 871 if (ret != -ENOSYS) 872 return ret; 873 874 ret = push_setup_xol_ops(auprobe, &insn); 875 if (ret != -ENOSYS) 876 return ret; 877 878 /* 879 * Figure out which fixups default_post_xol_op() will need to perform, 880 * and annotate defparam->fixups accordingly. 881 */ 882 switch (OPCODE1(&insn)) { 883 case 0x9d: /* popf */ 884 auprobe->defparam.fixups |= UPROBE_FIX_SETF; 885 break; 886 case 0xc3: /* ret or lret -- ip is correct */ 887 case 0xcb: 888 case 0xc2: 889 case 0xca: 890 case 0xea: /* jmp absolute -- ip is correct */ 891 fix_ip_or_call = 0; 892 break; 893 case 0x9a: /* call absolute - Fix return addr, not ip */ 894 fix_ip_or_call = UPROBE_FIX_CALL; 895 break; 896 case 0xff: 897 switch (MODRM_REG(&insn)) { 898 case 2: case 3: /* call or lcall, indirect */ 899 fix_ip_or_call = UPROBE_FIX_CALL; 900 break; 901 case 4: case 5: /* jmp or ljmp, indirect */ 902 fix_ip_or_call = 0; 903 break; 904 } 905 /* fall through */ 906 default: 907 riprel_analyze(auprobe, &insn); 908 } 909 910 auprobe->defparam.ilen = insn.length; 911 auprobe->defparam.fixups |= fix_ip_or_call; 912 913 auprobe->ops = &default_xol_ops; 914 return 0; 915 } 916 917 /* 918 * arch_uprobe_pre_xol - prepare to execute out of line. 919 * @auprobe: the probepoint information. 920 * @regs: reflects the saved user state of current task. 921 */ 922 int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) 923 { 924 struct uprobe_task *utask = current->utask; 925 926 if (auprobe->ops->pre_xol) { 927 int err = auprobe->ops->pre_xol(auprobe, regs); 928 if (err) 929 return err; 930 } 931 932 regs->ip = utask->xol_vaddr; 933 utask->autask.saved_trap_nr = current->thread.trap_nr; 934 current->thread.trap_nr = UPROBE_TRAP_NR; 935 936 utask->autask.saved_tf = !!(regs->flags & X86_EFLAGS_TF); 937 regs->flags |= X86_EFLAGS_TF; 938 if (test_tsk_thread_flag(current, TIF_BLOCKSTEP)) 939 set_task_blockstep(current, false); 940 941 return 0; 942 } 943 944 /* 945 * If xol insn itself traps and generates a signal(Say, 946 * SIGILL/SIGSEGV/etc), then detect the case where a singlestepped 947 * instruction jumps back to its own address. It is assumed that anything 948 * like do_page_fault/do_trap/etc sets thread.trap_nr != -1. 949 * 950 * arch_uprobe_pre_xol/arch_uprobe_post_xol save/restore thread.trap_nr, 951 * arch_uprobe_xol_was_trapped() simply checks that ->trap_nr is not equal to 952 * UPROBE_TRAP_NR == -1 set by arch_uprobe_pre_xol(). 953 */ 954 bool arch_uprobe_xol_was_trapped(struct task_struct *t) 955 { 956 if (t->thread.trap_nr != UPROBE_TRAP_NR) 957 return true; 958 959 return false; 960 } 961 962 /* 963 * Called after single-stepping. To avoid the SMP problems that can 964 * occur when we temporarily put back the original opcode to 965 * single-step, we single-stepped a copy of the instruction. 966 * 967 * This function prepares to resume execution after the single-step. 968 */ 969 int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) 970 { 971 struct uprobe_task *utask = current->utask; 972 bool send_sigtrap = utask->autask.saved_tf; 973 int err = 0; 974 975 WARN_ON_ONCE(current->thread.trap_nr != UPROBE_TRAP_NR); 976 current->thread.trap_nr = utask->autask.saved_trap_nr; 977 978 if (auprobe->ops->post_xol) { 979 err = auprobe->ops->post_xol(auprobe, regs); 980 if (err) { 981 /* 982 * Restore ->ip for restart or post mortem analysis. 983 * ->post_xol() must not return -ERESTART unless this 984 * is really possible. 985 */ 986 regs->ip = utask->vaddr; 987 if (err == -ERESTART) 988 err = 0; 989 send_sigtrap = false; 990 } 991 } 992 /* 993 * arch_uprobe_pre_xol() doesn't save the state of TIF_BLOCKSTEP 994 * so we can get an extra SIGTRAP if we do not clear TF. We need 995 * to examine the opcode to make it right. 996 */ 997 if (send_sigtrap) 998 send_sig(SIGTRAP, current, 0); 999 1000 if (!utask->autask.saved_tf) 1001 regs->flags &= ~X86_EFLAGS_TF; 1002 1003 return err; 1004 } 1005 1006 /* callback routine for handling exceptions. */ 1007 int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, void *data) 1008 { 1009 struct die_args *args = data; 1010 struct pt_regs *regs = args->regs; 1011 int ret = NOTIFY_DONE; 1012 1013 /* We are only interested in userspace traps */ 1014 if (regs && !user_mode(regs)) 1015 return NOTIFY_DONE; 1016 1017 switch (val) { 1018 case DIE_INT3: 1019 if (uprobe_pre_sstep_notifier(regs)) 1020 ret = NOTIFY_STOP; 1021 1022 break; 1023 1024 case DIE_DEBUG: 1025 if (uprobe_post_sstep_notifier(regs)) 1026 ret = NOTIFY_STOP; 1027 1028 default: 1029 break; 1030 } 1031 1032 return ret; 1033 } 1034 1035 /* 1036 * This function gets called when XOL instruction either gets trapped or 1037 * the thread has a fatal signal. Reset the instruction pointer to its 1038 * probed address for the potential restart or for post mortem analysis. 1039 */ 1040 void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) 1041 { 1042 struct uprobe_task *utask = current->utask; 1043 1044 if (auprobe->ops->abort) 1045 auprobe->ops->abort(auprobe, regs); 1046 1047 current->thread.trap_nr = utask->autask.saved_trap_nr; 1048 regs->ip = utask->vaddr; 1049 /* clear TF if it was set by us in arch_uprobe_pre_xol() */ 1050 if (!utask->autask.saved_tf) 1051 regs->flags &= ~X86_EFLAGS_TF; 1052 } 1053 1054 static bool __skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs) 1055 { 1056 if (auprobe->ops->emulate) 1057 return auprobe->ops->emulate(auprobe, regs); 1058 return false; 1059 } 1060 1061 bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs) 1062 { 1063 bool ret = __skip_sstep(auprobe, regs); 1064 if (ret && (regs->flags & X86_EFLAGS_TF)) 1065 send_sig(SIGTRAP, current, 0); 1066 return ret; 1067 } 1068 1069 unsigned long 1070 arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr, struct pt_regs *regs) 1071 { 1072 int rasize = sizeof_long(), nleft; 1073 unsigned long orig_ret_vaddr = 0; /* clear high bits for 32-bit apps */ 1074 1075 if (copy_from_user(&orig_ret_vaddr, (void __user *)regs->sp, rasize)) 1076 return -1; 1077 1078 /* check whether address has been already hijacked */ 1079 if (orig_ret_vaddr == trampoline_vaddr) 1080 return orig_ret_vaddr; 1081 1082 nleft = copy_to_user((void __user *)regs->sp, &trampoline_vaddr, rasize); 1083 if (likely(!nleft)) 1084 return orig_ret_vaddr; 1085 1086 if (nleft != rasize) { 1087 pr_err("return address clobbered: pid=%d, %%sp=%#lx, %%ip=%#lx\n", 1088 current->pid, regs->sp, regs->ip); 1089 1090 force_sig(SIGSEGV, current); 1091 } 1092 1093 return -1; 1094 } 1095 1096 bool arch_uretprobe_is_alive(struct return_instance *ret, enum rp_check ctx, 1097 struct pt_regs *regs) 1098 { 1099 if (ctx == RP_CHECK_CALL) /* sp was just decremented by "call" insn */ 1100 return regs->sp < ret->stack; 1101 else 1102 return regs->sp <= ret->stack; 1103 } 1104