1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * User-space Probes (UProbes) for x86 4 * 5 * Copyright (C) IBM Corporation, 2008-2011 6 * Authors: 7 * Srikar Dronamraju 8 * Jim Keniston 9 */ 10 #include <linux/kernel.h> 11 #include <linux/sched.h> 12 #include <linux/ptrace.h> 13 #include <linux/uprobes.h> 14 #include <linux/uaccess.h> 15 #include <linux/syscalls.h> 16 17 #include <linux/kdebug.h> 18 #include <asm/processor.h> 19 #include <asm/insn.h> 20 #include <asm/mmu_context.h> 21 22 /* Post-execution fixups. */ 23 24 /* Adjust IP back to vicinity of actual insn */ 25 #define UPROBE_FIX_IP 0x01 26 27 /* Adjust the return address of a call insn */ 28 #define UPROBE_FIX_CALL 0x02 29 30 /* Instruction will modify TF, don't change it */ 31 #define UPROBE_FIX_SETF 0x04 32 33 #define UPROBE_FIX_RIP_SI 0x08 34 #define UPROBE_FIX_RIP_DI 0x10 35 #define UPROBE_FIX_RIP_BX 0x20 36 #define UPROBE_FIX_RIP_MASK \ 37 (UPROBE_FIX_RIP_SI | UPROBE_FIX_RIP_DI | UPROBE_FIX_RIP_BX) 38 39 #define UPROBE_TRAP_NR UINT_MAX 40 41 /* Adaptations for mhiramat x86 decoder v14. */ 42 #define OPCODE1(insn) ((insn)->opcode.bytes[0]) 43 #define OPCODE2(insn) ((insn)->opcode.bytes[1]) 44 #define OPCODE3(insn) ((insn)->opcode.bytes[2]) 45 #define MODRM_REG(insn) X86_MODRM_REG((insn)->modrm.value) 46 47 #define W(row, b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, ba, bb, bc, bd, be, bf)\ 48 (((b0##UL << 0x0)|(b1##UL << 0x1)|(b2##UL << 0x2)|(b3##UL << 0x3) | \ 49 (b4##UL << 0x4)|(b5##UL << 0x5)|(b6##UL << 0x6)|(b7##UL << 0x7) | \ 50 (b8##UL << 0x8)|(b9##UL << 0x9)|(ba##UL << 0xa)|(bb##UL << 0xb) | \ 51 (bc##UL << 0xc)|(bd##UL << 0xd)|(be##UL << 0xe)|(bf##UL << 0xf)) \ 52 << (row % 32)) 53 54 /* 55 * Good-instruction tables for 32-bit apps. This is non-const and volatile 56 * to keep gcc from statically optimizing it out, as variable_test_bit makes 57 * some versions of gcc to think only *(unsigned long*) is used. 58 * 59 * Opcodes we'll probably never support: 60 * 6c-6f - ins,outs. SEGVs if used in userspace 61 * e4-e7 - in,out imm. SEGVs if used in userspace 62 * ec-ef - in,out acc. SEGVs if used in userspace 63 * cc - int3. SIGTRAP if used in userspace 64 * ce - into. Not used in userspace - no kernel support to make it useful. SEGVs 65 * (why we support bound (62) then? it's similar, and similarly unused...) 66 * f1 - int1. SIGTRAP if used in userspace 67 * f4 - hlt. SEGVs if used in userspace 68 * fa - cli. SEGVs if used in userspace 69 * fb - sti. SEGVs if used in userspace 70 * 71 * Opcodes which need some work to be supported: 72 * 07,17,1f - pop es/ss/ds 73 * Normally not used in userspace, but would execute if used. 74 * Can cause GP or stack exception if tries to load wrong segment descriptor. 75 * We hesitate to run them under single step since kernel's handling 76 * of userspace single-stepping (TF flag) is fragile. 77 * We can easily refuse to support push es/cs/ss/ds (06/0e/16/1e) 78 * on the same grounds that they are never used. 79 * cd - int N. 80 * Used by userspace for "int 80" syscall entry. (Other "int N" 81 * cause GP -> SEGV since their IDT gates don't allow calls from CPL 3). 82 * Not supported since kernel's handling of userspace single-stepping 83 * (TF flag) is fragile. 84 * cf - iret. Normally not used in userspace. Doesn't SEGV unless arguments are bad 85 */ 86 #if defined(CONFIG_X86_32) || defined(CONFIG_IA32_EMULATION) 87 static volatile u32 good_insns_32[256 / 32] = { 88 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 89 /* ---------------------------------------------- */ 90 W(0x00, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1) | /* 00 */ 91 W(0x10, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 10 */ 92 W(0x20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */ 93 W(0x30, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 30 */ 94 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */ 95 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */ 96 W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */ 97 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */ 98 W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */ 99 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */ 100 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */ 101 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */ 102 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */ 103 W(0xd0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */ 104 W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* e0 */ 105 W(0xf0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */ 106 /* ---------------------------------------------- */ 107 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 108 }; 109 #else 110 #define good_insns_32 NULL 111 #endif 112 113 /* Good-instruction tables for 64-bit apps. 114 * 115 * Genuinely invalid opcodes: 116 * 06,07 - formerly push/pop es 117 * 0e - formerly push cs 118 * 16,17 - formerly push/pop ss 119 * 1e,1f - formerly push/pop ds 120 * 27,2f,37,3f - formerly daa/das/aaa/aas 121 * 60,61 - formerly pusha/popa 122 * 62 - formerly bound. EVEX prefix for AVX512 (not yet supported) 123 * 82 - formerly redundant encoding of Group1 124 * 9a - formerly call seg:ofs 125 * ce - formerly into 126 * d4,d5 - formerly aam/aad 127 * d6 - formerly undocumented salc 128 * ea - formerly jmp seg:ofs 129 * 130 * Opcodes we'll probably never support: 131 * 6c-6f - ins,outs. SEGVs if used in userspace 132 * e4-e7 - in,out imm. SEGVs if used in userspace 133 * ec-ef - in,out acc. SEGVs if used in userspace 134 * cc - int3. SIGTRAP if used in userspace 135 * f1 - int1. SIGTRAP if used in userspace 136 * f4 - hlt. SEGVs if used in userspace 137 * fa - cli. SEGVs if used in userspace 138 * fb - sti. SEGVs if used in userspace 139 * 140 * Opcodes which need some work to be supported: 141 * cd - int N. 142 * Used by userspace for "int 80" syscall entry. (Other "int N" 143 * cause GP -> SEGV since their IDT gates don't allow calls from CPL 3). 144 * Not supported since kernel's handling of userspace single-stepping 145 * (TF flag) is fragile. 146 * cf - iret. Normally not used in userspace. Doesn't SEGV unless arguments are bad 147 */ 148 #if defined(CONFIG_X86_64) 149 static volatile u32 good_insns_64[256 / 32] = { 150 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 151 /* ---------------------------------------------- */ 152 W(0x00, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1) | /* 00 */ 153 W(0x10, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) , /* 10 */ 154 W(0x20, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) | /* 20 */ 155 W(0x30, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 30 */ 156 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */ 157 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */ 158 W(0x60, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */ 159 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */ 160 W(0x80, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */ 161 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1) , /* 90 */ 162 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */ 163 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */ 164 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */ 165 W(0xd0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */ 166 W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0) | /* e0 */ 167 W(0xf0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */ 168 /* ---------------------------------------------- */ 169 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 170 }; 171 #else 172 #define good_insns_64 NULL 173 #endif 174 175 /* Using this for both 64-bit and 32-bit apps. 176 * Opcodes we don't support: 177 * 0f 00 - SLDT/STR/LLDT/LTR/VERR/VERW/-/- group. System insns 178 * 0f 01 - SGDT/SIDT/LGDT/LIDT/SMSW/-/LMSW/INVLPG group. 179 * Also encodes tons of other system insns if mod=11. 180 * Some are in fact non-system: xend, xtest, rdtscp, maybe more 181 * 0f 05 - syscall 182 * 0f 06 - clts (CPL0 insn) 183 * 0f 07 - sysret 184 * 0f 08 - invd (CPL0 insn) 185 * 0f 09 - wbinvd (CPL0 insn) 186 * 0f 0b - ud2 187 * 0f 30 - wrmsr (CPL0 insn) (then why rdmsr is allowed, it's also CPL0 insn?) 188 * 0f 34 - sysenter 189 * 0f 35 - sysexit 190 * 0f 37 - getsec 191 * 0f 78 - vmread (Intel VMX. CPL0 insn) 192 * 0f 79 - vmwrite (Intel VMX. CPL0 insn) 193 * Note: with prefixes, these two opcodes are 194 * extrq/insertq/AVX512 convert vector ops. 195 * 0f ae - group15: [f]xsave,[f]xrstor,[v]{ld,st}mxcsr,clflush[opt], 196 * {rd,wr}{fs,gs}base,{s,l,m}fence. 197 * Why? They are all user-executable. 198 */ 199 static volatile u32 good_2byte_insns[256 / 32] = { 200 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 201 /* ---------------------------------------------- */ 202 W(0x00, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1) | /* 00 */ 203 W(0x10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 10 */ 204 W(0x20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */ 205 W(0x30, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1) , /* 30 */ 206 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */ 207 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */ 208 W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 60 */ 209 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1) , /* 70 */ 210 W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */ 211 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */ 212 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1) | /* a0 */ 213 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */ 214 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* c0 */ 215 W(0xd0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */ 216 W(0xe0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* e0 */ 217 W(0xf0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) /* f0 */ 218 /* ---------------------------------------------- */ 219 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 220 }; 221 #undef W 222 223 /* 224 * opcodes we may need to refine support for: 225 * 226 * 0f - 2-byte instructions: For many of these instructions, the validity 227 * depends on the prefix and/or the reg field. On such instructions, we 228 * just consider the opcode combination valid if it corresponds to any 229 * valid instruction. 230 * 231 * 8f - Group 1 - only reg = 0 is OK 232 * c6-c7 - Group 11 - only reg = 0 is OK 233 * d9-df - fpu insns with some illegal encodings 234 * f2, f3 - repnz, repz prefixes. These are also the first byte for 235 * certain floating-point instructions, such as addsd. 236 * 237 * fe - Group 4 - only reg = 0 or 1 is OK 238 * ff - Group 5 - only reg = 0-6 is OK 239 * 240 * others -- Do we need to support these? 241 * 242 * 0f - (floating-point?) prefetch instructions 243 * 07, 17, 1f - pop es, pop ss, pop ds 244 * 26, 2e, 36, 3e - es:, cs:, ss:, ds: segment prefixes -- 245 * but 64 and 65 (fs: and gs:) seem to be used, so we support them 246 * 67 - addr16 prefix 247 * ce - into 248 * f0 - lock prefix 249 */ 250 251 /* 252 * TODO: 253 * - Where necessary, examine the modrm byte and allow only valid instructions 254 * in the different Groups and fpu instructions. 255 */ 256 257 static bool is_prefix_bad(struct insn *insn) 258 { 259 insn_byte_t p; 260 int i; 261 262 for_each_insn_prefix(insn, i, p) { 263 insn_attr_t attr; 264 265 attr = inat_get_opcode_attribute(p); 266 switch (attr) { 267 case INAT_MAKE_PREFIX(INAT_PFX_ES): 268 case INAT_MAKE_PREFIX(INAT_PFX_CS): 269 case INAT_MAKE_PREFIX(INAT_PFX_DS): 270 case INAT_MAKE_PREFIX(INAT_PFX_SS): 271 case INAT_MAKE_PREFIX(INAT_PFX_LOCK): 272 return true; 273 } 274 } 275 return false; 276 } 277 278 static int uprobe_init_insn(struct arch_uprobe *auprobe, struct insn *insn, bool x86_64) 279 { 280 enum insn_mode m = x86_64 ? INSN_MODE_64 : INSN_MODE_32; 281 u32 volatile *good_insns; 282 int ret; 283 284 ret = insn_decode(insn, auprobe->insn, sizeof(auprobe->insn), m); 285 if (ret < 0) 286 return -ENOEXEC; 287 288 if (is_prefix_bad(insn)) 289 return -ENOTSUPP; 290 291 /* We should not singlestep on the exception masking instructions */ 292 if (insn_masking_exception(insn)) 293 return -ENOTSUPP; 294 295 if (x86_64) 296 good_insns = good_insns_64; 297 else 298 good_insns = good_insns_32; 299 300 if (test_bit(OPCODE1(insn), (unsigned long *)good_insns)) 301 return 0; 302 303 if (insn->opcode.nbytes == 2) { 304 if (test_bit(OPCODE2(insn), (unsigned long *)good_2byte_insns)) 305 return 0; 306 } 307 308 return -ENOTSUPP; 309 } 310 311 #ifdef CONFIG_X86_64 312 313 asm ( 314 ".pushsection .rodata\n" 315 ".global uretprobe_trampoline_entry\n" 316 "uretprobe_trampoline_entry:\n" 317 "pushq %rax\n" 318 "pushq %rcx\n" 319 "pushq %r11\n" 320 "movq $" __stringify(__NR_uretprobe) ", %rax\n" 321 "syscall\n" 322 ".global uretprobe_syscall_check\n" 323 "uretprobe_syscall_check:\n" 324 "popq %r11\n" 325 "popq %rcx\n" 326 327 /* The uretprobe syscall replaces stored %rax value with final 328 * return address, so we don't restore %rax in here and just 329 * call ret. 330 */ 331 "retq\n" 332 ".global uretprobe_trampoline_end\n" 333 "uretprobe_trampoline_end:\n" 334 ".popsection\n" 335 ); 336 337 extern u8 uretprobe_trampoline_entry[]; 338 extern u8 uretprobe_trampoline_end[]; 339 extern u8 uretprobe_syscall_check[]; 340 341 void *arch_uprobe_trampoline(unsigned long *psize) 342 { 343 static uprobe_opcode_t insn = UPROBE_SWBP_INSN; 344 struct pt_regs *regs = task_pt_regs(current); 345 346 /* 347 * At the moment the uretprobe syscall trampoline is supported 348 * only for native 64-bit process, the compat process still uses 349 * standard breakpoint. 350 */ 351 if (user_64bit_mode(regs)) { 352 *psize = uretprobe_trampoline_end - uretprobe_trampoline_entry; 353 return uretprobe_trampoline_entry; 354 } 355 356 *psize = UPROBE_SWBP_INSN_SIZE; 357 return &insn; 358 } 359 360 static unsigned long trampoline_check_ip(unsigned long tramp) 361 { 362 return tramp + (uretprobe_syscall_check - uretprobe_trampoline_entry); 363 } 364 365 SYSCALL_DEFINE0(uretprobe) 366 { 367 struct pt_regs *regs = task_pt_regs(current); 368 unsigned long err, ip, sp, r11_cx_ax[3], tramp; 369 370 /* If there's no trampoline, we are called from wrong place. */ 371 tramp = uprobe_get_trampoline_vaddr(); 372 if (unlikely(tramp == UPROBE_NO_TRAMPOLINE_VADDR)) 373 goto sigill; 374 375 /* Make sure the ip matches the only allowed sys_uretprobe caller. */ 376 if (unlikely(regs->ip != trampoline_check_ip(tramp))) 377 goto sigill; 378 379 err = copy_from_user(r11_cx_ax, (void __user *)regs->sp, sizeof(r11_cx_ax)); 380 if (err) 381 goto sigill; 382 383 /* expose the "right" values of r11/cx/ax/sp to uprobe_consumer/s */ 384 regs->r11 = r11_cx_ax[0]; 385 regs->cx = r11_cx_ax[1]; 386 regs->ax = r11_cx_ax[2]; 387 regs->sp += sizeof(r11_cx_ax); 388 regs->orig_ax = -1; 389 390 ip = regs->ip; 391 sp = regs->sp; 392 393 uprobe_handle_trampoline(regs); 394 395 /* 396 * Some of the uprobe consumers has changed sp, we can do nothing, 397 * just return via iret. 398 * .. or shadow stack is enabled, in which case we need to skip 399 * return through the user space stack address. 400 */ 401 if (regs->sp != sp || shstk_is_enabled()) 402 return regs->ax; 403 regs->sp -= sizeof(r11_cx_ax); 404 405 /* for the case uprobe_consumer has changed r11/cx */ 406 r11_cx_ax[0] = regs->r11; 407 r11_cx_ax[1] = regs->cx; 408 409 /* 410 * ax register is passed through as return value, so we can use 411 * its space on stack for ip value and jump to it through the 412 * trampoline's ret instruction 413 */ 414 r11_cx_ax[2] = regs->ip; 415 regs->ip = ip; 416 417 err = copy_to_user((void __user *)regs->sp, r11_cx_ax, sizeof(r11_cx_ax)); 418 if (err) 419 goto sigill; 420 421 /* ensure sysret, see do_syscall_64() */ 422 regs->r11 = regs->flags; 423 regs->cx = regs->ip; 424 425 return regs->ax; 426 427 sigill: 428 force_sig(SIGILL); 429 return -1; 430 } 431 432 /* 433 * If arch_uprobe->insn doesn't use rip-relative addressing, return 434 * immediately. Otherwise, rewrite the instruction so that it accesses 435 * its memory operand indirectly through a scratch register. Set 436 * defparam->fixups accordingly. (The contents of the scratch register 437 * will be saved before we single-step the modified instruction, 438 * and restored afterward). 439 * 440 * We do this because a rip-relative instruction can access only a 441 * relatively small area (+/- 2 GB from the instruction), and the XOL 442 * area typically lies beyond that area. At least for instructions 443 * that store to memory, we can't execute the original instruction 444 * and "fix things up" later, because the misdirected store could be 445 * disastrous. 446 * 447 * Some useful facts about rip-relative instructions: 448 * 449 * - There's always a modrm byte with bit layout "00 reg 101". 450 * - There's never a SIB byte. 451 * - The displacement is always 4 bytes. 452 * - REX.B=1 bit in REX prefix, which normally extends r/m field, 453 * has no effect on rip-relative mode. It doesn't make modrm byte 454 * with r/m=101 refer to register 1101 = R13. 455 */ 456 static void riprel_analyze(struct arch_uprobe *auprobe, struct insn *insn) 457 { 458 u8 *cursor; 459 u8 reg; 460 u8 reg2; 461 462 if (!insn_rip_relative(insn)) 463 return; 464 465 /* 466 * insn_rip_relative() would have decoded rex_prefix, vex_prefix, modrm. 467 * Clear REX.b bit (extension of MODRM.rm field): 468 * we want to encode low numbered reg, not r8+. 469 */ 470 if (insn->rex_prefix.nbytes) { 471 cursor = auprobe->insn + insn_offset_rex_prefix(insn); 472 /* REX byte has 0100wrxb layout, clearing REX.b bit */ 473 *cursor &= 0xfe; 474 } 475 /* 476 * Similar treatment for VEX3/EVEX prefix. 477 * TODO: add XOP treatment when insn decoder supports them 478 */ 479 if (insn->vex_prefix.nbytes >= 3) { 480 /* 481 * vex2: c5 rvvvvLpp (has no b bit) 482 * vex3/xop: c4/8f rxbmmmmm wvvvvLpp 483 * evex: 62 rxbR00mm wvvvv1pp zllBVaaa 484 * Setting VEX3.b (setting because it has inverted meaning). 485 * Setting EVEX.x since (in non-SIB encoding) EVEX.x 486 * is the 4th bit of MODRM.rm, and needs the same treatment. 487 * For VEX3-encoded insns, VEX3.x value has no effect in 488 * non-SIB encoding, the change is superfluous but harmless. 489 */ 490 cursor = auprobe->insn + insn_offset_vex_prefix(insn) + 1; 491 *cursor |= 0x60; 492 } 493 494 /* 495 * Convert from rip-relative addressing to register-relative addressing 496 * via a scratch register. 497 * 498 * This is tricky since there are insns with modrm byte 499 * which also use registers not encoded in modrm byte: 500 * [i]div/[i]mul: implicitly use dx:ax 501 * shift ops: implicitly use cx 502 * cmpxchg: implicitly uses ax 503 * cmpxchg8/16b: implicitly uses dx:ax and bx:cx 504 * Encoding: 0f c7/1 modrm 505 * The code below thinks that reg=1 (cx), chooses si as scratch. 506 * mulx: implicitly uses dx: mulx r/m,r1,r2 does r1:r2 = dx * r/m. 507 * First appeared in Haswell (BMI2 insn). It is vex-encoded. 508 * Example where none of bx,cx,dx can be used as scratch reg: 509 * c4 e2 63 f6 0d disp32 mulx disp32(%rip),%ebx,%ecx 510 * [v]pcmpistri: implicitly uses cx, xmm0 511 * [v]pcmpistrm: implicitly uses xmm0 512 * [v]pcmpestri: implicitly uses ax, dx, cx, xmm0 513 * [v]pcmpestrm: implicitly uses ax, dx, xmm0 514 * Evil SSE4.2 string comparison ops from hell. 515 * maskmovq/[v]maskmovdqu: implicitly uses (ds:rdi) as destination. 516 * Encoding: 0f f7 modrm, 66 0f f7 modrm, vex-encoded: c5 f9 f7 modrm. 517 * Store op1, byte-masked by op2 msb's in each byte, to (ds:rdi). 518 * AMD says it has no 3-operand form (vex.vvvv must be 1111) 519 * and that it can have only register operands, not mem 520 * (its modrm byte must have mode=11). 521 * If these restrictions will ever be lifted, 522 * we'll need code to prevent selection of di as scratch reg! 523 * 524 * Summary: I don't know any insns with modrm byte which 525 * use SI register implicitly. DI register is used only 526 * by one insn (maskmovq) and BX register is used 527 * only by one too (cmpxchg8b). 528 * BP is stack-segment based (may be a problem?). 529 * AX, DX, CX are off-limits (many implicit users). 530 * SP is unusable (it's stack pointer - think about "pop mem"; 531 * also, rsp+disp32 needs sib encoding -> insn length change). 532 */ 533 534 reg = MODRM_REG(insn); /* Fetch modrm.reg */ 535 reg2 = 0xff; /* Fetch vex.vvvv */ 536 if (insn->vex_prefix.nbytes) 537 reg2 = insn->vex_prefix.bytes[2]; 538 /* 539 * TODO: add XOP vvvv reading. 540 * 541 * vex.vvvv field is in bits 6-3, bits are inverted. 542 * But in 32-bit mode, high-order bit may be ignored. 543 * Therefore, let's consider only 3 low-order bits. 544 */ 545 reg2 = ((reg2 >> 3) & 0x7) ^ 0x7; 546 /* 547 * Register numbering is ax,cx,dx,bx, sp,bp,si,di, r8..r15. 548 * 549 * Choose scratch reg. Order is important: must not select bx 550 * if we can use si (cmpxchg8b case!) 551 */ 552 if (reg != 6 && reg2 != 6) { 553 reg2 = 6; 554 auprobe->defparam.fixups |= UPROBE_FIX_RIP_SI; 555 } else if (reg != 7 && reg2 != 7) { 556 reg2 = 7; 557 auprobe->defparam.fixups |= UPROBE_FIX_RIP_DI; 558 /* TODO (paranoia): force maskmovq to not use di */ 559 } else { 560 reg2 = 3; 561 auprobe->defparam.fixups |= UPROBE_FIX_RIP_BX; 562 } 563 /* 564 * Point cursor at the modrm byte. The next 4 bytes are the 565 * displacement. Beyond the displacement, for some instructions, 566 * is the immediate operand. 567 */ 568 cursor = auprobe->insn + insn_offset_modrm(insn); 569 /* 570 * Change modrm from "00 reg 101" to "10 reg reg2". Example: 571 * 89 05 disp32 mov %eax,disp32(%rip) becomes 572 * 89 86 disp32 mov %eax,disp32(%rsi) 573 */ 574 *cursor = 0x80 | (reg << 3) | reg2; 575 } 576 577 static inline unsigned long * 578 scratch_reg(struct arch_uprobe *auprobe, struct pt_regs *regs) 579 { 580 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_SI) 581 return ®s->si; 582 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_DI) 583 return ®s->di; 584 return ®s->bx; 585 } 586 587 /* 588 * If we're emulating a rip-relative instruction, save the contents 589 * of the scratch register and store the target address in that register. 590 */ 591 static void riprel_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) 592 { 593 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_MASK) { 594 struct uprobe_task *utask = current->utask; 595 unsigned long *sr = scratch_reg(auprobe, regs); 596 597 utask->autask.saved_scratch_register = *sr; 598 *sr = utask->vaddr + auprobe->defparam.ilen; 599 } 600 } 601 602 static void riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) 603 { 604 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_MASK) { 605 struct uprobe_task *utask = current->utask; 606 unsigned long *sr = scratch_reg(auprobe, regs); 607 608 *sr = utask->autask.saved_scratch_register; 609 } 610 } 611 #else /* 32-bit: */ 612 /* 613 * No RIP-relative addressing on 32-bit 614 */ 615 static void riprel_analyze(struct arch_uprobe *auprobe, struct insn *insn) 616 { 617 } 618 static void riprel_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) 619 { 620 } 621 static void riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) 622 { 623 } 624 #endif /* CONFIG_X86_64 */ 625 626 struct uprobe_xol_ops { 627 bool (*emulate)(struct arch_uprobe *, struct pt_regs *); 628 int (*pre_xol)(struct arch_uprobe *, struct pt_regs *); 629 int (*post_xol)(struct arch_uprobe *, struct pt_regs *); 630 void (*abort)(struct arch_uprobe *, struct pt_regs *); 631 }; 632 633 static inline int sizeof_long(struct pt_regs *regs) 634 { 635 /* 636 * Check registers for mode as in_xxx_syscall() does not apply here. 637 */ 638 return user_64bit_mode(regs) ? 8 : 4; 639 } 640 641 static int default_pre_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs) 642 { 643 riprel_pre_xol(auprobe, regs); 644 return 0; 645 } 646 647 static int emulate_push_stack(struct pt_regs *regs, unsigned long val) 648 { 649 unsigned long new_sp = regs->sp - sizeof_long(regs); 650 651 if (copy_to_user((void __user *)new_sp, &val, sizeof_long(regs))) 652 return -EFAULT; 653 654 regs->sp = new_sp; 655 return 0; 656 } 657 658 /* 659 * We have to fix things up as follows: 660 * 661 * Typically, the new ip is relative to the copied instruction. We need 662 * to make it relative to the original instruction (FIX_IP). Exceptions 663 * are return instructions and absolute or indirect jump or call instructions. 664 * 665 * If the single-stepped instruction was a call, the return address that 666 * is atop the stack is the address following the copied instruction. We 667 * need to make it the address following the original instruction (FIX_CALL). 668 * 669 * If the original instruction was a rip-relative instruction such as 670 * "movl %edx,0xnnnn(%rip)", we have instead executed an equivalent 671 * instruction using a scratch register -- e.g., "movl %edx,0xnnnn(%rsi)". 672 * We need to restore the contents of the scratch register 673 * (FIX_RIP_reg). 674 */ 675 static int default_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs) 676 { 677 struct uprobe_task *utask = current->utask; 678 679 riprel_post_xol(auprobe, regs); 680 if (auprobe->defparam.fixups & UPROBE_FIX_IP) { 681 long correction = utask->vaddr - utask->xol_vaddr; 682 regs->ip += correction; 683 } else if (auprobe->defparam.fixups & UPROBE_FIX_CALL) { 684 regs->sp += sizeof_long(regs); /* Pop incorrect return address */ 685 if (emulate_push_stack(regs, utask->vaddr + auprobe->defparam.ilen)) 686 return -ERESTART; 687 } 688 /* popf; tell the caller to not touch TF */ 689 if (auprobe->defparam.fixups & UPROBE_FIX_SETF) 690 utask->autask.saved_tf = true; 691 692 return 0; 693 } 694 695 static void default_abort_op(struct arch_uprobe *auprobe, struct pt_regs *regs) 696 { 697 riprel_post_xol(auprobe, regs); 698 } 699 700 static const struct uprobe_xol_ops default_xol_ops = { 701 .pre_xol = default_pre_xol_op, 702 .post_xol = default_post_xol_op, 703 .abort = default_abort_op, 704 }; 705 706 static bool branch_is_call(struct arch_uprobe *auprobe) 707 { 708 return auprobe->branch.opc1 == 0xe8; 709 } 710 711 #define CASE_COND \ 712 COND(70, 71, XF(OF)) \ 713 COND(72, 73, XF(CF)) \ 714 COND(74, 75, XF(ZF)) \ 715 COND(78, 79, XF(SF)) \ 716 COND(7a, 7b, XF(PF)) \ 717 COND(76, 77, XF(CF) || XF(ZF)) \ 718 COND(7c, 7d, XF(SF) != XF(OF)) \ 719 COND(7e, 7f, XF(ZF) || XF(SF) != XF(OF)) 720 721 #define COND(op_y, op_n, expr) \ 722 case 0x ## op_y: DO((expr) != 0) \ 723 case 0x ## op_n: DO((expr) == 0) 724 725 #define XF(xf) (!!(flags & X86_EFLAGS_ ## xf)) 726 727 static bool is_cond_jmp_opcode(u8 opcode) 728 { 729 switch (opcode) { 730 #define DO(expr) \ 731 return true; 732 CASE_COND 733 #undef DO 734 735 default: 736 return false; 737 } 738 } 739 740 static bool check_jmp_cond(struct arch_uprobe *auprobe, struct pt_regs *regs) 741 { 742 unsigned long flags = regs->flags; 743 744 switch (auprobe->branch.opc1) { 745 #define DO(expr) \ 746 return expr; 747 CASE_COND 748 #undef DO 749 750 default: /* not a conditional jmp */ 751 return true; 752 } 753 } 754 755 #undef XF 756 #undef COND 757 #undef CASE_COND 758 759 static bool branch_emulate_op(struct arch_uprobe *auprobe, struct pt_regs *regs) 760 { 761 unsigned long new_ip = regs->ip += auprobe->branch.ilen; 762 unsigned long offs = (long)auprobe->branch.offs; 763 764 if (branch_is_call(auprobe)) { 765 /* 766 * If it fails we execute this (mangled, see the comment in 767 * branch_clear_offset) insn out-of-line. In the likely case 768 * this should trigger the trap, and the probed application 769 * should die or restart the same insn after it handles the 770 * signal, arch_uprobe_post_xol() won't be even called. 771 * 772 * But there is corner case, see the comment in ->post_xol(). 773 */ 774 if (emulate_push_stack(regs, new_ip)) 775 return false; 776 } else if (!check_jmp_cond(auprobe, regs)) { 777 offs = 0; 778 } 779 780 regs->ip = new_ip + offs; 781 return true; 782 } 783 784 static bool push_emulate_op(struct arch_uprobe *auprobe, struct pt_regs *regs) 785 { 786 unsigned long *src_ptr = (void *)regs + auprobe->push.reg_offset; 787 788 if (emulate_push_stack(regs, *src_ptr)) 789 return false; 790 regs->ip += auprobe->push.ilen; 791 return true; 792 } 793 794 static int branch_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs) 795 { 796 BUG_ON(!branch_is_call(auprobe)); 797 /* 798 * We can only get here if branch_emulate_op() failed to push the ret 799 * address _and_ another thread expanded our stack before the (mangled) 800 * "call" insn was executed out-of-line. Just restore ->sp and restart. 801 * We could also restore ->ip and try to call branch_emulate_op() again. 802 */ 803 regs->sp += sizeof_long(regs); 804 return -ERESTART; 805 } 806 807 static void branch_clear_offset(struct arch_uprobe *auprobe, struct insn *insn) 808 { 809 /* 810 * Turn this insn into "call 1f; 1:", this is what we will execute 811 * out-of-line if ->emulate() fails. We only need this to generate 812 * a trap, so that the probed task receives the correct signal with 813 * the properly filled siginfo. 814 * 815 * But see the comment in ->post_xol(), in the unlikely case it can 816 * succeed. So we need to ensure that the new ->ip can not fall into 817 * the non-canonical area and trigger #GP. 818 * 819 * We could turn it into (say) "pushf", but then we would need to 820 * divorce ->insn[] and ->ixol[]. We need to preserve the 1st byte 821 * of ->insn[] for set_orig_insn(). 822 */ 823 memset(auprobe->insn + insn_offset_immediate(insn), 824 0, insn->immediate.nbytes); 825 } 826 827 static const struct uprobe_xol_ops branch_xol_ops = { 828 .emulate = branch_emulate_op, 829 .post_xol = branch_post_xol_op, 830 }; 831 832 static const struct uprobe_xol_ops push_xol_ops = { 833 .emulate = push_emulate_op, 834 }; 835 836 /* Returns -ENOSYS if branch_xol_ops doesn't handle this insn */ 837 static int branch_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn) 838 { 839 u8 opc1 = OPCODE1(insn); 840 insn_byte_t p; 841 int i; 842 843 /* x86_nops[insn->length]; same as jmp with .offs = 0 */ 844 if (insn->length <= ASM_NOP_MAX && 845 !memcmp(insn->kaddr, x86_nops[insn->length], insn->length)) 846 goto setup; 847 848 switch (opc1) { 849 case 0xeb: /* jmp 8 */ 850 case 0xe9: /* jmp 32 */ 851 break; 852 case 0x90: /* prefix* + nop; same as jmp with .offs = 0 */ 853 goto setup; 854 855 case 0xe8: /* call relative */ 856 branch_clear_offset(auprobe, insn); 857 break; 858 859 case 0x0f: 860 if (insn->opcode.nbytes != 2) 861 return -ENOSYS; 862 /* 863 * If it is a "near" conditional jmp, OPCODE2() - 0x10 matches 864 * OPCODE1() of the "short" jmp which checks the same condition. 865 */ 866 opc1 = OPCODE2(insn) - 0x10; 867 fallthrough; 868 default: 869 if (!is_cond_jmp_opcode(opc1)) 870 return -ENOSYS; 871 } 872 873 /* 874 * 16-bit overrides such as CALLW (66 e8 nn nn) are not supported. 875 * Intel and AMD behavior differ in 64-bit mode: Intel ignores 66 prefix. 876 * No one uses these insns, reject any branch insns with such prefix. 877 */ 878 for_each_insn_prefix(insn, i, p) { 879 if (p == 0x66) 880 return -ENOTSUPP; 881 } 882 883 setup: 884 auprobe->branch.opc1 = opc1; 885 auprobe->branch.ilen = insn->length; 886 auprobe->branch.offs = insn->immediate.value; 887 888 auprobe->ops = &branch_xol_ops; 889 return 0; 890 } 891 892 /* Returns -ENOSYS if push_xol_ops doesn't handle this insn */ 893 static int push_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn) 894 { 895 u8 opc1 = OPCODE1(insn), reg_offset = 0; 896 897 if (opc1 < 0x50 || opc1 > 0x57) 898 return -ENOSYS; 899 900 if (insn->length > 2) 901 return -ENOSYS; 902 if (insn->length == 2) { 903 /* only support rex_prefix 0x41 (x64 only) */ 904 #ifdef CONFIG_X86_64 905 if (insn->rex_prefix.nbytes != 1 || 906 insn->rex_prefix.bytes[0] != 0x41) 907 return -ENOSYS; 908 909 switch (opc1) { 910 case 0x50: 911 reg_offset = offsetof(struct pt_regs, r8); 912 break; 913 case 0x51: 914 reg_offset = offsetof(struct pt_regs, r9); 915 break; 916 case 0x52: 917 reg_offset = offsetof(struct pt_regs, r10); 918 break; 919 case 0x53: 920 reg_offset = offsetof(struct pt_regs, r11); 921 break; 922 case 0x54: 923 reg_offset = offsetof(struct pt_regs, r12); 924 break; 925 case 0x55: 926 reg_offset = offsetof(struct pt_regs, r13); 927 break; 928 case 0x56: 929 reg_offset = offsetof(struct pt_regs, r14); 930 break; 931 case 0x57: 932 reg_offset = offsetof(struct pt_regs, r15); 933 break; 934 } 935 #else 936 return -ENOSYS; 937 #endif 938 } else { 939 switch (opc1) { 940 case 0x50: 941 reg_offset = offsetof(struct pt_regs, ax); 942 break; 943 case 0x51: 944 reg_offset = offsetof(struct pt_regs, cx); 945 break; 946 case 0x52: 947 reg_offset = offsetof(struct pt_regs, dx); 948 break; 949 case 0x53: 950 reg_offset = offsetof(struct pt_regs, bx); 951 break; 952 case 0x54: 953 reg_offset = offsetof(struct pt_regs, sp); 954 break; 955 case 0x55: 956 reg_offset = offsetof(struct pt_regs, bp); 957 break; 958 case 0x56: 959 reg_offset = offsetof(struct pt_regs, si); 960 break; 961 case 0x57: 962 reg_offset = offsetof(struct pt_regs, di); 963 break; 964 } 965 } 966 967 auprobe->push.reg_offset = reg_offset; 968 auprobe->push.ilen = insn->length; 969 auprobe->ops = &push_xol_ops; 970 return 0; 971 } 972 973 /** 974 * arch_uprobe_analyze_insn - instruction analysis including validity and fixups. 975 * @auprobe: the probepoint information. 976 * @mm: the probed address space. 977 * @addr: virtual address at which to install the probepoint 978 * Return 0 on success or a -ve number on error. 979 */ 980 int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, unsigned long addr) 981 { 982 struct insn insn; 983 u8 fix_ip_or_call = UPROBE_FIX_IP; 984 int ret; 985 986 ret = uprobe_init_insn(auprobe, &insn, is_64bit_mm(mm)); 987 if (ret) 988 return ret; 989 990 ret = branch_setup_xol_ops(auprobe, &insn); 991 if (ret != -ENOSYS) 992 return ret; 993 994 ret = push_setup_xol_ops(auprobe, &insn); 995 if (ret != -ENOSYS) 996 return ret; 997 998 /* 999 * Figure out which fixups default_post_xol_op() will need to perform, 1000 * and annotate defparam->fixups accordingly. 1001 */ 1002 switch (OPCODE1(&insn)) { 1003 case 0x9d: /* popf */ 1004 auprobe->defparam.fixups |= UPROBE_FIX_SETF; 1005 break; 1006 case 0xc3: /* ret or lret -- ip is correct */ 1007 case 0xcb: 1008 case 0xc2: 1009 case 0xca: 1010 case 0xea: /* jmp absolute -- ip is correct */ 1011 fix_ip_or_call = 0; 1012 break; 1013 case 0x9a: /* call absolute - Fix return addr, not ip */ 1014 fix_ip_or_call = UPROBE_FIX_CALL; 1015 break; 1016 case 0xff: 1017 switch (MODRM_REG(&insn)) { 1018 case 2: case 3: /* call or lcall, indirect */ 1019 fix_ip_or_call = UPROBE_FIX_CALL; 1020 break; 1021 case 4: case 5: /* jmp or ljmp, indirect */ 1022 fix_ip_or_call = 0; 1023 break; 1024 } 1025 fallthrough; 1026 default: 1027 riprel_analyze(auprobe, &insn); 1028 } 1029 1030 auprobe->defparam.ilen = insn.length; 1031 auprobe->defparam.fixups |= fix_ip_or_call; 1032 1033 auprobe->ops = &default_xol_ops; 1034 return 0; 1035 } 1036 1037 /* 1038 * arch_uprobe_pre_xol - prepare to execute out of line. 1039 * @auprobe: the probepoint information. 1040 * @regs: reflects the saved user state of current task. 1041 */ 1042 int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) 1043 { 1044 struct uprobe_task *utask = current->utask; 1045 1046 if (auprobe->ops->pre_xol) { 1047 int err = auprobe->ops->pre_xol(auprobe, regs); 1048 if (err) 1049 return err; 1050 } 1051 1052 regs->ip = utask->xol_vaddr; 1053 utask->autask.saved_trap_nr = current->thread.trap_nr; 1054 current->thread.trap_nr = UPROBE_TRAP_NR; 1055 1056 utask->autask.saved_tf = !!(regs->flags & X86_EFLAGS_TF); 1057 regs->flags |= X86_EFLAGS_TF; 1058 if (test_tsk_thread_flag(current, TIF_BLOCKSTEP)) 1059 set_task_blockstep(current, false); 1060 1061 return 0; 1062 } 1063 1064 /* 1065 * If xol insn itself traps and generates a signal(Say, 1066 * SIGILL/SIGSEGV/etc), then detect the case where a singlestepped 1067 * instruction jumps back to its own address. It is assumed that anything 1068 * like do_page_fault/do_trap/etc sets thread.trap_nr != -1. 1069 * 1070 * arch_uprobe_pre_xol/arch_uprobe_post_xol save/restore thread.trap_nr, 1071 * arch_uprobe_xol_was_trapped() simply checks that ->trap_nr is not equal to 1072 * UPROBE_TRAP_NR == -1 set by arch_uprobe_pre_xol(). 1073 */ 1074 bool arch_uprobe_xol_was_trapped(struct task_struct *t) 1075 { 1076 if (t->thread.trap_nr != UPROBE_TRAP_NR) 1077 return true; 1078 1079 return false; 1080 } 1081 1082 /* 1083 * Called after single-stepping. To avoid the SMP problems that can 1084 * occur when we temporarily put back the original opcode to 1085 * single-step, we single-stepped a copy of the instruction. 1086 * 1087 * This function prepares to resume execution after the single-step. 1088 */ 1089 int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) 1090 { 1091 struct uprobe_task *utask = current->utask; 1092 bool send_sigtrap = utask->autask.saved_tf; 1093 int err = 0; 1094 1095 WARN_ON_ONCE(current->thread.trap_nr != UPROBE_TRAP_NR); 1096 current->thread.trap_nr = utask->autask.saved_trap_nr; 1097 1098 if (auprobe->ops->post_xol) { 1099 err = auprobe->ops->post_xol(auprobe, regs); 1100 if (err) { 1101 /* 1102 * Restore ->ip for restart or post mortem analysis. 1103 * ->post_xol() must not return -ERESTART unless this 1104 * is really possible. 1105 */ 1106 regs->ip = utask->vaddr; 1107 if (err == -ERESTART) 1108 err = 0; 1109 send_sigtrap = false; 1110 } 1111 } 1112 /* 1113 * arch_uprobe_pre_xol() doesn't save the state of TIF_BLOCKSTEP 1114 * so we can get an extra SIGTRAP if we do not clear TF. We need 1115 * to examine the opcode to make it right. 1116 */ 1117 if (send_sigtrap) 1118 send_sig(SIGTRAP, current, 0); 1119 1120 if (!utask->autask.saved_tf) 1121 regs->flags &= ~X86_EFLAGS_TF; 1122 1123 return err; 1124 } 1125 1126 /* callback routine for handling exceptions. */ 1127 int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, void *data) 1128 { 1129 struct die_args *args = data; 1130 struct pt_regs *regs = args->regs; 1131 int ret = NOTIFY_DONE; 1132 1133 /* We are only interested in userspace traps */ 1134 if (regs && !user_mode(regs)) 1135 return NOTIFY_DONE; 1136 1137 switch (val) { 1138 case DIE_INT3: 1139 if (uprobe_pre_sstep_notifier(regs)) 1140 ret = NOTIFY_STOP; 1141 1142 break; 1143 1144 case DIE_DEBUG: 1145 if (uprobe_post_sstep_notifier(regs)) 1146 ret = NOTIFY_STOP; 1147 1148 break; 1149 1150 default: 1151 break; 1152 } 1153 1154 return ret; 1155 } 1156 1157 /* 1158 * This function gets called when XOL instruction either gets trapped or 1159 * the thread has a fatal signal. Reset the instruction pointer to its 1160 * probed address for the potential restart or for post mortem analysis. 1161 */ 1162 void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs) 1163 { 1164 struct uprobe_task *utask = current->utask; 1165 1166 if (auprobe->ops->abort) 1167 auprobe->ops->abort(auprobe, regs); 1168 1169 current->thread.trap_nr = utask->autask.saved_trap_nr; 1170 regs->ip = utask->vaddr; 1171 /* clear TF if it was set by us in arch_uprobe_pre_xol() */ 1172 if (!utask->autask.saved_tf) 1173 regs->flags &= ~X86_EFLAGS_TF; 1174 } 1175 1176 static bool __skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs) 1177 { 1178 if (auprobe->ops->emulate) 1179 return auprobe->ops->emulate(auprobe, regs); 1180 return false; 1181 } 1182 1183 bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs) 1184 { 1185 bool ret = __skip_sstep(auprobe, regs); 1186 if (ret && (regs->flags & X86_EFLAGS_TF)) 1187 send_sig(SIGTRAP, current, 0); 1188 return ret; 1189 } 1190 1191 unsigned long 1192 arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr, struct pt_regs *regs) 1193 { 1194 int rasize = sizeof_long(regs), nleft; 1195 unsigned long orig_ret_vaddr = 0; /* clear high bits for 32-bit apps */ 1196 1197 if (copy_from_user(&orig_ret_vaddr, (void __user *)regs->sp, rasize)) 1198 return -1; 1199 1200 /* check whether address has been already hijacked */ 1201 if (orig_ret_vaddr == trampoline_vaddr) 1202 return orig_ret_vaddr; 1203 1204 nleft = copy_to_user((void __user *)regs->sp, &trampoline_vaddr, rasize); 1205 if (likely(!nleft)) { 1206 if (shstk_update_last_frame(trampoline_vaddr)) { 1207 force_sig(SIGSEGV); 1208 return -1; 1209 } 1210 return orig_ret_vaddr; 1211 } 1212 1213 if (nleft != rasize) { 1214 pr_err("return address clobbered: pid=%d, %%sp=%#lx, %%ip=%#lx\n", 1215 current->pid, regs->sp, regs->ip); 1216 1217 force_sig(SIGSEGV); 1218 } 1219 1220 return -1; 1221 } 1222 1223 bool arch_uretprobe_is_alive(struct return_instance *ret, enum rp_check ctx, 1224 struct pt_regs *regs) 1225 { 1226 if (ctx == RP_CHECK_CALL) /* sp was just decremented by "call" insn */ 1227 return regs->sp < ret->stack; 1228 else 1229 return regs->sp <= ret->stack; 1230 } 1231