1 // SPDX-License-Identifier: GPL-2.0-only 2 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 3 4 #include <linux/kernel.h> 5 #include <linux/sched.h> 6 #include <linux/sched/clock.h> 7 #include <linux/init.h> 8 #include <linux/export.h> 9 #include <linux/timer.h> 10 #include <linux/acpi_pmtmr.h> 11 #include <linux/cpufreq.h> 12 #include <linux/delay.h> 13 #include <linux/clocksource.h> 14 #include <linux/percpu.h> 15 #include <linux/timex.h> 16 #include <linux/static_key.h> 17 #include <linux/static_call.h> 18 19 #include <asm/cpuid.h> 20 #include <asm/hpet.h> 21 #include <asm/timer.h> 22 #include <asm/vgtod.h> 23 #include <asm/time.h> 24 #include <asm/delay.h> 25 #include <asm/hypervisor.h> 26 #include <asm/nmi.h> 27 #include <asm/x86_init.h> 28 #include <asm/geode.h> 29 #include <asm/apic.h> 30 #include <asm/cpu_device_id.h> 31 #include <asm/i8259.h> 32 #include <asm/topology.h> 33 #include <asm/uv/uv.h> 34 #include <asm/sev.h> 35 36 unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */ 37 EXPORT_SYMBOL(cpu_khz); 38 39 unsigned int __read_mostly tsc_khz; 40 EXPORT_SYMBOL(tsc_khz); 41 42 #define KHZ 1000 43 44 /* 45 * TSC can be unstable due to cpufreq or due to unsynced TSCs 46 */ 47 static int __read_mostly tsc_unstable; 48 static unsigned int __initdata tsc_early_khz; 49 50 static DEFINE_STATIC_KEY_FALSE_RO(__use_tsc); 51 52 int tsc_clocksource_reliable; 53 54 static int __read_mostly tsc_force_recalibrate; 55 56 static struct clocksource_base art_base_clk = { 57 .id = CSID_X86_ART, 58 }; 59 static bool have_art; 60 61 struct cyc2ns { 62 struct cyc2ns_data data[2]; /* 0 + 2*16 = 32 */ 63 seqcount_latch_t seq; /* 32 + 4 = 36 */ 64 65 }; /* fits one cacheline */ 66 67 static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns); 68 69 static int __init tsc_early_khz_setup(char *buf) 70 { 71 return kstrtouint(buf, 0, &tsc_early_khz); 72 } 73 early_param("tsc_early_khz", tsc_early_khz_setup); 74 75 __always_inline void __cyc2ns_read(struct cyc2ns_data *data) 76 { 77 int seq, idx; 78 79 do { 80 seq = this_cpu_read(cyc2ns.seq.seqcount.sequence); 81 idx = seq & 1; 82 83 data->cyc2ns_offset = this_cpu_read(cyc2ns.data[idx].cyc2ns_offset); 84 data->cyc2ns_mul = this_cpu_read(cyc2ns.data[idx].cyc2ns_mul); 85 data->cyc2ns_shift = this_cpu_read(cyc2ns.data[idx].cyc2ns_shift); 86 87 } while (unlikely(seq != this_cpu_read(cyc2ns.seq.seqcount.sequence))); 88 } 89 90 __always_inline void cyc2ns_read_begin(struct cyc2ns_data *data) 91 { 92 preempt_disable_notrace(); 93 __cyc2ns_read(data); 94 } 95 96 __always_inline void cyc2ns_read_end(void) 97 { 98 preempt_enable_notrace(); 99 } 100 101 /* 102 * Accelerators for sched_clock() 103 * convert from cycles(64bits) => nanoseconds (64bits) 104 * basic equation: 105 * ns = cycles / (freq / ns_per_sec) 106 * ns = cycles * (ns_per_sec / freq) 107 * ns = cycles * (10^9 / (cpu_khz * 10^3)) 108 * ns = cycles * (10^6 / cpu_khz) 109 * 110 * Then we use scaling math (suggested by george@mvista.com) to get: 111 * ns = cycles * (10^6 * SC / cpu_khz) / SC 112 * ns = cycles * cyc2ns_scale / SC 113 * 114 * And since SC is a constant power of two, we can convert the div 115 * into a shift. The larger SC is, the more accurate the conversion, but 116 * cyc2ns_scale needs to be a 32-bit value so that 32-bit multiplication 117 * (64-bit result) can be used. 118 * 119 * We can use khz divisor instead of mhz to keep a better precision. 120 * (mathieu.desnoyers@polymtl.ca) 121 * 122 * -johnstul@us.ibm.com "math is hard, lets go shopping!" 123 */ 124 125 static __always_inline unsigned long long __cycles_2_ns(unsigned long long cyc) 126 { 127 struct cyc2ns_data data; 128 unsigned long long ns; 129 130 __cyc2ns_read(&data); 131 132 ns = data.cyc2ns_offset; 133 ns += mul_u64_u32_shr(cyc, data.cyc2ns_mul, data.cyc2ns_shift); 134 135 return ns; 136 } 137 138 static __always_inline unsigned long long cycles_2_ns(unsigned long long cyc) 139 { 140 unsigned long long ns; 141 preempt_disable_notrace(); 142 ns = __cycles_2_ns(cyc); 143 preempt_enable_notrace(); 144 return ns; 145 } 146 147 static void __set_cyc2ns_scale(unsigned long khz, int cpu, unsigned long long tsc_now) 148 { 149 unsigned long long ns_now; 150 struct cyc2ns_data data; 151 struct cyc2ns *c2n; 152 153 ns_now = cycles_2_ns(tsc_now); 154 155 /* 156 * Compute a new multiplier as per the above comment and ensure our 157 * time function is continuous; see the comment near struct 158 * cyc2ns_data. 159 */ 160 clocks_calc_mult_shift(&data.cyc2ns_mul, &data.cyc2ns_shift, khz, 161 NSEC_PER_MSEC, 0); 162 163 /* 164 * cyc2ns_shift is exported via arch_perf_update_userpage() where it is 165 * not expected to be greater than 31 due to the original published 166 * conversion algorithm shifting a 32-bit value (now specifies a 64-bit 167 * value) - refer perf_event_mmap_page documentation in perf_event.h. 168 */ 169 if (data.cyc2ns_shift == 32) { 170 data.cyc2ns_shift = 31; 171 data.cyc2ns_mul >>= 1; 172 } 173 174 data.cyc2ns_offset = ns_now - 175 mul_u64_u32_shr(tsc_now, data.cyc2ns_mul, data.cyc2ns_shift); 176 177 c2n = per_cpu_ptr(&cyc2ns, cpu); 178 179 write_seqcount_latch_begin(&c2n->seq); 180 c2n->data[0] = data; 181 write_seqcount_latch(&c2n->seq); 182 c2n->data[1] = data; 183 write_seqcount_latch_end(&c2n->seq); 184 } 185 186 static void set_cyc2ns_scale(unsigned long khz, int cpu, unsigned long long tsc_now) 187 { 188 unsigned long flags; 189 190 local_irq_save(flags); 191 sched_clock_idle_sleep_event(); 192 193 if (khz) 194 __set_cyc2ns_scale(khz, cpu, tsc_now); 195 196 sched_clock_idle_wakeup_event(); 197 local_irq_restore(flags); 198 } 199 200 /* 201 * Initialize cyc2ns for boot cpu 202 */ 203 static void __init cyc2ns_init_boot_cpu(void) 204 { 205 struct cyc2ns *c2n = this_cpu_ptr(&cyc2ns); 206 207 seqcount_latch_init(&c2n->seq); 208 __set_cyc2ns_scale(tsc_khz, smp_processor_id(), rdtsc()); 209 } 210 211 /* 212 * Secondary CPUs do not run through tsc_init(), so set up 213 * all the scale factors for all CPUs, assuming the same 214 * speed as the bootup CPU. 215 */ 216 static void __init cyc2ns_init_secondary_cpus(void) 217 { 218 unsigned int cpu, this_cpu = smp_processor_id(); 219 struct cyc2ns *c2n = this_cpu_ptr(&cyc2ns); 220 struct cyc2ns_data *data = c2n->data; 221 222 for_each_possible_cpu(cpu) { 223 if (cpu != this_cpu) { 224 seqcount_latch_init(&c2n->seq); 225 c2n = per_cpu_ptr(&cyc2ns, cpu); 226 c2n->data[0] = data[0]; 227 c2n->data[1] = data[1]; 228 } 229 } 230 } 231 232 /* 233 * Scheduler clock - returns current time in nanosec units. 234 */ 235 noinstr u64 native_sched_clock(void) 236 { 237 if (static_branch_likely(&__use_tsc)) { 238 u64 tsc_now = rdtsc(); 239 240 /* return the value in ns */ 241 return __cycles_2_ns(tsc_now); 242 } 243 244 /* 245 * Fall back to jiffies if there's no TSC available: 246 * ( But note that we still use it if the TSC is marked 247 * unstable. We do this because unlike Time Of Day, 248 * the scheduler clock tolerates small errors and it's 249 * very important for it to be as fast as the platform 250 * can achieve it. ) 251 */ 252 253 /* No locking but a rare wrong value is not a big deal: */ 254 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ); 255 } 256 257 /* 258 * Generate a sched_clock if you already have a TSC value. 259 */ 260 u64 native_sched_clock_from_tsc(u64 tsc) 261 { 262 return cycles_2_ns(tsc); 263 } 264 265 /* We need to define a real function for sched_clock, to override the 266 weak default version */ 267 #ifdef CONFIG_PARAVIRT 268 noinstr u64 sched_clock_noinstr(void) 269 { 270 return paravirt_sched_clock(); 271 } 272 273 bool using_native_sched_clock(void) 274 { 275 return static_call_query(pv_sched_clock) == native_sched_clock; 276 } 277 #else 278 u64 sched_clock_noinstr(void) __attribute__((alias("native_sched_clock"))); 279 280 bool using_native_sched_clock(void) { return true; } 281 #endif 282 283 notrace u64 sched_clock(void) 284 { 285 u64 now; 286 preempt_disable_notrace(); 287 now = sched_clock_noinstr(); 288 preempt_enable_notrace(); 289 return now; 290 } 291 292 int check_tsc_unstable(void) 293 { 294 return tsc_unstable; 295 } 296 EXPORT_SYMBOL_GPL(check_tsc_unstable); 297 298 #ifdef CONFIG_X86_TSC 299 int __init notsc_setup(char *str) 300 { 301 mark_tsc_unstable("boot parameter notsc"); 302 return 1; 303 } 304 #else 305 /* 306 * disable flag for tsc. Takes effect by clearing the TSC cpu flag 307 * in cpu/common.c 308 */ 309 int __init notsc_setup(char *str) 310 { 311 setup_clear_cpu_cap(X86_FEATURE_TSC); 312 return 1; 313 } 314 #endif 315 316 __setup("notsc", notsc_setup); 317 318 static int no_sched_irq_time; 319 static int no_tsc_watchdog; 320 static int tsc_as_watchdog; 321 322 static int __init tsc_setup(char *str) 323 { 324 if (!strcmp(str, "reliable")) 325 tsc_clocksource_reliable = 1; 326 if (!strncmp(str, "noirqtime", 9)) 327 no_sched_irq_time = 1; 328 if (!strcmp(str, "unstable")) 329 mark_tsc_unstable("boot parameter"); 330 if (!strcmp(str, "nowatchdog")) { 331 no_tsc_watchdog = 1; 332 if (tsc_as_watchdog) 333 pr_alert("%s: Overriding earlier tsc=watchdog with tsc=nowatchdog\n", 334 __func__); 335 tsc_as_watchdog = 0; 336 } 337 if (!strcmp(str, "recalibrate")) 338 tsc_force_recalibrate = 1; 339 if (!strcmp(str, "watchdog")) { 340 if (no_tsc_watchdog) 341 pr_alert("%s: tsc=watchdog overridden by earlier tsc=nowatchdog\n", 342 __func__); 343 else 344 tsc_as_watchdog = 1; 345 } 346 return 1; 347 } 348 349 __setup("tsc=", tsc_setup); 350 351 #define MAX_RETRIES 5 352 #define TSC_DEFAULT_THRESHOLD 0x20000 353 354 /* 355 * Read TSC and the reference counters. Take care of any disturbances 356 */ 357 static u64 tsc_read_refs(u64 *p, int hpet) 358 { 359 u64 t1, t2; 360 u64 thresh = tsc_khz ? tsc_khz >> 5 : TSC_DEFAULT_THRESHOLD; 361 int i; 362 363 for (i = 0; i < MAX_RETRIES; i++) { 364 t1 = get_cycles(); 365 if (hpet) 366 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF; 367 else 368 *p = acpi_pm_read_early(); 369 t2 = get_cycles(); 370 if ((t2 - t1) < thresh) 371 return t2; 372 } 373 return ULLONG_MAX; 374 } 375 376 /* 377 * Calculate the TSC frequency from HPET reference 378 */ 379 static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2) 380 { 381 u64 tmp; 382 383 if (hpet2 < hpet1) 384 hpet2 += 0x100000000ULL; 385 hpet2 -= hpet1; 386 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD)); 387 do_div(tmp, 1000000); 388 deltatsc = div64_u64(deltatsc, tmp); 389 390 return (unsigned long) deltatsc; 391 } 392 393 /* 394 * Calculate the TSC frequency from PMTimer reference 395 */ 396 static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2) 397 { 398 u64 tmp; 399 400 if (!pm1 && !pm2) 401 return ULONG_MAX; 402 403 if (pm2 < pm1) 404 pm2 += (u64)ACPI_PM_OVRRUN; 405 pm2 -= pm1; 406 tmp = pm2 * 1000000000LL; 407 do_div(tmp, PMTMR_TICKS_PER_SEC); 408 do_div(deltatsc, tmp); 409 410 return (unsigned long) deltatsc; 411 } 412 413 #define CAL_MS 10 414 #define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS)) 415 #define CAL_PIT_LOOPS 1000 416 417 #define CAL2_MS 50 418 #define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS)) 419 #define CAL2_PIT_LOOPS 5000 420 421 422 /* 423 * Try to calibrate the TSC against the Programmable 424 * Interrupt Timer and return the frequency of the TSC 425 * in kHz. 426 * 427 * Return ULONG_MAX on failure to calibrate. 428 */ 429 static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin) 430 { 431 u64 tsc, t1, t2, delta; 432 unsigned long tscmin, tscmax; 433 int pitcnt; 434 435 if (!has_legacy_pic()) { 436 /* 437 * Relies on tsc_early_delay_calibrate() to have given us semi 438 * usable udelay(), wait for the same 50ms we would have with 439 * the PIT loop below. 440 */ 441 udelay(10 * USEC_PER_MSEC); 442 udelay(10 * USEC_PER_MSEC); 443 udelay(10 * USEC_PER_MSEC); 444 udelay(10 * USEC_PER_MSEC); 445 udelay(10 * USEC_PER_MSEC); 446 return ULONG_MAX; 447 } 448 449 /* Set the Gate high, disable speaker */ 450 outb((inb(0x61) & ~0x02) | 0x01, 0x61); 451 452 /* 453 * Setup CTC channel 2* for mode 0, (interrupt on terminal 454 * count mode), binary count. Set the latch register to 50ms 455 * (LSB then MSB) to begin countdown. 456 */ 457 outb(0xb0, 0x43); 458 outb(latch & 0xff, 0x42); 459 outb(latch >> 8, 0x42); 460 461 tsc = t1 = t2 = get_cycles(); 462 463 pitcnt = 0; 464 tscmax = 0; 465 tscmin = ULONG_MAX; 466 while ((inb(0x61) & 0x20) == 0) { 467 t2 = get_cycles(); 468 delta = t2 - tsc; 469 tsc = t2; 470 if ((unsigned long) delta < tscmin) 471 tscmin = (unsigned int) delta; 472 if ((unsigned long) delta > tscmax) 473 tscmax = (unsigned int) delta; 474 pitcnt++; 475 } 476 477 /* 478 * Sanity checks: 479 * 480 * If we were not able to read the PIT more than loopmin 481 * times, then we have been hit by a massive SMI 482 * 483 * If the maximum is 10 times larger than the minimum, 484 * then we got hit by an SMI as well. 485 */ 486 if (pitcnt < loopmin || tscmax > 10 * tscmin) 487 return ULONG_MAX; 488 489 /* Calculate the PIT value */ 490 delta = t2 - t1; 491 do_div(delta, ms); 492 return delta; 493 } 494 495 /* 496 * This reads the current MSB of the PIT counter, and 497 * checks if we are running on sufficiently fast and 498 * non-virtualized hardware. 499 * 500 * Our expectations are: 501 * 502 * - the PIT is running at roughly 1.19MHz 503 * 504 * - each IO is going to take about 1us on real hardware, 505 * but we allow it to be much faster (by a factor of 10) or 506 * _slightly_ slower (ie we allow up to a 2us read+counter 507 * update - anything else implies a unacceptably slow CPU 508 * or PIT for the fast calibration to work. 509 * 510 * - with 256 PIT ticks to read the value, we have 214us to 511 * see the same MSB (and overhead like doing a single TSC 512 * read per MSB value etc). 513 * 514 * - We're doing 2 reads per loop (LSB, MSB), and we expect 515 * them each to take about a microsecond on real hardware. 516 * So we expect a count value of around 100. But we'll be 517 * generous, and accept anything over 50. 518 * 519 * - if the PIT is stuck, and we see *many* more reads, we 520 * return early (and the next caller of pit_expect_msb() 521 * then consider it a failure when they don't see the 522 * next expected value). 523 * 524 * These expectations mean that we know that we have seen the 525 * transition from one expected value to another with a fairly 526 * high accuracy, and we didn't miss any events. We can thus 527 * use the TSC value at the transitions to calculate a pretty 528 * good value for the TSC frequency. 529 */ 530 static inline int pit_verify_msb(unsigned char val) 531 { 532 /* Ignore LSB */ 533 inb(0x42); 534 return inb(0x42) == val; 535 } 536 537 static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap) 538 { 539 int count; 540 u64 tsc = 0, prev_tsc = 0; 541 542 for (count = 0; count < 50000; count++) { 543 if (!pit_verify_msb(val)) 544 break; 545 prev_tsc = tsc; 546 tsc = get_cycles(); 547 } 548 *deltap = get_cycles() - prev_tsc; 549 *tscp = tsc; 550 551 /* 552 * We require _some_ success, but the quality control 553 * will be based on the error terms on the TSC values. 554 */ 555 return count > 5; 556 } 557 558 /* 559 * How many MSB values do we want to see? We aim for 560 * a maximum error rate of 500ppm (in practice the 561 * real error is much smaller), but refuse to spend 562 * more than 50ms on it. 563 */ 564 #define MAX_QUICK_PIT_MS 50 565 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) 566 567 static unsigned long quick_pit_calibrate(void) 568 { 569 int i; 570 u64 tsc, delta; 571 unsigned long d1, d2; 572 573 if (!has_legacy_pic()) 574 return 0; 575 576 /* Set the Gate high, disable speaker */ 577 outb((inb(0x61) & ~0x02) | 0x01, 0x61); 578 579 /* 580 * Counter 2, mode 0 (one-shot), binary count 581 * 582 * NOTE! Mode 2 decrements by two (and then the 583 * output is flipped each time, giving the same 584 * final output frequency as a decrement-by-one), 585 * so mode 0 is much better when looking at the 586 * individual counts. 587 */ 588 outb(0xb0, 0x43); 589 590 /* Start at 0xffff */ 591 outb(0xff, 0x42); 592 outb(0xff, 0x42); 593 594 /* 595 * The PIT starts counting at the next edge, so we 596 * need to delay for a microsecond. The easiest way 597 * to do that is to just read back the 16-bit counter 598 * once from the PIT. 599 */ 600 pit_verify_msb(0); 601 602 if (pit_expect_msb(0xff, &tsc, &d1)) { 603 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) { 604 if (!pit_expect_msb(0xff-i, &delta, &d2)) 605 break; 606 607 delta -= tsc; 608 609 /* 610 * Extrapolate the error and fail fast if the error will 611 * never be below 500 ppm. 612 */ 613 if (i == 1 && 614 d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11) 615 return 0; 616 617 /* 618 * Iterate until the error is less than 500 ppm 619 */ 620 if (d1+d2 >= delta >> 11) 621 continue; 622 623 /* 624 * Check the PIT one more time to verify that 625 * all TSC reads were stable wrt the PIT. 626 * 627 * This also guarantees serialization of the 628 * last cycle read ('d2') in pit_expect_msb. 629 */ 630 if (!pit_verify_msb(0xfe - i)) 631 break; 632 goto success; 633 } 634 } 635 pr_info("Fast TSC calibration failed\n"); 636 return 0; 637 638 success: 639 /* 640 * Ok, if we get here, then we've seen the 641 * MSB of the PIT decrement 'i' times, and the 642 * error has shrunk to less than 500 ppm. 643 * 644 * As a result, we can depend on there not being 645 * any odd delays anywhere, and the TSC reads are 646 * reliable (within the error). 647 * 648 * kHz = ticks / time-in-seconds / 1000; 649 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000 650 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000) 651 */ 652 delta *= PIT_TICK_RATE; 653 do_div(delta, i*256*1000); 654 pr_info("Fast TSC calibration using PIT\n"); 655 return delta; 656 } 657 658 /** 659 * native_calibrate_tsc - determine TSC frequency 660 * Determine TSC frequency via CPUID, else return 0. 661 */ 662 unsigned long native_calibrate_tsc(void) 663 { 664 unsigned int eax_denominator, ebx_numerator, ecx_hz, edx; 665 unsigned int crystal_khz; 666 667 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 668 return 0; 669 670 if (boot_cpu_data.cpuid_level < CPUID_LEAF_TSC) 671 return 0; 672 673 eax_denominator = ebx_numerator = ecx_hz = edx = 0; 674 675 /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */ 676 cpuid(CPUID_LEAF_TSC, &eax_denominator, &ebx_numerator, &ecx_hz, &edx); 677 678 if (ebx_numerator == 0 || eax_denominator == 0) 679 return 0; 680 681 crystal_khz = ecx_hz / 1000; 682 683 /* 684 * Denverton SoCs don't report crystal clock, and also don't support 685 * CPUID_LEAF_FREQ for the calculation below, so hardcode the 25MHz 686 * crystal clock. 687 */ 688 if (crystal_khz == 0 && 689 boot_cpu_data.x86_vfm == INTEL_ATOM_GOLDMONT_D) 690 crystal_khz = 25000; 691 692 /* 693 * TSC frequency reported directly by CPUID is a "hardware reported" 694 * frequency and is the most accurate one so far we have. This 695 * is considered a known frequency. 696 */ 697 if (crystal_khz != 0) 698 setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ); 699 700 /* 701 * Some Intel SoCs like Skylake and Kabylake don't report the crystal 702 * clock, but we can easily calculate it to a high degree of accuracy 703 * by considering the crystal ratio and the CPU speed. 704 */ 705 if (crystal_khz == 0 && boot_cpu_data.cpuid_level >= CPUID_LEAF_FREQ) { 706 unsigned int eax_base_mhz, ebx, ecx, edx; 707 708 cpuid(CPUID_LEAF_FREQ, &eax_base_mhz, &ebx, &ecx, &edx); 709 crystal_khz = eax_base_mhz * 1000 * 710 eax_denominator / ebx_numerator; 711 } 712 713 if (crystal_khz == 0) 714 return 0; 715 716 /* 717 * For Atom SoCs TSC is the only reliable clocksource. 718 * Mark TSC reliable so no watchdog on it. 719 */ 720 if (boot_cpu_data.x86_vfm == INTEL_ATOM_GOLDMONT) 721 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); 722 723 #ifdef CONFIG_X86_LOCAL_APIC 724 /* 725 * The local APIC appears to be fed by the core crystal clock 726 * (which sounds entirely sensible). We can set the global 727 * lapic_timer_period here to avoid having to calibrate the APIC 728 * timer later. 729 */ 730 lapic_timer_period = crystal_khz * 1000 / HZ; 731 #endif 732 733 return crystal_khz * ebx_numerator / eax_denominator; 734 } 735 736 static unsigned long cpu_khz_from_cpuid(void) 737 { 738 unsigned int eax_base_mhz, ebx_max_mhz, ecx_bus_mhz, edx; 739 740 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 741 return 0; 742 743 if (boot_cpu_data.cpuid_level < CPUID_LEAF_FREQ) 744 return 0; 745 746 eax_base_mhz = ebx_max_mhz = ecx_bus_mhz = edx = 0; 747 748 cpuid(CPUID_LEAF_FREQ, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx); 749 750 return eax_base_mhz * 1000; 751 } 752 753 /* 754 * calibrate cpu using pit, hpet, and ptimer methods. They are available 755 * later in boot after acpi is initialized. 756 */ 757 static unsigned long pit_hpet_ptimer_calibrate_cpu(void) 758 { 759 u64 tsc1, tsc2, delta, ref1, ref2; 760 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX; 761 unsigned long flags, latch, ms; 762 int hpet = is_hpet_enabled(), i, loopmin; 763 764 /* 765 * Run 5 calibration loops to get the lowest frequency value 766 * (the best estimate). We use two different calibration modes 767 * here: 768 * 769 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and 770 * load a timeout of 50ms. We read the time right after we 771 * started the timer and wait until the PIT count down reaches 772 * zero. In each wait loop iteration we read the TSC and check 773 * the delta to the previous read. We keep track of the min 774 * and max values of that delta. The delta is mostly defined 775 * by the IO time of the PIT access, so we can detect when 776 * any disturbance happened between the two reads. If the 777 * maximum time is significantly larger than the minimum time, 778 * then we discard the result and have another try. 779 * 780 * 2) Reference counter. If available we use the HPET or the 781 * PMTIMER as a reference to check the sanity of that value. 782 * We use separate TSC readouts and check inside of the 783 * reference read for any possible disturbance. We discard 784 * disturbed values here as well. We do that around the PIT 785 * calibration delay loop as we have to wait for a certain 786 * amount of time anyway. 787 */ 788 789 /* Preset PIT loop values */ 790 latch = CAL_LATCH; 791 ms = CAL_MS; 792 loopmin = CAL_PIT_LOOPS; 793 794 for (i = 0; i < 3; i++) { 795 unsigned long tsc_pit_khz; 796 797 /* 798 * Read the start value and the reference count of 799 * hpet/pmtimer when available. Then do the PIT 800 * calibration, which will take at least 50ms, and 801 * read the end value. 802 */ 803 local_irq_save(flags); 804 tsc1 = tsc_read_refs(&ref1, hpet); 805 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin); 806 tsc2 = tsc_read_refs(&ref2, hpet); 807 local_irq_restore(flags); 808 809 /* Pick the lowest PIT TSC calibration so far */ 810 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz); 811 812 /* hpet or pmtimer available ? */ 813 if (ref1 == ref2) 814 continue; 815 816 /* Check, whether the sampling was disturbed */ 817 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX) 818 continue; 819 820 tsc2 = (tsc2 - tsc1) * 1000000LL; 821 if (hpet) 822 tsc2 = calc_hpet_ref(tsc2, ref1, ref2); 823 else 824 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2); 825 826 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2); 827 828 /* Check the reference deviation */ 829 delta = ((u64) tsc_pit_min) * 100; 830 do_div(delta, tsc_ref_min); 831 832 /* 833 * If both calibration results are inside a 10% window 834 * then we can be sure, that the calibration 835 * succeeded. We break out of the loop right away. We 836 * use the reference value, as it is more precise. 837 */ 838 if (delta >= 90 && delta <= 110) { 839 pr_info("PIT calibration matches %s. %d loops\n", 840 hpet ? "HPET" : "PMTIMER", i + 1); 841 return tsc_ref_min; 842 } 843 844 /* 845 * Check whether PIT failed more than once. This 846 * happens in virtualized environments. We need to 847 * give the virtual PC a slightly longer timeframe for 848 * the HPET/PMTIMER to make the result precise. 849 */ 850 if (i == 1 && tsc_pit_min == ULONG_MAX) { 851 latch = CAL2_LATCH; 852 ms = CAL2_MS; 853 loopmin = CAL2_PIT_LOOPS; 854 } 855 } 856 857 /* 858 * Now check the results. 859 */ 860 if (tsc_pit_min == ULONG_MAX) { 861 /* PIT gave no useful value */ 862 pr_warn("Unable to calibrate against PIT\n"); 863 864 /* We don't have an alternative source, disable TSC */ 865 if (!hpet && !ref1 && !ref2) { 866 pr_notice("No reference (HPET/PMTIMER) available\n"); 867 return 0; 868 } 869 870 /* The alternative source failed as well, disable TSC */ 871 if (tsc_ref_min == ULONG_MAX) { 872 pr_warn("HPET/PMTIMER calibration failed\n"); 873 return 0; 874 } 875 876 /* Use the alternative source */ 877 pr_info("using %s reference calibration\n", 878 hpet ? "HPET" : "PMTIMER"); 879 880 return tsc_ref_min; 881 } 882 883 /* We don't have an alternative source, use the PIT calibration value */ 884 if (!hpet && !ref1 && !ref2) { 885 pr_info("Using PIT calibration value\n"); 886 return tsc_pit_min; 887 } 888 889 /* The alternative source failed, use the PIT calibration value */ 890 if (tsc_ref_min == ULONG_MAX) { 891 pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n"); 892 return tsc_pit_min; 893 } 894 895 /* 896 * The calibration values differ too much. In doubt, we use 897 * the PIT value as we know that there are PMTIMERs around 898 * running at double speed. At least we let the user know: 899 */ 900 pr_warn("PIT calibration deviates from %s: %lu %lu\n", 901 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min); 902 pr_info("Using PIT calibration value\n"); 903 return tsc_pit_min; 904 } 905 906 /** 907 * native_calibrate_cpu_early - can calibrate the cpu early in boot 908 */ 909 unsigned long native_calibrate_cpu_early(void) 910 { 911 unsigned long flags, fast_calibrate = cpu_khz_from_cpuid(); 912 913 if (!fast_calibrate) 914 fast_calibrate = cpu_khz_from_msr(); 915 if (!fast_calibrate) { 916 local_irq_save(flags); 917 fast_calibrate = quick_pit_calibrate(); 918 local_irq_restore(flags); 919 } 920 return fast_calibrate; 921 } 922 923 924 /** 925 * native_calibrate_cpu - calibrate the cpu 926 */ 927 static unsigned long native_calibrate_cpu(void) 928 { 929 unsigned long tsc_freq = native_calibrate_cpu_early(); 930 931 if (!tsc_freq) 932 tsc_freq = pit_hpet_ptimer_calibrate_cpu(); 933 934 return tsc_freq; 935 } 936 937 void recalibrate_cpu_khz(void) 938 { 939 #ifndef CONFIG_SMP 940 unsigned long cpu_khz_old = cpu_khz; 941 942 if (!boot_cpu_has(X86_FEATURE_TSC)) 943 return; 944 945 cpu_khz = x86_platform.calibrate_cpu(); 946 tsc_khz = x86_platform.calibrate_tsc(); 947 if (tsc_khz == 0) 948 tsc_khz = cpu_khz; 949 else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz) 950 cpu_khz = tsc_khz; 951 cpu_data(0).loops_per_jiffy = cpufreq_scale(cpu_data(0).loops_per_jiffy, 952 cpu_khz_old, cpu_khz); 953 #endif 954 } 955 EXPORT_SYMBOL_GPL(recalibrate_cpu_khz); 956 957 958 static unsigned long long cyc2ns_suspend; 959 960 void tsc_save_sched_clock_state(void) 961 { 962 if (!sched_clock_stable()) 963 return; 964 965 cyc2ns_suspend = sched_clock(); 966 } 967 968 /* 969 * Even on processors with invariant TSC, TSC gets reset in some the 970 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to 971 * arbitrary value (still sync'd across cpu's) during resume from such sleep 972 * states. To cope up with this, recompute the cyc2ns_offset for each cpu so 973 * that sched_clock() continues from the point where it was left off during 974 * suspend. 975 */ 976 void tsc_restore_sched_clock_state(void) 977 { 978 unsigned long long offset; 979 unsigned long flags; 980 int cpu; 981 982 if (!sched_clock_stable()) 983 return; 984 985 local_irq_save(flags); 986 987 /* 988 * We're coming out of suspend, there's no concurrency yet; don't 989 * bother being nice about the RCU stuff, just write to both 990 * data fields. 991 */ 992 993 this_cpu_write(cyc2ns.data[0].cyc2ns_offset, 0); 994 this_cpu_write(cyc2ns.data[1].cyc2ns_offset, 0); 995 996 offset = cyc2ns_suspend - sched_clock(); 997 998 for_each_possible_cpu(cpu) { 999 per_cpu(cyc2ns.data[0].cyc2ns_offset, cpu) = offset; 1000 per_cpu(cyc2ns.data[1].cyc2ns_offset, cpu) = offset; 1001 } 1002 1003 local_irq_restore(flags); 1004 } 1005 1006 #ifdef CONFIG_CPU_FREQ 1007 /* 1008 * Frequency scaling support. Adjust the TSC based timer when the CPU frequency 1009 * changes. 1010 * 1011 * NOTE: On SMP the situation is not fixable in general, so simply mark the TSC 1012 * as unstable and give up in those cases. 1013 * 1014 * Should fix up last_tsc too. Currently gettimeofday in the 1015 * first tick after the change will be slightly wrong. 1016 */ 1017 1018 static unsigned int ref_freq; 1019 static unsigned long loops_per_jiffy_ref; 1020 static unsigned long tsc_khz_ref; 1021 1022 static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 1023 void *data) 1024 { 1025 struct cpufreq_freqs *freq = data; 1026 1027 if (num_online_cpus() > 1) { 1028 mark_tsc_unstable("cpufreq changes on SMP"); 1029 return 0; 1030 } 1031 1032 if (!ref_freq) { 1033 ref_freq = freq->old; 1034 loops_per_jiffy_ref = boot_cpu_data.loops_per_jiffy; 1035 tsc_khz_ref = tsc_khz; 1036 } 1037 1038 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || 1039 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) { 1040 boot_cpu_data.loops_per_jiffy = 1041 cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new); 1042 1043 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new); 1044 if (!(freq->flags & CPUFREQ_CONST_LOOPS)) 1045 mark_tsc_unstable("cpufreq changes"); 1046 1047 set_cyc2ns_scale(tsc_khz, freq->policy->cpu, rdtsc()); 1048 } 1049 1050 return 0; 1051 } 1052 1053 static struct notifier_block time_cpufreq_notifier_block = { 1054 .notifier_call = time_cpufreq_notifier 1055 }; 1056 1057 static int __init cpufreq_register_tsc_scaling(void) 1058 { 1059 if (!boot_cpu_has(X86_FEATURE_TSC)) 1060 return 0; 1061 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 1062 return 0; 1063 cpufreq_register_notifier(&time_cpufreq_notifier_block, 1064 CPUFREQ_TRANSITION_NOTIFIER); 1065 return 0; 1066 } 1067 1068 core_initcall(cpufreq_register_tsc_scaling); 1069 1070 #endif /* CONFIG_CPU_FREQ */ 1071 1072 #define ART_MIN_DENOMINATOR (1) 1073 1074 /* 1075 * If ART is present detect the numerator:denominator to convert to TSC 1076 */ 1077 static void __init detect_art(void) 1078 { 1079 unsigned int unused; 1080 1081 if (boot_cpu_data.cpuid_level < CPUID_LEAF_TSC) 1082 return; 1083 1084 /* 1085 * Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required, 1086 * and the TSC counter resets must not occur asynchronously. 1087 */ 1088 if (boot_cpu_has(X86_FEATURE_HYPERVISOR) || 1089 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC) || 1090 !boot_cpu_has(X86_FEATURE_TSC_ADJUST) || 1091 tsc_async_resets) 1092 return; 1093 1094 cpuid(CPUID_LEAF_TSC, &art_base_clk.denominator, 1095 &art_base_clk.numerator, &art_base_clk.freq_khz, &unused); 1096 1097 art_base_clk.freq_khz /= KHZ; 1098 if (art_base_clk.denominator < ART_MIN_DENOMINATOR) 1099 return; 1100 1101 rdmsrl(MSR_IA32_TSC_ADJUST, art_base_clk.offset); 1102 1103 /* Make this sticky over multiple CPU init calls */ 1104 setup_force_cpu_cap(X86_FEATURE_ART); 1105 } 1106 1107 1108 /* clocksource code */ 1109 1110 static void tsc_resume(struct clocksource *cs) 1111 { 1112 tsc_verify_tsc_adjust(true); 1113 } 1114 1115 /* 1116 * We used to compare the TSC to the cycle_last value in the clocksource 1117 * structure to avoid a nasty time-warp. This can be observed in a 1118 * very small window right after one CPU updated cycle_last under 1119 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which 1120 * is smaller than the cycle_last reference value due to a TSC which 1121 * is slightly behind. This delta is nowhere else observable, but in 1122 * that case it results in a forward time jump in the range of hours 1123 * due to the unsigned delta calculation of the time keeping core 1124 * code, which is necessary to support wrapping clocksources like pm 1125 * timer. 1126 * 1127 * This sanity check is now done in the core timekeeping code. 1128 * checking the result of read_tsc() - cycle_last for being negative. 1129 * That works because CLOCKSOURCE_MASK(64) does not mask out any bit. 1130 */ 1131 static u64 read_tsc(struct clocksource *cs) 1132 { 1133 return (u64)rdtsc_ordered(); 1134 } 1135 1136 static void tsc_cs_mark_unstable(struct clocksource *cs) 1137 { 1138 if (tsc_unstable) 1139 return; 1140 1141 tsc_unstable = 1; 1142 if (using_native_sched_clock()) 1143 clear_sched_clock_stable(); 1144 disable_sched_clock_irqtime(); 1145 pr_info("Marking TSC unstable due to clocksource watchdog\n"); 1146 } 1147 1148 static void tsc_cs_tick_stable(struct clocksource *cs) 1149 { 1150 if (tsc_unstable) 1151 return; 1152 1153 if (using_native_sched_clock()) 1154 sched_clock_tick_stable(); 1155 } 1156 1157 static int tsc_cs_enable(struct clocksource *cs) 1158 { 1159 vclocks_set_used(VDSO_CLOCKMODE_TSC); 1160 return 0; 1161 } 1162 1163 /* 1164 * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc() 1165 */ 1166 static struct clocksource clocksource_tsc_early = { 1167 .name = "tsc-early", 1168 .rating = 299, 1169 .uncertainty_margin = 32 * NSEC_PER_MSEC, 1170 .read = read_tsc, 1171 .mask = CLOCKSOURCE_MASK(64), 1172 .flags = CLOCK_SOURCE_IS_CONTINUOUS | 1173 CLOCK_SOURCE_MUST_VERIFY, 1174 .id = CSID_X86_TSC_EARLY, 1175 .vdso_clock_mode = VDSO_CLOCKMODE_TSC, 1176 .enable = tsc_cs_enable, 1177 .resume = tsc_resume, 1178 .mark_unstable = tsc_cs_mark_unstable, 1179 .tick_stable = tsc_cs_tick_stable, 1180 .list = LIST_HEAD_INIT(clocksource_tsc_early.list), 1181 }; 1182 1183 /* 1184 * Must mark VALID_FOR_HRES early such that when we unregister tsc_early 1185 * this one will immediately take over. We will only register if TSC has 1186 * been found good. 1187 */ 1188 static struct clocksource clocksource_tsc = { 1189 .name = "tsc", 1190 .rating = 300, 1191 .read = read_tsc, 1192 .mask = CLOCKSOURCE_MASK(64), 1193 .flags = CLOCK_SOURCE_IS_CONTINUOUS | 1194 CLOCK_SOURCE_VALID_FOR_HRES | 1195 CLOCK_SOURCE_MUST_VERIFY | 1196 CLOCK_SOURCE_VERIFY_PERCPU, 1197 .id = CSID_X86_TSC, 1198 .vdso_clock_mode = VDSO_CLOCKMODE_TSC, 1199 .enable = tsc_cs_enable, 1200 .resume = tsc_resume, 1201 .mark_unstable = tsc_cs_mark_unstable, 1202 .tick_stable = tsc_cs_tick_stable, 1203 .list = LIST_HEAD_INIT(clocksource_tsc.list), 1204 }; 1205 1206 void mark_tsc_unstable(char *reason) 1207 { 1208 if (tsc_unstable) 1209 return; 1210 1211 tsc_unstable = 1; 1212 if (using_native_sched_clock()) 1213 clear_sched_clock_stable(); 1214 disable_sched_clock_irqtime(); 1215 pr_info("Marking TSC unstable due to %s\n", reason); 1216 1217 clocksource_mark_unstable(&clocksource_tsc_early); 1218 clocksource_mark_unstable(&clocksource_tsc); 1219 } 1220 1221 EXPORT_SYMBOL_GPL(mark_tsc_unstable); 1222 1223 static void __init tsc_disable_clocksource_watchdog(void) 1224 { 1225 clocksource_tsc_early.flags &= ~CLOCK_SOURCE_MUST_VERIFY; 1226 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY; 1227 } 1228 1229 bool tsc_clocksource_watchdog_disabled(void) 1230 { 1231 return !(clocksource_tsc.flags & CLOCK_SOURCE_MUST_VERIFY) && 1232 tsc_as_watchdog && !no_tsc_watchdog; 1233 } 1234 1235 static void __init check_system_tsc_reliable(void) 1236 { 1237 #if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC) 1238 if (is_geode_lx()) { 1239 /* RTSC counts during suspend */ 1240 #define RTSC_SUSP 0x100 1241 unsigned long res_low, res_high; 1242 1243 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high); 1244 /* Geode_LX - the OLPC CPU has a very reliable TSC */ 1245 if (res_low & RTSC_SUSP) 1246 tsc_clocksource_reliable = 1; 1247 } 1248 #endif 1249 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) 1250 tsc_clocksource_reliable = 1; 1251 1252 /* 1253 * Disable the clocksource watchdog when the system has: 1254 * - TSC running at constant frequency 1255 * - TSC which does not stop in C-States 1256 * - the TSC_ADJUST register which allows to detect even minimal 1257 * modifications 1258 * - not more than four packages 1259 */ 1260 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC) && 1261 boot_cpu_has(X86_FEATURE_NONSTOP_TSC) && 1262 boot_cpu_has(X86_FEATURE_TSC_ADJUST) && 1263 topology_max_packages() <= 4) 1264 tsc_disable_clocksource_watchdog(); 1265 } 1266 1267 /* 1268 * Make an educated guess if the TSC is trustworthy and synchronized 1269 * over all CPUs. 1270 */ 1271 int unsynchronized_tsc(void) 1272 { 1273 if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_unstable) 1274 return 1; 1275 1276 #ifdef CONFIG_SMP 1277 if (apic_is_clustered_box()) 1278 return 1; 1279 #endif 1280 1281 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 1282 return 0; 1283 1284 if (tsc_clocksource_reliable) 1285 return 0; 1286 /* 1287 * Intel systems are normally all synchronized. 1288 * Exceptions must mark TSC as unstable: 1289 */ 1290 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) { 1291 /* assume multi socket systems are not synchronized: */ 1292 if (topology_max_packages() > 1) 1293 return 1; 1294 } 1295 1296 return 0; 1297 } 1298 1299 static void tsc_refine_calibration_work(struct work_struct *work); 1300 static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work); 1301 /** 1302 * tsc_refine_calibration_work - Further refine tsc freq calibration 1303 * @work: ignored. 1304 * 1305 * This functions uses delayed work over a period of a 1306 * second to further refine the TSC freq value. Since this is 1307 * timer based, instead of loop based, we don't block the boot 1308 * process while this longer calibration is done. 1309 * 1310 * If there are any calibration anomalies (too many SMIs, etc), 1311 * or the refined calibration is off by 1% of the fast early 1312 * calibration, we throw out the new calibration and use the 1313 * early calibration. 1314 */ 1315 static void tsc_refine_calibration_work(struct work_struct *work) 1316 { 1317 static u64 tsc_start = ULLONG_MAX, ref_start; 1318 static int hpet; 1319 u64 tsc_stop, ref_stop, delta; 1320 unsigned long freq; 1321 int cpu; 1322 1323 /* Don't bother refining TSC on unstable systems */ 1324 if (tsc_unstable) 1325 goto unreg; 1326 1327 /* 1328 * Since the work is started early in boot, we may be 1329 * delayed the first time we expire. So set the workqueue 1330 * again once we know timers are working. 1331 */ 1332 if (tsc_start == ULLONG_MAX) { 1333 restart: 1334 /* 1335 * Only set hpet once, to avoid mixing hardware 1336 * if the hpet becomes enabled later. 1337 */ 1338 hpet = is_hpet_enabled(); 1339 tsc_start = tsc_read_refs(&ref_start, hpet); 1340 schedule_delayed_work(&tsc_irqwork, HZ); 1341 return; 1342 } 1343 1344 tsc_stop = tsc_read_refs(&ref_stop, hpet); 1345 1346 /* hpet or pmtimer available ? */ 1347 if (ref_start == ref_stop) 1348 goto out; 1349 1350 /* Check, whether the sampling was disturbed */ 1351 if (tsc_stop == ULLONG_MAX) 1352 goto restart; 1353 1354 delta = tsc_stop - tsc_start; 1355 delta *= 1000000LL; 1356 if (hpet) 1357 freq = calc_hpet_ref(delta, ref_start, ref_stop); 1358 else 1359 freq = calc_pmtimer_ref(delta, ref_start, ref_stop); 1360 1361 /* Will hit this only if tsc_force_recalibrate has been set */ 1362 if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) { 1363 1364 /* Warn if the deviation exceeds 500 ppm */ 1365 if (abs(tsc_khz - freq) > (tsc_khz >> 11)) { 1366 pr_warn("Warning: TSC freq calibrated by CPUID/MSR differs from what is calibrated by HW timer, please check with vendor!!\n"); 1367 pr_info("Previous calibrated TSC freq:\t %lu.%03lu MHz\n", 1368 (unsigned long)tsc_khz / 1000, 1369 (unsigned long)tsc_khz % 1000); 1370 } 1371 1372 pr_info("TSC freq recalibrated by [%s]:\t %lu.%03lu MHz\n", 1373 hpet ? "HPET" : "PM_TIMER", 1374 (unsigned long)freq / 1000, 1375 (unsigned long)freq % 1000); 1376 1377 return; 1378 } 1379 1380 /* Make sure we're within 1% */ 1381 if (abs(tsc_khz - freq) > tsc_khz/100) 1382 goto out; 1383 1384 tsc_khz = freq; 1385 pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n", 1386 (unsigned long)tsc_khz / 1000, 1387 (unsigned long)tsc_khz % 1000); 1388 1389 /* Inform the TSC deadline clockevent devices about the recalibration */ 1390 lapic_update_tsc_freq(); 1391 1392 /* Update the sched_clock() rate to match the clocksource one */ 1393 for_each_possible_cpu(cpu) 1394 set_cyc2ns_scale(tsc_khz, cpu, tsc_stop); 1395 1396 out: 1397 if (tsc_unstable) 1398 goto unreg; 1399 1400 if (boot_cpu_has(X86_FEATURE_ART)) { 1401 have_art = true; 1402 clocksource_tsc.base = &art_base_clk; 1403 } 1404 clocksource_register_khz(&clocksource_tsc, tsc_khz); 1405 unreg: 1406 clocksource_unregister(&clocksource_tsc_early); 1407 } 1408 1409 1410 static int __init init_tsc_clocksource(void) 1411 { 1412 if (!boot_cpu_has(X86_FEATURE_TSC) || !tsc_khz) 1413 return 0; 1414 1415 if (tsc_unstable) { 1416 clocksource_unregister(&clocksource_tsc_early); 1417 return 0; 1418 } 1419 1420 if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3)) 1421 clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP; 1422 1423 /* 1424 * When TSC frequency is known (retrieved via MSR or CPUID), we skip 1425 * the refined calibration and directly register it as a clocksource. 1426 */ 1427 if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) { 1428 if (boot_cpu_has(X86_FEATURE_ART)) { 1429 have_art = true; 1430 clocksource_tsc.base = &art_base_clk; 1431 } 1432 clocksource_register_khz(&clocksource_tsc, tsc_khz); 1433 clocksource_unregister(&clocksource_tsc_early); 1434 1435 if (!tsc_force_recalibrate) 1436 return 0; 1437 } 1438 1439 schedule_delayed_work(&tsc_irqwork, 0); 1440 return 0; 1441 } 1442 /* 1443 * We use device_initcall here, to ensure we run after the hpet 1444 * is fully initialized, which may occur at fs_initcall time. 1445 */ 1446 device_initcall(init_tsc_clocksource); 1447 1448 static bool __init determine_cpu_tsc_frequencies(bool early) 1449 { 1450 /* Make sure that cpu and tsc are not already calibrated */ 1451 WARN_ON(cpu_khz || tsc_khz); 1452 1453 if (early) { 1454 cpu_khz = x86_platform.calibrate_cpu(); 1455 if (tsc_early_khz) { 1456 tsc_khz = tsc_early_khz; 1457 } else { 1458 tsc_khz = x86_platform.calibrate_tsc(); 1459 clocksource_tsc.freq_khz = tsc_khz; 1460 } 1461 } else { 1462 /* We should not be here with non-native cpu calibration */ 1463 WARN_ON(x86_platform.calibrate_cpu != native_calibrate_cpu); 1464 cpu_khz = pit_hpet_ptimer_calibrate_cpu(); 1465 } 1466 1467 /* 1468 * Trust non-zero tsc_khz as authoritative, 1469 * and use it to sanity check cpu_khz, 1470 * which will be off if system timer is off. 1471 */ 1472 if (tsc_khz == 0) 1473 tsc_khz = cpu_khz; 1474 else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz) 1475 cpu_khz = tsc_khz; 1476 1477 if (tsc_khz == 0) 1478 return false; 1479 1480 pr_info("Detected %lu.%03lu MHz processor\n", 1481 (unsigned long)cpu_khz / KHZ, 1482 (unsigned long)cpu_khz % KHZ); 1483 1484 if (cpu_khz != tsc_khz) { 1485 pr_info("Detected %lu.%03lu MHz TSC", 1486 (unsigned long)tsc_khz / KHZ, 1487 (unsigned long)tsc_khz % KHZ); 1488 } 1489 return true; 1490 } 1491 1492 static unsigned long __init get_loops_per_jiffy(void) 1493 { 1494 u64 lpj = (u64)tsc_khz * KHZ; 1495 1496 do_div(lpj, HZ); 1497 return lpj; 1498 } 1499 1500 static void __init tsc_enable_sched_clock(void) 1501 { 1502 loops_per_jiffy = get_loops_per_jiffy(); 1503 use_tsc_delay(); 1504 1505 /* Sanitize TSC ADJUST before cyc2ns gets initialized */ 1506 tsc_store_and_check_tsc_adjust(true); 1507 cyc2ns_init_boot_cpu(); 1508 static_branch_enable(&__use_tsc); 1509 } 1510 1511 void __init tsc_early_init(void) 1512 { 1513 if (!boot_cpu_has(X86_FEATURE_TSC)) 1514 return; 1515 /* Don't change UV TSC multi-chassis synchronization */ 1516 if (is_early_uv_system()) 1517 return; 1518 1519 snp_secure_tsc_init(); 1520 1521 if (!determine_cpu_tsc_frequencies(true)) 1522 return; 1523 tsc_enable_sched_clock(); 1524 } 1525 1526 void __init tsc_init(void) 1527 { 1528 if (!cpu_feature_enabled(X86_FEATURE_TSC)) { 1529 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 1530 return; 1531 } 1532 1533 /* 1534 * native_calibrate_cpu_early can only calibrate using methods that are 1535 * available early in boot. 1536 */ 1537 if (x86_platform.calibrate_cpu == native_calibrate_cpu_early) 1538 x86_platform.calibrate_cpu = native_calibrate_cpu; 1539 1540 if (!tsc_khz) { 1541 /* We failed to determine frequencies earlier, try again */ 1542 if (!determine_cpu_tsc_frequencies(false)) { 1543 mark_tsc_unstable("could not calculate TSC khz"); 1544 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 1545 return; 1546 } 1547 tsc_enable_sched_clock(); 1548 } 1549 1550 cyc2ns_init_secondary_cpus(); 1551 1552 if (!no_sched_irq_time) 1553 enable_sched_clock_irqtime(); 1554 1555 lpj_fine = get_loops_per_jiffy(); 1556 1557 check_system_tsc_reliable(); 1558 1559 if (unsynchronized_tsc()) { 1560 mark_tsc_unstable("TSCs unsynchronized"); 1561 return; 1562 } 1563 1564 if (tsc_clocksource_reliable || no_tsc_watchdog) 1565 tsc_disable_clocksource_watchdog(); 1566 1567 clocksource_register_khz(&clocksource_tsc_early, tsc_khz); 1568 detect_art(); 1569 } 1570 1571 #ifdef CONFIG_SMP 1572 /* 1573 * Check whether existing calibration data can be reused. 1574 */ 1575 unsigned long calibrate_delay_is_known(void) 1576 { 1577 int sibling, cpu = smp_processor_id(); 1578 int constant_tsc = cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC); 1579 const struct cpumask *mask = topology_core_cpumask(cpu); 1580 1581 /* 1582 * If TSC has constant frequency and TSC is synchronized across 1583 * sockets then reuse CPU0 calibration. 1584 */ 1585 if (constant_tsc && !tsc_unstable) 1586 return cpu_data(0).loops_per_jiffy; 1587 1588 /* 1589 * If TSC has constant frequency and TSC is not synchronized across 1590 * sockets and this is not the first CPU in the socket, then reuse 1591 * the calibration value of an already online CPU on that socket. 1592 * 1593 * This assumes that CONSTANT_TSC is consistent for all CPUs in a 1594 * socket. 1595 */ 1596 if (!constant_tsc || !mask) 1597 return 0; 1598 1599 sibling = cpumask_any_but(mask, cpu); 1600 if (sibling < nr_cpu_ids) 1601 return cpu_data(sibling).loops_per_jiffy; 1602 return 0; 1603 } 1604 #endif 1605