1 // SPDX-License-Identifier: GPL-2.0-only 2 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 3 4 #include <linux/kernel.h> 5 #include <linux/sched.h> 6 #include <linux/sched/clock.h> 7 #include <linux/init.h> 8 #include <linux/export.h> 9 #include <linux/timer.h> 10 #include <linux/acpi_pmtmr.h> 11 #include <linux/cpufreq.h> 12 #include <linux/delay.h> 13 #include <linux/clocksource.h> 14 #include <linux/percpu.h> 15 #include <linux/timex.h> 16 #include <linux/static_key.h> 17 #include <linux/static_call.h> 18 19 #include <asm/hpet.h> 20 #include <asm/timer.h> 21 #include <asm/vgtod.h> 22 #include <asm/time.h> 23 #include <asm/delay.h> 24 #include <asm/hypervisor.h> 25 #include <asm/nmi.h> 26 #include <asm/x86_init.h> 27 #include <asm/geode.h> 28 #include <asm/apic.h> 29 #include <asm/cpu_device_id.h> 30 #include <asm/i8259.h> 31 #include <asm/topology.h> 32 #include <asm/uv/uv.h> 33 34 unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */ 35 EXPORT_SYMBOL(cpu_khz); 36 37 unsigned int __read_mostly tsc_khz; 38 EXPORT_SYMBOL(tsc_khz); 39 40 #define KHZ 1000 41 42 /* 43 * TSC can be unstable due to cpufreq or due to unsynced TSCs 44 */ 45 static int __read_mostly tsc_unstable; 46 static unsigned int __initdata tsc_early_khz; 47 48 static DEFINE_STATIC_KEY_FALSE_RO(__use_tsc); 49 50 int tsc_clocksource_reliable; 51 52 static int __read_mostly tsc_force_recalibrate; 53 54 static struct clocksource_base art_base_clk = { 55 .id = CSID_X86_ART, 56 }; 57 static bool have_art; 58 59 struct cyc2ns { 60 struct cyc2ns_data data[2]; /* 0 + 2*16 = 32 */ 61 seqcount_latch_t seq; /* 32 + 4 = 36 */ 62 63 }; /* fits one cacheline */ 64 65 static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns); 66 67 static int __init tsc_early_khz_setup(char *buf) 68 { 69 return kstrtouint(buf, 0, &tsc_early_khz); 70 } 71 early_param("tsc_early_khz", tsc_early_khz_setup); 72 73 __always_inline void __cyc2ns_read(struct cyc2ns_data *data) 74 { 75 int seq, idx; 76 77 do { 78 seq = this_cpu_read(cyc2ns.seq.seqcount.sequence); 79 idx = seq & 1; 80 81 data->cyc2ns_offset = this_cpu_read(cyc2ns.data[idx].cyc2ns_offset); 82 data->cyc2ns_mul = this_cpu_read(cyc2ns.data[idx].cyc2ns_mul); 83 data->cyc2ns_shift = this_cpu_read(cyc2ns.data[idx].cyc2ns_shift); 84 85 } while (unlikely(seq != this_cpu_read(cyc2ns.seq.seqcount.sequence))); 86 } 87 88 __always_inline void cyc2ns_read_begin(struct cyc2ns_data *data) 89 { 90 preempt_disable_notrace(); 91 __cyc2ns_read(data); 92 } 93 94 __always_inline void cyc2ns_read_end(void) 95 { 96 preempt_enable_notrace(); 97 } 98 99 /* 100 * Accelerators for sched_clock() 101 * convert from cycles(64bits) => nanoseconds (64bits) 102 * basic equation: 103 * ns = cycles / (freq / ns_per_sec) 104 * ns = cycles * (ns_per_sec / freq) 105 * ns = cycles * (10^9 / (cpu_khz * 10^3)) 106 * ns = cycles * (10^6 / cpu_khz) 107 * 108 * Then we use scaling math (suggested by george@mvista.com) to get: 109 * ns = cycles * (10^6 * SC / cpu_khz) / SC 110 * ns = cycles * cyc2ns_scale / SC 111 * 112 * And since SC is a constant power of two, we can convert the div 113 * into a shift. The larger SC is, the more accurate the conversion, but 114 * cyc2ns_scale needs to be a 32-bit value so that 32-bit multiplication 115 * (64-bit result) can be used. 116 * 117 * We can use khz divisor instead of mhz to keep a better precision. 118 * (mathieu.desnoyers@polymtl.ca) 119 * 120 * -johnstul@us.ibm.com "math is hard, lets go shopping!" 121 */ 122 123 static __always_inline unsigned long long __cycles_2_ns(unsigned long long cyc) 124 { 125 struct cyc2ns_data data; 126 unsigned long long ns; 127 128 __cyc2ns_read(&data); 129 130 ns = data.cyc2ns_offset; 131 ns += mul_u64_u32_shr(cyc, data.cyc2ns_mul, data.cyc2ns_shift); 132 133 return ns; 134 } 135 136 static __always_inline unsigned long long cycles_2_ns(unsigned long long cyc) 137 { 138 unsigned long long ns; 139 preempt_disable_notrace(); 140 ns = __cycles_2_ns(cyc); 141 preempt_enable_notrace(); 142 return ns; 143 } 144 145 static void __set_cyc2ns_scale(unsigned long khz, int cpu, unsigned long long tsc_now) 146 { 147 unsigned long long ns_now; 148 struct cyc2ns_data data; 149 struct cyc2ns *c2n; 150 151 ns_now = cycles_2_ns(tsc_now); 152 153 /* 154 * Compute a new multiplier as per the above comment and ensure our 155 * time function is continuous; see the comment near struct 156 * cyc2ns_data. 157 */ 158 clocks_calc_mult_shift(&data.cyc2ns_mul, &data.cyc2ns_shift, khz, 159 NSEC_PER_MSEC, 0); 160 161 /* 162 * cyc2ns_shift is exported via arch_perf_update_userpage() where it is 163 * not expected to be greater than 31 due to the original published 164 * conversion algorithm shifting a 32-bit value (now specifies a 64-bit 165 * value) - refer perf_event_mmap_page documentation in perf_event.h. 166 */ 167 if (data.cyc2ns_shift == 32) { 168 data.cyc2ns_shift = 31; 169 data.cyc2ns_mul >>= 1; 170 } 171 172 data.cyc2ns_offset = ns_now - 173 mul_u64_u32_shr(tsc_now, data.cyc2ns_mul, data.cyc2ns_shift); 174 175 c2n = per_cpu_ptr(&cyc2ns, cpu); 176 177 raw_write_seqcount_latch(&c2n->seq); 178 c2n->data[0] = data; 179 raw_write_seqcount_latch(&c2n->seq); 180 c2n->data[1] = data; 181 } 182 183 static void set_cyc2ns_scale(unsigned long khz, int cpu, unsigned long long tsc_now) 184 { 185 unsigned long flags; 186 187 local_irq_save(flags); 188 sched_clock_idle_sleep_event(); 189 190 if (khz) 191 __set_cyc2ns_scale(khz, cpu, tsc_now); 192 193 sched_clock_idle_wakeup_event(); 194 local_irq_restore(flags); 195 } 196 197 /* 198 * Initialize cyc2ns for boot cpu 199 */ 200 static void __init cyc2ns_init_boot_cpu(void) 201 { 202 struct cyc2ns *c2n = this_cpu_ptr(&cyc2ns); 203 204 seqcount_latch_init(&c2n->seq); 205 __set_cyc2ns_scale(tsc_khz, smp_processor_id(), rdtsc()); 206 } 207 208 /* 209 * Secondary CPUs do not run through tsc_init(), so set up 210 * all the scale factors for all CPUs, assuming the same 211 * speed as the bootup CPU. 212 */ 213 static void __init cyc2ns_init_secondary_cpus(void) 214 { 215 unsigned int cpu, this_cpu = smp_processor_id(); 216 struct cyc2ns *c2n = this_cpu_ptr(&cyc2ns); 217 struct cyc2ns_data *data = c2n->data; 218 219 for_each_possible_cpu(cpu) { 220 if (cpu != this_cpu) { 221 seqcount_latch_init(&c2n->seq); 222 c2n = per_cpu_ptr(&cyc2ns, cpu); 223 c2n->data[0] = data[0]; 224 c2n->data[1] = data[1]; 225 } 226 } 227 } 228 229 /* 230 * Scheduler clock - returns current time in nanosec units. 231 */ 232 noinstr u64 native_sched_clock(void) 233 { 234 if (static_branch_likely(&__use_tsc)) { 235 u64 tsc_now = rdtsc(); 236 237 /* return the value in ns */ 238 return __cycles_2_ns(tsc_now); 239 } 240 241 /* 242 * Fall back to jiffies if there's no TSC available: 243 * ( But note that we still use it if the TSC is marked 244 * unstable. We do this because unlike Time Of Day, 245 * the scheduler clock tolerates small errors and it's 246 * very important for it to be as fast as the platform 247 * can achieve it. ) 248 */ 249 250 /* No locking but a rare wrong value is not a big deal: */ 251 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ); 252 } 253 254 /* 255 * Generate a sched_clock if you already have a TSC value. 256 */ 257 u64 native_sched_clock_from_tsc(u64 tsc) 258 { 259 return cycles_2_ns(tsc); 260 } 261 262 /* We need to define a real function for sched_clock, to override the 263 weak default version */ 264 #ifdef CONFIG_PARAVIRT 265 noinstr u64 sched_clock_noinstr(void) 266 { 267 return paravirt_sched_clock(); 268 } 269 270 bool using_native_sched_clock(void) 271 { 272 return static_call_query(pv_sched_clock) == native_sched_clock; 273 } 274 #else 275 u64 sched_clock_noinstr(void) __attribute__((alias("native_sched_clock"))); 276 277 bool using_native_sched_clock(void) { return true; } 278 #endif 279 280 notrace u64 sched_clock(void) 281 { 282 u64 now; 283 preempt_disable_notrace(); 284 now = sched_clock_noinstr(); 285 preempt_enable_notrace(); 286 return now; 287 } 288 289 int check_tsc_unstable(void) 290 { 291 return tsc_unstable; 292 } 293 EXPORT_SYMBOL_GPL(check_tsc_unstable); 294 295 #ifdef CONFIG_X86_TSC 296 int __init notsc_setup(char *str) 297 { 298 mark_tsc_unstable("boot parameter notsc"); 299 return 1; 300 } 301 #else 302 /* 303 * disable flag for tsc. Takes effect by clearing the TSC cpu flag 304 * in cpu/common.c 305 */ 306 int __init notsc_setup(char *str) 307 { 308 setup_clear_cpu_cap(X86_FEATURE_TSC); 309 return 1; 310 } 311 #endif 312 313 __setup("notsc", notsc_setup); 314 315 static int no_sched_irq_time; 316 static int no_tsc_watchdog; 317 static int tsc_as_watchdog; 318 319 static int __init tsc_setup(char *str) 320 { 321 if (!strcmp(str, "reliable")) 322 tsc_clocksource_reliable = 1; 323 if (!strncmp(str, "noirqtime", 9)) 324 no_sched_irq_time = 1; 325 if (!strcmp(str, "unstable")) 326 mark_tsc_unstable("boot parameter"); 327 if (!strcmp(str, "nowatchdog")) { 328 no_tsc_watchdog = 1; 329 if (tsc_as_watchdog) 330 pr_alert("%s: Overriding earlier tsc=watchdog with tsc=nowatchdog\n", 331 __func__); 332 tsc_as_watchdog = 0; 333 } 334 if (!strcmp(str, "recalibrate")) 335 tsc_force_recalibrate = 1; 336 if (!strcmp(str, "watchdog")) { 337 if (no_tsc_watchdog) 338 pr_alert("%s: tsc=watchdog overridden by earlier tsc=nowatchdog\n", 339 __func__); 340 else 341 tsc_as_watchdog = 1; 342 } 343 return 1; 344 } 345 346 __setup("tsc=", tsc_setup); 347 348 #define MAX_RETRIES 5 349 #define TSC_DEFAULT_THRESHOLD 0x20000 350 351 /* 352 * Read TSC and the reference counters. Take care of any disturbances 353 */ 354 static u64 tsc_read_refs(u64 *p, int hpet) 355 { 356 u64 t1, t2; 357 u64 thresh = tsc_khz ? tsc_khz >> 5 : TSC_DEFAULT_THRESHOLD; 358 int i; 359 360 for (i = 0; i < MAX_RETRIES; i++) { 361 t1 = get_cycles(); 362 if (hpet) 363 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF; 364 else 365 *p = acpi_pm_read_early(); 366 t2 = get_cycles(); 367 if ((t2 - t1) < thresh) 368 return t2; 369 } 370 return ULLONG_MAX; 371 } 372 373 /* 374 * Calculate the TSC frequency from HPET reference 375 */ 376 static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2) 377 { 378 u64 tmp; 379 380 if (hpet2 < hpet1) 381 hpet2 += 0x100000000ULL; 382 hpet2 -= hpet1; 383 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD)); 384 do_div(tmp, 1000000); 385 deltatsc = div64_u64(deltatsc, tmp); 386 387 return (unsigned long) deltatsc; 388 } 389 390 /* 391 * Calculate the TSC frequency from PMTimer reference 392 */ 393 static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2) 394 { 395 u64 tmp; 396 397 if (!pm1 && !pm2) 398 return ULONG_MAX; 399 400 if (pm2 < pm1) 401 pm2 += (u64)ACPI_PM_OVRRUN; 402 pm2 -= pm1; 403 tmp = pm2 * 1000000000LL; 404 do_div(tmp, PMTMR_TICKS_PER_SEC); 405 do_div(deltatsc, tmp); 406 407 return (unsigned long) deltatsc; 408 } 409 410 #define CAL_MS 10 411 #define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS)) 412 #define CAL_PIT_LOOPS 1000 413 414 #define CAL2_MS 50 415 #define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS)) 416 #define CAL2_PIT_LOOPS 5000 417 418 419 /* 420 * Try to calibrate the TSC against the Programmable 421 * Interrupt Timer and return the frequency of the TSC 422 * in kHz. 423 * 424 * Return ULONG_MAX on failure to calibrate. 425 */ 426 static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin) 427 { 428 u64 tsc, t1, t2, delta; 429 unsigned long tscmin, tscmax; 430 int pitcnt; 431 432 if (!has_legacy_pic()) { 433 /* 434 * Relies on tsc_early_delay_calibrate() to have given us semi 435 * usable udelay(), wait for the same 50ms we would have with 436 * the PIT loop below. 437 */ 438 udelay(10 * USEC_PER_MSEC); 439 udelay(10 * USEC_PER_MSEC); 440 udelay(10 * USEC_PER_MSEC); 441 udelay(10 * USEC_PER_MSEC); 442 udelay(10 * USEC_PER_MSEC); 443 return ULONG_MAX; 444 } 445 446 /* Set the Gate high, disable speaker */ 447 outb((inb(0x61) & ~0x02) | 0x01, 0x61); 448 449 /* 450 * Setup CTC channel 2* for mode 0, (interrupt on terminal 451 * count mode), binary count. Set the latch register to 50ms 452 * (LSB then MSB) to begin countdown. 453 */ 454 outb(0xb0, 0x43); 455 outb(latch & 0xff, 0x42); 456 outb(latch >> 8, 0x42); 457 458 tsc = t1 = t2 = get_cycles(); 459 460 pitcnt = 0; 461 tscmax = 0; 462 tscmin = ULONG_MAX; 463 while ((inb(0x61) & 0x20) == 0) { 464 t2 = get_cycles(); 465 delta = t2 - tsc; 466 tsc = t2; 467 if ((unsigned long) delta < tscmin) 468 tscmin = (unsigned int) delta; 469 if ((unsigned long) delta > tscmax) 470 tscmax = (unsigned int) delta; 471 pitcnt++; 472 } 473 474 /* 475 * Sanity checks: 476 * 477 * If we were not able to read the PIT more than loopmin 478 * times, then we have been hit by a massive SMI 479 * 480 * If the maximum is 10 times larger than the minimum, 481 * then we got hit by an SMI as well. 482 */ 483 if (pitcnt < loopmin || tscmax > 10 * tscmin) 484 return ULONG_MAX; 485 486 /* Calculate the PIT value */ 487 delta = t2 - t1; 488 do_div(delta, ms); 489 return delta; 490 } 491 492 /* 493 * This reads the current MSB of the PIT counter, and 494 * checks if we are running on sufficiently fast and 495 * non-virtualized hardware. 496 * 497 * Our expectations are: 498 * 499 * - the PIT is running at roughly 1.19MHz 500 * 501 * - each IO is going to take about 1us on real hardware, 502 * but we allow it to be much faster (by a factor of 10) or 503 * _slightly_ slower (ie we allow up to a 2us read+counter 504 * update - anything else implies a unacceptably slow CPU 505 * or PIT for the fast calibration to work. 506 * 507 * - with 256 PIT ticks to read the value, we have 214us to 508 * see the same MSB (and overhead like doing a single TSC 509 * read per MSB value etc). 510 * 511 * - We're doing 2 reads per loop (LSB, MSB), and we expect 512 * them each to take about a microsecond on real hardware. 513 * So we expect a count value of around 100. But we'll be 514 * generous, and accept anything over 50. 515 * 516 * - if the PIT is stuck, and we see *many* more reads, we 517 * return early (and the next caller of pit_expect_msb() 518 * then consider it a failure when they don't see the 519 * next expected value). 520 * 521 * These expectations mean that we know that we have seen the 522 * transition from one expected value to another with a fairly 523 * high accuracy, and we didn't miss any events. We can thus 524 * use the TSC value at the transitions to calculate a pretty 525 * good value for the TSC frequency. 526 */ 527 static inline int pit_verify_msb(unsigned char val) 528 { 529 /* Ignore LSB */ 530 inb(0x42); 531 return inb(0x42) == val; 532 } 533 534 static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap) 535 { 536 int count; 537 u64 tsc = 0, prev_tsc = 0; 538 539 for (count = 0; count < 50000; count++) { 540 if (!pit_verify_msb(val)) 541 break; 542 prev_tsc = tsc; 543 tsc = get_cycles(); 544 } 545 *deltap = get_cycles() - prev_tsc; 546 *tscp = tsc; 547 548 /* 549 * We require _some_ success, but the quality control 550 * will be based on the error terms on the TSC values. 551 */ 552 return count > 5; 553 } 554 555 /* 556 * How many MSB values do we want to see? We aim for 557 * a maximum error rate of 500ppm (in practice the 558 * real error is much smaller), but refuse to spend 559 * more than 50ms on it. 560 */ 561 #define MAX_QUICK_PIT_MS 50 562 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) 563 564 static unsigned long quick_pit_calibrate(void) 565 { 566 int i; 567 u64 tsc, delta; 568 unsigned long d1, d2; 569 570 if (!has_legacy_pic()) 571 return 0; 572 573 /* Set the Gate high, disable speaker */ 574 outb((inb(0x61) & ~0x02) | 0x01, 0x61); 575 576 /* 577 * Counter 2, mode 0 (one-shot), binary count 578 * 579 * NOTE! Mode 2 decrements by two (and then the 580 * output is flipped each time, giving the same 581 * final output frequency as a decrement-by-one), 582 * so mode 0 is much better when looking at the 583 * individual counts. 584 */ 585 outb(0xb0, 0x43); 586 587 /* Start at 0xffff */ 588 outb(0xff, 0x42); 589 outb(0xff, 0x42); 590 591 /* 592 * The PIT starts counting at the next edge, so we 593 * need to delay for a microsecond. The easiest way 594 * to do that is to just read back the 16-bit counter 595 * once from the PIT. 596 */ 597 pit_verify_msb(0); 598 599 if (pit_expect_msb(0xff, &tsc, &d1)) { 600 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) { 601 if (!pit_expect_msb(0xff-i, &delta, &d2)) 602 break; 603 604 delta -= tsc; 605 606 /* 607 * Extrapolate the error and fail fast if the error will 608 * never be below 500 ppm. 609 */ 610 if (i == 1 && 611 d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11) 612 return 0; 613 614 /* 615 * Iterate until the error is less than 500 ppm 616 */ 617 if (d1+d2 >= delta >> 11) 618 continue; 619 620 /* 621 * Check the PIT one more time to verify that 622 * all TSC reads were stable wrt the PIT. 623 * 624 * This also guarantees serialization of the 625 * last cycle read ('d2') in pit_expect_msb. 626 */ 627 if (!pit_verify_msb(0xfe - i)) 628 break; 629 goto success; 630 } 631 } 632 pr_info("Fast TSC calibration failed\n"); 633 return 0; 634 635 success: 636 /* 637 * Ok, if we get here, then we've seen the 638 * MSB of the PIT decrement 'i' times, and the 639 * error has shrunk to less than 500 ppm. 640 * 641 * As a result, we can depend on there not being 642 * any odd delays anywhere, and the TSC reads are 643 * reliable (within the error). 644 * 645 * kHz = ticks / time-in-seconds / 1000; 646 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000 647 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000) 648 */ 649 delta *= PIT_TICK_RATE; 650 do_div(delta, i*256*1000); 651 pr_info("Fast TSC calibration using PIT\n"); 652 return delta; 653 } 654 655 /** 656 * native_calibrate_tsc - determine TSC frequency 657 * Determine TSC frequency via CPUID, else return 0. 658 */ 659 unsigned long native_calibrate_tsc(void) 660 { 661 unsigned int eax_denominator, ebx_numerator, ecx_hz, edx; 662 unsigned int crystal_khz; 663 664 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 665 return 0; 666 667 if (boot_cpu_data.cpuid_level < 0x15) 668 return 0; 669 670 eax_denominator = ebx_numerator = ecx_hz = edx = 0; 671 672 /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */ 673 cpuid(0x15, &eax_denominator, &ebx_numerator, &ecx_hz, &edx); 674 675 if (ebx_numerator == 0 || eax_denominator == 0) 676 return 0; 677 678 crystal_khz = ecx_hz / 1000; 679 680 /* 681 * Denverton SoCs don't report crystal clock, and also don't support 682 * CPUID.0x16 for the calculation below, so hardcode the 25MHz crystal 683 * clock. 684 */ 685 if (crystal_khz == 0 && 686 boot_cpu_data.x86_vfm == INTEL_ATOM_GOLDMONT_D) 687 crystal_khz = 25000; 688 689 /* 690 * TSC frequency reported directly by CPUID is a "hardware reported" 691 * frequency and is the most accurate one so far we have. This 692 * is considered a known frequency. 693 */ 694 if (crystal_khz != 0) 695 setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ); 696 697 /* 698 * Some Intel SoCs like Skylake and Kabylake don't report the crystal 699 * clock, but we can easily calculate it to a high degree of accuracy 700 * by considering the crystal ratio and the CPU speed. 701 */ 702 if (crystal_khz == 0 && boot_cpu_data.cpuid_level >= 0x16) { 703 unsigned int eax_base_mhz, ebx, ecx, edx; 704 705 cpuid(0x16, &eax_base_mhz, &ebx, &ecx, &edx); 706 crystal_khz = eax_base_mhz * 1000 * 707 eax_denominator / ebx_numerator; 708 } 709 710 if (crystal_khz == 0) 711 return 0; 712 713 /* 714 * For Atom SoCs TSC is the only reliable clocksource. 715 * Mark TSC reliable so no watchdog on it. 716 */ 717 if (boot_cpu_data.x86_vfm == INTEL_ATOM_GOLDMONT) 718 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); 719 720 #ifdef CONFIG_X86_LOCAL_APIC 721 /* 722 * The local APIC appears to be fed by the core crystal clock 723 * (which sounds entirely sensible). We can set the global 724 * lapic_timer_period here to avoid having to calibrate the APIC 725 * timer later. 726 */ 727 lapic_timer_period = crystal_khz * 1000 / HZ; 728 #endif 729 730 return crystal_khz * ebx_numerator / eax_denominator; 731 } 732 733 static unsigned long cpu_khz_from_cpuid(void) 734 { 735 unsigned int eax_base_mhz, ebx_max_mhz, ecx_bus_mhz, edx; 736 737 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 738 return 0; 739 740 if (boot_cpu_data.cpuid_level < 0x16) 741 return 0; 742 743 eax_base_mhz = ebx_max_mhz = ecx_bus_mhz = edx = 0; 744 745 cpuid(0x16, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx); 746 747 return eax_base_mhz * 1000; 748 } 749 750 /* 751 * calibrate cpu using pit, hpet, and ptimer methods. They are available 752 * later in boot after acpi is initialized. 753 */ 754 static unsigned long pit_hpet_ptimer_calibrate_cpu(void) 755 { 756 u64 tsc1, tsc2, delta, ref1, ref2; 757 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX; 758 unsigned long flags, latch, ms; 759 int hpet = is_hpet_enabled(), i, loopmin; 760 761 /* 762 * Run 5 calibration loops to get the lowest frequency value 763 * (the best estimate). We use two different calibration modes 764 * here: 765 * 766 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and 767 * load a timeout of 50ms. We read the time right after we 768 * started the timer and wait until the PIT count down reaches 769 * zero. In each wait loop iteration we read the TSC and check 770 * the delta to the previous read. We keep track of the min 771 * and max values of that delta. The delta is mostly defined 772 * by the IO time of the PIT access, so we can detect when 773 * any disturbance happened between the two reads. If the 774 * maximum time is significantly larger than the minimum time, 775 * then we discard the result and have another try. 776 * 777 * 2) Reference counter. If available we use the HPET or the 778 * PMTIMER as a reference to check the sanity of that value. 779 * We use separate TSC readouts and check inside of the 780 * reference read for any possible disturbance. We discard 781 * disturbed values here as well. We do that around the PIT 782 * calibration delay loop as we have to wait for a certain 783 * amount of time anyway. 784 */ 785 786 /* Preset PIT loop values */ 787 latch = CAL_LATCH; 788 ms = CAL_MS; 789 loopmin = CAL_PIT_LOOPS; 790 791 for (i = 0; i < 3; i++) { 792 unsigned long tsc_pit_khz; 793 794 /* 795 * Read the start value and the reference count of 796 * hpet/pmtimer when available. Then do the PIT 797 * calibration, which will take at least 50ms, and 798 * read the end value. 799 */ 800 local_irq_save(flags); 801 tsc1 = tsc_read_refs(&ref1, hpet); 802 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin); 803 tsc2 = tsc_read_refs(&ref2, hpet); 804 local_irq_restore(flags); 805 806 /* Pick the lowest PIT TSC calibration so far */ 807 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz); 808 809 /* hpet or pmtimer available ? */ 810 if (ref1 == ref2) 811 continue; 812 813 /* Check, whether the sampling was disturbed */ 814 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX) 815 continue; 816 817 tsc2 = (tsc2 - tsc1) * 1000000LL; 818 if (hpet) 819 tsc2 = calc_hpet_ref(tsc2, ref1, ref2); 820 else 821 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2); 822 823 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2); 824 825 /* Check the reference deviation */ 826 delta = ((u64) tsc_pit_min) * 100; 827 do_div(delta, tsc_ref_min); 828 829 /* 830 * If both calibration results are inside a 10% window 831 * then we can be sure, that the calibration 832 * succeeded. We break out of the loop right away. We 833 * use the reference value, as it is more precise. 834 */ 835 if (delta >= 90 && delta <= 110) { 836 pr_info("PIT calibration matches %s. %d loops\n", 837 hpet ? "HPET" : "PMTIMER", i + 1); 838 return tsc_ref_min; 839 } 840 841 /* 842 * Check whether PIT failed more than once. This 843 * happens in virtualized environments. We need to 844 * give the virtual PC a slightly longer timeframe for 845 * the HPET/PMTIMER to make the result precise. 846 */ 847 if (i == 1 && tsc_pit_min == ULONG_MAX) { 848 latch = CAL2_LATCH; 849 ms = CAL2_MS; 850 loopmin = CAL2_PIT_LOOPS; 851 } 852 } 853 854 /* 855 * Now check the results. 856 */ 857 if (tsc_pit_min == ULONG_MAX) { 858 /* PIT gave no useful value */ 859 pr_warn("Unable to calibrate against PIT\n"); 860 861 /* We don't have an alternative source, disable TSC */ 862 if (!hpet && !ref1 && !ref2) { 863 pr_notice("No reference (HPET/PMTIMER) available\n"); 864 return 0; 865 } 866 867 /* The alternative source failed as well, disable TSC */ 868 if (tsc_ref_min == ULONG_MAX) { 869 pr_warn("HPET/PMTIMER calibration failed\n"); 870 return 0; 871 } 872 873 /* Use the alternative source */ 874 pr_info("using %s reference calibration\n", 875 hpet ? "HPET" : "PMTIMER"); 876 877 return tsc_ref_min; 878 } 879 880 /* We don't have an alternative source, use the PIT calibration value */ 881 if (!hpet && !ref1 && !ref2) { 882 pr_info("Using PIT calibration value\n"); 883 return tsc_pit_min; 884 } 885 886 /* The alternative source failed, use the PIT calibration value */ 887 if (tsc_ref_min == ULONG_MAX) { 888 pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n"); 889 return tsc_pit_min; 890 } 891 892 /* 893 * The calibration values differ too much. In doubt, we use 894 * the PIT value as we know that there are PMTIMERs around 895 * running at double speed. At least we let the user know: 896 */ 897 pr_warn("PIT calibration deviates from %s: %lu %lu\n", 898 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min); 899 pr_info("Using PIT calibration value\n"); 900 return tsc_pit_min; 901 } 902 903 /** 904 * native_calibrate_cpu_early - can calibrate the cpu early in boot 905 */ 906 unsigned long native_calibrate_cpu_early(void) 907 { 908 unsigned long flags, fast_calibrate = cpu_khz_from_cpuid(); 909 910 if (!fast_calibrate) 911 fast_calibrate = cpu_khz_from_msr(); 912 if (!fast_calibrate) { 913 local_irq_save(flags); 914 fast_calibrate = quick_pit_calibrate(); 915 local_irq_restore(flags); 916 } 917 return fast_calibrate; 918 } 919 920 921 /** 922 * native_calibrate_cpu - calibrate the cpu 923 */ 924 static unsigned long native_calibrate_cpu(void) 925 { 926 unsigned long tsc_freq = native_calibrate_cpu_early(); 927 928 if (!tsc_freq) 929 tsc_freq = pit_hpet_ptimer_calibrate_cpu(); 930 931 return tsc_freq; 932 } 933 934 void recalibrate_cpu_khz(void) 935 { 936 #ifndef CONFIG_SMP 937 unsigned long cpu_khz_old = cpu_khz; 938 939 if (!boot_cpu_has(X86_FEATURE_TSC)) 940 return; 941 942 cpu_khz = x86_platform.calibrate_cpu(); 943 tsc_khz = x86_platform.calibrate_tsc(); 944 if (tsc_khz == 0) 945 tsc_khz = cpu_khz; 946 else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz) 947 cpu_khz = tsc_khz; 948 cpu_data(0).loops_per_jiffy = cpufreq_scale(cpu_data(0).loops_per_jiffy, 949 cpu_khz_old, cpu_khz); 950 #endif 951 } 952 EXPORT_SYMBOL_GPL(recalibrate_cpu_khz); 953 954 955 static unsigned long long cyc2ns_suspend; 956 957 void tsc_save_sched_clock_state(void) 958 { 959 if (!sched_clock_stable()) 960 return; 961 962 cyc2ns_suspend = sched_clock(); 963 } 964 965 /* 966 * Even on processors with invariant TSC, TSC gets reset in some the 967 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to 968 * arbitrary value (still sync'd across cpu's) during resume from such sleep 969 * states. To cope up with this, recompute the cyc2ns_offset for each cpu so 970 * that sched_clock() continues from the point where it was left off during 971 * suspend. 972 */ 973 void tsc_restore_sched_clock_state(void) 974 { 975 unsigned long long offset; 976 unsigned long flags; 977 int cpu; 978 979 if (!sched_clock_stable()) 980 return; 981 982 local_irq_save(flags); 983 984 /* 985 * We're coming out of suspend, there's no concurrency yet; don't 986 * bother being nice about the RCU stuff, just write to both 987 * data fields. 988 */ 989 990 this_cpu_write(cyc2ns.data[0].cyc2ns_offset, 0); 991 this_cpu_write(cyc2ns.data[1].cyc2ns_offset, 0); 992 993 offset = cyc2ns_suspend - sched_clock(); 994 995 for_each_possible_cpu(cpu) { 996 per_cpu(cyc2ns.data[0].cyc2ns_offset, cpu) = offset; 997 per_cpu(cyc2ns.data[1].cyc2ns_offset, cpu) = offset; 998 } 999 1000 local_irq_restore(flags); 1001 } 1002 1003 #ifdef CONFIG_CPU_FREQ 1004 /* 1005 * Frequency scaling support. Adjust the TSC based timer when the CPU frequency 1006 * changes. 1007 * 1008 * NOTE: On SMP the situation is not fixable in general, so simply mark the TSC 1009 * as unstable and give up in those cases. 1010 * 1011 * Should fix up last_tsc too. Currently gettimeofday in the 1012 * first tick after the change will be slightly wrong. 1013 */ 1014 1015 static unsigned int ref_freq; 1016 static unsigned long loops_per_jiffy_ref; 1017 static unsigned long tsc_khz_ref; 1018 1019 static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 1020 void *data) 1021 { 1022 struct cpufreq_freqs *freq = data; 1023 1024 if (num_online_cpus() > 1) { 1025 mark_tsc_unstable("cpufreq changes on SMP"); 1026 return 0; 1027 } 1028 1029 if (!ref_freq) { 1030 ref_freq = freq->old; 1031 loops_per_jiffy_ref = boot_cpu_data.loops_per_jiffy; 1032 tsc_khz_ref = tsc_khz; 1033 } 1034 1035 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || 1036 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) { 1037 boot_cpu_data.loops_per_jiffy = 1038 cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new); 1039 1040 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new); 1041 if (!(freq->flags & CPUFREQ_CONST_LOOPS)) 1042 mark_tsc_unstable("cpufreq changes"); 1043 1044 set_cyc2ns_scale(tsc_khz, freq->policy->cpu, rdtsc()); 1045 } 1046 1047 return 0; 1048 } 1049 1050 static struct notifier_block time_cpufreq_notifier_block = { 1051 .notifier_call = time_cpufreq_notifier 1052 }; 1053 1054 static int __init cpufreq_register_tsc_scaling(void) 1055 { 1056 if (!boot_cpu_has(X86_FEATURE_TSC)) 1057 return 0; 1058 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 1059 return 0; 1060 cpufreq_register_notifier(&time_cpufreq_notifier_block, 1061 CPUFREQ_TRANSITION_NOTIFIER); 1062 return 0; 1063 } 1064 1065 core_initcall(cpufreq_register_tsc_scaling); 1066 1067 #endif /* CONFIG_CPU_FREQ */ 1068 1069 #define ART_CPUID_LEAF (0x15) 1070 #define ART_MIN_DENOMINATOR (1) 1071 1072 1073 /* 1074 * If ART is present detect the numerator:denominator to convert to TSC 1075 */ 1076 static void __init detect_art(void) 1077 { 1078 unsigned int unused; 1079 1080 if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF) 1081 return; 1082 1083 /* 1084 * Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required, 1085 * and the TSC counter resets must not occur asynchronously. 1086 */ 1087 if (boot_cpu_has(X86_FEATURE_HYPERVISOR) || 1088 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC) || 1089 !boot_cpu_has(X86_FEATURE_TSC_ADJUST) || 1090 tsc_async_resets) 1091 return; 1092 1093 cpuid(ART_CPUID_LEAF, &art_base_clk.denominator, 1094 &art_base_clk.numerator, &art_base_clk.freq_khz, &unused); 1095 1096 art_base_clk.freq_khz /= KHZ; 1097 if (art_base_clk.denominator < ART_MIN_DENOMINATOR) 1098 return; 1099 1100 rdmsrl(MSR_IA32_TSC_ADJUST, art_base_clk.offset); 1101 1102 /* Make this sticky over multiple CPU init calls */ 1103 setup_force_cpu_cap(X86_FEATURE_ART); 1104 } 1105 1106 1107 /* clocksource code */ 1108 1109 static void tsc_resume(struct clocksource *cs) 1110 { 1111 tsc_verify_tsc_adjust(true); 1112 } 1113 1114 /* 1115 * We used to compare the TSC to the cycle_last value in the clocksource 1116 * structure to avoid a nasty time-warp. This can be observed in a 1117 * very small window right after one CPU updated cycle_last under 1118 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which 1119 * is smaller than the cycle_last reference value due to a TSC which 1120 * is slightly behind. This delta is nowhere else observable, but in 1121 * that case it results in a forward time jump in the range of hours 1122 * due to the unsigned delta calculation of the time keeping core 1123 * code, which is necessary to support wrapping clocksources like pm 1124 * timer. 1125 * 1126 * This sanity check is now done in the core timekeeping code. 1127 * checking the result of read_tsc() - cycle_last for being negative. 1128 * That works because CLOCKSOURCE_MASK(64) does not mask out any bit. 1129 */ 1130 static u64 read_tsc(struct clocksource *cs) 1131 { 1132 return (u64)rdtsc_ordered(); 1133 } 1134 1135 static void tsc_cs_mark_unstable(struct clocksource *cs) 1136 { 1137 if (tsc_unstable) 1138 return; 1139 1140 tsc_unstable = 1; 1141 if (using_native_sched_clock()) 1142 clear_sched_clock_stable(); 1143 disable_sched_clock_irqtime(); 1144 pr_info("Marking TSC unstable due to clocksource watchdog\n"); 1145 } 1146 1147 static void tsc_cs_tick_stable(struct clocksource *cs) 1148 { 1149 if (tsc_unstable) 1150 return; 1151 1152 if (using_native_sched_clock()) 1153 sched_clock_tick_stable(); 1154 } 1155 1156 static int tsc_cs_enable(struct clocksource *cs) 1157 { 1158 vclocks_set_used(VDSO_CLOCKMODE_TSC); 1159 return 0; 1160 } 1161 1162 /* 1163 * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc() 1164 */ 1165 static struct clocksource clocksource_tsc_early = { 1166 .name = "tsc-early", 1167 .rating = 299, 1168 .uncertainty_margin = 32 * NSEC_PER_MSEC, 1169 .read = read_tsc, 1170 .mask = CLOCKSOURCE_MASK(64), 1171 .flags = CLOCK_SOURCE_IS_CONTINUOUS | 1172 CLOCK_SOURCE_MUST_VERIFY, 1173 .id = CSID_X86_TSC_EARLY, 1174 .vdso_clock_mode = VDSO_CLOCKMODE_TSC, 1175 .enable = tsc_cs_enable, 1176 .resume = tsc_resume, 1177 .mark_unstable = tsc_cs_mark_unstable, 1178 .tick_stable = tsc_cs_tick_stable, 1179 .list = LIST_HEAD_INIT(clocksource_tsc_early.list), 1180 }; 1181 1182 /* 1183 * Must mark VALID_FOR_HRES early such that when we unregister tsc_early 1184 * this one will immediately take over. We will only register if TSC has 1185 * been found good. 1186 */ 1187 static struct clocksource clocksource_tsc = { 1188 .name = "tsc", 1189 .rating = 300, 1190 .read = read_tsc, 1191 .mask = CLOCKSOURCE_MASK(64), 1192 .flags = CLOCK_SOURCE_IS_CONTINUOUS | 1193 CLOCK_SOURCE_VALID_FOR_HRES | 1194 CLOCK_SOURCE_MUST_VERIFY | 1195 CLOCK_SOURCE_VERIFY_PERCPU, 1196 .id = CSID_X86_TSC, 1197 .vdso_clock_mode = VDSO_CLOCKMODE_TSC, 1198 .enable = tsc_cs_enable, 1199 .resume = tsc_resume, 1200 .mark_unstable = tsc_cs_mark_unstable, 1201 .tick_stable = tsc_cs_tick_stable, 1202 .list = LIST_HEAD_INIT(clocksource_tsc.list), 1203 }; 1204 1205 void mark_tsc_unstable(char *reason) 1206 { 1207 if (tsc_unstable) 1208 return; 1209 1210 tsc_unstable = 1; 1211 if (using_native_sched_clock()) 1212 clear_sched_clock_stable(); 1213 disable_sched_clock_irqtime(); 1214 pr_info("Marking TSC unstable due to %s\n", reason); 1215 1216 clocksource_mark_unstable(&clocksource_tsc_early); 1217 clocksource_mark_unstable(&clocksource_tsc); 1218 } 1219 1220 EXPORT_SYMBOL_GPL(mark_tsc_unstable); 1221 1222 static void __init tsc_disable_clocksource_watchdog(void) 1223 { 1224 clocksource_tsc_early.flags &= ~CLOCK_SOURCE_MUST_VERIFY; 1225 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY; 1226 } 1227 1228 bool tsc_clocksource_watchdog_disabled(void) 1229 { 1230 return !(clocksource_tsc.flags & CLOCK_SOURCE_MUST_VERIFY) && 1231 tsc_as_watchdog && !no_tsc_watchdog; 1232 } 1233 1234 static void __init check_system_tsc_reliable(void) 1235 { 1236 #if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC) 1237 if (is_geode_lx()) { 1238 /* RTSC counts during suspend */ 1239 #define RTSC_SUSP 0x100 1240 unsigned long res_low, res_high; 1241 1242 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high); 1243 /* Geode_LX - the OLPC CPU has a very reliable TSC */ 1244 if (res_low & RTSC_SUSP) 1245 tsc_clocksource_reliable = 1; 1246 } 1247 #endif 1248 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) 1249 tsc_clocksource_reliable = 1; 1250 1251 /* 1252 * Disable the clocksource watchdog when the system has: 1253 * - TSC running at constant frequency 1254 * - TSC which does not stop in C-States 1255 * - the TSC_ADJUST register which allows to detect even minimal 1256 * modifications 1257 * - not more than four packages 1258 */ 1259 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC) && 1260 boot_cpu_has(X86_FEATURE_NONSTOP_TSC) && 1261 boot_cpu_has(X86_FEATURE_TSC_ADJUST) && 1262 topology_max_packages() <= 4) 1263 tsc_disable_clocksource_watchdog(); 1264 } 1265 1266 /* 1267 * Make an educated guess if the TSC is trustworthy and synchronized 1268 * over all CPUs. 1269 */ 1270 int unsynchronized_tsc(void) 1271 { 1272 if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_unstable) 1273 return 1; 1274 1275 #ifdef CONFIG_SMP 1276 if (apic_is_clustered_box()) 1277 return 1; 1278 #endif 1279 1280 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 1281 return 0; 1282 1283 if (tsc_clocksource_reliable) 1284 return 0; 1285 /* 1286 * Intel systems are normally all synchronized. 1287 * Exceptions must mark TSC as unstable: 1288 */ 1289 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) { 1290 /* assume multi socket systems are not synchronized: */ 1291 if (topology_max_packages() > 1) 1292 return 1; 1293 } 1294 1295 return 0; 1296 } 1297 1298 static void tsc_refine_calibration_work(struct work_struct *work); 1299 static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work); 1300 /** 1301 * tsc_refine_calibration_work - Further refine tsc freq calibration 1302 * @work: ignored. 1303 * 1304 * This functions uses delayed work over a period of a 1305 * second to further refine the TSC freq value. Since this is 1306 * timer based, instead of loop based, we don't block the boot 1307 * process while this longer calibration is done. 1308 * 1309 * If there are any calibration anomalies (too many SMIs, etc), 1310 * or the refined calibration is off by 1% of the fast early 1311 * calibration, we throw out the new calibration and use the 1312 * early calibration. 1313 */ 1314 static void tsc_refine_calibration_work(struct work_struct *work) 1315 { 1316 static u64 tsc_start = ULLONG_MAX, ref_start; 1317 static int hpet; 1318 u64 tsc_stop, ref_stop, delta; 1319 unsigned long freq; 1320 int cpu; 1321 1322 /* Don't bother refining TSC on unstable systems */ 1323 if (tsc_unstable) 1324 goto unreg; 1325 1326 /* 1327 * Since the work is started early in boot, we may be 1328 * delayed the first time we expire. So set the workqueue 1329 * again once we know timers are working. 1330 */ 1331 if (tsc_start == ULLONG_MAX) { 1332 restart: 1333 /* 1334 * Only set hpet once, to avoid mixing hardware 1335 * if the hpet becomes enabled later. 1336 */ 1337 hpet = is_hpet_enabled(); 1338 tsc_start = tsc_read_refs(&ref_start, hpet); 1339 schedule_delayed_work(&tsc_irqwork, HZ); 1340 return; 1341 } 1342 1343 tsc_stop = tsc_read_refs(&ref_stop, hpet); 1344 1345 /* hpet or pmtimer available ? */ 1346 if (ref_start == ref_stop) 1347 goto out; 1348 1349 /* Check, whether the sampling was disturbed */ 1350 if (tsc_stop == ULLONG_MAX) 1351 goto restart; 1352 1353 delta = tsc_stop - tsc_start; 1354 delta *= 1000000LL; 1355 if (hpet) 1356 freq = calc_hpet_ref(delta, ref_start, ref_stop); 1357 else 1358 freq = calc_pmtimer_ref(delta, ref_start, ref_stop); 1359 1360 /* Will hit this only if tsc_force_recalibrate has been set */ 1361 if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) { 1362 1363 /* Warn if the deviation exceeds 500 ppm */ 1364 if (abs(tsc_khz - freq) > (tsc_khz >> 11)) { 1365 pr_warn("Warning: TSC freq calibrated by CPUID/MSR differs from what is calibrated by HW timer, please check with vendor!!\n"); 1366 pr_info("Previous calibrated TSC freq:\t %lu.%03lu MHz\n", 1367 (unsigned long)tsc_khz / 1000, 1368 (unsigned long)tsc_khz % 1000); 1369 } 1370 1371 pr_info("TSC freq recalibrated by [%s]:\t %lu.%03lu MHz\n", 1372 hpet ? "HPET" : "PM_TIMER", 1373 (unsigned long)freq / 1000, 1374 (unsigned long)freq % 1000); 1375 1376 return; 1377 } 1378 1379 /* Make sure we're within 1% */ 1380 if (abs(tsc_khz - freq) > tsc_khz/100) 1381 goto out; 1382 1383 tsc_khz = freq; 1384 pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n", 1385 (unsigned long)tsc_khz / 1000, 1386 (unsigned long)tsc_khz % 1000); 1387 1388 /* Inform the TSC deadline clockevent devices about the recalibration */ 1389 lapic_update_tsc_freq(); 1390 1391 /* Update the sched_clock() rate to match the clocksource one */ 1392 for_each_possible_cpu(cpu) 1393 set_cyc2ns_scale(tsc_khz, cpu, tsc_stop); 1394 1395 out: 1396 if (tsc_unstable) 1397 goto unreg; 1398 1399 if (boot_cpu_has(X86_FEATURE_ART)) { 1400 have_art = true; 1401 clocksource_tsc.base = &art_base_clk; 1402 } 1403 clocksource_register_khz(&clocksource_tsc, tsc_khz); 1404 unreg: 1405 clocksource_unregister(&clocksource_tsc_early); 1406 } 1407 1408 1409 static int __init init_tsc_clocksource(void) 1410 { 1411 if (!boot_cpu_has(X86_FEATURE_TSC) || !tsc_khz) 1412 return 0; 1413 1414 if (tsc_unstable) { 1415 clocksource_unregister(&clocksource_tsc_early); 1416 return 0; 1417 } 1418 1419 if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3)) 1420 clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP; 1421 1422 /* 1423 * When TSC frequency is known (retrieved via MSR or CPUID), we skip 1424 * the refined calibration and directly register it as a clocksource. 1425 */ 1426 if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) { 1427 if (boot_cpu_has(X86_FEATURE_ART)) { 1428 have_art = true; 1429 clocksource_tsc.base = &art_base_clk; 1430 } 1431 clocksource_register_khz(&clocksource_tsc, tsc_khz); 1432 clocksource_unregister(&clocksource_tsc_early); 1433 1434 if (!tsc_force_recalibrate) 1435 return 0; 1436 } 1437 1438 schedule_delayed_work(&tsc_irqwork, 0); 1439 return 0; 1440 } 1441 /* 1442 * We use device_initcall here, to ensure we run after the hpet 1443 * is fully initialized, which may occur at fs_initcall time. 1444 */ 1445 device_initcall(init_tsc_clocksource); 1446 1447 static bool __init determine_cpu_tsc_frequencies(bool early) 1448 { 1449 /* Make sure that cpu and tsc are not already calibrated */ 1450 WARN_ON(cpu_khz || tsc_khz); 1451 1452 if (early) { 1453 cpu_khz = x86_platform.calibrate_cpu(); 1454 if (tsc_early_khz) { 1455 tsc_khz = tsc_early_khz; 1456 } else { 1457 tsc_khz = x86_platform.calibrate_tsc(); 1458 clocksource_tsc.freq_khz = tsc_khz; 1459 } 1460 } else { 1461 /* We should not be here with non-native cpu calibration */ 1462 WARN_ON(x86_platform.calibrate_cpu != native_calibrate_cpu); 1463 cpu_khz = pit_hpet_ptimer_calibrate_cpu(); 1464 } 1465 1466 /* 1467 * Trust non-zero tsc_khz as authoritative, 1468 * and use it to sanity check cpu_khz, 1469 * which will be off if system timer is off. 1470 */ 1471 if (tsc_khz == 0) 1472 tsc_khz = cpu_khz; 1473 else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz) 1474 cpu_khz = tsc_khz; 1475 1476 if (tsc_khz == 0) 1477 return false; 1478 1479 pr_info("Detected %lu.%03lu MHz processor\n", 1480 (unsigned long)cpu_khz / KHZ, 1481 (unsigned long)cpu_khz % KHZ); 1482 1483 if (cpu_khz != tsc_khz) { 1484 pr_info("Detected %lu.%03lu MHz TSC", 1485 (unsigned long)tsc_khz / KHZ, 1486 (unsigned long)tsc_khz % KHZ); 1487 } 1488 return true; 1489 } 1490 1491 static unsigned long __init get_loops_per_jiffy(void) 1492 { 1493 u64 lpj = (u64)tsc_khz * KHZ; 1494 1495 do_div(lpj, HZ); 1496 return lpj; 1497 } 1498 1499 static void __init tsc_enable_sched_clock(void) 1500 { 1501 loops_per_jiffy = get_loops_per_jiffy(); 1502 use_tsc_delay(); 1503 1504 /* Sanitize TSC ADJUST before cyc2ns gets initialized */ 1505 tsc_store_and_check_tsc_adjust(true); 1506 cyc2ns_init_boot_cpu(); 1507 static_branch_enable(&__use_tsc); 1508 } 1509 1510 void __init tsc_early_init(void) 1511 { 1512 if (!boot_cpu_has(X86_FEATURE_TSC)) 1513 return; 1514 /* Don't change UV TSC multi-chassis synchronization */ 1515 if (is_early_uv_system()) 1516 return; 1517 if (!determine_cpu_tsc_frequencies(true)) 1518 return; 1519 tsc_enable_sched_clock(); 1520 } 1521 1522 void __init tsc_init(void) 1523 { 1524 if (!cpu_feature_enabled(X86_FEATURE_TSC)) { 1525 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 1526 return; 1527 } 1528 1529 /* 1530 * native_calibrate_cpu_early can only calibrate using methods that are 1531 * available early in boot. 1532 */ 1533 if (x86_platform.calibrate_cpu == native_calibrate_cpu_early) 1534 x86_platform.calibrate_cpu = native_calibrate_cpu; 1535 1536 if (!tsc_khz) { 1537 /* We failed to determine frequencies earlier, try again */ 1538 if (!determine_cpu_tsc_frequencies(false)) { 1539 mark_tsc_unstable("could not calculate TSC khz"); 1540 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 1541 return; 1542 } 1543 tsc_enable_sched_clock(); 1544 } 1545 1546 cyc2ns_init_secondary_cpus(); 1547 1548 if (!no_sched_irq_time) 1549 enable_sched_clock_irqtime(); 1550 1551 lpj_fine = get_loops_per_jiffy(); 1552 1553 check_system_tsc_reliable(); 1554 1555 if (unsynchronized_tsc()) { 1556 mark_tsc_unstable("TSCs unsynchronized"); 1557 return; 1558 } 1559 1560 if (tsc_clocksource_reliable || no_tsc_watchdog) 1561 tsc_disable_clocksource_watchdog(); 1562 1563 clocksource_register_khz(&clocksource_tsc_early, tsc_khz); 1564 detect_art(); 1565 } 1566 1567 #ifdef CONFIG_SMP 1568 /* 1569 * Check whether existing calibration data can be reused. 1570 */ 1571 unsigned long calibrate_delay_is_known(void) 1572 { 1573 int sibling, cpu = smp_processor_id(); 1574 int constant_tsc = cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC); 1575 const struct cpumask *mask = topology_core_cpumask(cpu); 1576 1577 /* 1578 * If TSC has constant frequency and TSC is synchronized across 1579 * sockets then reuse CPU0 calibration. 1580 */ 1581 if (constant_tsc && !tsc_unstable) 1582 return cpu_data(0).loops_per_jiffy; 1583 1584 /* 1585 * If TSC has constant frequency and TSC is not synchronized across 1586 * sockets and this is not the first CPU in the socket, then reuse 1587 * the calibration value of an already online CPU on that socket. 1588 * 1589 * This assumes that CONSTANT_TSC is consistent for all CPUs in a 1590 * socket. 1591 */ 1592 if (!constant_tsc || !mask) 1593 return 0; 1594 1595 sibling = cpumask_any_but(mask, cpu); 1596 if (sibling < nr_cpu_ids) 1597 return cpu_data(sibling).loops_per_jiffy; 1598 return 0; 1599 } 1600 #endif 1601