1 #include <linux/kernel.h> 2 #include <linux/sched.h> 3 #include <linux/init.h> 4 #include <linux/module.h> 5 #include <linux/timer.h> 6 #include <linux/acpi_pmtmr.h> 7 #include <linux/cpufreq.h> 8 #include <linux/dmi.h> 9 #include <linux/delay.h> 10 #include <linux/clocksource.h> 11 #include <linux/percpu.h> 12 #include <linux/timex.h> 13 14 #include <asm/hpet.h> 15 #include <asm/timer.h> 16 #include <asm/vgtod.h> 17 #include <asm/time.h> 18 #include <asm/delay.h> 19 #include <asm/hypervisor.h> 20 21 unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */ 22 EXPORT_SYMBOL(cpu_khz); 23 24 unsigned int __read_mostly tsc_khz; 25 EXPORT_SYMBOL(tsc_khz); 26 27 /* 28 * TSC can be unstable due to cpufreq or due to unsynced TSCs 29 */ 30 static int __read_mostly tsc_unstable; 31 32 /* native_sched_clock() is called before tsc_init(), so 33 we must start with the TSC soft disabled to prevent 34 erroneous rdtsc usage on !cpu_has_tsc processors */ 35 static int __read_mostly tsc_disabled = -1; 36 37 static int tsc_clocksource_reliable; 38 /* 39 * Scheduler clock - returns current time in nanosec units. 40 */ 41 u64 native_sched_clock(void) 42 { 43 u64 this_offset; 44 45 /* 46 * Fall back to jiffies if there's no TSC available: 47 * ( But note that we still use it if the TSC is marked 48 * unstable. We do this because unlike Time Of Day, 49 * the scheduler clock tolerates small errors and it's 50 * very important for it to be as fast as the platform 51 * can achive it. ) 52 */ 53 if (unlikely(tsc_disabled)) { 54 /* No locking but a rare wrong value is not a big deal: */ 55 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ); 56 } 57 58 /* read the Time Stamp Counter: */ 59 rdtscll(this_offset); 60 61 /* return the value in ns */ 62 return __cycles_2_ns(this_offset); 63 } 64 65 /* We need to define a real function for sched_clock, to override the 66 weak default version */ 67 #ifdef CONFIG_PARAVIRT 68 unsigned long long sched_clock(void) 69 { 70 return paravirt_sched_clock(); 71 } 72 #else 73 unsigned long long 74 sched_clock(void) __attribute__((alias("native_sched_clock"))); 75 #endif 76 77 int check_tsc_unstable(void) 78 { 79 return tsc_unstable; 80 } 81 EXPORT_SYMBOL_GPL(check_tsc_unstable); 82 83 #ifdef CONFIG_X86_TSC 84 int __init notsc_setup(char *str) 85 { 86 printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, " 87 "cannot disable TSC completely.\n"); 88 tsc_disabled = 1; 89 return 1; 90 } 91 #else 92 /* 93 * disable flag for tsc. Takes effect by clearing the TSC cpu flag 94 * in cpu/common.c 95 */ 96 int __init notsc_setup(char *str) 97 { 98 setup_clear_cpu_cap(X86_FEATURE_TSC); 99 return 1; 100 } 101 #endif 102 103 __setup("notsc", notsc_setup); 104 105 static int __init tsc_setup(char *str) 106 { 107 if (!strcmp(str, "reliable")) 108 tsc_clocksource_reliable = 1; 109 return 1; 110 } 111 112 __setup("tsc=", tsc_setup); 113 114 #define MAX_RETRIES 5 115 #define SMI_TRESHOLD 50000 116 117 /* 118 * Read TSC and the reference counters. Take care of SMI disturbance 119 */ 120 static u64 tsc_read_refs(u64 *p, int hpet) 121 { 122 u64 t1, t2; 123 int i; 124 125 for (i = 0; i < MAX_RETRIES; i++) { 126 t1 = get_cycles(); 127 if (hpet) 128 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF; 129 else 130 *p = acpi_pm_read_early(); 131 t2 = get_cycles(); 132 if ((t2 - t1) < SMI_TRESHOLD) 133 return t2; 134 } 135 return ULLONG_MAX; 136 } 137 138 /* 139 * Calculate the TSC frequency from HPET reference 140 */ 141 static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2) 142 { 143 u64 tmp; 144 145 if (hpet2 < hpet1) 146 hpet2 += 0x100000000ULL; 147 hpet2 -= hpet1; 148 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD)); 149 do_div(tmp, 1000000); 150 do_div(deltatsc, tmp); 151 152 return (unsigned long) deltatsc; 153 } 154 155 /* 156 * Calculate the TSC frequency from PMTimer reference 157 */ 158 static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2) 159 { 160 u64 tmp; 161 162 if (!pm1 && !pm2) 163 return ULONG_MAX; 164 165 if (pm2 < pm1) 166 pm2 += (u64)ACPI_PM_OVRRUN; 167 pm2 -= pm1; 168 tmp = pm2 * 1000000000LL; 169 do_div(tmp, PMTMR_TICKS_PER_SEC); 170 do_div(deltatsc, tmp); 171 172 return (unsigned long) deltatsc; 173 } 174 175 #define CAL_MS 10 176 #define CAL_LATCH (CLOCK_TICK_RATE / (1000 / CAL_MS)) 177 #define CAL_PIT_LOOPS 1000 178 179 #define CAL2_MS 50 180 #define CAL2_LATCH (CLOCK_TICK_RATE / (1000 / CAL2_MS)) 181 #define CAL2_PIT_LOOPS 5000 182 183 184 /* 185 * Try to calibrate the TSC against the Programmable 186 * Interrupt Timer and return the frequency of the TSC 187 * in kHz. 188 * 189 * Return ULONG_MAX on failure to calibrate. 190 */ 191 static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin) 192 { 193 u64 tsc, t1, t2, delta; 194 unsigned long tscmin, tscmax; 195 int pitcnt; 196 197 /* Set the Gate high, disable speaker */ 198 outb((inb(0x61) & ~0x02) | 0x01, 0x61); 199 200 /* 201 * Setup CTC channel 2* for mode 0, (interrupt on terminal 202 * count mode), binary count. Set the latch register to 50ms 203 * (LSB then MSB) to begin countdown. 204 */ 205 outb(0xb0, 0x43); 206 outb(latch & 0xff, 0x42); 207 outb(latch >> 8, 0x42); 208 209 tsc = t1 = t2 = get_cycles(); 210 211 pitcnt = 0; 212 tscmax = 0; 213 tscmin = ULONG_MAX; 214 while ((inb(0x61) & 0x20) == 0) { 215 t2 = get_cycles(); 216 delta = t2 - tsc; 217 tsc = t2; 218 if ((unsigned long) delta < tscmin) 219 tscmin = (unsigned int) delta; 220 if ((unsigned long) delta > tscmax) 221 tscmax = (unsigned int) delta; 222 pitcnt++; 223 } 224 225 /* 226 * Sanity checks: 227 * 228 * If we were not able to read the PIT more than loopmin 229 * times, then we have been hit by a massive SMI 230 * 231 * If the maximum is 10 times larger than the minimum, 232 * then we got hit by an SMI as well. 233 */ 234 if (pitcnt < loopmin || tscmax > 10 * tscmin) 235 return ULONG_MAX; 236 237 /* Calculate the PIT value */ 238 delta = t2 - t1; 239 do_div(delta, ms); 240 return delta; 241 } 242 243 /* 244 * This reads the current MSB of the PIT counter, and 245 * checks if we are running on sufficiently fast and 246 * non-virtualized hardware. 247 * 248 * Our expectations are: 249 * 250 * - the PIT is running at roughly 1.19MHz 251 * 252 * - each IO is going to take about 1us on real hardware, 253 * but we allow it to be much faster (by a factor of 10) or 254 * _slightly_ slower (ie we allow up to a 2us read+counter 255 * update - anything else implies a unacceptably slow CPU 256 * or PIT for the fast calibration to work. 257 * 258 * - with 256 PIT ticks to read the value, we have 214us to 259 * see the same MSB (and overhead like doing a single TSC 260 * read per MSB value etc). 261 * 262 * - We're doing 2 reads per loop (LSB, MSB), and we expect 263 * them each to take about a microsecond on real hardware. 264 * So we expect a count value of around 100. But we'll be 265 * generous, and accept anything over 50. 266 * 267 * - if the PIT is stuck, and we see *many* more reads, we 268 * return early (and the next caller of pit_expect_msb() 269 * then consider it a failure when they don't see the 270 * next expected value). 271 * 272 * These expectations mean that we know that we have seen the 273 * transition from one expected value to another with a fairly 274 * high accuracy, and we didn't miss any events. We can thus 275 * use the TSC value at the transitions to calculate a pretty 276 * good value for the TSC frequencty. 277 */ 278 static inline int pit_verify_msb(unsigned char val) 279 { 280 /* Ignore LSB */ 281 inb(0x42); 282 return inb(0x42) == val; 283 } 284 285 static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap) 286 { 287 int count; 288 u64 tsc = 0; 289 290 for (count = 0; count < 50000; count++) { 291 if (!pit_verify_msb(val)) 292 break; 293 tsc = get_cycles(); 294 } 295 *deltap = get_cycles() - tsc; 296 *tscp = tsc; 297 298 /* 299 * We require _some_ success, but the quality control 300 * will be based on the error terms on the TSC values. 301 */ 302 return count > 5; 303 } 304 305 /* 306 * How many MSB values do we want to see? We aim for 307 * a maximum error rate of 500ppm (in practice the 308 * real error is much smaller), but refuse to spend 309 * more than 25ms on it. 310 */ 311 #define MAX_QUICK_PIT_MS 25 312 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) 313 314 static unsigned long quick_pit_calibrate(void) 315 { 316 int i; 317 u64 tsc, delta; 318 unsigned long d1, d2; 319 320 /* Set the Gate high, disable speaker */ 321 outb((inb(0x61) & ~0x02) | 0x01, 0x61); 322 323 /* 324 * Counter 2, mode 0 (one-shot), binary count 325 * 326 * NOTE! Mode 2 decrements by two (and then the 327 * output is flipped each time, giving the same 328 * final output frequency as a decrement-by-one), 329 * so mode 0 is much better when looking at the 330 * individual counts. 331 */ 332 outb(0xb0, 0x43); 333 334 /* Start at 0xffff */ 335 outb(0xff, 0x42); 336 outb(0xff, 0x42); 337 338 /* 339 * The PIT starts counting at the next edge, so we 340 * need to delay for a microsecond. The easiest way 341 * to do that is to just read back the 16-bit counter 342 * once from the PIT. 343 */ 344 pit_verify_msb(0); 345 346 if (pit_expect_msb(0xff, &tsc, &d1)) { 347 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) { 348 if (!pit_expect_msb(0xff-i, &delta, &d2)) 349 break; 350 351 /* 352 * Iterate until the error is less than 500 ppm 353 */ 354 delta -= tsc; 355 if (d1+d2 >= delta >> 11) 356 continue; 357 358 /* 359 * Check the PIT one more time to verify that 360 * all TSC reads were stable wrt the PIT. 361 * 362 * This also guarantees serialization of the 363 * last cycle read ('d2') in pit_expect_msb. 364 */ 365 if (!pit_verify_msb(0xfe - i)) 366 break; 367 goto success; 368 } 369 } 370 printk("Fast TSC calibration failed\n"); 371 return 0; 372 373 success: 374 /* 375 * Ok, if we get here, then we've seen the 376 * MSB of the PIT decrement 'i' times, and the 377 * error has shrunk to less than 500 ppm. 378 * 379 * As a result, we can depend on there not being 380 * any odd delays anywhere, and the TSC reads are 381 * reliable (within the error). We also adjust the 382 * delta to the middle of the error bars, just 383 * because it looks nicer. 384 * 385 * kHz = ticks / time-in-seconds / 1000; 386 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000 387 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000) 388 */ 389 delta += (long)(d2 - d1)/2; 390 delta *= PIT_TICK_RATE; 391 do_div(delta, i*256*1000); 392 printk("Fast TSC calibration using PIT\n"); 393 return delta; 394 } 395 396 /** 397 * native_calibrate_tsc - calibrate the tsc on boot 398 */ 399 unsigned long native_calibrate_tsc(void) 400 { 401 u64 tsc1, tsc2, delta, ref1, ref2; 402 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX; 403 unsigned long flags, latch, ms, fast_calibrate, hv_tsc_khz; 404 int hpet = is_hpet_enabled(), i, loopmin; 405 406 hv_tsc_khz = get_hypervisor_tsc_freq(); 407 if (hv_tsc_khz) { 408 printk(KERN_INFO "TSC: Frequency read from the hypervisor\n"); 409 return hv_tsc_khz; 410 } 411 412 local_irq_save(flags); 413 fast_calibrate = quick_pit_calibrate(); 414 local_irq_restore(flags); 415 if (fast_calibrate) 416 return fast_calibrate; 417 418 /* 419 * Run 5 calibration loops to get the lowest frequency value 420 * (the best estimate). We use two different calibration modes 421 * here: 422 * 423 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and 424 * load a timeout of 50ms. We read the time right after we 425 * started the timer and wait until the PIT count down reaches 426 * zero. In each wait loop iteration we read the TSC and check 427 * the delta to the previous read. We keep track of the min 428 * and max values of that delta. The delta is mostly defined 429 * by the IO time of the PIT access, so we can detect when a 430 * SMI/SMM disturbance happend between the two reads. If the 431 * maximum time is significantly larger than the minimum time, 432 * then we discard the result and have another try. 433 * 434 * 2) Reference counter. If available we use the HPET or the 435 * PMTIMER as a reference to check the sanity of that value. 436 * We use separate TSC readouts and check inside of the 437 * reference read for a SMI/SMM disturbance. We dicard 438 * disturbed values here as well. We do that around the PIT 439 * calibration delay loop as we have to wait for a certain 440 * amount of time anyway. 441 */ 442 443 /* Preset PIT loop values */ 444 latch = CAL_LATCH; 445 ms = CAL_MS; 446 loopmin = CAL_PIT_LOOPS; 447 448 for (i = 0; i < 3; i++) { 449 unsigned long tsc_pit_khz; 450 451 /* 452 * Read the start value and the reference count of 453 * hpet/pmtimer when available. Then do the PIT 454 * calibration, which will take at least 50ms, and 455 * read the end value. 456 */ 457 local_irq_save(flags); 458 tsc1 = tsc_read_refs(&ref1, hpet); 459 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin); 460 tsc2 = tsc_read_refs(&ref2, hpet); 461 local_irq_restore(flags); 462 463 /* Pick the lowest PIT TSC calibration so far */ 464 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz); 465 466 /* hpet or pmtimer available ? */ 467 if (!hpet && !ref1 && !ref2) 468 continue; 469 470 /* Check, whether the sampling was disturbed by an SMI */ 471 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX) 472 continue; 473 474 tsc2 = (tsc2 - tsc1) * 1000000LL; 475 if (hpet) 476 tsc2 = calc_hpet_ref(tsc2, ref1, ref2); 477 else 478 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2); 479 480 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2); 481 482 /* Check the reference deviation */ 483 delta = ((u64) tsc_pit_min) * 100; 484 do_div(delta, tsc_ref_min); 485 486 /* 487 * If both calibration results are inside a 10% window 488 * then we can be sure, that the calibration 489 * succeeded. We break out of the loop right away. We 490 * use the reference value, as it is more precise. 491 */ 492 if (delta >= 90 && delta <= 110) { 493 printk(KERN_INFO 494 "TSC: PIT calibration matches %s. %d loops\n", 495 hpet ? "HPET" : "PMTIMER", i + 1); 496 return tsc_ref_min; 497 } 498 499 /* 500 * Check whether PIT failed more than once. This 501 * happens in virtualized environments. We need to 502 * give the virtual PC a slightly longer timeframe for 503 * the HPET/PMTIMER to make the result precise. 504 */ 505 if (i == 1 && tsc_pit_min == ULONG_MAX) { 506 latch = CAL2_LATCH; 507 ms = CAL2_MS; 508 loopmin = CAL2_PIT_LOOPS; 509 } 510 } 511 512 /* 513 * Now check the results. 514 */ 515 if (tsc_pit_min == ULONG_MAX) { 516 /* PIT gave no useful value */ 517 printk(KERN_WARNING "TSC: Unable to calibrate against PIT\n"); 518 519 /* We don't have an alternative source, disable TSC */ 520 if (!hpet && !ref1 && !ref2) { 521 printk("TSC: No reference (HPET/PMTIMER) available\n"); 522 return 0; 523 } 524 525 /* The alternative source failed as well, disable TSC */ 526 if (tsc_ref_min == ULONG_MAX) { 527 printk(KERN_WARNING "TSC: HPET/PMTIMER calibration " 528 "failed.\n"); 529 return 0; 530 } 531 532 /* Use the alternative source */ 533 printk(KERN_INFO "TSC: using %s reference calibration\n", 534 hpet ? "HPET" : "PMTIMER"); 535 536 return tsc_ref_min; 537 } 538 539 /* We don't have an alternative source, use the PIT calibration value */ 540 if (!hpet && !ref1 && !ref2) { 541 printk(KERN_INFO "TSC: Using PIT calibration value\n"); 542 return tsc_pit_min; 543 } 544 545 /* The alternative source failed, use the PIT calibration value */ 546 if (tsc_ref_min == ULONG_MAX) { 547 printk(KERN_WARNING "TSC: HPET/PMTIMER calibration failed. " 548 "Using PIT calibration\n"); 549 return tsc_pit_min; 550 } 551 552 /* 553 * The calibration values differ too much. In doubt, we use 554 * the PIT value as we know that there are PMTIMERs around 555 * running at double speed. At least we let the user know: 556 */ 557 printk(KERN_WARNING "TSC: PIT calibration deviates from %s: %lu %lu.\n", 558 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min); 559 printk(KERN_INFO "TSC: Using PIT calibration value\n"); 560 return tsc_pit_min; 561 } 562 563 int recalibrate_cpu_khz(void) 564 { 565 #ifndef CONFIG_SMP 566 unsigned long cpu_khz_old = cpu_khz; 567 568 if (cpu_has_tsc) { 569 tsc_khz = calibrate_tsc(); 570 cpu_khz = tsc_khz; 571 cpu_data(0).loops_per_jiffy = 572 cpufreq_scale(cpu_data(0).loops_per_jiffy, 573 cpu_khz_old, cpu_khz); 574 return 0; 575 } else 576 return -ENODEV; 577 #else 578 return -ENODEV; 579 #endif 580 } 581 582 EXPORT_SYMBOL(recalibrate_cpu_khz); 583 584 585 /* Accelerators for sched_clock() 586 * convert from cycles(64bits) => nanoseconds (64bits) 587 * basic equation: 588 * ns = cycles / (freq / ns_per_sec) 589 * ns = cycles * (ns_per_sec / freq) 590 * ns = cycles * (10^9 / (cpu_khz * 10^3)) 591 * ns = cycles * (10^6 / cpu_khz) 592 * 593 * Then we use scaling math (suggested by george@mvista.com) to get: 594 * ns = cycles * (10^6 * SC / cpu_khz) / SC 595 * ns = cycles * cyc2ns_scale / SC 596 * 597 * And since SC is a constant power of two, we can convert the div 598 * into a shift. 599 * 600 * We can use khz divisor instead of mhz to keep a better precision, since 601 * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits. 602 * (mathieu.desnoyers@polymtl.ca) 603 * 604 * -johnstul@us.ibm.com "math is hard, lets go shopping!" 605 */ 606 607 DEFINE_PER_CPU(unsigned long, cyc2ns); 608 DEFINE_PER_CPU(unsigned long long, cyc2ns_offset); 609 610 static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu) 611 { 612 unsigned long long tsc_now, ns_now, *offset; 613 unsigned long flags, *scale; 614 615 local_irq_save(flags); 616 sched_clock_idle_sleep_event(); 617 618 scale = &per_cpu(cyc2ns, cpu); 619 offset = &per_cpu(cyc2ns_offset, cpu); 620 621 rdtscll(tsc_now); 622 ns_now = __cycles_2_ns(tsc_now); 623 624 if (cpu_khz) { 625 *scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz; 626 *offset = ns_now - (tsc_now * *scale >> CYC2NS_SCALE_FACTOR); 627 } 628 629 sched_clock_idle_wakeup_event(0); 630 local_irq_restore(flags); 631 } 632 633 #ifdef CONFIG_CPU_FREQ 634 635 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency 636 * changes. 637 * 638 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's 639 * not that important because current Opteron setups do not support 640 * scaling on SMP anyroads. 641 * 642 * Should fix up last_tsc too. Currently gettimeofday in the 643 * first tick after the change will be slightly wrong. 644 */ 645 646 static unsigned int ref_freq; 647 static unsigned long loops_per_jiffy_ref; 648 static unsigned long tsc_khz_ref; 649 650 static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 651 void *data) 652 { 653 struct cpufreq_freqs *freq = data; 654 unsigned long *lpj; 655 656 if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC)) 657 return 0; 658 659 lpj = &boot_cpu_data.loops_per_jiffy; 660 #ifdef CONFIG_SMP 661 if (!(freq->flags & CPUFREQ_CONST_LOOPS)) 662 lpj = &cpu_data(freq->cpu).loops_per_jiffy; 663 #endif 664 665 if (!ref_freq) { 666 ref_freq = freq->old; 667 loops_per_jiffy_ref = *lpj; 668 tsc_khz_ref = tsc_khz; 669 } 670 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || 671 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) || 672 (val == CPUFREQ_RESUMECHANGE)) { 673 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new); 674 675 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new); 676 if (!(freq->flags & CPUFREQ_CONST_LOOPS)) 677 mark_tsc_unstable("cpufreq changes"); 678 } 679 680 set_cyc2ns_scale(tsc_khz, freq->cpu); 681 682 return 0; 683 } 684 685 static struct notifier_block time_cpufreq_notifier_block = { 686 .notifier_call = time_cpufreq_notifier 687 }; 688 689 static int __init cpufreq_tsc(void) 690 { 691 if (!cpu_has_tsc) 692 return 0; 693 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 694 return 0; 695 cpufreq_register_notifier(&time_cpufreq_notifier_block, 696 CPUFREQ_TRANSITION_NOTIFIER); 697 return 0; 698 } 699 700 core_initcall(cpufreq_tsc); 701 702 #endif /* CONFIG_CPU_FREQ */ 703 704 /* clocksource code */ 705 706 static struct clocksource clocksource_tsc; 707 708 /* 709 * We compare the TSC to the cycle_last value in the clocksource 710 * structure to avoid a nasty time-warp. This can be observed in a 711 * very small window right after one CPU updated cycle_last under 712 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which 713 * is smaller than the cycle_last reference value due to a TSC which 714 * is slighty behind. This delta is nowhere else observable, but in 715 * that case it results in a forward time jump in the range of hours 716 * due to the unsigned delta calculation of the time keeping core 717 * code, which is necessary to support wrapping clocksources like pm 718 * timer. 719 */ 720 static cycle_t read_tsc(struct clocksource *cs) 721 { 722 cycle_t ret = (cycle_t)get_cycles(); 723 724 return ret >= clocksource_tsc.cycle_last ? 725 ret : clocksource_tsc.cycle_last; 726 } 727 728 #ifdef CONFIG_X86_64 729 static cycle_t __vsyscall_fn vread_tsc(void) 730 { 731 cycle_t ret; 732 733 /* 734 * Surround the RDTSC by barriers, to make sure it's not 735 * speculated to outside the seqlock critical section and 736 * does not cause time warps: 737 */ 738 rdtsc_barrier(); 739 ret = (cycle_t)vget_cycles(); 740 rdtsc_barrier(); 741 742 return ret >= __vsyscall_gtod_data.clock.cycle_last ? 743 ret : __vsyscall_gtod_data.clock.cycle_last; 744 } 745 #endif 746 747 static struct clocksource clocksource_tsc = { 748 .name = "tsc", 749 .rating = 300, 750 .read = read_tsc, 751 .mask = CLOCKSOURCE_MASK(64), 752 .shift = 22, 753 .flags = CLOCK_SOURCE_IS_CONTINUOUS | 754 CLOCK_SOURCE_MUST_VERIFY, 755 #ifdef CONFIG_X86_64 756 .vread = vread_tsc, 757 #endif 758 }; 759 760 void mark_tsc_unstable(char *reason) 761 { 762 if (!tsc_unstable) { 763 tsc_unstable = 1; 764 printk("Marking TSC unstable due to %s\n", reason); 765 /* Change only the rating, when not registered */ 766 if (clocksource_tsc.mult) 767 clocksource_change_rating(&clocksource_tsc, 0); 768 else 769 clocksource_tsc.rating = 0; 770 } 771 } 772 773 EXPORT_SYMBOL_GPL(mark_tsc_unstable); 774 775 static int __init dmi_mark_tsc_unstable(const struct dmi_system_id *d) 776 { 777 printk(KERN_NOTICE "%s detected: marking TSC unstable.\n", 778 d->ident); 779 tsc_unstable = 1; 780 return 0; 781 } 782 783 /* List of systems that have known TSC problems */ 784 static struct dmi_system_id __initdata bad_tsc_dmi_table[] = { 785 { 786 .callback = dmi_mark_tsc_unstable, 787 .ident = "IBM Thinkpad 380XD", 788 .matches = { 789 DMI_MATCH(DMI_BOARD_VENDOR, "IBM"), 790 DMI_MATCH(DMI_BOARD_NAME, "2635FA0"), 791 }, 792 }, 793 {} 794 }; 795 796 static void __init check_system_tsc_reliable(void) 797 { 798 #ifdef CONFIG_MGEODE_LX 799 /* RTSC counts during suspend */ 800 #define RTSC_SUSP 0x100 801 unsigned long res_low, res_high; 802 803 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high); 804 /* Geode_LX - the OLPC CPU has a possibly a very reliable TSC */ 805 if (res_low & RTSC_SUSP) 806 tsc_clocksource_reliable = 1; 807 #endif 808 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) 809 tsc_clocksource_reliable = 1; 810 } 811 812 /* 813 * Make an educated guess if the TSC is trustworthy and synchronized 814 * over all CPUs. 815 */ 816 __cpuinit int unsynchronized_tsc(void) 817 { 818 if (!cpu_has_tsc || tsc_unstable) 819 return 1; 820 821 #ifdef CONFIG_SMP 822 if (apic_is_clustered_box()) 823 return 1; 824 #endif 825 826 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 827 return 0; 828 /* 829 * Intel systems are normally all synchronized. 830 * Exceptions must mark TSC as unstable: 831 */ 832 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) { 833 /* assume multi socket systems are not synchronized: */ 834 if (num_possible_cpus() > 1) 835 tsc_unstable = 1; 836 } 837 838 return tsc_unstable; 839 } 840 841 static void __init init_tsc_clocksource(void) 842 { 843 clocksource_tsc.mult = clocksource_khz2mult(tsc_khz, 844 clocksource_tsc.shift); 845 if (tsc_clocksource_reliable) 846 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY; 847 /* lower the rating if we already know its unstable: */ 848 if (check_tsc_unstable()) { 849 clocksource_tsc.rating = 0; 850 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS; 851 } 852 clocksource_register(&clocksource_tsc); 853 } 854 855 void __init tsc_init(void) 856 { 857 u64 lpj; 858 int cpu; 859 860 if (!cpu_has_tsc) 861 return; 862 863 tsc_khz = calibrate_tsc(); 864 cpu_khz = tsc_khz; 865 866 if (!tsc_khz) { 867 mark_tsc_unstable("could not calculate TSC khz"); 868 return; 869 } 870 871 #ifdef CONFIG_X86_64 872 if (cpu_has(&boot_cpu_data, X86_FEATURE_CONSTANT_TSC) && 873 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)) 874 cpu_khz = calibrate_cpu(); 875 #endif 876 877 printk("Detected %lu.%03lu MHz processor.\n", 878 (unsigned long)cpu_khz / 1000, 879 (unsigned long)cpu_khz % 1000); 880 881 /* 882 * Secondary CPUs do not run through tsc_init(), so set up 883 * all the scale factors for all CPUs, assuming the same 884 * speed as the bootup CPU. (cpufreq notifiers will fix this 885 * up if their speed diverges) 886 */ 887 for_each_possible_cpu(cpu) 888 set_cyc2ns_scale(cpu_khz, cpu); 889 890 if (tsc_disabled > 0) 891 return; 892 893 /* now allow native_sched_clock() to use rdtsc */ 894 tsc_disabled = 0; 895 896 lpj = ((u64)tsc_khz * 1000); 897 do_div(lpj, HZ); 898 lpj_fine = lpj; 899 900 use_tsc_delay(); 901 /* Check and install the TSC clocksource */ 902 dmi_check_system(bad_tsc_dmi_table); 903 904 if (unsynchronized_tsc()) 905 mark_tsc_unstable("TSCs unsynchronized"); 906 907 check_system_tsc_reliable(); 908 init_tsc_clocksource(); 909 } 910 911