1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 2 3 #include <linux/kernel.h> 4 #include <linux/sched.h> 5 #include <linux/sched/clock.h> 6 #include <linux/init.h> 7 #include <linux/export.h> 8 #include <linux/timer.h> 9 #include <linux/acpi_pmtmr.h> 10 #include <linux/cpufreq.h> 11 #include <linux/delay.h> 12 #include <linux/clocksource.h> 13 #include <linux/percpu.h> 14 #include <linux/timex.h> 15 #include <linux/static_key.h> 16 17 #include <asm/hpet.h> 18 #include <asm/timer.h> 19 #include <asm/vgtod.h> 20 #include <asm/time.h> 21 #include <asm/delay.h> 22 #include <asm/hypervisor.h> 23 #include <asm/nmi.h> 24 #include <asm/x86_init.h> 25 #include <asm/geode.h> 26 #include <asm/apic.h> 27 #include <asm/intel-family.h> 28 #include <asm/i8259.h> 29 #include <asm/uv/uv.h> 30 31 unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */ 32 EXPORT_SYMBOL(cpu_khz); 33 34 unsigned int __read_mostly tsc_khz; 35 EXPORT_SYMBOL(tsc_khz); 36 37 #define KHZ 1000 38 39 /* 40 * TSC can be unstable due to cpufreq or due to unsynced TSCs 41 */ 42 static int __read_mostly tsc_unstable; 43 44 static DEFINE_STATIC_KEY_FALSE(__use_tsc); 45 46 int tsc_clocksource_reliable; 47 48 static u32 art_to_tsc_numerator; 49 static u32 art_to_tsc_denominator; 50 static u64 art_to_tsc_offset; 51 struct clocksource *art_related_clocksource; 52 53 struct cyc2ns { 54 struct cyc2ns_data data[2]; /* 0 + 2*16 = 32 */ 55 seqcount_t seq; /* 32 + 4 = 36 */ 56 57 }; /* fits one cacheline */ 58 59 static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns); 60 61 void __always_inline cyc2ns_read_begin(struct cyc2ns_data *data) 62 { 63 int seq, idx; 64 65 preempt_disable_notrace(); 66 67 do { 68 seq = this_cpu_read(cyc2ns.seq.sequence); 69 idx = seq & 1; 70 71 data->cyc2ns_offset = this_cpu_read(cyc2ns.data[idx].cyc2ns_offset); 72 data->cyc2ns_mul = this_cpu_read(cyc2ns.data[idx].cyc2ns_mul); 73 data->cyc2ns_shift = this_cpu_read(cyc2ns.data[idx].cyc2ns_shift); 74 75 } while (unlikely(seq != this_cpu_read(cyc2ns.seq.sequence))); 76 } 77 78 void __always_inline cyc2ns_read_end(void) 79 { 80 preempt_enable_notrace(); 81 } 82 83 /* 84 * Accelerators for sched_clock() 85 * convert from cycles(64bits) => nanoseconds (64bits) 86 * basic equation: 87 * ns = cycles / (freq / ns_per_sec) 88 * ns = cycles * (ns_per_sec / freq) 89 * ns = cycles * (10^9 / (cpu_khz * 10^3)) 90 * ns = cycles * (10^6 / cpu_khz) 91 * 92 * Then we use scaling math (suggested by george@mvista.com) to get: 93 * ns = cycles * (10^6 * SC / cpu_khz) / SC 94 * ns = cycles * cyc2ns_scale / SC 95 * 96 * And since SC is a constant power of two, we can convert the div 97 * into a shift. The larger SC is, the more accurate the conversion, but 98 * cyc2ns_scale needs to be a 32-bit value so that 32-bit multiplication 99 * (64-bit result) can be used. 100 * 101 * We can use khz divisor instead of mhz to keep a better precision. 102 * (mathieu.desnoyers@polymtl.ca) 103 * 104 * -johnstul@us.ibm.com "math is hard, lets go shopping!" 105 */ 106 107 static __always_inline unsigned long long cycles_2_ns(unsigned long long cyc) 108 { 109 struct cyc2ns_data data; 110 unsigned long long ns; 111 112 cyc2ns_read_begin(&data); 113 114 ns = data.cyc2ns_offset; 115 ns += mul_u64_u32_shr(cyc, data.cyc2ns_mul, data.cyc2ns_shift); 116 117 cyc2ns_read_end(); 118 119 return ns; 120 } 121 122 static void __set_cyc2ns_scale(unsigned long khz, int cpu, unsigned long long tsc_now) 123 { 124 unsigned long long ns_now; 125 struct cyc2ns_data data; 126 struct cyc2ns *c2n; 127 128 ns_now = cycles_2_ns(tsc_now); 129 130 /* 131 * Compute a new multiplier as per the above comment and ensure our 132 * time function is continuous; see the comment near struct 133 * cyc2ns_data. 134 */ 135 clocks_calc_mult_shift(&data.cyc2ns_mul, &data.cyc2ns_shift, khz, 136 NSEC_PER_MSEC, 0); 137 138 /* 139 * cyc2ns_shift is exported via arch_perf_update_userpage() where it is 140 * not expected to be greater than 31 due to the original published 141 * conversion algorithm shifting a 32-bit value (now specifies a 64-bit 142 * value) - refer perf_event_mmap_page documentation in perf_event.h. 143 */ 144 if (data.cyc2ns_shift == 32) { 145 data.cyc2ns_shift = 31; 146 data.cyc2ns_mul >>= 1; 147 } 148 149 data.cyc2ns_offset = ns_now - 150 mul_u64_u32_shr(tsc_now, data.cyc2ns_mul, data.cyc2ns_shift); 151 152 c2n = per_cpu_ptr(&cyc2ns, cpu); 153 154 raw_write_seqcount_latch(&c2n->seq); 155 c2n->data[0] = data; 156 raw_write_seqcount_latch(&c2n->seq); 157 c2n->data[1] = data; 158 } 159 160 static void set_cyc2ns_scale(unsigned long khz, int cpu, unsigned long long tsc_now) 161 { 162 unsigned long flags; 163 164 local_irq_save(flags); 165 sched_clock_idle_sleep_event(); 166 167 if (khz) 168 __set_cyc2ns_scale(khz, cpu, tsc_now); 169 170 sched_clock_idle_wakeup_event(); 171 local_irq_restore(flags); 172 } 173 174 /* 175 * Initialize cyc2ns for boot cpu 176 */ 177 static void __init cyc2ns_init_boot_cpu(void) 178 { 179 struct cyc2ns *c2n = this_cpu_ptr(&cyc2ns); 180 181 seqcount_init(&c2n->seq); 182 __set_cyc2ns_scale(tsc_khz, smp_processor_id(), rdtsc()); 183 } 184 185 /* 186 * Secondary CPUs do not run through tsc_init(), so set up 187 * all the scale factors for all CPUs, assuming the same 188 * speed as the bootup CPU. (cpufreq notifiers will fix this 189 * up if their speed diverges) 190 */ 191 static void __init cyc2ns_init_secondary_cpus(void) 192 { 193 unsigned int cpu, this_cpu = smp_processor_id(); 194 struct cyc2ns *c2n = this_cpu_ptr(&cyc2ns); 195 struct cyc2ns_data *data = c2n->data; 196 197 for_each_possible_cpu(cpu) { 198 if (cpu != this_cpu) { 199 seqcount_init(&c2n->seq); 200 c2n = per_cpu_ptr(&cyc2ns, cpu); 201 c2n->data[0] = data[0]; 202 c2n->data[1] = data[1]; 203 } 204 } 205 } 206 207 /* 208 * Scheduler clock - returns current time in nanosec units. 209 */ 210 u64 native_sched_clock(void) 211 { 212 if (static_branch_likely(&__use_tsc)) { 213 u64 tsc_now = rdtsc(); 214 215 /* return the value in ns */ 216 return cycles_2_ns(tsc_now); 217 } 218 219 /* 220 * Fall back to jiffies if there's no TSC available: 221 * ( But note that we still use it if the TSC is marked 222 * unstable. We do this because unlike Time Of Day, 223 * the scheduler clock tolerates small errors and it's 224 * very important for it to be as fast as the platform 225 * can achieve it. ) 226 */ 227 228 /* No locking but a rare wrong value is not a big deal: */ 229 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ); 230 } 231 232 /* 233 * Generate a sched_clock if you already have a TSC value. 234 */ 235 u64 native_sched_clock_from_tsc(u64 tsc) 236 { 237 return cycles_2_ns(tsc); 238 } 239 240 /* We need to define a real function for sched_clock, to override the 241 weak default version */ 242 #ifdef CONFIG_PARAVIRT 243 unsigned long long sched_clock(void) 244 { 245 return paravirt_sched_clock(); 246 } 247 248 bool using_native_sched_clock(void) 249 { 250 return pv_time_ops.sched_clock == native_sched_clock; 251 } 252 #else 253 unsigned long long 254 sched_clock(void) __attribute__((alias("native_sched_clock"))); 255 256 bool using_native_sched_clock(void) { return true; } 257 #endif 258 259 int check_tsc_unstable(void) 260 { 261 return tsc_unstable; 262 } 263 EXPORT_SYMBOL_GPL(check_tsc_unstable); 264 265 #ifdef CONFIG_X86_TSC 266 int __init notsc_setup(char *str) 267 { 268 mark_tsc_unstable("boot parameter notsc"); 269 return 1; 270 } 271 #else 272 /* 273 * disable flag for tsc. Takes effect by clearing the TSC cpu flag 274 * in cpu/common.c 275 */ 276 int __init notsc_setup(char *str) 277 { 278 setup_clear_cpu_cap(X86_FEATURE_TSC); 279 return 1; 280 } 281 #endif 282 283 __setup("notsc", notsc_setup); 284 285 static int no_sched_irq_time; 286 287 static int __init tsc_setup(char *str) 288 { 289 if (!strcmp(str, "reliable")) 290 tsc_clocksource_reliable = 1; 291 if (!strncmp(str, "noirqtime", 9)) 292 no_sched_irq_time = 1; 293 if (!strcmp(str, "unstable")) 294 mark_tsc_unstable("boot parameter"); 295 return 1; 296 } 297 298 __setup("tsc=", tsc_setup); 299 300 #define MAX_RETRIES 5 301 #define SMI_TRESHOLD 50000 302 303 /* 304 * Read TSC and the reference counters. Take care of SMI disturbance 305 */ 306 static u64 tsc_read_refs(u64 *p, int hpet) 307 { 308 u64 t1, t2; 309 int i; 310 311 for (i = 0; i < MAX_RETRIES; i++) { 312 t1 = get_cycles(); 313 if (hpet) 314 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF; 315 else 316 *p = acpi_pm_read_early(); 317 t2 = get_cycles(); 318 if ((t2 - t1) < SMI_TRESHOLD) 319 return t2; 320 } 321 return ULLONG_MAX; 322 } 323 324 /* 325 * Calculate the TSC frequency from HPET reference 326 */ 327 static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2) 328 { 329 u64 tmp; 330 331 if (hpet2 < hpet1) 332 hpet2 += 0x100000000ULL; 333 hpet2 -= hpet1; 334 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD)); 335 do_div(tmp, 1000000); 336 deltatsc = div64_u64(deltatsc, tmp); 337 338 return (unsigned long) deltatsc; 339 } 340 341 /* 342 * Calculate the TSC frequency from PMTimer reference 343 */ 344 static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2) 345 { 346 u64 tmp; 347 348 if (!pm1 && !pm2) 349 return ULONG_MAX; 350 351 if (pm2 < pm1) 352 pm2 += (u64)ACPI_PM_OVRRUN; 353 pm2 -= pm1; 354 tmp = pm2 * 1000000000LL; 355 do_div(tmp, PMTMR_TICKS_PER_SEC); 356 do_div(deltatsc, tmp); 357 358 return (unsigned long) deltatsc; 359 } 360 361 #define CAL_MS 10 362 #define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS)) 363 #define CAL_PIT_LOOPS 1000 364 365 #define CAL2_MS 50 366 #define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS)) 367 #define CAL2_PIT_LOOPS 5000 368 369 370 /* 371 * Try to calibrate the TSC against the Programmable 372 * Interrupt Timer and return the frequency of the TSC 373 * in kHz. 374 * 375 * Return ULONG_MAX on failure to calibrate. 376 */ 377 static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin) 378 { 379 u64 tsc, t1, t2, delta; 380 unsigned long tscmin, tscmax; 381 int pitcnt; 382 383 if (!has_legacy_pic()) { 384 /* 385 * Relies on tsc_early_delay_calibrate() to have given us semi 386 * usable udelay(), wait for the same 50ms we would have with 387 * the PIT loop below. 388 */ 389 udelay(10 * USEC_PER_MSEC); 390 udelay(10 * USEC_PER_MSEC); 391 udelay(10 * USEC_PER_MSEC); 392 udelay(10 * USEC_PER_MSEC); 393 udelay(10 * USEC_PER_MSEC); 394 return ULONG_MAX; 395 } 396 397 /* Set the Gate high, disable speaker */ 398 outb((inb(0x61) & ~0x02) | 0x01, 0x61); 399 400 /* 401 * Setup CTC channel 2* for mode 0, (interrupt on terminal 402 * count mode), binary count. Set the latch register to 50ms 403 * (LSB then MSB) to begin countdown. 404 */ 405 outb(0xb0, 0x43); 406 outb(latch & 0xff, 0x42); 407 outb(latch >> 8, 0x42); 408 409 tsc = t1 = t2 = get_cycles(); 410 411 pitcnt = 0; 412 tscmax = 0; 413 tscmin = ULONG_MAX; 414 while ((inb(0x61) & 0x20) == 0) { 415 t2 = get_cycles(); 416 delta = t2 - tsc; 417 tsc = t2; 418 if ((unsigned long) delta < tscmin) 419 tscmin = (unsigned int) delta; 420 if ((unsigned long) delta > tscmax) 421 tscmax = (unsigned int) delta; 422 pitcnt++; 423 } 424 425 /* 426 * Sanity checks: 427 * 428 * If we were not able to read the PIT more than loopmin 429 * times, then we have been hit by a massive SMI 430 * 431 * If the maximum is 10 times larger than the minimum, 432 * then we got hit by an SMI as well. 433 */ 434 if (pitcnt < loopmin || tscmax > 10 * tscmin) 435 return ULONG_MAX; 436 437 /* Calculate the PIT value */ 438 delta = t2 - t1; 439 do_div(delta, ms); 440 return delta; 441 } 442 443 /* 444 * This reads the current MSB of the PIT counter, and 445 * checks if we are running on sufficiently fast and 446 * non-virtualized hardware. 447 * 448 * Our expectations are: 449 * 450 * - the PIT is running at roughly 1.19MHz 451 * 452 * - each IO is going to take about 1us on real hardware, 453 * but we allow it to be much faster (by a factor of 10) or 454 * _slightly_ slower (ie we allow up to a 2us read+counter 455 * update - anything else implies a unacceptably slow CPU 456 * or PIT for the fast calibration to work. 457 * 458 * - with 256 PIT ticks to read the value, we have 214us to 459 * see the same MSB (and overhead like doing a single TSC 460 * read per MSB value etc). 461 * 462 * - We're doing 2 reads per loop (LSB, MSB), and we expect 463 * them each to take about a microsecond on real hardware. 464 * So we expect a count value of around 100. But we'll be 465 * generous, and accept anything over 50. 466 * 467 * - if the PIT is stuck, and we see *many* more reads, we 468 * return early (and the next caller of pit_expect_msb() 469 * then consider it a failure when they don't see the 470 * next expected value). 471 * 472 * These expectations mean that we know that we have seen the 473 * transition from one expected value to another with a fairly 474 * high accuracy, and we didn't miss any events. We can thus 475 * use the TSC value at the transitions to calculate a pretty 476 * good value for the TSC frequencty. 477 */ 478 static inline int pit_verify_msb(unsigned char val) 479 { 480 /* Ignore LSB */ 481 inb(0x42); 482 return inb(0x42) == val; 483 } 484 485 static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap) 486 { 487 int count; 488 u64 tsc = 0, prev_tsc = 0; 489 490 for (count = 0; count < 50000; count++) { 491 if (!pit_verify_msb(val)) 492 break; 493 prev_tsc = tsc; 494 tsc = get_cycles(); 495 } 496 *deltap = get_cycles() - prev_tsc; 497 *tscp = tsc; 498 499 /* 500 * We require _some_ success, but the quality control 501 * will be based on the error terms on the TSC values. 502 */ 503 return count > 5; 504 } 505 506 /* 507 * How many MSB values do we want to see? We aim for 508 * a maximum error rate of 500ppm (in practice the 509 * real error is much smaller), but refuse to spend 510 * more than 50ms on it. 511 */ 512 #define MAX_QUICK_PIT_MS 50 513 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) 514 515 static unsigned long quick_pit_calibrate(void) 516 { 517 int i; 518 u64 tsc, delta; 519 unsigned long d1, d2; 520 521 if (!has_legacy_pic()) 522 return 0; 523 524 /* Set the Gate high, disable speaker */ 525 outb((inb(0x61) & ~0x02) | 0x01, 0x61); 526 527 /* 528 * Counter 2, mode 0 (one-shot), binary count 529 * 530 * NOTE! Mode 2 decrements by two (and then the 531 * output is flipped each time, giving the same 532 * final output frequency as a decrement-by-one), 533 * so mode 0 is much better when looking at the 534 * individual counts. 535 */ 536 outb(0xb0, 0x43); 537 538 /* Start at 0xffff */ 539 outb(0xff, 0x42); 540 outb(0xff, 0x42); 541 542 /* 543 * The PIT starts counting at the next edge, so we 544 * need to delay for a microsecond. The easiest way 545 * to do that is to just read back the 16-bit counter 546 * once from the PIT. 547 */ 548 pit_verify_msb(0); 549 550 if (pit_expect_msb(0xff, &tsc, &d1)) { 551 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) { 552 if (!pit_expect_msb(0xff-i, &delta, &d2)) 553 break; 554 555 delta -= tsc; 556 557 /* 558 * Extrapolate the error and fail fast if the error will 559 * never be below 500 ppm. 560 */ 561 if (i == 1 && 562 d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11) 563 return 0; 564 565 /* 566 * Iterate until the error is less than 500 ppm 567 */ 568 if (d1+d2 >= delta >> 11) 569 continue; 570 571 /* 572 * Check the PIT one more time to verify that 573 * all TSC reads were stable wrt the PIT. 574 * 575 * This also guarantees serialization of the 576 * last cycle read ('d2') in pit_expect_msb. 577 */ 578 if (!pit_verify_msb(0xfe - i)) 579 break; 580 goto success; 581 } 582 } 583 pr_info("Fast TSC calibration failed\n"); 584 return 0; 585 586 success: 587 /* 588 * Ok, if we get here, then we've seen the 589 * MSB of the PIT decrement 'i' times, and the 590 * error has shrunk to less than 500 ppm. 591 * 592 * As a result, we can depend on there not being 593 * any odd delays anywhere, and the TSC reads are 594 * reliable (within the error). 595 * 596 * kHz = ticks / time-in-seconds / 1000; 597 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000 598 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000) 599 */ 600 delta *= PIT_TICK_RATE; 601 do_div(delta, i*256*1000); 602 pr_info("Fast TSC calibration using PIT\n"); 603 return delta; 604 } 605 606 /** 607 * native_calibrate_tsc 608 * Determine TSC frequency via CPUID, else return 0. 609 */ 610 unsigned long native_calibrate_tsc(void) 611 { 612 unsigned int eax_denominator, ebx_numerator, ecx_hz, edx; 613 unsigned int crystal_khz; 614 615 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 616 return 0; 617 618 if (boot_cpu_data.cpuid_level < 0x15) 619 return 0; 620 621 eax_denominator = ebx_numerator = ecx_hz = edx = 0; 622 623 /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */ 624 cpuid(0x15, &eax_denominator, &ebx_numerator, &ecx_hz, &edx); 625 626 if (ebx_numerator == 0 || eax_denominator == 0) 627 return 0; 628 629 crystal_khz = ecx_hz / 1000; 630 631 if (crystal_khz == 0) { 632 switch (boot_cpu_data.x86_model) { 633 case INTEL_FAM6_SKYLAKE_MOBILE: 634 case INTEL_FAM6_SKYLAKE_DESKTOP: 635 case INTEL_FAM6_KABYLAKE_MOBILE: 636 case INTEL_FAM6_KABYLAKE_DESKTOP: 637 crystal_khz = 24000; /* 24.0 MHz */ 638 break; 639 case INTEL_FAM6_ATOM_DENVERTON: 640 crystal_khz = 25000; /* 25.0 MHz */ 641 break; 642 case INTEL_FAM6_ATOM_GOLDMONT: 643 crystal_khz = 19200; /* 19.2 MHz */ 644 break; 645 } 646 } 647 648 if (crystal_khz == 0) 649 return 0; 650 /* 651 * TSC frequency determined by CPUID is a "hardware reported" 652 * frequency and is the most accurate one so far we have. This 653 * is considered a known frequency. 654 */ 655 setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ); 656 657 /* 658 * For Atom SoCs TSC is the only reliable clocksource. 659 * Mark TSC reliable so no watchdog on it. 660 */ 661 if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT) 662 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); 663 664 return crystal_khz * ebx_numerator / eax_denominator; 665 } 666 667 static unsigned long cpu_khz_from_cpuid(void) 668 { 669 unsigned int eax_base_mhz, ebx_max_mhz, ecx_bus_mhz, edx; 670 671 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) 672 return 0; 673 674 if (boot_cpu_data.cpuid_level < 0x16) 675 return 0; 676 677 eax_base_mhz = ebx_max_mhz = ecx_bus_mhz = edx = 0; 678 679 cpuid(0x16, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx); 680 681 return eax_base_mhz * 1000; 682 } 683 684 /* 685 * calibrate cpu using pit, hpet, and ptimer methods. They are available 686 * later in boot after acpi is initialized. 687 */ 688 static unsigned long pit_hpet_ptimer_calibrate_cpu(void) 689 { 690 u64 tsc1, tsc2, delta, ref1, ref2; 691 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX; 692 unsigned long flags, latch, ms; 693 int hpet = is_hpet_enabled(), i, loopmin; 694 695 /* 696 * Run 5 calibration loops to get the lowest frequency value 697 * (the best estimate). We use two different calibration modes 698 * here: 699 * 700 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and 701 * load a timeout of 50ms. We read the time right after we 702 * started the timer and wait until the PIT count down reaches 703 * zero. In each wait loop iteration we read the TSC and check 704 * the delta to the previous read. We keep track of the min 705 * and max values of that delta. The delta is mostly defined 706 * by the IO time of the PIT access, so we can detect when a 707 * SMI/SMM disturbance happened between the two reads. If the 708 * maximum time is significantly larger than the minimum time, 709 * then we discard the result and have another try. 710 * 711 * 2) Reference counter. If available we use the HPET or the 712 * PMTIMER as a reference to check the sanity of that value. 713 * We use separate TSC readouts and check inside of the 714 * reference read for a SMI/SMM disturbance. We dicard 715 * disturbed values here as well. We do that around the PIT 716 * calibration delay loop as we have to wait for a certain 717 * amount of time anyway. 718 */ 719 720 /* Preset PIT loop values */ 721 latch = CAL_LATCH; 722 ms = CAL_MS; 723 loopmin = CAL_PIT_LOOPS; 724 725 for (i = 0; i < 3; i++) { 726 unsigned long tsc_pit_khz; 727 728 /* 729 * Read the start value and the reference count of 730 * hpet/pmtimer when available. Then do the PIT 731 * calibration, which will take at least 50ms, and 732 * read the end value. 733 */ 734 local_irq_save(flags); 735 tsc1 = tsc_read_refs(&ref1, hpet); 736 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin); 737 tsc2 = tsc_read_refs(&ref2, hpet); 738 local_irq_restore(flags); 739 740 /* Pick the lowest PIT TSC calibration so far */ 741 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz); 742 743 /* hpet or pmtimer available ? */ 744 if (ref1 == ref2) 745 continue; 746 747 /* Check, whether the sampling was disturbed by an SMI */ 748 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX) 749 continue; 750 751 tsc2 = (tsc2 - tsc1) * 1000000LL; 752 if (hpet) 753 tsc2 = calc_hpet_ref(tsc2, ref1, ref2); 754 else 755 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2); 756 757 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2); 758 759 /* Check the reference deviation */ 760 delta = ((u64) tsc_pit_min) * 100; 761 do_div(delta, tsc_ref_min); 762 763 /* 764 * If both calibration results are inside a 10% window 765 * then we can be sure, that the calibration 766 * succeeded. We break out of the loop right away. We 767 * use the reference value, as it is more precise. 768 */ 769 if (delta >= 90 && delta <= 110) { 770 pr_info("PIT calibration matches %s. %d loops\n", 771 hpet ? "HPET" : "PMTIMER", i + 1); 772 return tsc_ref_min; 773 } 774 775 /* 776 * Check whether PIT failed more than once. This 777 * happens in virtualized environments. We need to 778 * give the virtual PC a slightly longer timeframe for 779 * the HPET/PMTIMER to make the result precise. 780 */ 781 if (i == 1 && tsc_pit_min == ULONG_MAX) { 782 latch = CAL2_LATCH; 783 ms = CAL2_MS; 784 loopmin = CAL2_PIT_LOOPS; 785 } 786 } 787 788 /* 789 * Now check the results. 790 */ 791 if (tsc_pit_min == ULONG_MAX) { 792 /* PIT gave no useful value */ 793 pr_warn("Unable to calibrate against PIT\n"); 794 795 /* We don't have an alternative source, disable TSC */ 796 if (!hpet && !ref1 && !ref2) { 797 pr_notice("No reference (HPET/PMTIMER) available\n"); 798 return 0; 799 } 800 801 /* The alternative source failed as well, disable TSC */ 802 if (tsc_ref_min == ULONG_MAX) { 803 pr_warn("HPET/PMTIMER calibration failed\n"); 804 return 0; 805 } 806 807 /* Use the alternative source */ 808 pr_info("using %s reference calibration\n", 809 hpet ? "HPET" : "PMTIMER"); 810 811 return tsc_ref_min; 812 } 813 814 /* We don't have an alternative source, use the PIT calibration value */ 815 if (!hpet && !ref1 && !ref2) { 816 pr_info("Using PIT calibration value\n"); 817 return tsc_pit_min; 818 } 819 820 /* The alternative source failed, use the PIT calibration value */ 821 if (tsc_ref_min == ULONG_MAX) { 822 pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n"); 823 return tsc_pit_min; 824 } 825 826 /* 827 * The calibration values differ too much. In doubt, we use 828 * the PIT value as we know that there are PMTIMERs around 829 * running at double speed. At least we let the user know: 830 */ 831 pr_warn("PIT calibration deviates from %s: %lu %lu\n", 832 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min); 833 pr_info("Using PIT calibration value\n"); 834 return tsc_pit_min; 835 } 836 837 /** 838 * native_calibrate_cpu_early - can calibrate the cpu early in boot 839 */ 840 unsigned long native_calibrate_cpu_early(void) 841 { 842 unsigned long flags, fast_calibrate = cpu_khz_from_cpuid(); 843 844 if (!fast_calibrate) 845 fast_calibrate = cpu_khz_from_msr(); 846 if (!fast_calibrate) { 847 local_irq_save(flags); 848 fast_calibrate = quick_pit_calibrate(); 849 local_irq_restore(flags); 850 } 851 return fast_calibrate; 852 } 853 854 855 /** 856 * native_calibrate_cpu - calibrate the cpu 857 */ 858 static unsigned long native_calibrate_cpu(void) 859 { 860 unsigned long tsc_freq = native_calibrate_cpu_early(); 861 862 if (!tsc_freq) 863 tsc_freq = pit_hpet_ptimer_calibrate_cpu(); 864 865 return tsc_freq; 866 } 867 868 void recalibrate_cpu_khz(void) 869 { 870 #ifndef CONFIG_SMP 871 unsigned long cpu_khz_old = cpu_khz; 872 873 if (!boot_cpu_has(X86_FEATURE_TSC)) 874 return; 875 876 cpu_khz = x86_platform.calibrate_cpu(); 877 tsc_khz = x86_platform.calibrate_tsc(); 878 if (tsc_khz == 0) 879 tsc_khz = cpu_khz; 880 else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz) 881 cpu_khz = tsc_khz; 882 cpu_data(0).loops_per_jiffy = cpufreq_scale(cpu_data(0).loops_per_jiffy, 883 cpu_khz_old, cpu_khz); 884 #endif 885 } 886 887 EXPORT_SYMBOL(recalibrate_cpu_khz); 888 889 890 static unsigned long long cyc2ns_suspend; 891 892 void tsc_save_sched_clock_state(void) 893 { 894 if (!sched_clock_stable()) 895 return; 896 897 cyc2ns_suspend = sched_clock(); 898 } 899 900 /* 901 * Even on processors with invariant TSC, TSC gets reset in some the 902 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to 903 * arbitrary value (still sync'd across cpu's) during resume from such sleep 904 * states. To cope up with this, recompute the cyc2ns_offset for each cpu so 905 * that sched_clock() continues from the point where it was left off during 906 * suspend. 907 */ 908 void tsc_restore_sched_clock_state(void) 909 { 910 unsigned long long offset; 911 unsigned long flags; 912 int cpu; 913 914 if (!sched_clock_stable()) 915 return; 916 917 local_irq_save(flags); 918 919 /* 920 * We're coming out of suspend, there's no concurrency yet; don't 921 * bother being nice about the RCU stuff, just write to both 922 * data fields. 923 */ 924 925 this_cpu_write(cyc2ns.data[0].cyc2ns_offset, 0); 926 this_cpu_write(cyc2ns.data[1].cyc2ns_offset, 0); 927 928 offset = cyc2ns_suspend - sched_clock(); 929 930 for_each_possible_cpu(cpu) { 931 per_cpu(cyc2ns.data[0].cyc2ns_offset, cpu) = offset; 932 per_cpu(cyc2ns.data[1].cyc2ns_offset, cpu) = offset; 933 } 934 935 local_irq_restore(flags); 936 } 937 938 #ifdef CONFIG_CPU_FREQ 939 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency 940 * changes. 941 * 942 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's 943 * not that important because current Opteron setups do not support 944 * scaling on SMP anyroads. 945 * 946 * Should fix up last_tsc too. Currently gettimeofday in the 947 * first tick after the change will be slightly wrong. 948 */ 949 950 static unsigned int ref_freq; 951 static unsigned long loops_per_jiffy_ref; 952 static unsigned long tsc_khz_ref; 953 954 static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 955 void *data) 956 { 957 struct cpufreq_freqs *freq = data; 958 unsigned long *lpj; 959 960 lpj = &boot_cpu_data.loops_per_jiffy; 961 #ifdef CONFIG_SMP 962 if (!(freq->flags & CPUFREQ_CONST_LOOPS)) 963 lpj = &cpu_data(freq->cpu).loops_per_jiffy; 964 #endif 965 966 if (!ref_freq) { 967 ref_freq = freq->old; 968 loops_per_jiffy_ref = *lpj; 969 tsc_khz_ref = tsc_khz; 970 } 971 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || 972 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) { 973 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new); 974 975 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new); 976 if (!(freq->flags & CPUFREQ_CONST_LOOPS)) 977 mark_tsc_unstable("cpufreq changes"); 978 979 set_cyc2ns_scale(tsc_khz, freq->cpu, rdtsc()); 980 } 981 982 return 0; 983 } 984 985 static struct notifier_block time_cpufreq_notifier_block = { 986 .notifier_call = time_cpufreq_notifier 987 }; 988 989 static int __init cpufreq_register_tsc_scaling(void) 990 { 991 if (!boot_cpu_has(X86_FEATURE_TSC)) 992 return 0; 993 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 994 return 0; 995 cpufreq_register_notifier(&time_cpufreq_notifier_block, 996 CPUFREQ_TRANSITION_NOTIFIER); 997 return 0; 998 } 999 1000 core_initcall(cpufreq_register_tsc_scaling); 1001 1002 #endif /* CONFIG_CPU_FREQ */ 1003 1004 #define ART_CPUID_LEAF (0x15) 1005 #define ART_MIN_DENOMINATOR (1) 1006 1007 1008 /* 1009 * If ART is present detect the numerator:denominator to convert to TSC 1010 */ 1011 static void __init detect_art(void) 1012 { 1013 unsigned int unused[2]; 1014 1015 if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF) 1016 return; 1017 1018 /* 1019 * Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required, 1020 * and the TSC counter resets must not occur asynchronously. 1021 */ 1022 if (boot_cpu_has(X86_FEATURE_HYPERVISOR) || 1023 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC) || 1024 !boot_cpu_has(X86_FEATURE_TSC_ADJUST) || 1025 tsc_async_resets) 1026 return; 1027 1028 cpuid(ART_CPUID_LEAF, &art_to_tsc_denominator, 1029 &art_to_tsc_numerator, unused, unused+1); 1030 1031 if (art_to_tsc_denominator < ART_MIN_DENOMINATOR) 1032 return; 1033 1034 rdmsrl(MSR_IA32_TSC_ADJUST, art_to_tsc_offset); 1035 1036 /* Make this sticky over multiple CPU init calls */ 1037 setup_force_cpu_cap(X86_FEATURE_ART); 1038 } 1039 1040 1041 /* clocksource code */ 1042 1043 static void tsc_resume(struct clocksource *cs) 1044 { 1045 tsc_verify_tsc_adjust(true); 1046 } 1047 1048 /* 1049 * We used to compare the TSC to the cycle_last value in the clocksource 1050 * structure to avoid a nasty time-warp. This can be observed in a 1051 * very small window right after one CPU updated cycle_last under 1052 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which 1053 * is smaller than the cycle_last reference value due to a TSC which 1054 * is slighty behind. This delta is nowhere else observable, but in 1055 * that case it results in a forward time jump in the range of hours 1056 * due to the unsigned delta calculation of the time keeping core 1057 * code, which is necessary to support wrapping clocksources like pm 1058 * timer. 1059 * 1060 * This sanity check is now done in the core timekeeping code. 1061 * checking the result of read_tsc() - cycle_last for being negative. 1062 * That works because CLOCKSOURCE_MASK(64) does not mask out any bit. 1063 */ 1064 static u64 read_tsc(struct clocksource *cs) 1065 { 1066 return (u64)rdtsc_ordered(); 1067 } 1068 1069 static void tsc_cs_mark_unstable(struct clocksource *cs) 1070 { 1071 if (tsc_unstable) 1072 return; 1073 1074 tsc_unstable = 1; 1075 if (using_native_sched_clock()) 1076 clear_sched_clock_stable(); 1077 disable_sched_clock_irqtime(); 1078 pr_info("Marking TSC unstable due to clocksource watchdog\n"); 1079 } 1080 1081 static void tsc_cs_tick_stable(struct clocksource *cs) 1082 { 1083 if (tsc_unstable) 1084 return; 1085 1086 if (using_native_sched_clock()) 1087 sched_clock_tick_stable(); 1088 } 1089 1090 /* 1091 * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc() 1092 */ 1093 static struct clocksource clocksource_tsc_early = { 1094 .name = "tsc-early", 1095 .rating = 299, 1096 .read = read_tsc, 1097 .mask = CLOCKSOURCE_MASK(64), 1098 .flags = CLOCK_SOURCE_IS_CONTINUOUS | 1099 CLOCK_SOURCE_MUST_VERIFY, 1100 .archdata = { .vclock_mode = VCLOCK_TSC }, 1101 .resume = tsc_resume, 1102 .mark_unstable = tsc_cs_mark_unstable, 1103 .tick_stable = tsc_cs_tick_stable, 1104 .list = LIST_HEAD_INIT(clocksource_tsc_early.list), 1105 }; 1106 1107 /* 1108 * Must mark VALID_FOR_HRES early such that when we unregister tsc_early 1109 * this one will immediately take over. We will only register if TSC has 1110 * been found good. 1111 */ 1112 static struct clocksource clocksource_tsc = { 1113 .name = "tsc", 1114 .rating = 300, 1115 .read = read_tsc, 1116 .mask = CLOCKSOURCE_MASK(64), 1117 .flags = CLOCK_SOURCE_IS_CONTINUOUS | 1118 CLOCK_SOURCE_VALID_FOR_HRES | 1119 CLOCK_SOURCE_MUST_VERIFY, 1120 .archdata = { .vclock_mode = VCLOCK_TSC }, 1121 .resume = tsc_resume, 1122 .mark_unstable = tsc_cs_mark_unstable, 1123 .tick_stable = tsc_cs_tick_stable, 1124 .list = LIST_HEAD_INIT(clocksource_tsc.list), 1125 }; 1126 1127 void mark_tsc_unstable(char *reason) 1128 { 1129 if (tsc_unstable) 1130 return; 1131 1132 tsc_unstable = 1; 1133 if (using_native_sched_clock()) 1134 clear_sched_clock_stable(); 1135 disable_sched_clock_irqtime(); 1136 pr_info("Marking TSC unstable due to %s\n", reason); 1137 1138 clocksource_mark_unstable(&clocksource_tsc_early); 1139 clocksource_mark_unstable(&clocksource_tsc); 1140 } 1141 1142 EXPORT_SYMBOL_GPL(mark_tsc_unstable); 1143 1144 static void __init check_system_tsc_reliable(void) 1145 { 1146 #if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC) 1147 if (is_geode_lx()) { 1148 /* RTSC counts during suspend */ 1149 #define RTSC_SUSP 0x100 1150 unsigned long res_low, res_high; 1151 1152 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high); 1153 /* Geode_LX - the OLPC CPU has a very reliable TSC */ 1154 if (res_low & RTSC_SUSP) 1155 tsc_clocksource_reliable = 1; 1156 } 1157 #endif 1158 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) 1159 tsc_clocksource_reliable = 1; 1160 } 1161 1162 /* 1163 * Make an educated guess if the TSC is trustworthy and synchronized 1164 * over all CPUs. 1165 */ 1166 int unsynchronized_tsc(void) 1167 { 1168 if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_unstable) 1169 return 1; 1170 1171 #ifdef CONFIG_SMP 1172 if (apic_is_clustered_box()) 1173 return 1; 1174 #endif 1175 1176 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 1177 return 0; 1178 1179 if (tsc_clocksource_reliable) 1180 return 0; 1181 /* 1182 * Intel systems are normally all synchronized. 1183 * Exceptions must mark TSC as unstable: 1184 */ 1185 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) { 1186 /* assume multi socket systems are not synchronized: */ 1187 if (num_possible_cpus() > 1) 1188 return 1; 1189 } 1190 1191 return 0; 1192 } 1193 1194 /* 1195 * Convert ART to TSC given numerator/denominator found in detect_art() 1196 */ 1197 struct system_counterval_t convert_art_to_tsc(u64 art) 1198 { 1199 u64 tmp, res, rem; 1200 1201 rem = do_div(art, art_to_tsc_denominator); 1202 1203 res = art * art_to_tsc_numerator; 1204 tmp = rem * art_to_tsc_numerator; 1205 1206 do_div(tmp, art_to_tsc_denominator); 1207 res += tmp + art_to_tsc_offset; 1208 1209 return (struct system_counterval_t) {.cs = art_related_clocksource, 1210 .cycles = res}; 1211 } 1212 EXPORT_SYMBOL(convert_art_to_tsc); 1213 1214 /** 1215 * convert_art_ns_to_tsc() - Convert ART in nanoseconds to TSC. 1216 * @art_ns: ART (Always Running Timer) in unit of nanoseconds 1217 * 1218 * PTM requires all timestamps to be in units of nanoseconds. When user 1219 * software requests a cross-timestamp, this function converts system timestamp 1220 * to TSC. 1221 * 1222 * This is valid when CPU feature flag X86_FEATURE_TSC_KNOWN_FREQ is set 1223 * indicating the tsc_khz is derived from CPUID[15H]. Drivers should check 1224 * that this flag is set before conversion to TSC is attempted. 1225 * 1226 * Return: 1227 * struct system_counterval_t - system counter value with the pointer to the 1228 * corresponding clocksource 1229 * @cycles: System counter value 1230 * @cs: Clocksource corresponding to system counter value. Used 1231 * by timekeeping code to verify comparibility of two cycle 1232 * values. 1233 */ 1234 1235 struct system_counterval_t convert_art_ns_to_tsc(u64 art_ns) 1236 { 1237 u64 tmp, res, rem; 1238 1239 rem = do_div(art_ns, USEC_PER_SEC); 1240 1241 res = art_ns * tsc_khz; 1242 tmp = rem * tsc_khz; 1243 1244 do_div(tmp, USEC_PER_SEC); 1245 res += tmp; 1246 1247 return (struct system_counterval_t) { .cs = art_related_clocksource, 1248 .cycles = res}; 1249 } 1250 EXPORT_SYMBOL(convert_art_ns_to_tsc); 1251 1252 1253 static void tsc_refine_calibration_work(struct work_struct *work); 1254 static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work); 1255 /** 1256 * tsc_refine_calibration_work - Further refine tsc freq calibration 1257 * @work - ignored. 1258 * 1259 * This functions uses delayed work over a period of a 1260 * second to further refine the TSC freq value. Since this is 1261 * timer based, instead of loop based, we don't block the boot 1262 * process while this longer calibration is done. 1263 * 1264 * If there are any calibration anomalies (too many SMIs, etc), 1265 * or the refined calibration is off by 1% of the fast early 1266 * calibration, we throw out the new calibration and use the 1267 * early calibration. 1268 */ 1269 static void tsc_refine_calibration_work(struct work_struct *work) 1270 { 1271 static u64 tsc_start = -1, ref_start; 1272 static int hpet; 1273 u64 tsc_stop, ref_stop, delta; 1274 unsigned long freq; 1275 int cpu; 1276 1277 /* Don't bother refining TSC on unstable systems */ 1278 if (tsc_unstable) 1279 goto unreg; 1280 1281 /* 1282 * Since the work is started early in boot, we may be 1283 * delayed the first time we expire. So set the workqueue 1284 * again once we know timers are working. 1285 */ 1286 if (tsc_start == -1) { 1287 /* 1288 * Only set hpet once, to avoid mixing hardware 1289 * if the hpet becomes enabled later. 1290 */ 1291 hpet = is_hpet_enabled(); 1292 schedule_delayed_work(&tsc_irqwork, HZ); 1293 tsc_start = tsc_read_refs(&ref_start, hpet); 1294 return; 1295 } 1296 1297 tsc_stop = tsc_read_refs(&ref_stop, hpet); 1298 1299 /* hpet or pmtimer available ? */ 1300 if (ref_start == ref_stop) 1301 goto out; 1302 1303 /* Check, whether the sampling was disturbed by an SMI */ 1304 if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX) 1305 goto out; 1306 1307 delta = tsc_stop - tsc_start; 1308 delta *= 1000000LL; 1309 if (hpet) 1310 freq = calc_hpet_ref(delta, ref_start, ref_stop); 1311 else 1312 freq = calc_pmtimer_ref(delta, ref_start, ref_stop); 1313 1314 /* Make sure we're within 1% */ 1315 if (abs(tsc_khz - freq) > tsc_khz/100) 1316 goto out; 1317 1318 tsc_khz = freq; 1319 pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n", 1320 (unsigned long)tsc_khz / 1000, 1321 (unsigned long)tsc_khz % 1000); 1322 1323 /* Inform the TSC deadline clockevent devices about the recalibration */ 1324 lapic_update_tsc_freq(); 1325 1326 /* Update the sched_clock() rate to match the clocksource one */ 1327 for_each_possible_cpu(cpu) 1328 set_cyc2ns_scale(tsc_khz, cpu, tsc_stop); 1329 1330 out: 1331 if (tsc_unstable) 1332 goto unreg; 1333 1334 if (boot_cpu_has(X86_FEATURE_ART)) 1335 art_related_clocksource = &clocksource_tsc; 1336 clocksource_register_khz(&clocksource_tsc, tsc_khz); 1337 unreg: 1338 clocksource_unregister(&clocksource_tsc_early); 1339 } 1340 1341 1342 static int __init init_tsc_clocksource(void) 1343 { 1344 if (!boot_cpu_has(X86_FEATURE_TSC) || !tsc_khz) 1345 return 0; 1346 1347 if (tsc_unstable) 1348 goto unreg; 1349 1350 if (tsc_clocksource_reliable) 1351 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY; 1352 1353 if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3)) 1354 clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP; 1355 1356 /* 1357 * When TSC frequency is known (retrieved via MSR or CPUID), we skip 1358 * the refined calibration and directly register it as a clocksource. 1359 */ 1360 if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) { 1361 if (boot_cpu_has(X86_FEATURE_ART)) 1362 art_related_clocksource = &clocksource_tsc; 1363 clocksource_register_khz(&clocksource_tsc, tsc_khz); 1364 unreg: 1365 clocksource_unregister(&clocksource_tsc_early); 1366 return 0; 1367 } 1368 1369 schedule_delayed_work(&tsc_irqwork, 0); 1370 return 0; 1371 } 1372 /* 1373 * We use device_initcall here, to ensure we run after the hpet 1374 * is fully initialized, which may occur at fs_initcall time. 1375 */ 1376 device_initcall(init_tsc_clocksource); 1377 1378 static bool __init determine_cpu_tsc_frequencies(bool early) 1379 { 1380 /* Make sure that cpu and tsc are not already calibrated */ 1381 WARN_ON(cpu_khz || tsc_khz); 1382 1383 if (early) { 1384 cpu_khz = x86_platform.calibrate_cpu(); 1385 tsc_khz = x86_platform.calibrate_tsc(); 1386 } else { 1387 /* We should not be here with non-native cpu calibration */ 1388 WARN_ON(x86_platform.calibrate_cpu != native_calibrate_cpu); 1389 cpu_khz = pit_hpet_ptimer_calibrate_cpu(); 1390 } 1391 1392 /* 1393 * Trust non-zero tsc_khz as authoritative, 1394 * and use it to sanity check cpu_khz, 1395 * which will be off if system timer is off. 1396 */ 1397 if (tsc_khz == 0) 1398 tsc_khz = cpu_khz; 1399 else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz) 1400 cpu_khz = tsc_khz; 1401 1402 if (tsc_khz == 0) 1403 return false; 1404 1405 pr_info("Detected %lu.%03lu MHz processor\n", 1406 (unsigned long)cpu_khz / KHZ, 1407 (unsigned long)cpu_khz % KHZ); 1408 1409 if (cpu_khz != tsc_khz) { 1410 pr_info("Detected %lu.%03lu MHz TSC", 1411 (unsigned long)tsc_khz / KHZ, 1412 (unsigned long)tsc_khz % KHZ); 1413 } 1414 return true; 1415 } 1416 1417 static unsigned long __init get_loops_per_jiffy(void) 1418 { 1419 u64 lpj = (u64)tsc_khz * KHZ; 1420 1421 do_div(lpj, HZ); 1422 return lpj; 1423 } 1424 1425 static void __init tsc_enable_sched_clock(void) 1426 { 1427 /* Sanitize TSC ADJUST before cyc2ns gets initialized */ 1428 tsc_store_and_check_tsc_adjust(true); 1429 cyc2ns_init_boot_cpu(); 1430 static_branch_enable(&__use_tsc); 1431 } 1432 1433 void __init tsc_early_init(void) 1434 { 1435 if (!boot_cpu_has(X86_FEATURE_TSC)) 1436 return; 1437 /* Don't change UV TSC multi-chassis synchronization */ 1438 if (is_early_uv_system()) 1439 return; 1440 if (!determine_cpu_tsc_frequencies(true)) 1441 return; 1442 loops_per_jiffy = get_loops_per_jiffy(); 1443 1444 tsc_enable_sched_clock(); 1445 } 1446 1447 void __init tsc_init(void) 1448 { 1449 /* 1450 * native_calibrate_cpu_early can only calibrate using methods that are 1451 * available early in boot. 1452 */ 1453 if (x86_platform.calibrate_cpu == native_calibrate_cpu_early) 1454 x86_platform.calibrate_cpu = native_calibrate_cpu; 1455 1456 if (!boot_cpu_has(X86_FEATURE_TSC)) { 1457 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 1458 return; 1459 } 1460 1461 if (!tsc_khz) { 1462 /* We failed to determine frequencies earlier, try again */ 1463 if (!determine_cpu_tsc_frequencies(false)) { 1464 mark_tsc_unstable("could not calculate TSC khz"); 1465 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 1466 return; 1467 } 1468 tsc_enable_sched_clock(); 1469 } 1470 1471 cyc2ns_init_secondary_cpus(); 1472 1473 if (!no_sched_irq_time) 1474 enable_sched_clock_irqtime(); 1475 1476 lpj_fine = get_loops_per_jiffy(); 1477 use_tsc_delay(); 1478 1479 check_system_tsc_reliable(); 1480 1481 if (unsynchronized_tsc()) { 1482 mark_tsc_unstable("TSCs unsynchronized"); 1483 return; 1484 } 1485 1486 clocksource_register_khz(&clocksource_tsc_early, tsc_khz); 1487 detect_art(); 1488 } 1489 1490 #ifdef CONFIG_SMP 1491 /* 1492 * If we have a constant TSC and are using the TSC for the delay loop, 1493 * we can skip clock calibration if another cpu in the same socket has already 1494 * been calibrated. This assumes that CONSTANT_TSC applies to all 1495 * cpus in the socket - this should be a safe assumption. 1496 */ 1497 unsigned long calibrate_delay_is_known(void) 1498 { 1499 int sibling, cpu = smp_processor_id(); 1500 int constant_tsc = cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC); 1501 const struct cpumask *mask = topology_core_cpumask(cpu); 1502 1503 if (!constant_tsc || !mask) 1504 return 0; 1505 1506 sibling = cpumask_any_but(mask, cpu); 1507 if (sibling < nr_cpu_ids) 1508 return cpu_data(sibling).loops_per_jiffy; 1509 return 0; 1510 } 1511 #endif 1512