1 #include <linux/kernel.h> 2 #include <linux/sched.h> 3 #include <linux/init.h> 4 #include <linux/module.h> 5 #include <linux/timer.h> 6 #include <linux/acpi_pmtmr.h> 7 #include <linux/cpufreq.h> 8 #include <linux/dmi.h> 9 #include <linux/delay.h> 10 #include <linux/clocksource.h> 11 #include <linux/percpu.h> 12 #include <linux/timex.h> 13 14 #include <asm/hpet.h> 15 #include <asm/timer.h> 16 #include <asm/vgtod.h> 17 #include <asm/time.h> 18 #include <asm/delay.h> 19 #include <asm/hypervisor.h> 20 21 unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */ 22 EXPORT_SYMBOL(cpu_khz); 23 24 unsigned int __read_mostly tsc_khz; 25 EXPORT_SYMBOL(tsc_khz); 26 27 /* 28 * TSC can be unstable due to cpufreq or due to unsynced TSCs 29 */ 30 static int __read_mostly tsc_unstable; 31 32 /* native_sched_clock() is called before tsc_init(), so 33 we must start with the TSC soft disabled to prevent 34 erroneous rdtsc usage on !cpu_has_tsc processors */ 35 static int __read_mostly tsc_disabled = -1; 36 37 static int tsc_clocksource_reliable; 38 /* 39 * Scheduler clock - returns current time in nanosec units. 40 */ 41 u64 native_sched_clock(void) 42 { 43 u64 this_offset; 44 45 /* 46 * Fall back to jiffies if there's no TSC available: 47 * ( But note that we still use it if the TSC is marked 48 * unstable. We do this because unlike Time Of Day, 49 * the scheduler clock tolerates small errors and it's 50 * very important for it to be as fast as the platform 51 * can achive it. ) 52 */ 53 if (unlikely(tsc_disabled)) { 54 /* No locking but a rare wrong value is not a big deal: */ 55 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ); 56 } 57 58 /* read the Time Stamp Counter: */ 59 rdtscll(this_offset); 60 61 /* return the value in ns */ 62 return __cycles_2_ns(this_offset); 63 } 64 65 /* We need to define a real function for sched_clock, to override the 66 weak default version */ 67 #ifdef CONFIG_PARAVIRT 68 unsigned long long sched_clock(void) 69 { 70 return paravirt_sched_clock(); 71 } 72 #else 73 unsigned long long 74 sched_clock(void) __attribute__((alias("native_sched_clock"))); 75 #endif 76 77 int check_tsc_unstable(void) 78 { 79 return tsc_unstable; 80 } 81 EXPORT_SYMBOL_GPL(check_tsc_unstable); 82 83 #ifdef CONFIG_X86_TSC 84 int __init notsc_setup(char *str) 85 { 86 printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, " 87 "cannot disable TSC completely.\n"); 88 tsc_disabled = 1; 89 return 1; 90 } 91 #else 92 /* 93 * disable flag for tsc. Takes effect by clearing the TSC cpu flag 94 * in cpu/common.c 95 */ 96 int __init notsc_setup(char *str) 97 { 98 setup_clear_cpu_cap(X86_FEATURE_TSC); 99 return 1; 100 } 101 #endif 102 103 __setup("notsc", notsc_setup); 104 105 static int __init tsc_setup(char *str) 106 { 107 if (!strcmp(str, "reliable")) 108 tsc_clocksource_reliable = 1; 109 return 1; 110 } 111 112 __setup("tsc=", tsc_setup); 113 114 #define MAX_RETRIES 5 115 #define SMI_TRESHOLD 50000 116 117 /* 118 * Read TSC and the reference counters. Take care of SMI disturbance 119 */ 120 static u64 tsc_read_refs(u64 *p, int hpet) 121 { 122 u64 t1, t2; 123 int i; 124 125 for (i = 0; i < MAX_RETRIES; i++) { 126 t1 = get_cycles(); 127 if (hpet) 128 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF; 129 else 130 *p = acpi_pm_read_early(); 131 t2 = get_cycles(); 132 if ((t2 - t1) < SMI_TRESHOLD) 133 return t2; 134 } 135 return ULLONG_MAX; 136 } 137 138 /* 139 * Calculate the TSC frequency from HPET reference 140 */ 141 static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2) 142 { 143 u64 tmp; 144 145 if (hpet2 < hpet1) 146 hpet2 += 0x100000000ULL; 147 hpet2 -= hpet1; 148 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD)); 149 do_div(tmp, 1000000); 150 do_div(deltatsc, tmp); 151 152 return (unsigned long) deltatsc; 153 } 154 155 /* 156 * Calculate the TSC frequency from PMTimer reference 157 */ 158 static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2) 159 { 160 u64 tmp; 161 162 if (!pm1 && !pm2) 163 return ULONG_MAX; 164 165 if (pm2 < pm1) 166 pm2 += (u64)ACPI_PM_OVRRUN; 167 pm2 -= pm1; 168 tmp = pm2 * 1000000000LL; 169 do_div(tmp, PMTMR_TICKS_PER_SEC); 170 do_div(deltatsc, tmp); 171 172 return (unsigned long) deltatsc; 173 } 174 175 #define CAL_MS 10 176 #define CAL_LATCH (CLOCK_TICK_RATE / (1000 / CAL_MS)) 177 #define CAL_PIT_LOOPS 1000 178 179 #define CAL2_MS 50 180 #define CAL2_LATCH (CLOCK_TICK_RATE / (1000 / CAL2_MS)) 181 #define CAL2_PIT_LOOPS 5000 182 183 184 /* 185 * Try to calibrate the TSC against the Programmable 186 * Interrupt Timer and return the frequency of the TSC 187 * in kHz. 188 * 189 * Return ULONG_MAX on failure to calibrate. 190 */ 191 static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin) 192 { 193 u64 tsc, t1, t2, delta; 194 unsigned long tscmin, tscmax; 195 int pitcnt; 196 197 /* Set the Gate high, disable speaker */ 198 outb((inb(0x61) & ~0x02) | 0x01, 0x61); 199 200 /* 201 * Setup CTC channel 2* for mode 0, (interrupt on terminal 202 * count mode), binary count. Set the latch register to 50ms 203 * (LSB then MSB) to begin countdown. 204 */ 205 outb(0xb0, 0x43); 206 outb(latch & 0xff, 0x42); 207 outb(latch >> 8, 0x42); 208 209 tsc = t1 = t2 = get_cycles(); 210 211 pitcnt = 0; 212 tscmax = 0; 213 tscmin = ULONG_MAX; 214 while ((inb(0x61) & 0x20) == 0) { 215 t2 = get_cycles(); 216 delta = t2 - tsc; 217 tsc = t2; 218 if ((unsigned long) delta < tscmin) 219 tscmin = (unsigned int) delta; 220 if ((unsigned long) delta > tscmax) 221 tscmax = (unsigned int) delta; 222 pitcnt++; 223 } 224 225 /* 226 * Sanity checks: 227 * 228 * If we were not able to read the PIT more than loopmin 229 * times, then we have been hit by a massive SMI 230 * 231 * If the maximum is 10 times larger than the minimum, 232 * then we got hit by an SMI as well. 233 */ 234 if (pitcnt < loopmin || tscmax > 10 * tscmin) 235 return ULONG_MAX; 236 237 /* Calculate the PIT value */ 238 delta = t2 - t1; 239 do_div(delta, ms); 240 return delta; 241 } 242 243 /* 244 * This reads the current MSB of the PIT counter, and 245 * checks if we are running on sufficiently fast and 246 * non-virtualized hardware. 247 * 248 * Our expectations are: 249 * 250 * - the PIT is running at roughly 1.19MHz 251 * 252 * - each IO is going to take about 1us on real hardware, 253 * but we allow it to be much faster (by a factor of 10) or 254 * _slightly_ slower (ie we allow up to a 2us read+counter 255 * update - anything else implies a unacceptably slow CPU 256 * or PIT for the fast calibration to work. 257 * 258 * - with 256 PIT ticks to read the value, we have 214us to 259 * see the same MSB (and overhead like doing a single TSC 260 * read per MSB value etc). 261 * 262 * - We're doing 2 reads per loop (LSB, MSB), and we expect 263 * them each to take about a microsecond on real hardware. 264 * So we expect a count value of around 100. But we'll be 265 * generous, and accept anything over 50. 266 * 267 * - if the PIT is stuck, and we see *many* more reads, we 268 * return early (and the next caller of pit_expect_msb() 269 * then consider it a failure when they don't see the 270 * next expected value). 271 * 272 * These expectations mean that we know that we have seen the 273 * transition from one expected value to another with a fairly 274 * high accuracy, and we didn't miss any events. We can thus 275 * use the TSC value at the transitions to calculate a pretty 276 * good value for the TSC frequencty. 277 */ 278 static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap) 279 { 280 int count; 281 u64 tsc = 0; 282 283 for (count = 0; count < 50000; count++) { 284 /* Ignore LSB */ 285 inb(0x42); 286 if (inb(0x42) != val) 287 break; 288 tsc = get_cycles(); 289 } 290 *deltap = get_cycles() - tsc; 291 *tscp = tsc; 292 293 /* 294 * We require _some_ success, but the quality control 295 * will be based on the error terms on the TSC values. 296 */ 297 return count > 5; 298 } 299 300 /* 301 * How many MSB values do we want to see? We aim for 302 * a maximum error rate of 500ppm (in practice the 303 * real error is much smaller), but refuse to spend 304 * more than 25ms on it. 305 */ 306 #define MAX_QUICK_PIT_MS 25 307 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) 308 309 static unsigned long quick_pit_calibrate(void) 310 { 311 int i; 312 u64 tsc, delta; 313 unsigned long d1, d2; 314 315 /* Set the Gate high, disable speaker */ 316 outb((inb(0x61) & ~0x02) | 0x01, 0x61); 317 318 /* 319 * Counter 2, mode 0 (one-shot), binary count 320 * 321 * NOTE! Mode 2 decrements by two (and then the 322 * output is flipped each time, giving the same 323 * final output frequency as a decrement-by-one), 324 * so mode 0 is much better when looking at the 325 * individual counts. 326 */ 327 outb(0xb0, 0x43); 328 329 /* Start at 0xffff */ 330 outb(0xff, 0x42); 331 outb(0xff, 0x42); 332 333 /* 334 * The PIT starts counting at the next edge, so we 335 * need to delay for a microsecond. The easiest way 336 * to do that is to just read back the 16-bit counter 337 * once from the PIT. 338 */ 339 inb(0x42); 340 inb(0x42); 341 342 if (pit_expect_msb(0xff, &tsc, &d1)) { 343 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) { 344 if (!pit_expect_msb(0xff-i, &delta, &d2)) 345 break; 346 347 /* 348 * Iterate until the error is less than 500 ppm 349 */ 350 delta -= tsc; 351 if (d1+d2 < delta >> 11) 352 goto success; 353 } 354 } 355 printk("Fast TSC calibration failed\n"); 356 return 0; 357 358 success: 359 /* 360 * Ok, if we get here, then we've seen the 361 * MSB of the PIT decrement 'i' times, and the 362 * error has shrunk to less than 500 ppm. 363 * 364 * As a result, we can depend on there not being 365 * any odd delays anywhere, and the TSC reads are 366 * reliable (within the error). We also adjust the 367 * delta to the middle of the error bars, just 368 * because it looks nicer. 369 * 370 * kHz = ticks / time-in-seconds / 1000; 371 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000 372 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000) 373 */ 374 delta += (long)(d2 - d1)/2; 375 delta *= PIT_TICK_RATE; 376 do_div(delta, i*256*1000); 377 printk("Fast TSC calibration using PIT\n"); 378 return delta; 379 } 380 381 /** 382 * native_calibrate_tsc - calibrate the tsc on boot 383 */ 384 unsigned long native_calibrate_tsc(void) 385 { 386 u64 tsc1, tsc2, delta, ref1, ref2; 387 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX; 388 unsigned long flags, latch, ms, fast_calibrate, hv_tsc_khz; 389 int hpet = is_hpet_enabled(), i, loopmin; 390 391 hv_tsc_khz = get_hypervisor_tsc_freq(); 392 if (hv_tsc_khz) { 393 printk(KERN_INFO "TSC: Frequency read from the hypervisor\n"); 394 return hv_tsc_khz; 395 } 396 397 local_irq_save(flags); 398 fast_calibrate = quick_pit_calibrate(); 399 local_irq_restore(flags); 400 if (fast_calibrate) 401 return fast_calibrate; 402 403 /* 404 * Run 5 calibration loops to get the lowest frequency value 405 * (the best estimate). We use two different calibration modes 406 * here: 407 * 408 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and 409 * load a timeout of 50ms. We read the time right after we 410 * started the timer and wait until the PIT count down reaches 411 * zero. In each wait loop iteration we read the TSC and check 412 * the delta to the previous read. We keep track of the min 413 * and max values of that delta. The delta is mostly defined 414 * by the IO time of the PIT access, so we can detect when a 415 * SMI/SMM disturbance happend between the two reads. If the 416 * maximum time is significantly larger than the minimum time, 417 * then we discard the result and have another try. 418 * 419 * 2) Reference counter. If available we use the HPET or the 420 * PMTIMER as a reference to check the sanity of that value. 421 * We use separate TSC readouts and check inside of the 422 * reference read for a SMI/SMM disturbance. We dicard 423 * disturbed values here as well. We do that around the PIT 424 * calibration delay loop as we have to wait for a certain 425 * amount of time anyway. 426 */ 427 428 /* Preset PIT loop values */ 429 latch = CAL_LATCH; 430 ms = CAL_MS; 431 loopmin = CAL_PIT_LOOPS; 432 433 for (i = 0; i < 3; i++) { 434 unsigned long tsc_pit_khz; 435 436 /* 437 * Read the start value and the reference count of 438 * hpet/pmtimer when available. Then do the PIT 439 * calibration, which will take at least 50ms, and 440 * read the end value. 441 */ 442 local_irq_save(flags); 443 tsc1 = tsc_read_refs(&ref1, hpet); 444 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin); 445 tsc2 = tsc_read_refs(&ref2, hpet); 446 local_irq_restore(flags); 447 448 /* Pick the lowest PIT TSC calibration so far */ 449 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz); 450 451 /* hpet or pmtimer available ? */ 452 if (!hpet && !ref1 && !ref2) 453 continue; 454 455 /* Check, whether the sampling was disturbed by an SMI */ 456 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX) 457 continue; 458 459 tsc2 = (tsc2 - tsc1) * 1000000LL; 460 if (hpet) 461 tsc2 = calc_hpet_ref(tsc2, ref1, ref2); 462 else 463 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2); 464 465 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2); 466 467 /* Check the reference deviation */ 468 delta = ((u64) tsc_pit_min) * 100; 469 do_div(delta, tsc_ref_min); 470 471 /* 472 * If both calibration results are inside a 10% window 473 * then we can be sure, that the calibration 474 * succeeded. We break out of the loop right away. We 475 * use the reference value, as it is more precise. 476 */ 477 if (delta >= 90 && delta <= 110) { 478 printk(KERN_INFO 479 "TSC: PIT calibration matches %s. %d loops\n", 480 hpet ? "HPET" : "PMTIMER", i + 1); 481 return tsc_ref_min; 482 } 483 484 /* 485 * Check whether PIT failed more than once. This 486 * happens in virtualized environments. We need to 487 * give the virtual PC a slightly longer timeframe for 488 * the HPET/PMTIMER to make the result precise. 489 */ 490 if (i == 1 && tsc_pit_min == ULONG_MAX) { 491 latch = CAL2_LATCH; 492 ms = CAL2_MS; 493 loopmin = CAL2_PIT_LOOPS; 494 } 495 } 496 497 /* 498 * Now check the results. 499 */ 500 if (tsc_pit_min == ULONG_MAX) { 501 /* PIT gave no useful value */ 502 printk(KERN_WARNING "TSC: Unable to calibrate against PIT\n"); 503 504 /* We don't have an alternative source, disable TSC */ 505 if (!hpet && !ref1 && !ref2) { 506 printk("TSC: No reference (HPET/PMTIMER) available\n"); 507 return 0; 508 } 509 510 /* The alternative source failed as well, disable TSC */ 511 if (tsc_ref_min == ULONG_MAX) { 512 printk(KERN_WARNING "TSC: HPET/PMTIMER calibration " 513 "failed.\n"); 514 return 0; 515 } 516 517 /* Use the alternative source */ 518 printk(KERN_INFO "TSC: using %s reference calibration\n", 519 hpet ? "HPET" : "PMTIMER"); 520 521 return tsc_ref_min; 522 } 523 524 /* We don't have an alternative source, use the PIT calibration value */ 525 if (!hpet && !ref1 && !ref2) { 526 printk(KERN_INFO "TSC: Using PIT calibration value\n"); 527 return tsc_pit_min; 528 } 529 530 /* The alternative source failed, use the PIT calibration value */ 531 if (tsc_ref_min == ULONG_MAX) { 532 printk(KERN_WARNING "TSC: HPET/PMTIMER calibration failed. " 533 "Using PIT calibration\n"); 534 return tsc_pit_min; 535 } 536 537 /* 538 * The calibration values differ too much. In doubt, we use 539 * the PIT value as we know that there are PMTIMERs around 540 * running at double speed. At least we let the user know: 541 */ 542 printk(KERN_WARNING "TSC: PIT calibration deviates from %s: %lu %lu.\n", 543 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min); 544 printk(KERN_INFO "TSC: Using PIT calibration value\n"); 545 return tsc_pit_min; 546 } 547 548 int recalibrate_cpu_khz(void) 549 { 550 #ifndef CONFIG_SMP 551 unsigned long cpu_khz_old = cpu_khz; 552 553 if (cpu_has_tsc) { 554 tsc_khz = calibrate_tsc(); 555 cpu_khz = tsc_khz; 556 cpu_data(0).loops_per_jiffy = 557 cpufreq_scale(cpu_data(0).loops_per_jiffy, 558 cpu_khz_old, cpu_khz); 559 return 0; 560 } else 561 return -ENODEV; 562 #else 563 return -ENODEV; 564 #endif 565 } 566 567 EXPORT_SYMBOL(recalibrate_cpu_khz); 568 569 570 /* Accelerators for sched_clock() 571 * convert from cycles(64bits) => nanoseconds (64bits) 572 * basic equation: 573 * ns = cycles / (freq / ns_per_sec) 574 * ns = cycles * (ns_per_sec / freq) 575 * ns = cycles * (10^9 / (cpu_khz * 10^3)) 576 * ns = cycles * (10^6 / cpu_khz) 577 * 578 * Then we use scaling math (suggested by george@mvista.com) to get: 579 * ns = cycles * (10^6 * SC / cpu_khz) / SC 580 * ns = cycles * cyc2ns_scale / SC 581 * 582 * And since SC is a constant power of two, we can convert the div 583 * into a shift. 584 * 585 * We can use khz divisor instead of mhz to keep a better precision, since 586 * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits. 587 * (mathieu.desnoyers@polymtl.ca) 588 * 589 * -johnstul@us.ibm.com "math is hard, lets go shopping!" 590 */ 591 592 DEFINE_PER_CPU(unsigned long, cyc2ns); 593 DEFINE_PER_CPU(unsigned long long, cyc2ns_offset); 594 595 static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu) 596 { 597 unsigned long long tsc_now, ns_now, *offset; 598 unsigned long flags, *scale; 599 600 local_irq_save(flags); 601 sched_clock_idle_sleep_event(); 602 603 scale = &per_cpu(cyc2ns, cpu); 604 offset = &per_cpu(cyc2ns_offset, cpu); 605 606 rdtscll(tsc_now); 607 ns_now = __cycles_2_ns(tsc_now); 608 609 if (cpu_khz) { 610 *scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz; 611 *offset = ns_now - (tsc_now * *scale >> CYC2NS_SCALE_FACTOR); 612 } 613 614 sched_clock_idle_wakeup_event(0); 615 local_irq_restore(flags); 616 } 617 618 #ifdef CONFIG_CPU_FREQ 619 620 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency 621 * changes. 622 * 623 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's 624 * not that important because current Opteron setups do not support 625 * scaling on SMP anyroads. 626 * 627 * Should fix up last_tsc too. Currently gettimeofday in the 628 * first tick after the change will be slightly wrong. 629 */ 630 631 static unsigned int ref_freq; 632 static unsigned long loops_per_jiffy_ref; 633 static unsigned long tsc_khz_ref; 634 635 static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 636 void *data) 637 { 638 struct cpufreq_freqs *freq = data; 639 unsigned long *lpj; 640 641 if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC)) 642 return 0; 643 644 lpj = &boot_cpu_data.loops_per_jiffy; 645 #ifdef CONFIG_SMP 646 if (!(freq->flags & CPUFREQ_CONST_LOOPS)) 647 lpj = &cpu_data(freq->cpu).loops_per_jiffy; 648 #endif 649 650 if (!ref_freq) { 651 ref_freq = freq->old; 652 loops_per_jiffy_ref = *lpj; 653 tsc_khz_ref = tsc_khz; 654 } 655 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || 656 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) || 657 (val == CPUFREQ_RESUMECHANGE)) { 658 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new); 659 660 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new); 661 if (!(freq->flags & CPUFREQ_CONST_LOOPS)) 662 mark_tsc_unstable("cpufreq changes"); 663 } 664 665 set_cyc2ns_scale(tsc_khz, freq->cpu); 666 667 return 0; 668 } 669 670 static struct notifier_block time_cpufreq_notifier_block = { 671 .notifier_call = time_cpufreq_notifier 672 }; 673 674 static int __init cpufreq_tsc(void) 675 { 676 if (!cpu_has_tsc) 677 return 0; 678 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 679 return 0; 680 cpufreq_register_notifier(&time_cpufreq_notifier_block, 681 CPUFREQ_TRANSITION_NOTIFIER); 682 return 0; 683 } 684 685 core_initcall(cpufreq_tsc); 686 687 #endif /* CONFIG_CPU_FREQ */ 688 689 /* clocksource code */ 690 691 static struct clocksource clocksource_tsc; 692 693 /* 694 * We compare the TSC to the cycle_last value in the clocksource 695 * structure to avoid a nasty time-warp. This can be observed in a 696 * very small window right after one CPU updated cycle_last under 697 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which 698 * is smaller than the cycle_last reference value due to a TSC which 699 * is slighty behind. This delta is nowhere else observable, but in 700 * that case it results in a forward time jump in the range of hours 701 * due to the unsigned delta calculation of the time keeping core 702 * code, which is necessary to support wrapping clocksources like pm 703 * timer. 704 */ 705 static cycle_t read_tsc(struct clocksource *cs) 706 { 707 cycle_t ret = (cycle_t)get_cycles(); 708 709 return ret >= clocksource_tsc.cycle_last ? 710 ret : clocksource_tsc.cycle_last; 711 } 712 713 #ifdef CONFIG_X86_64 714 static cycle_t __vsyscall_fn vread_tsc(void) 715 { 716 cycle_t ret; 717 718 /* 719 * Surround the RDTSC by barriers, to make sure it's not 720 * speculated to outside the seqlock critical section and 721 * does not cause time warps: 722 */ 723 rdtsc_barrier(); 724 ret = (cycle_t)vget_cycles(); 725 rdtsc_barrier(); 726 727 return ret >= __vsyscall_gtod_data.clock.cycle_last ? 728 ret : __vsyscall_gtod_data.clock.cycle_last; 729 } 730 #endif 731 732 static struct clocksource clocksource_tsc = { 733 .name = "tsc", 734 .rating = 300, 735 .read = read_tsc, 736 .mask = CLOCKSOURCE_MASK(64), 737 .shift = 22, 738 .flags = CLOCK_SOURCE_IS_CONTINUOUS | 739 CLOCK_SOURCE_MUST_VERIFY, 740 #ifdef CONFIG_X86_64 741 .vread = vread_tsc, 742 #endif 743 }; 744 745 void mark_tsc_unstable(char *reason) 746 { 747 if (!tsc_unstable) { 748 tsc_unstable = 1; 749 printk("Marking TSC unstable due to %s\n", reason); 750 /* Change only the rating, when not registered */ 751 if (clocksource_tsc.mult) 752 clocksource_change_rating(&clocksource_tsc, 0); 753 else 754 clocksource_tsc.rating = 0; 755 } 756 } 757 758 EXPORT_SYMBOL_GPL(mark_tsc_unstable); 759 760 static int __init dmi_mark_tsc_unstable(const struct dmi_system_id *d) 761 { 762 printk(KERN_NOTICE "%s detected: marking TSC unstable.\n", 763 d->ident); 764 tsc_unstable = 1; 765 return 0; 766 } 767 768 /* List of systems that have known TSC problems */ 769 static struct dmi_system_id __initdata bad_tsc_dmi_table[] = { 770 { 771 .callback = dmi_mark_tsc_unstable, 772 .ident = "IBM Thinkpad 380XD", 773 .matches = { 774 DMI_MATCH(DMI_BOARD_VENDOR, "IBM"), 775 DMI_MATCH(DMI_BOARD_NAME, "2635FA0"), 776 }, 777 }, 778 {} 779 }; 780 781 static void __init check_system_tsc_reliable(void) 782 { 783 #ifdef CONFIG_MGEODE_LX 784 /* RTSC counts during suspend */ 785 #define RTSC_SUSP 0x100 786 unsigned long res_low, res_high; 787 788 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high); 789 /* Geode_LX - the OLPC CPU has a possibly a very reliable TSC */ 790 if (res_low & RTSC_SUSP) 791 tsc_clocksource_reliable = 1; 792 #endif 793 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) 794 tsc_clocksource_reliable = 1; 795 } 796 797 /* 798 * Make an educated guess if the TSC is trustworthy and synchronized 799 * over all CPUs. 800 */ 801 __cpuinit int unsynchronized_tsc(void) 802 { 803 if (!cpu_has_tsc || tsc_unstable) 804 return 1; 805 806 #ifdef CONFIG_SMP 807 if (apic_is_clustered_box()) 808 return 1; 809 #endif 810 811 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 812 return 0; 813 /* 814 * Intel systems are normally all synchronized. 815 * Exceptions must mark TSC as unstable: 816 */ 817 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) { 818 /* assume multi socket systems are not synchronized: */ 819 if (num_possible_cpus() > 1) 820 tsc_unstable = 1; 821 } 822 823 return tsc_unstable; 824 } 825 826 static void __init init_tsc_clocksource(void) 827 { 828 clocksource_tsc.mult = clocksource_khz2mult(tsc_khz, 829 clocksource_tsc.shift); 830 if (tsc_clocksource_reliable) 831 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY; 832 /* lower the rating if we already know its unstable: */ 833 if (check_tsc_unstable()) { 834 clocksource_tsc.rating = 0; 835 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS; 836 } 837 clocksource_register(&clocksource_tsc); 838 } 839 840 void __init tsc_init(void) 841 { 842 u64 lpj; 843 int cpu; 844 845 if (!cpu_has_tsc) 846 return; 847 848 tsc_khz = calibrate_tsc(); 849 cpu_khz = tsc_khz; 850 851 if (!tsc_khz) { 852 mark_tsc_unstable("could not calculate TSC khz"); 853 return; 854 } 855 856 #ifdef CONFIG_X86_64 857 if (cpu_has(&boot_cpu_data, X86_FEATURE_CONSTANT_TSC) && 858 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)) 859 cpu_khz = calibrate_cpu(); 860 #endif 861 862 printk("Detected %lu.%03lu MHz processor.\n", 863 (unsigned long)cpu_khz / 1000, 864 (unsigned long)cpu_khz % 1000); 865 866 /* 867 * Secondary CPUs do not run through tsc_init(), so set up 868 * all the scale factors for all CPUs, assuming the same 869 * speed as the bootup CPU. (cpufreq notifiers will fix this 870 * up if their speed diverges) 871 */ 872 for_each_possible_cpu(cpu) 873 set_cyc2ns_scale(cpu_khz, cpu); 874 875 if (tsc_disabled > 0) 876 return; 877 878 /* now allow native_sched_clock() to use rdtsc */ 879 tsc_disabled = 0; 880 881 lpj = ((u64)tsc_khz * 1000); 882 do_div(lpj, HZ); 883 lpj_fine = lpj; 884 885 use_tsc_delay(); 886 /* Check and install the TSC clocksource */ 887 dmi_check_system(bad_tsc_dmi_table); 888 889 if (unsynchronized_tsc()) 890 mark_tsc_unstable("TSCs unsynchronized"); 891 892 check_system_tsc_reliable(); 893 init_tsc_clocksource(); 894 } 895 896