1 #include <linux/kernel.h> 2 #include <linux/sched.h> 3 #include <linux/init.h> 4 #include <linux/module.h> 5 #include <linux/timer.h> 6 #include <linux/acpi_pmtmr.h> 7 #include <linux/cpufreq.h> 8 #include <linux/dmi.h> 9 #include <linux/delay.h> 10 #include <linux/clocksource.h> 11 #include <linux/percpu.h> 12 13 #include <asm/hpet.h> 14 #include <asm/timer.h> 15 #include <asm/vgtod.h> 16 #include <asm/time.h> 17 #include <asm/delay.h> 18 #include <asm/hypervisor.h> 19 20 unsigned int cpu_khz; /* TSC clocks / usec, not used here */ 21 EXPORT_SYMBOL(cpu_khz); 22 unsigned int tsc_khz; 23 EXPORT_SYMBOL(tsc_khz); 24 25 /* 26 * TSC can be unstable due to cpufreq or due to unsynced TSCs 27 */ 28 static int tsc_unstable; 29 30 /* native_sched_clock() is called before tsc_init(), so 31 we must start with the TSC soft disabled to prevent 32 erroneous rdtsc usage on !cpu_has_tsc processors */ 33 static int tsc_disabled = -1; 34 35 static int tsc_clocksource_reliable; 36 /* 37 * Scheduler clock - returns current time in nanosec units. 38 */ 39 u64 native_sched_clock(void) 40 { 41 u64 this_offset; 42 43 /* 44 * Fall back to jiffies if there's no TSC available: 45 * ( But note that we still use it if the TSC is marked 46 * unstable. We do this because unlike Time Of Day, 47 * the scheduler clock tolerates small errors and it's 48 * very important for it to be as fast as the platform 49 * can achive it. ) 50 */ 51 if (unlikely(tsc_disabled)) { 52 /* No locking but a rare wrong value is not a big deal: */ 53 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ); 54 } 55 56 /* read the Time Stamp Counter: */ 57 rdtscll(this_offset); 58 59 /* return the value in ns */ 60 return __cycles_2_ns(this_offset); 61 } 62 63 /* We need to define a real function for sched_clock, to override the 64 weak default version */ 65 #ifdef CONFIG_PARAVIRT 66 unsigned long long sched_clock(void) 67 { 68 return paravirt_sched_clock(); 69 } 70 #else 71 unsigned long long 72 sched_clock(void) __attribute__((alias("native_sched_clock"))); 73 #endif 74 75 int check_tsc_unstable(void) 76 { 77 return tsc_unstable; 78 } 79 EXPORT_SYMBOL_GPL(check_tsc_unstable); 80 81 #ifdef CONFIG_X86_TSC 82 int __init notsc_setup(char *str) 83 { 84 printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, " 85 "cannot disable TSC completely.\n"); 86 tsc_disabled = 1; 87 return 1; 88 } 89 #else 90 /* 91 * disable flag for tsc. Takes effect by clearing the TSC cpu flag 92 * in cpu/common.c 93 */ 94 int __init notsc_setup(char *str) 95 { 96 setup_clear_cpu_cap(X86_FEATURE_TSC); 97 return 1; 98 } 99 #endif 100 101 __setup("notsc", notsc_setup); 102 103 static int __init tsc_setup(char *str) 104 { 105 if (!strcmp(str, "reliable")) 106 tsc_clocksource_reliable = 1; 107 return 1; 108 } 109 110 __setup("tsc=", tsc_setup); 111 112 #define MAX_RETRIES 5 113 #define SMI_TRESHOLD 50000 114 115 /* 116 * Read TSC and the reference counters. Take care of SMI disturbance 117 */ 118 static u64 tsc_read_refs(u64 *p, int hpet) 119 { 120 u64 t1, t2; 121 int i; 122 123 for (i = 0; i < MAX_RETRIES; i++) { 124 t1 = get_cycles(); 125 if (hpet) 126 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF; 127 else 128 *p = acpi_pm_read_early(); 129 t2 = get_cycles(); 130 if ((t2 - t1) < SMI_TRESHOLD) 131 return t2; 132 } 133 return ULLONG_MAX; 134 } 135 136 /* 137 * Calculate the TSC frequency from HPET reference 138 */ 139 static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2) 140 { 141 u64 tmp; 142 143 if (hpet2 < hpet1) 144 hpet2 += 0x100000000ULL; 145 hpet2 -= hpet1; 146 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD)); 147 do_div(tmp, 1000000); 148 do_div(deltatsc, tmp); 149 150 return (unsigned long) deltatsc; 151 } 152 153 /* 154 * Calculate the TSC frequency from PMTimer reference 155 */ 156 static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2) 157 { 158 u64 tmp; 159 160 if (!pm1 && !pm2) 161 return ULONG_MAX; 162 163 if (pm2 < pm1) 164 pm2 += (u64)ACPI_PM_OVRRUN; 165 pm2 -= pm1; 166 tmp = pm2 * 1000000000LL; 167 do_div(tmp, PMTMR_TICKS_PER_SEC); 168 do_div(deltatsc, tmp); 169 170 return (unsigned long) deltatsc; 171 } 172 173 #define CAL_MS 10 174 #define CAL_LATCH (CLOCK_TICK_RATE / (1000 / CAL_MS)) 175 #define CAL_PIT_LOOPS 1000 176 177 #define CAL2_MS 50 178 #define CAL2_LATCH (CLOCK_TICK_RATE / (1000 / CAL2_MS)) 179 #define CAL2_PIT_LOOPS 5000 180 181 182 /* 183 * Try to calibrate the TSC against the Programmable 184 * Interrupt Timer and return the frequency of the TSC 185 * in kHz. 186 * 187 * Return ULONG_MAX on failure to calibrate. 188 */ 189 static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin) 190 { 191 u64 tsc, t1, t2, delta; 192 unsigned long tscmin, tscmax; 193 int pitcnt; 194 195 /* Set the Gate high, disable speaker */ 196 outb((inb(0x61) & ~0x02) | 0x01, 0x61); 197 198 /* 199 * Setup CTC channel 2* for mode 0, (interrupt on terminal 200 * count mode), binary count. Set the latch register to 50ms 201 * (LSB then MSB) to begin countdown. 202 */ 203 outb(0xb0, 0x43); 204 outb(latch & 0xff, 0x42); 205 outb(latch >> 8, 0x42); 206 207 tsc = t1 = t2 = get_cycles(); 208 209 pitcnt = 0; 210 tscmax = 0; 211 tscmin = ULONG_MAX; 212 while ((inb(0x61) & 0x20) == 0) { 213 t2 = get_cycles(); 214 delta = t2 - tsc; 215 tsc = t2; 216 if ((unsigned long) delta < tscmin) 217 tscmin = (unsigned int) delta; 218 if ((unsigned long) delta > tscmax) 219 tscmax = (unsigned int) delta; 220 pitcnt++; 221 } 222 223 /* 224 * Sanity checks: 225 * 226 * If we were not able to read the PIT more than loopmin 227 * times, then we have been hit by a massive SMI 228 * 229 * If the maximum is 10 times larger than the minimum, 230 * then we got hit by an SMI as well. 231 */ 232 if (pitcnt < loopmin || tscmax > 10 * tscmin) 233 return ULONG_MAX; 234 235 /* Calculate the PIT value */ 236 delta = t2 - t1; 237 do_div(delta, ms); 238 return delta; 239 } 240 241 /* 242 * This reads the current MSB of the PIT counter, and 243 * checks if we are running on sufficiently fast and 244 * non-virtualized hardware. 245 * 246 * Our expectations are: 247 * 248 * - the PIT is running at roughly 1.19MHz 249 * 250 * - each IO is going to take about 1us on real hardware, 251 * but we allow it to be much faster (by a factor of 10) or 252 * _slightly_ slower (ie we allow up to a 2us read+counter 253 * update - anything else implies a unacceptably slow CPU 254 * or PIT for the fast calibration to work. 255 * 256 * - with 256 PIT ticks to read the value, we have 214us to 257 * see the same MSB (and overhead like doing a single TSC 258 * read per MSB value etc). 259 * 260 * - We're doing 2 reads per loop (LSB, MSB), and we expect 261 * them each to take about a microsecond on real hardware. 262 * So we expect a count value of around 100. But we'll be 263 * generous, and accept anything over 50. 264 * 265 * - if the PIT is stuck, and we see *many* more reads, we 266 * return early (and the next caller of pit_expect_msb() 267 * then consider it a failure when they don't see the 268 * next expected value). 269 * 270 * These expectations mean that we know that we have seen the 271 * transition from one expected value to another with a fairly 272 * high accuracy, and we didn't miss any events. We can thus 273 * use the TSC value at the transitions to calculate a pretty 274 * good value for the TSC frequencty. 275 */ 276 static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap) 277 { 278 int count; 279 u64 tsc = 0; 280 281 for (count = 0; count < 50000; count++) { 282 /* Ignore LSB */ 283 inb(0x42); 284 if (inb(0x42) != val) 285 break; 286 tsc = get_cycles(); 287 } 288 *deltap = get_cycles() - tsc; 289 *tscp = tsc; 290 291 /* 292 * We require _some_ success, but the quality control 293 * will be based on the error terms on the TSC values. 294 */ 295 return count > 5; 296 } 297 298 /* 299 * How many MSB values do we want to see? We aim for 300 * a maximum error rate of 500ppm (in practice the 301 * real error is much smaller), but refuse to spend 302 * more than 25ms on it. 303 */ 304 #define MAX_QUICK_PIT_MS 25 305 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) 306 307 static unsigned long quick_pit_calibrate(void) 308 { 309 int i; 310 u64 tsc, delta; 311 unsigned long d1, d2; 312 313 /* Set the Gate high, disable speaker */ 314 outb((inb(0x61) & ~0x02) | 0x01, 0x61); 315 316 /* 317 * Counter 2, mode 0 (one-shot), binary count 318 * 319 * NOTE! Mode 2 decrements by two (and then the 320 * output is flipped each time, giving the same 321 * final output frequency as a decrement-by-one), 322 * so mode 0 is much better when looking at the 323 * individual counts. 324 */ 325 outb(0xb0, 0x43); 326 327 /* Start at 0xffff */ 328 outb(0xff, 0x42); 329 outb(0xff, 0x42); 330 331 /* 332 * The PIT starts counting at the next edge, so we 333 * need to delay for a microsecond. The easiest way 334 * to do that is to just read back the 16-bit counter 335 * once from the PIT. 336 */ 337 inb(0x42); 338 inb(0x42); 339 340 if (pit_expect_msb(0xff, &tsc, &d1)) { 341 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) { 342 if (!pit_expect_msb(0xff-i, &delta, &d2)) 343 break; 344 345 /* 346 * Iterate until the error is less than 500 ppm 347 */ 348 delta -= tsc; 349 if (d1+d2 < delta >> 11) 350 goto success; 351 } 352 } 353 printk("Fast TSC calibration failed\n"); 354 return 0; 355 356 success: 357 /* 358 * Ok, if we get here, then we've seen the 359 * MSB of the PIT decrement 'i' times, and the 360 * error has shrunk to less than 500 ppm. 361 * 362 * As a result, we can depend on there not being 363 * any odd delays anywhere, and the TSC reads are 364 * reliable (within the error). We also adjust the 365 * delta to the middle of the error bars, just 366 * because it looks nicer. 367 * 368 * kHz = ticks / time-in-seconds / 1000; 369 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000 370 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000) 371 */ 372 delta += (long)(d2 - d1)/2; 373 delta *= PIT_TICK_RATE; 374 do_div(delta, i*256*1000); 375 printk("Fast TSC calibration using PIT\n"); 376 return delta; 377 } 378 379 /** 380 * native_calibrate_tsc - calibrate the tsc on boot 381 */ 382 unsigned long native_calibrate_tsc(void) 383 { 384 u64 tsc1, tsc2, delta, ref1, ref2; 385 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX; 386 unsigned long flags, latch, ms, fast_calibrate, tsc_khz; 387 int hpet = is_hpet_enabled(), i, loopmin; 388 389 tsc_khz = get_hypervisor_tsc_freq(); 390 if (tsc_khz) { 391 printk(KERN_INFO "TSC: Frequency read from the hypervisor\n"); 392 return tsc_khz; 393 } 394 395 local_irq_save(flags); 396 fast_calibrate = quick_pit_calibrate(); 397 local_irq_restore(flags); 398 if (fast_calibrate) 399 return fast_calibrate; 400 401 /* 402 * Run 5 calibration loops to get the lowest frequency value 403 * (the best estimate). We use two different calibration modes 404 * here: 405 * 406 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and 407 * load a timeout of 50ms. We read the time right after we 408 * started the timer and wait until the PIT count down reaches 409 * zero. In each wait loop iteration we read the TSC and check 410 * the delta to the previous read. We keep track of the min 411 * and max values of that delta. The delta is mostly defined 412 * by the IO time of the PIT access, so we can detect when a 413 * SMI/SMM disturbance happend between the two reads. If the 414 * maximum time is significantly larger than the minimum time, 415 * then we discard the result and have another try. 416 * 417 * 2) Reference counter. If available we use the HPET or the 418 * PMTIMER as a reference to check the sanity of that value. 419 * We use separate TSC readouts and check inside of the 420 * reference read for a SMI/SMM disturbance. We dicard 421 * disturbed values here as well. We do that around the PIT 422 * calibration delay loop as we have to wait for a certain 423 * amount of time anyway. 424 */ 425 426 /* Preset PIT loop values */ 427 latch = CAL_LATCH; 428 ms = CAL_MS; 429 loopmin = CAL_PIT_LOOPS; 430 431 for (i = 0; i < 3; i++) { 432 unsigned long tsc_pit_khz; 433 434 /* 435 * Read the start value and the reference count of 436 * hpet/pmtimer when available. Then do the PIT 437 * calibration, which will take at least 50ms, and 438 * read the end value. 439 */ 440 local_irq_save(flags); 441 tsc1 = tsc_read_refs(&ref1, hpet); 442 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin); 443 tsc2 = tsc_read_refs(&ref2, hpet); 444 local_irq_restore(flags); 445 446 /* Pick the lowest PIT TSC calibration so far */ 447 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz); 448 449 /* hpet or pmtimer available ? */ 450 if (!hpet && !ref1 && !ref2) 451 continue; 452 453 /* Check, whether the sampling was disturbed by an SMI */ 454 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX) 455 continue; 456 457 tsc2 = (tsc2 - tsc1) * 1000000LL; 458 if (hpet) 459 tsc2 = calc_hpet_ref(tsc2, ref1, ref2); 460 else 461 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2); 462 463 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2); 464 465 /* Check the reference deviation */ 466 delta = ((u64) tsc_pit_min) * 100; 467 do_div(delta, tsc_ref_min); 468 469 /* 470 * If both calibration results are inside a 10% window 471 * then we can be sure, that the calibration 472 * succeeded. We break out of the loop right away. We 473 * use the reference value, as it is more precise. 474 */ 475 if (delta >= 90 && delta <= 110) { 476 printk(KERN_INFO 477 "TSC: PIT calibration matches %s. %d loops\n", 478 hpet ? "HPET" : "PMTIMER", i + 1); 479 return tsc_ref_min; 480 } 481 482 /* 483 * Check whether PIT failed more than once. This 484 * happens in virtualized environments. We need to 485 * give the virtual PC a slightly longer timeframe for 486 * the HPET/PMTIMER to make the result precise. 487 */ 488 if (i == 1 && tsc_pit_min == ULONG_MAX) { 489 latch = CAL2_LATCH; 490 ms = CAL2_MS; 491 loopmin = CAL2_PIT_LOOPS; 492 } 493 } 494 495 /* 496 * Now check the results. 497 */ 498 if (tsc_pit_min == ULONG_MAX) { 499 /* PIT gave no useful value */ 500 printk(KERN_WARNING "TSC: Unable to calibrate against PIT\n"); 501 502 /* We don't have an alternative source, disable TSC */ 503 if (!hpet && !ref1 && !ref2) { 504 printk("TSC: No reference (HPET/PMTIMER) available\n"); 505 return 0; 506 } 507 508 /* The alternative source failed as well, disable TSC */ 509 if (tsc_ref_min == ULONG_MAX) { 510 printk(KERN_WARNING "TSC: HPET/PMTIMER calibration " 511 "failed.\n"); 512 return 0; 513 } 514 515 /* Use the alternative source */ 516 printk(KERN_INFO "TSC: using %s reference calibration\n", 517 hpet ? "HPET" : "PMTIMER"); 518 519 return tsc_ref_min; 520 } 521 522 /* We don't have an alternative source, use the PIT calibration value */ 523 if (!hpet && !ref1 && !ref2) { 524 printk(KERN_INFO "TSC: Using PIT calibration value\n"); 525 return tsc_pit_min; 526 } 527 528 /* The alternative source failed, use the PIT calibration value */ 529 if (tsc_ref_min == ULONG_MAX) { 530 printk(KERN_WARNING "TSC: HPET/PMTIMER calibration failed. " 531 "Using PIT calibration\n"); 532 return tsc_pit_min; 533 } 534 535 /* 536 * The calibration values differ too much. In doubt, we use 537 * the PIT value as we know that there are PMTIMERs around 538 * running at double speed. At least we let the user know: 539 */ 540 printk(KERN_WARNING "TSC: PIT calibration deviates from %s: %lu %lu.\n", 541 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min); 542 printk(KERN_INFO "TSC: Using PIT calibration value\n"); 543 return tsc_pit_min; 544 } 545 546 int recalibrate_cpu_khz(void) 547 { 548 #ifndef CONFIG_SMP 549 unsigned long cpu_khz_old = cpu_khz; 550 551 if (cpu_has_tsc) { 552 tsc_khz = calibrate_tsc(); 553 cpu_khz = tsc_khz; 554 cpu_data(0).loops_per_jiffy = 555 cpufreq_scale(cpu_data(0).loops_per_jiffy, 556 cpu_khz_old, cpu_khz); 557 return 0; 558 } else 559 return -ENODEV; 560 #else 561 return -ENODEV; 562 #endif 563 } 564 565 EXPORT_SYMBOL(recalibrate_cpu_khz); 566 567 568 /* Accelerators for sched_clock() 569 * convert from cycles(64bits) => nanoseconds (64bits) 570 * basic equation: 571 * ns = cycles / (freq / ns_per_sec) 572 * ns = cycles * (ns_per_sec / freq) 573 * ns = cycles * (10^9 / (cpu_khz * 10^3)) 574 * ns = cycles * (10^6 / cpu_khz) 575 * 576 * Then we use scaling math (suggested by george@mvista.com) to get: 577 * ns = cycles * (10^6 * SC / cpu_khz) / SC 578 * ns = cycles * cyc2ns_scale / SC 579 * 580 * And since SC is a constant power of two, we can convert the div 581 * into a shift. 582 * 583 * We can use khz divisor instead of mhz to keep a better precision, since 584 * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits. 585 * (mathieu.desnoyers@polymtl.ca) 586 * 587 * -johnstul@us.ibm.com "math is hard, lets go shopping!" 588 */ 589 590 DEFINE_PER_CPU(unsigned long, cyc2ns); 591 592 static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu) 593 { 594 unsigned long long tsc_now, ns_now; 595 unsigned long flags, *scale; 596 597 local_irq_save(flags); 598 sched_clock_idle_sleep_event(); 599 600 scale = &per_cpu(cyc2ns, cpu); 601 602 rdtscll(tsc_now); 603 ns_now = __cycles_2_ns(tsc_now); 604 605 if (cpu_khz) 606 *scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz; 607 608 sched_clock_idle_wakeup_event(0); 609 local_irq_restore(flags); 610 } 611 612 #ifdef CONFIG_CPU_FREQ 613 614 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency 615 * changes. 616 * 617 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's 618 * not that important because current Opteron setups do not support 619 * scaling on SMP anyroads. 620 * 621 * Should fix up last_tsc too. Currently gettimeofday in the 622 * first tick after the change will be slightly wrong. 623 */ 624 625 static unsigned int ref_freq; 626 static unsigned long loops_per_jiffy_ref; 627 static unsigned long tsc_khz_ref; 628 629 static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 630 void *data) 631 { 632 struct cpufreq_freqs *freq = data; 633 unsigned long *lpj, dummy; 634 635 if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC)) 636 return 0; 637 638 lpj = &dummy; 639 if (!(freq->flags & CPUFREQ_CONST_LOOPS)) 640 #ifdef CONFIG_SMP 641 lpj = &cpu_data(freq->cpu).loops_per_jiffy; 642 #else 643 lpj = &boot_cpu_data.loops_per_jiffy; 644 #endif 645 646 if (!ref_freq) { 647 ref_freq = freq->old; 648 loops_per_jiffy_ref = *lpj; 649 tsc_khz_ref = tsc_khz; 650 } 651 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || 652 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) || 653 (val == CPUFREQ_RESUMECHANGE)) { 654 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new); 655 656 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new); 657 if (!(freq->flags & CPUFREQ_CONST_LOOPS)) 658 mark_tsc_unstable("cpufreq changes"); 659 } 660 661 set_cyc2ns_scale(tsc_khz, freq->cpu); 662 663 return 0; 664 } 665 666 static struct notifier_block time_cpufreq_notifier_block = { 667 .notifier_call = time_cpufreq_notifier 668 }; 669 670 static int __init cpufreq_tsc(void) 671 { 672 if (!cpu_has_tsc) 673 return 0; 674 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 675 return 0; 676 cpufreq_register_notifier(&time_cpufreq_notifier_block, 677 CPUFREQ_TRANSITION_NOTIFIER); 678 return 0; 679 } 680 681 core_initcall(cpufreq_tsc); 682 683 #endif /* CONFIG_CPU_FREQ */ 684 685 /* clocksource code */ 686 687 static struct clocksource clocksource_tsc; 688 689 /* 690 * We compare the TSC to the cycle_last value in the clocksource 691 * structure to avoid a nasty time-warp. This can be observed in a 692 * very small window right after one CPU updated cycle_last under 693 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which 694 * is smaller than the cycle_last reference value due to a TSC which 695 * is slighty behind. This delta is nowhere else observable, but in 696 * that case it results in a forward time jump in the range of hours 697 * due to the unsigned delta calculation of the time keeping core 698 * code, which is necessary to support wrapping clocksources like pm 699 * timer. 700 */ 701 static cycle_t read_tsc(void) 702 { 703 cycle_t ret = (cycle_t)get_cycles(); 704 705 return ret >= clocksource_tsc.cycle_last ? 706 ret : clocksource_tsc.cycle_last; 707 } 708 709 #ifdef CONFIG_X86_64 710 static cycle_t __vsyscall_fn vread_tsc(void) 711 { 712 cycle_t ret = (cycle_t)vget_cycles(); 713 714 return ret >= __vsyscall_gtod_data.clock.cycle_last ? 715 ret : __vsyscall_gtod_data.clock.cycle_last; 716 } 717 #endif 718 719 static struct clocksource clocksource_tsc = { 720 .name = "tsc", 721 .rating = 300, 722 .read = read_tsc, 723 .mask = CLOCKSOURCE_MASK(64), 724 .shift = 22, 725 .flags = CLOCK_SOURCE_IS_CONTINUOUS | 726 CLOCK_SOURCE_MUST_VERIFY, 727 #ifdef CONFIG_X86_64 728 .vread = vread_tsc, 729 #endif 730 }; 731 732 void mark_tsc_unstable(char *reason) 733 { 734 if (!tsc_unstable) { 735 tsc_unstable = 1; 736 printk("Marking TSC unstable due to %s\n", reason); 737 /* Change only the rating, when not registered */ 738 if (clocksource_tsc.mult) 739 clocksource_change_rating(&clocksource_tsc, 0); 740 else 741 clocksource_tsc.rating = 0; 742 } 743 } 744 745 EXPORT_SYMBOL_GPL(mark_tsc_unstable); 746 747 static int __init dmi_mark_tsc_unstable(const struct dmi_system_id *d) 748 { 749 printk(KERN_NOTICE "%s detected: marking TSC unstable.\n", 750 d->ident); 751 tsc_unstable = 1; 752 return 0; 753 } 754 755 /* List of systems that have known TSC problems */ 756 static struct dmi_system_id __initdata bad_tsc_dmi_table[] = { 757 { 758 .callback = dmi_mark_tsc_unstable, 759 .ident = "IBM Thinkpad 380XD", 760 .matches = { 761 DMI_MATCH(DMI_BOARD_VENDOR, "IBM"), 762 DMI_MATCH(DMI_BOARD_NAME, "2635FA0"), 763 }, 764 }, 765 {} 766 }; 767 768 static void __init check_system_tsc_reliable(void) 769 { 770 #ifdef CONFIG_MGEODE_LX 771 /* RTSC counts during suspend */ 772 #define RTSC_SUSP 0x100 773 unsigned long res_low, res_high; 774 775 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high); 776 /* Geode_LX - the OLPC CPU has a possibly a very reliable TSC */ 777 if (res_low & RTSC_SUSP) 778 tsc_clocksource_reliable = 1; 779 #endif 780 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) 781 tsc_clocksource_reliable = 1; 782 } 783 784 /* 785 * Make an educated guess if the TSC is trustworthy and synchronized 786 * over all CPUs. 787 */ 788 __cpuinit int unsynchronized_tsc(void) 789 { 790 if (!cpu_has_tsc || tsc_unstable) 791 return 1; 792 793 #ifdef CONFIG_X86_SMP 794 if (apic_is_clustered_box()) 795 return 1; 796 #endif 797 798 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 799 return 0; 800 /* 801 * Intel systems are normally all synchronized. 802 * Exceptions must mark TSC as unstable: 803 */ 804 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) { 805 /* assume multi socket systems are not synchronized: */ 806 if (num_possible_cpus() > 1) 807 tsc_unstable = 1; 808 } 809 810 return tsc_unstable; 811 } 812 813 static void __init init_tsc_clocksource(void) 814 { 815 clocksource_tsc.mult = clocksource_khz2mult(tsc_khz, 816 clocksource_tsc.shift); 817 if (tsc_clocksource_reliable) 818 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY; 819 /* lower the rating if we already know its unstable: */ 820 if (check_tsc_unstable()) { 821 clocksource_tsc.rating = 0; 822 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS; 823 } 824 clocksource_register(&clocksource_tsc); 825 } 826 827 void __init tsc_init(void) 828 { 829 u64 lpj; 830 int cpu; 831 832 if (!cpu_has_tsc) 833 return; 834 835 tsc_khz = calibrate_tsc(); 836 cpu_khz = tsc_khz; 837 838 if (!tsc_khz) { 839 mark_tsc_unstable("could not calculate TSC khz"); 840 return; 841 } 842 843 #ifdef CONFIG_X86_64 844 if (cpu_has(&boot_cpu_data, X86_FEATURE_CONSTANT_TSC) && 845 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)) 846 cpu_khz = calibrate_cpu(); 847 #endif 848 849 printk("Detected %lu.%03lu MHz processor.\n", 850 (unsigned long)cpu_khz / 1000, 851 (unsigned long)cpu_khz % 1000); 852 853 /* 854 * Secondary CPUs do not run through tsc_init(), so set up 855 * all the scale factors for all CPUs, assuming the same 856 * speed as the bootup CPU. (cpufreq notifiers will fix this 857 * up if their speed diverges) 858 */ 859 for_each_possible_cpu(cpu) 860 set_cyc2ns_scale(cpu_khz, cpu); 861 862 if (tsc_disabled > 0) 863 return; 864 865 /* now allow native_sched_clock() to use rdtsc */ 866 tsc_disabled = 0; 867 868 lpj = ((u64)tsc_khz * 1000); 869 do_div(lpj, HZ); 870 lpj_fine = lpj; 871 872 use_tsc_delay(); 873 /* Check and install the TSC clocksource */ 874 dmi_check_system(bad_tsc_dmi_table); 875 876 if (unsynchronized_tsc()) 877 mark_tsc_unstable("TSCs unsynchronized"); 878 879 check_system_tsc_reliable(); 880 init_tsc_clocksource(); 881 } 882 883