1 /* 2 * Copyright (C) 1991, 1992 Linus Torvalds 3 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs 4 * 5 * Pentium III FXSR, SSE support 6 * Gareth Hughes <gareth@valinux.com>, May 2000 7 */ 8 9 /* 10 * Handle hardware traps and faults. 11 */ 12 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 15 #include <linux/context_tracking.h> 16 #include <linux/interrupt.h> 17 #include <linux/kallsyms.h> 18 #include <linux/kmsan.h> 19 #include <linux/spinlock.h> 20 #include <linux/kprobes.h> 21 #include <linux/uaccess.h> 22 #include <linux/kdebug.h> 23 #include <linux/kgdb.h> 24 #include <linux/kernel.h> 25 #include <linux/export.h> 26 #include <linux/ptrace.h> 27 #include <linux/uprobes.h> 28 #include <linux/string.h> 29 #include <linux/delay.h> 30 #include <linux/errno.h> 31 #include <linux/kexec.h> 32 #include <linux/sched.h> 33 #include <linux/sched/task_stack.h> 34 #include <linux/timer.h> 35 #include <linux/init.h> 36 #include <linux/bug.h> 37 #include <linux/nmi.h> 38 #include <linux/mm.h> 39 #include <linux/smp.h> 40 #include <linux/io.h> 41 #include <linux/hardirq.h> 42 #include <linux/atomic.h> 43 #include <linux/iommu.h> 44 45 #include <asm/stacktrace.h> 46 #include <asm/processor.h> 47 #include <asm/debugreg.h> 48 #include <asm/realmode.h> 49 #include <asm/text-patching.h> 50 #include <asm/ftrace.h> 51 #include <asm/traps.h> 52 #include <asm/desc.h> 53 #include <asm/fpu/api.h> 54 #include <asm/cpu.h> 55 #include <asm/cpu_entry_area.h> 56 #include <asm/mce.h> 57 #include <asm/fixmap.h> 58 #include <asm/mach_traps.h> 59 #include <asm/alternative.h> 60 #include <asm/fpu/xstate.h> 61 #include <asm/vm86.h> 62 #include <asm/umip.h> 63 #include <asm/insn.h> 64 #include <asm/insn-eval.h> 65 #include <asm/vdso.h> 66 #include <asm/tdx.h> 67 #include <asm/cfi.h> 68 69 #ifdef CONFIG_X86_64 70 #include <asm/x86_init.h> 71 #else 72 #include <asm/processor-flags.h> 73 #include <asm/setup.h> 74 #endif 75 76 #include <asm/proto.h> 77 78 DECLARE_BITMAP(system_vectors, NR_VECTORS); 79 80 static inline void cond_local_irq_enable(struct pt_regs *regs) 81 { 82 if (regs->flags & X86_EFLAGS_IF) 83 local_irq_enable(); 84 } 85 86 static inline void cond_local_irq_disable(struct pt_regs *regs) 87 { 88 if (regs->flags & X86_EFLAGS_IF) 89 local_irq_disable(); 90 } 91 92 __always_inline int is_valid_bugaddr(unsigned long addr) 93 { 94 if (addr < TASK_SIZE_MAX) 95 return 0; 96 97 /* 98 * We got #UD, if the text isn't readable we'd have gotten 99 * a different exception. 100 */ 101 return *(unsigned short *)addr == INSN_UD2; 102 } 103 104 static nokprobe_inline int 105 do_trap_no_signal(struct task_struct *tsk, int trapnr, const char *str, 106 struct pt_regs *regs, long error_code) 107 { 108 if (v8086_mode(regs)) { 109 /* 110 * Traps 0, 1, 3, 4, and 5 should be forwarded to vm86. 111 * On nmi (interrupt 2), do_trap should not be called. 112 */ 113 if (trapnr < X86_TRAP_UD) { 114 if (!handle_vm86_trap((struct kernel_vm86_regs *) regs, 115 error_code, trapnr)) 116 return 0; 117 } 118 } else if (!user_mode(regs)) { 119 if (fixup_exception(regs, trapnr, error_code, 0)) 120 return 0; 121 122 tsk->thread.error_code = error_code; 123 tsk->thread.trap_nr = trapnr; 124 die(str, regs, error_code); 125 } else { 126 if (fixup_vdso_exception(regs, trapnr, error_code, 0)) 127 return 0; 128 } 129 130 /* 131 * We want error_code and trap_nr set for userspace faults and 132 * kernelspace faults which result in die(), but not 133 * kernelspace faults which are fixed up. die() gives the 134 * process no chance to handle the signal and notice the 135 * kernel fault information, so that won't result in polluting 136 * the information about previously queued, but not yet 137 * delivered, faults. See also exc_general_protection below. 138 */ 139 tsk->thread.error_code = error_code; 140 tsk->thread.trap_nr = trapnr; 141 142 return -1; 143 } 144 145 static void show_signal(struct task_struct *tsk, int signr, 146 const char *type, const char *desc, 147 struct pt_regs *regs, long error_code) 148 { 149 if (show_unhandled_signals && unhandled_signal(tsk, signr) && 150 printk_ratelimit()) { 151 pr_info("%s[%d] %s%s ip:%lx sp:%lx error:%lx", 152 tsk->comm, task_pid_nr(tsk), type, desc, 153 regs->ip, regs->sp, error_code); 154 print_vma_addr(KERN_CONT " in ", regs->ip); 155 pr_cont("\n"); 156 } 157 } 158 159 static void 160 do_trap(int trapnr, int signr, char *str, struct pt_regs *regs, 161 long error_code, int sicode, void __user *addr) 162 { 163 struct task_struct *tsk = current; 164 165 if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code)) 166 return; 167 168 show_signal(tsk, signr, "trap ", str, regs, error_code); 169 170 if (!sicode) 171 force_sig(signr); 172 else 173 force_sig_fault(signr, sicode, addr); 174 } 175 NOKPROBE_SYMBOL(do_trap); 176 177 static void do_error_trap(struct pt_regs *regs, long error_code, char *str, 178 unsigned long trapnr, int signr, int sicode, void __user *addr) 179 { 180 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); 181 182 if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) != 183 NOTIFY_STOP) { 184 cond_local_irq_enable(regs); 185 do_trap(trapnr, signr, str, regs, error_code, sicode, addr); 186 cond_local_irq_disable(regs); 187 } 188 } 189 190 /* 191 * Posix requires to provide the address of the faulting instruction for 192 * SIGILL (#UD) and SIGFPE (#DE) in the si_addr member of siginfo_t. 193 * 194 * This address is usually regs->ip, but when an uprobe moved the code out 195 * of line then regs->ip points to the XOL code which would confuse 196 * anything which analyzes the fault address vs. the unmodified binary. If 197 * a trap happened in XOL code then uprobe maps regs->ip back to the 198 * original instruction address. 199 */ 200 static __always_inline void __user *error_get_trap_addr(struct pt_regs *regs) 201 { 202 return (void __user *)uprobe_get_trap_addr(regs); 203 } 204 205 DEFINE_IDTENTRY(exc_divide_error) 206 { 207 do_error_trap(regs, 0, "divide error", X86_TRAP_DE, SIGFPE, 208 FPE_INTDIV, error_get_trap_addr(regs)); 209 } 210 211 DEFINE_IDTENTRY(exc_overflow) 212 { 213 do_error_trap(regs, 0, "overflow", X86_TRAP_OF, SIGSEGV, 0, NULL); 214 } 215 216 #ifdef CONFIG_X86_KERNEL_IBT 217 218 static __ro_after_init bool ibt_fatal = true; 219 220 extern void ibt_selftest_ip(void); /* code label defined in asm below */ 221 222 enum cp_error_code { 223 CP_EC = (1 << 15) - 1, 224 225 CP_RET = 1, 226 CP_IRET = 2, 227 CP_ENDBR = 3, 228 CP_RSTRORSSP = 4, 229 CP_SETSSBSY = 5, 230 231 CP_ENCL = 1 << 15, 232 }; 233 234 DEFINE_IDTENTRY_ERRORCODE(exc_control_protection) 235 { 236 if (!cpu_feature_enabled(X86_FEATURE_IBT)) { 237 pr_err("Unexpected #CP\n"); 238 BUG(); 239 } 240 241 if (WARN_ON_ONCE(user_mode(regs) || (error_code & CP_EC) != CP_ENDBR)) 242 return; 243 244 if (unlikely(regs->ip == (unsigned long)&ibt_selftest_ip)) { 245 regs->ax = 0; 246 return; 247 } 248 249 pr_err("Missing ENDBR: %pS\n", (void *)instruction_pointer(regs)); 250 if (!ibt_fatal) { 251 printk(KERN_DEFAULT CUT_HERE); 252 __warn(__FILE__, __LINE__, (void *)regs->ip, TAINT_WARN, regs, NULL); 253 return; 254 } 255 BUG(); 256 } 257 258 /* Must be noinline to ensure uniqueness of ibt_selftest_ip. */ 259 noinline bool ibt_selftest(void) 260 { 261 unsigned long ret; 262 263 asm (" lea ibt_selftest_ip(%%rip), %%rax\n\t" 264 ANNOTATE_RETPOLINE_SAFE 265 " jmp *%%rax\n\t" 266 "ibt_selftest_ip:\n\t" 267 UNWIND_HINT_FUNC 268 ANNOTATE_NOENDBR 269 " nop\n\t" 270 271 : "=a" (ret) : : "memory"); 272 273 return !ret; 274 } 275 276 static int __init ibt_setup(char *str) 277 { 278 if (!strcmp(str, "off")) 279 setup_clear_cpu_cap(X86_FEATURE_IBT); 280 281 if (!strcmp(str, "warn")) 282 ibt_fatal = false; 283 284 return 1; 285 } 286 287 __setup("ibt=", ibt_setup); 288 289 #endif /* CONFIG_X86_KERNEL_IBT */ 290 291 #ifdef CONFIG_X86_F00F_BUG 292 void handle_invalid_op(struct pt_regs *regs) 293 #else 294 static inline void handle_invalid_op(struct pt_regs *regs) 295 #endif 296 { 297 do_error_trap(regs, 0, "invalid opcode", X86_TRAP_UD, SIGILL, 298 ILL_ILLOPN, error_get_trap_addr(regs)); 299 } 300 301 static noinstr bool handle_bug(struct pt_regs *regs) 302 { 303 bool handled = false; 304 305 /* 306 * Normally @regs are unpoisoned by irqentry_enter(), but handle_bug() 307 * is a rare case that uses @regs without passing them to 308 * irqentry_enter(). 309 */ 310 kmsan_unpoison_entry_regs(regs); 311 if (!is_valid_bugaddr(regs->ip)) 312 return handled; 313 314 /* 315 * All lies, just get the WARN/BUG out. 316 */ 317 instrumentation_begin(); 318 /* 319 * Since we're emulating a CALL with exceptions, restore the interrupt 320 * state to what it was at the exception site. 321 */ 322 if (regs->flags & X86_EFLAGS_IF) 323 raw_local_irq_enable(); 324 if (report_bug(regs->ip, regs) == BUG_TRAP_TYPE_WARN || 325 handle_cfi_failure(regs) == BUG_TRAP_TYPE_WARN) { 326 regs->ip += LEN_UD2; 327 handled = true; 328 } 329 if (regs->flags & X86_EFLAGS_IF) 330 raw_local_irq_disable(); 331 instrumentation_end(); 332 333 return handled; 334 } 335 336 DEFINE_IDTENTRY_RAW(exc_invalid_op) 337 { 338 irqentry_state_t state; 339 340 /* 341 * We use UD2 as a short encoding for 'CALL __WARN', as such 342 * handle it before exception entry to avoid recursive WARN 343 * in case exception entry is the one triggering WARNs. 344 */ 345 if (!user_mode(regs) && handle_bug(regs)) 346 return; 347 348 state = irqentry_enter(regs); 349 instrumentation_begin(); 350 handle_invalid_op(regs); 351 instrumentation_end(); 352 irqentry_exit(regs, state); 353 } 354 355 DEFINE_IDTENTRY(exc_coproc_segment_overrun) 356 { 357 do_error_trap(regs, 0, "coprocessor segment overrun", 358 X86_TRAP_OLD_MF, SIGFPE, 0, NULL); 359 } 360 361 DEFINE_IDTENTRY_ERRORCODE(exc_invalid_tss) 362 { 363 do_error_trap(regs, error_code, "invalid TSS", X86_TRAP_TS, SIGSEGV, 364 0, NULL); 365 } 366 367 DEFINE_IDTENTRY_ERRORCODE(exc_segment_not_present) 368 { 369 do_error_trap(regs, error_code, "segment not present", X86_TRAP_NP, 370 SIGBUS, 0, NULL); 371 } 372 373 DEFINE_IDTENTRY_ERRORCODE(exc_stack_segment) 374 { 375 do_error_trap(regs, error_code, "stack segment", X86_TRAP_SS, SIGBUS, 376 0, NULL); 377 } 378 379 DEFINE_IDTENTRY_ERRORCODE(exc_alignment_check) 380 { 381 char *str = "alignment check"; 382 383 if (notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_AC, SIGBUS) == NOTIFY_STOP) 384 return; 385 386 if (!user_mode(regs)) 387 die("Split lock detected\n", regs, error_code); 388 389 local_irq_enable(); 390 391 if (handle_user_split_lock(regs, error_code)) 392 goto out; 393 394 do_trap(X86_TRAP_AC, SIGBUS, "alignment check", regs, 395 error_code, BUS_ADRALN, NULL); 396 397 out: 398 local_irq_disable(); 399 } 400 401 #ifdef CONFIG_VMAP_STACK 402 __visible void __noreturn handle_stack_overflow(struct pt_regs *regs, 403 unsigned long fault_address, 404 struct stack_info *info) 405 { 406 const char *name = stack_type_name(info->type); 407 408 printk(KERN_EMERG "BUG: %s stack guard page was hit at %p (stack is %p..%p)\n", 409 name, (void *)fault_address, info->begin, info->end); 410 411 die("stack guard page", regs, 0); 412 413 /* Be absolutely certain we don't return. */ 414 panic("%s stack guard hit", name); 415 } 416 #endif 417 418 /* 419 * Runs on an IST stack for x86_64 and on a special task stack for x86_32. 420 * 421 * On x86_64, this is more or less a normal kernel entry. Notwithstanding the 422 * SDM's warnings about double faults being unrecoverable, returning works as 423 * expected. Presumably what the SDM actually means is that the CPU may get 424 * the register state wrong on entry, so returning could be a bad idea. 425 * 426 * Various CPU engineers have promised that double faults due to an IRET fault 427 * while the stack is read-only are, in fact, recoverable. 428 * 429 * On x86_32, this is entered through a task gate, and regs are synthesized 430 * from the TSS. Returning is, in principle, okay, but changes to regs will 431 * be lost. If, for some reason, we need to return to a context with modified 432 * regs, the shim code could be adjusted to synchronize the registers. 433 * 434 * The 32bit #DF shim provides CR2 already as an argument. On 64bit it needs 435 * to be read before doing anything else. 436 */ 437 DEFINE_IDTENTRY_DF(exc_double_fault) 438 { 439 static const char str[] = "double fault"; 440 struct task_struct *tsk = current; 441 442 #ifdef CONFIG_VMAP_STACK 443 unsigned long address = read_cr2(); 444 struct stack_info info; 445 #endif 446 447 #ifdef CONFIG_X86_ESPFIX64 448 extern unsigned char native_irq_return_iret[]; 449 450 /* 451 * If IRET takes a non-IST fault on the espfix64 stack, then we 452 * end up promoting it to a doublefault. In that case, take 453 * advantage of the fact that we're not using the normal (TSS.sp0) 454 * stack right now. We can write a fake #GP(0) frame at TSS.sp0 455 * and then modify our own IRET frame so that, when we return, 456 * we land directly at the #GP(0) vector with the stack already 457 * set up according to its expectations. 458 * 459 * The net result is that our #GP handler will think that we 460 * entered from usermode with the bad user context. 461 * 462 * No need for nmi_enter() here because we don't use RCU. 463 */ 464 if (((long)regs->sp >> P4D_SHIFT) == ESPFIX_PGD_ENTRY && 465 regs->cs == __KERNEL_CS && 466 regs->ip == (unsigned long)native_irq_return_iret) 467 { 468 struct pt_regs *gpregs = (struct pt_regs *)this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1; 469 unsigned long *p = (unsigned long *)regs->sp; 470 471 /* 472 * regs->sp points to the failing IRET frame on the 473 * ESPFIX64 stack. Copy it to the entry stack. This fills 474 * in gpregs->ss through gpregs->ip. 475 * 476 */ 477 gpregs->ip = p[0]; 478 gpregs->cs = p[1]; 479 gpregs->flags = p[2]; 480 gpregs->sp = p[3]; 481 gpregs->ss = p[4]; 482 gpregs->orig_ax = 0; /* Missing (lost) #GP error code */ 483 484 /* 485 * Adjust our frame so that we return straight to the #GP 486 * vector with the expected RSP value. This is safe because 487 * we won't enable interrupts or schedule before we invoke 488 * general_protection, so nothing will clobber the stack 489 * frame we just set up. 490 * 491 * We will enter general_protection with kernel GSBASE, 492 * which is what the stub expects, given that the faulting 493 * RIP will be the IRET instruction. 494 */ 495 regs->ip = (unsigned long)asm_exc_general_protection; 496 regs->sp = (unsigned long)&gpregs->orig_ax; 497 498 return; 499 } 500 #endif 501 502 irqentry_nmi_enter(regs); 503 instrumentation_begin(); 504 notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV); 505 506 tsk->thread.error_code = error_code; 507 tsk->thread.trap_nr = X86_TRAP_DF; 508 509 #ifdef CONFIG_VMAP_STACK 510 /* 511 * If we overflow the stack into a guard page, the CPU will fail 512 * to deliver #PF and will send #DF instead. Similarly, if we 513 * take any non-IST exception while too close to the bottom of 514 * the stack, the processor will get a page fault while 515 * delivering the exception and will generate a double fault. 516 * 517 * According to the SDM (footnote in 6.15 under "Interrupt 14 - 518 * Page-Fault Exception (#PF): 519 * 520 * Processors update CR2 whenever a page fault is detected. If a 521 * second page fault occurs while an earlier page fault is being 522 * delivered, the faulting linear address of the second fault will 523 * overwrite the contents of CR2 (replacing the previous 524 * address). These updates to CR2 occur even if the page fault 525 * results in a double fault or occurs during the delivery of a 526 * double fault. 527 * 528 * The logic below has a small possibility of incorrectly diagnosing 529 * some errors as stack overflows. For example, if the IDT or GDT 530 * gets corrupted such that #GP delivery fails due to a bad descriptor 531 * causing #GP and we hit this condition while CR2 coincidentally 532 * points to the stack guard page, we'll think we overflowed the 533 * stack. Given that we're going to panic one way or another 534 * if this happens, this isn't necessarily worth fixing. 535 * 536 * If necessary, we could improve the test by only diagnosing 537 * a stack overflow if the saved RSP points within 47 bytes of 538 * the bottom of the stack: if RSP == tsk_stack + 48 and we 539 * take an exception, the stack is already aligned and there 540 * will be enough room SS, RSP, RFLAGS, CS, RIP, and a 541 * possible error code, so a stack overflow would *not* double 542 * fault. With any less space left, exception delivery could 543 * fail, and, as a practical matter, we've overflowed the 544 * stack even if the actual trigger for the double fault was 545 * something else. 546 */ 547 if (get_stack_guard_info((void *)address, &info)) 548 handle_stack_overflow(regs, address, &info); 549 #endif 550 551 pr_emerg("PANIC: double fault, error_code: 0x%lx\n", error_code); 552 die("double fault", regs, error_code); 553 panic("Machine halted."); 554 instrumentation_end(); 555 } 556 557 DEFINE_IDTENTRY(exc_bounds) 558 { 559 if (notify_die(DIE_TRAP, "bounds", regs, 0, 560 X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP) 561 return; 562 cond_local_irq_enable(regs); 563 564 if (!user_mode(regs)) 565 die("bounds", regs, 0); 566 567 do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, 0, 0, NULL); 568 569 cond_local_irq_disable(regs); 570 } 571 572 enum kernel_gp_hint { 573 GP_NO_HINT, 574 GP_NON_CANONICAL, 575 GP_CANONICAL 576 }; 577 578 /* 579 * When an uncaught #GP occurs, try to determine the memory address accessed by 580 * the instruction and return that address to the caller. Also, try to figure 581 * out whether any part of the access to that address was non-canonical. 582 */ 583 static enum kernel_gp_hint get_kernel_gp_address(struct pt_regs *regs, 584 unsigned long *addr) 585 { 586 u8 insn_buf[MAX_INSN_SIZE]; 587 struct insn insn; 588 int ret; 589 590 if (copy_from_kernel_nofault(insn_buf, (void *)regs->ip, 591 MAX_INSN_SIZE)) 592 return GP_NO_HINT; 593 594 ret = insn_decode_kernel(&insn, insn_buf); 595 if (ret < 0) 596 return GP_NO_HINT; 597 598 *addr = (unsigned long)insn_get_addr_ref(&insn, regs); 599 if (*addr == -1UL) 600 return GP_NO_HINT; 601 602 #ifdef CONFIG_X86_64 603 /* 604 * Check that: 605 * - the operand is not in the kernel half 606 * - the last byte of the operand is not in the user canonical half 607 */ 608 if (*addr < ~__VIRTUAL_MASK && 609 *addr + insn.opnd_bytes - 1 > __VIRTUAL_MASK) 610 return GP_NON_CANONICAL; 611 #endif 612 613 return GP_CANONICAL; 614 } 615 616 #define GPFSTR "general protection fault" 617 618 static bool fixup_iopl_exception(struct pt_regs *regs) 619 { 620 struct thread_struct *t = ¤t->thread; 621 unsigned char byte; 622 unsigned long ip; 623 624 if (!IS_ENABLED(CONFIG_X86_IOPL_IOPERM) || t->iopl_emul != 3) 625 return false; 626 627 if (insn_get_effective_ip(regs, &ip)) 628 return false; 629 630 if (get_user(byte, (const char __user *)ip)) 631 return false; 632 633 if (byte != 0xfa && byte != 0xfb) 634 return false; 635 636 if (!t->iopl_warn && printk_ratelimit()) { 637 pr_err("%s[%d] attempts to use CLI/STI, pretending it's a NOP, ip:%lx", 638 current->comm, task_pid_nr(current), ip); 639 print_vma_addr(KERN_CONT " in ", ip); 640 pr_cont("\n"); 641 t->iopl_warn = 1; 642 } 643 644 regs->ip += 1; 645 return true; 646 } 647 648 /* 649 * The unprivileged ENQCMD instruction generates #GPs if the 650 * IA32_PASID MSR has not been populated. If possible, populate 651 * the MSR from a PASID previously allocated to the mm. 652 */ 653 static bool try_fixup_enqcmd_gp(void) 654 { 655 #ifdef CONFIG_IOMMU_SVA 656 u32 pasid; 657 658 /* 659 * MSR_IA32_PASID is managed using XSAVE. Directly 660 * writing to the MSR is only possible when fpregs 661 * are valid and the fpstate is not. This is 662 * guaranteed when handling a userspace exception 663 * in *before* interrupts are re-enabled. 664 */ 665 lockdep_assert_irqs_disabled(); 666 667 /* 668 * Hardware without ENQCMD will not generate 669 * #GPs that can be fixed up here. 670 */ 671 if (!cpu_feature_enabled(X86_FEATURE_ENQCMD)) 672 return false; 673 674 /* 675 * If the mm has not been allocated a 676 * PASID, the #GP can not be fixed up. 677 */ 678 if (!mm_valid_pasid(current->mm)) 679 return false; 680 681 pasid = current->mm->pasid; 682 683 /* 684 * Did this thread already have its PASID activated? 685 * If so, the #GP must be from something else. 686 */ 687 if (current->pasid_activated) 688 return false; 689 690 wrmsrl(MSR_IA32_PASID, pasid | MSR_IA32_PASID_VALID); 691 current->pasid_activated = 1; 692 693 return true; 694 #else 695 return false; 696 #endif 697 } 698 699 static bool gp_try_fixup_and_notify(struct pt_regs *regs, int trapnr, 700 unsigned long error_code, const char *str, 701 unsigned long address) 702 { 703 if (fixup_exception(regs, trapnr, error_code, address)) 704 return true; 705 706 current->thread.error_code = error_code; 707 current->thread.trap_nr = trapnr; 708 709 /* 710 * To be potentially processing a kprobe fault and to trust the result 711 * from kprobe_running(), we have to be non-preemptible. 712 */ 713 if (!preemptible() && kprobe_running() && 714 kprobe_fault_handler(regs, trapnr)) 715 return true; 716 717 return notify_die(DIE_GPF, str, regs, error_code, trapnr, SIGSEGV) == NOTIFY_STOP; 718 } 719 720 static void gp_user_force_sig_segv(struct pt_regs *regs, int trapnr, 721 unsigned long error_code, const char *str) 722 { 723 current->thread.error_code = error_code; 724 current->thread.trap_nr = trapnr; 725 show_signal(current, SIGSEGV, "", str, regs, error_code); 726 force_sig(SIGSEGV); 727 } 728 729 DEFINE_IDTENTRY_ERRORCODE(exc_general_protection) 730 { 731 char desc[sizeof(GPFSTR) + 50 + 2*sizeof(unsigned long) + 1] = GPFSTR; 732 enum kernel_gp_hint hint = GP_NO_HINT; 733 unsigned long gp_addr; 734 735 if (user_mode(regs) && try_fixup_enqcmd_gp()) 736 return; 737 738 cond_local_irq_enable(regs); 739 740 if (static_cpu_has(X86_FEATURE_UMIP)) { 741 if (user_mode(regs) && fixup_umip_exception(regs)) 742 goto exit; 743 } 744 745 if (v8086_mode(regs)) { 746 local_irq_enable(); 747 handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code); 748 local_irq_disable(); 749 return; 750 } 751 752 if (user_mode(regs)) { 753 if (fixup_iopl_exception(regs)) 754 goto exit; 755 756 if (fixup_vdso_exception(regs, X86_TRAP_GP, error_code, 0)) 757 goto exit; 758 759 gp_user_force_sig_segv(regs, X86_TRAP_GP, error_code, desc); 760 goto exit; 761 } 762 763 if (gp_try_fixup_and_notify(regs, X86_TRAP_GP, error_code, desc, 0)) 764 goto exit; 765 766 if (error_code) 767 snprintf(desc, sizeof(desc), "segment-related " GPFSTR); 768 else 769 hint = get_kernel_gp_address(regs, &gp_addr); 770 771 if (hint != GP_NO_HINT) 772 snprintf(desc, sizeof(desc), GPFSTR ", %s 0x%lx", 773 (hint == GP_NON_CANONICAL) ? "probably for non-canonical address" 774 : "maybe for address", 775 gp_addr); 776 777 /* 778 * KASAN is interested only in the non-canonical case, clear it 779 * otherwise. 780 */ 781 if (hint != GP_NON_CANONICAL) 782 gp_addr = 0; 783 784 die_addr(desc, regs, error_code, gp_addr); 785 786 exit: 787 cond_local_irq_disable(regs); 788 } 789 790 static bool do_int3(struct pt_regs *regs) 791 { 792 int res; 793 794 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP 795 if (kgdb_ll_trap(DIE_INT3, "int3", regs, 0, X86_TRAP_BP, 796 SIGTRAP) == NOTIFY_STOP) 797 return true; 798 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ 799 800 #ifdef CONFIG_KPROBES 801 if (kprobe_int3_handler(regs)) 802 return true; 803 #endif 804 res = notify_die(DIE_INT3, "int3", regs, 0, X86_TRAP_BP, SIGTRAP); 805 806 return res == NOTIFY_STOP; 807 } 808 NOKPROBE_SYMBOL(do_int3); 809 810 static void do_int3_user(struct pt_regs *regs) 811 { 812 if (do_int3(regs)) 813 return; 814 815 cond_local_irq_enable(regs); 816 do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, 0, 0, NULL); 817 cond_local_irq_disable(regs); 818 } 819 820 DEFINE_IDTENTRY_RAW(exc_int3) 821 { 822 /* 823 * poke_int3_handler() is completely self contained code; it does (and 824 * must) *NOT* call out to anything, lest it hits upon yet another 825 * INT3. 826 */ 827 if (poke_int3_handler(regs)) 828 return; 829 830 /* 831 * irqentry_enter_from_user_mode() uses static_branch_{,un}likely() 832 * and therefore can trigger INT3, hence poke_int3_handler() must 833 * be done before. If the entry came from kernel mode, then use 834 * nmi_enter() because the INT3 could have been hit in any context 835 * including NMI. 836 */ 837 if (user_mode(regs)) { 838 irqentry_enter_from_user_mode(regs); 839 instrumentation_begin(); 840 do_int3_user(regs); 841 instrumentation_end(); 842 irqentry_exit_to_user_mode(regs); 843 } else { 844 irqentry_state_t irq_state = irqentry_nmi_enter(regs); 845 846 instrumentation_begin(); 847 if (!do_int3(regs)) 848 die("int3", regs, 0); 849 instrumentation_end(); 850 irqentry_nmi_exit(regs, irq_state); 851 } 852 } 853 854 #ifdef CONFIG_X86_64 855 /* 856 * Help handler running on a per-cpu (IST or entry trampoline) stack 857 * to switch to the normal thread stack if the interrupted code was in 858 * user mode. The actual stack switch is done in entry_64.S 859 */ 860 asmlinkage __visible noinstr struct pt_regs *sync_regs(struct pt_regs *eregs) 861 { 862 struct pt_regs *regs = (struct pt_regs *)this_cpu_read(pcpu_hot.top_of_stack) - 1; 863 if (regs != eregs) 864 *regs = *eregs; 865 return regs; 866 } 867 868 #ifdef CONFIG_AMD_MEM_ENCRYPT 869 asmlinkage __visible noinstr struct pt_regs *vc_switch_off_ist(struct pt_regs *regs) 870 { 871 unsigned long sp, *stack; 872 struct stack_info info; 873 struct pt_regs *regs_ret; 874 875 /* 876 * In the SYSCALL entry path the RSP value comes from user-space - don't 877 * trust it and switch to the current kernel stack 878 */ 879 if (ip_within_syscall_gap(regs)) { 880 sp = this_cpu_read(pcpu_hot.top_of_stack); 881 goto sync; 882 } 883 884 /* 885 * From here on the RSP value is trusted. Now check whether entry 886 * happened from a safe stack. Not safe are the entry or unknown stacks, 887 * use the fall-back stack instead in this case. 888 */ 889 sp = regs->sp; 890 stack = (unsigned long *)sp; 891 892 if (!get_stack_info_noinstr(stack, current, &info) || info.type == STACK_TYPE_ENTRY || 893 info.type > STACK_TYPE_EXCEPTION_LAST) 894 sp = __this_cpu_ist_top_va(VC2); 895 896 sync: 897 /* 898 * Found a safe stack - switch to it as if the entry didn't happen via 899 * IST stack. The code below only copies pt_regs, the real switch happens 900 * in assembly code. 901 */ 902 sp = ALIGN_DOWN(sp, 8) - sizeof(*regs_ret); 903 904 regs_ret = (struct pt_regs *)sp; 905 *regs_ret = *regs; 906 907 return regs_ret; 908 } 909 #endif 910 911 asmlinkage __visible noinstr struct pt_regs *fixup_bad_iret(struct pt_regs *bad_regs) 912 { 913 struct pt_regs tmp, *new_stack; 914 915 /* 916 * This is called from entry_64.S early in handling a fault 917 * caused by a bad iret to user mode. To handle the fault 918 * correctly, we want to move our stack frame to where it would 919 * be had we entered directly on the entry stack (rather than 920 * just below the IRET frame) and we want to pretend that the 921 * exception came from the IRET target. 922 */ 923 new_stack = (struct pt_regs *)__this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1; 924 925 /* Copy the IRET target to the temporary storage. */ 926 __memcpy(&tmp.ip, (void *)bad_regs->sp, 5*8); 927 928 /* Copy the remainder of the stack from the current stack. */ 929 __memcpy(&tmp, bad_regs, offsetof(struct pt_regs, ip)); 930 931 /* Update the entry stack */ 932 __memcpy(new_stack, &tmp, sizeof(tmp)); 933 934 BUG_ON(!user_mode(new_stack)); 935 return new_stack; 936 } 937 #endif 938 939 static bool is_sysenter_singlestep(struct pt_regs *regs) 940 { 941 /* 942 * We don't try for precision here. If we're anywhere in the region of 943 * code that can be single-stepped in the SYSENTER entry path, then 944 * assume that this is a useless single-step trap due to SYSENTER 945 * being invoked with TF set. (We don't know in advance exactly 946 * which instructions will be hit because BTF could plausibly 947 * be set.) 948 */ 949 #ifdef CONFIG_X86_32 950 return (regs->ip - (unsigned long)__begin_SYSENTER_singlestep_region) < 951 (unsigned long)__end_SYSENTER_singlestep_region - 952 (unsigned long)__begin_SYSENTER_singlestep_region; 953 #elif defined(CONFIG_IA32_EMULATION) 954 return (regs->ip - (unsigned long)entry_SYSENTER_compat) < 955 (unsigned long)__end_entry_SYSENTER_compat - 956 (unsigned long)entry_SYSENTER_compat; 957 #else 958 return false; 959 #endif 960 } 961 962 static __always_inline unsigned long debug_read_clear_dr6(void) 963 { 964 unsigned long dr6; 965 966 /* 967 * The Intel SDM says: 968 * 969 * Certain debug exceptions may clear bits 0-3. The remaining 970 * contents of the DR6 register are never cleared by the 971 * processor. To avoid confusion in identifying debug 972 * exceptions, debug handlers should clear the register before 973 * returning to the interrupted task. 974 * 975 * Keep it simple: clear DR6 immediately. 976 */ 977 get_debugreg(dr6, 6); 978 set_debugreg(DR6_RESERVED, 6); 979 dr6 ^= DR6_RESERVED; /* Flip to positive polarity */ 980 981 return dr6; 982 } 983 984 /* 985 * Our handling of the processor debug registers is non-trivial. 986 * We do not clear them on entry and exit from the kernel. Therefore 987 * it is possible to get a watchpoint trap here from inside the kernel. 988 * However, the code in ./ptrace.c has ensured that the user can 989 * only set watchpoints on userspace addresses. Therefore the in-kernel 990 * watchpoint trap can only occur in code which is reading/writing 991 * from user space. Such code must not hold kernel locks (since it 992 * can equally take a page fault), therefore it is safe to call 993 * force_sig_info even though that claims and releases locks. 994 * 995 * Code in ./signal.c ensures that the debug control register 996 * is restored before we deliver any signal, and therefore that 997 * user code runs with the correct debug control register even though 998 * we clear it here. 999 * 1000 * Being careful here means that we don't have to be as careful in a 1001 * lot of more complicated places (task switching can be a bit lazy 1002 * about restoring all the debug state, and ptrace doesn't have to 1003 * find every occurrence of the TF bit that could be saved away even 1004 * by user code) 1005 * 1006 * May run on IST stack. 1007 */ 1008 1009 static bool notify_debug(struct pt_regs *regs, unsigned long *dr6) 1010 { 1011 /* 1012 * Notifiers will clear bits in @dr6 to indicate the event has been 1013 * consumed - hw_breakpoint_handler(), single_stop_cont(). 1014 * 1015 * Notifiers will set bits in @virtual_dr6 to indicate the desire 1016 * for signals - ptrace_triggered(), kgdb_hw_overflow_handler(). 1017 */ 1018 if (notify_die(DIE_DEBUG, "debug", regs, (long)dr6, 0, SIGTRAP) == NOTIFY_STOP) 1019 return true; 1020 1021 return false; 1022 } 1023 1024 static __always_inline void exc_debug_kernel(struct pt_regs *regs, 1025 unsigned long dr6) 1026 { 1027 /* 1028 * Disable breakpoints during exception handling; recursive exceptions 1029 * are exceedingly 'fun'. 1030 * 1031 * Since this function is NOKPROBE, and that also applies to 1032 * HW_BREAKPOINT_X, we can't hit a breakpoint before this (XXX except a 1033 * HW_BREAKPOINT_W on our stack) 1034 * 1035 * Entry text is excluded for HW_BP_X and cpu_entry_area, which 1036 * includes the entry stack is excluded for everything. 1037 */ 1038 unsigned long dr7 = local_db_save(); 1039 irqentry_state_t irq_state = irqentry_nmi_enter(regs); 1040 instrumentation_begin(); 1041 1042 /* 1043 * If something gets miswired and we end up here for a user mode 1044 * #DB, we will malfunction. 1045 */ 1046 WARN_ON_ONCE(user_mode(regs)); 1047 1048 if (test_thread_flag(TIF_BLOCKSTEP)) { 1049 /* 1050 * The SDM says "The processor clears the BTF flag when it 1051 * generates a debug exception." but PTRACE_BLOCKSTEP requested 1052 * it for userspace, but we just took a kernel #DB, so re-set 1053 * BTF. 1054 */ 1055 unsigned long debugctl; 1056 1057 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 1058 debugctl |= DEBUGCTLMSR_BTF; 1059 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 1060 } 1061 1062 /* 1063 * Catch SYSENTER with TF set and clear DR_STEP. If this hit a 1064 * watchpoint at the same time then that will still be handled. 1065 */ 1066 if ((dr6 & DR_STEP) && is_sysenter_singlestep(regs)) 1067 dr6 &= ~DR_STEP; 1068 1069 /* 1070 * The kernel doesn't use INT1 1071 */ 1072 if (!dr6) 1073 goto out; 1074 1075 if (notify_debug(regs, &dr6)) 1076 goto out; 1077 1078 /* 1079 * The kernel doesn't use TF single-step outside of: 1080 * 1081 * - Kprobes, consumed through kprobe_debug_handler() 1082 * - KGDB, consumed through notify_debug() 1083 * 1084 * So if we get here with DR_STEP set, something is wonky. 1085 * 1086 * A known way to trigger this is through QEMU's GDB stub, 1087 * which leaks #DB into the guest and causes IST recursion. 1088 */ 1089 if (WARN_ON_ONCE(dr6 & DR_STEP)) 1090 regs->flags &= ~X86_EFLAGS_TF; 1091 out: 1092 instrumentation_end(); 1093 irqentry_nmi_exit(regs, irq_state); 1094 1095 local_db_restore(dr7); 1096 } 1097 1098 static __always_inline void exc_debug_user(struct pt_regs *regs, 1099 unsigned long dr6) 1100 { 1101 bool icebp; 1102 1103 /* 1104 * If something gets miswired and we end up here for a kernel mode 1105 * #DB, we will malfunction. 1106 */ 1107 WARN_ON_ONCE(!user_mode(regs)); 1108 1109 /* 1110 * NB: We can't easily clear DR7 here because 1111 * irqentry_exit_to_usermode() can invoke ptrace, schedule, access 1112 * user memory, etc. This means that a recursive #DB is possible. If 1113 * this happens, that #DB will hit exc_debug_kernel() and clear DR7. 1114 * Since we're not on the IST stack right now, everything will be 1115 * fine. 1116 */ 1117 1118 irqentry_enter_from_user_mode(regs); 1119 instrumentation_begin(); 1120 1121 /* 1122 * Start the virtual/ptrace DR6 value with just the DR_STEP mask 1123 * of the real DR6. ptrace_triggered() will set the DR_TRAPn bits. 1124 * 1125 * Userspace expects DR_STEP to be visible in ptrace_get_debugreg(6) 1126 * even if it is not the result of PTRACE_SINGLESTEP. 1127 */ 1128 current->thread.virtual_dr6 = (dr6 & DR_STEP); 1129 1130 /* 1131 * The SDM says "The processor clears the BTF flag when it 1132 * generates a debug exception." Clear TIF_BLOCKSTEP to keep 1133 * TIF_BLOCKSTEP in sync with the hardware BTF flag. 1134 */ 1135 clear_thread_flag(TIF_BLOCKSTEP); 1136 1137 /* 1138 * If dr6 has no reason to give us about the origin of this trap, 1139 * then it's very likely the result of an icebp/int01 trap. 1140 * User wants a sigtrap for that. 1141 */ 1142 icebp = !dr6; 1143 1144 if (notify_debug(regs, &dr6)) 1145 goto out; 1146 1147 /* It's safe to allow irq's after DR6 has been saved */ 1148 local_irq_enable(); 1149 1150 if (v8086_mode(regs)) { 1151 handle_vm86_trap((struct kernel_vm86_regs *)regs, 0, X86_TRAP_DB); 1152 goto out_irq; 1153 } 1154 1155 /* #DB for bus lock can only be triggered from userspace. */ 1156 if (dr6 & DR_BUS_LOCK) 1157 handle_bus_lock(regs); 1158 1159 /* Add the virtual_dr6 bits for signals. */ 1160 dr6 |= current->thread.virtual_dr6; 1161 if (dr6 & (DR_STEP | DR_TRAP_BITS) || icebp) 1162 send_sigtrap(regs, 0, get_si_code(dr6)); 1163 1164 out_irq: 1165 local_irq_disable(); 1166 out: 1167 instrumentation_end(); 1168 irqentry_exit_to_user_mode(regs); 1169 } 1170 1171 #ifdef CONFIG_X86_64 1172 /* IST stack entry */ 1173 DEFINE_IDTENTRY_DEBUG(exc_debug) 1174 { 1175 exc_debug_kernel(regs, debug_read_clear_dr6()); 1176 } 1177 1178 /* User entry, runs on regular task stack */ 1179 DEFINE_IDTENTRY_DEBUG_USER(exc_debug) 1180 { 1181 exc_debug_user(regs, debug_read_clear_dr6()); 1182 } 1183 #else 1184 /* 32 bit does not have separate entry points. */ 1185 DEFINE_IDTENTRY_RAW(exc_debug) 1186 { 1187 unsigned long dr6 = debug_read_clear_dr6(); 1188 1189 if (user_mode(regs)) 1190 exc_debug_user(regs, dr6); 1191 else 1192 exc_debug_kernel(regs, dr6); 1193 } 1194 #endif 1195 1196 /* 1197 * Note that we play around with the 'TS' bit in an attempt to get 1198 * the correct behaviour even in the presence of the asynchronous 1199 * IRQ13 behaviour 1200 */ 1201 static void math_error(struct pt_regs *regs, int trapnr) 1202 { 1203 struct task_struct *task = current; 1204 struct fpu *fpu = &task->thread.fpu; 1205 int si_code; 1206 char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" : 1207 "simd exception"; 1208 1209 cond_local_irq_enable(regs); 1210 1211 if (!user_mode(regs)) { 1212 if (fixup_exception(regs, trapnr, 0, 0)) 1213 goto exit; 1214 1215 task->thread.error_code = 0; 1216 task->thread.trap_nr = trapnr; 1217 1218 if (notify_die(DIE_TRAP, str, regs, 0, trapnr, 1219 SIGFPE) != NOTIFY_STOP) 1220 die(str, regs, 0); 1221 goto exit; 1222 } 1223 1224 /* 1225 * Synchronize the FPU register state to the memory register state 1226 * if necessary. This allows the exception handler to inspect it. 1227 */ 1228 fpu_sync_fpstate(fpu); 1229 1230 task->thread.trap_nr = trapnr; 1231 task->thread.error_code = 0; 1232 1233 si_code = fpu__exception_code(fpu, trapnr); 1234 /* Retry when we get spurious exceptions: */ 1235 if (!si_code) 1236 goto exit; 1237 1238 if (fixup_vdso_exception(regs, trapnr, 0, 0)) 1239 goto exit; 1240 1241 force_sig_fault(SIGFPE, si_code, 1242 (void __user *)uprobe_get_trap_addr(regs)); 1243 exit: 1244 cond_local_irq_disable(regs); 1245 } 1246 1247 DEFINE_IDTENTRY(exc_coprocessor_error) 1248 { 1249 math_error(regs, X86_TRAP_MF); 1250 } 1251 1252 DEFINE_IDTENTRY(exc_simd_coprocessor_error) 1253 { 1254 if (IS_ENABLED(CONFIG_X86_INVD_BUG)) { 1255 /* AMD 486 bug: INVD in CPL 0 raises #XF instead of #GP */ 1256 if (!static_cpu_has(X86_FEATURE_XMM)) { 1257 __exc_general_protection(regs, 0); 1258 return; 1259 } 1260 } 1261 math_error(regs, X86_TRAP_XF); 1262 } 1263 1264 DEFINE_IDTENTRY(exc_spurious_interrupt_bug) 1265 { 1266 /* 1267 * This addresses a Pentium Pro Erratum: 1268 * 1269 * PROBLEM: If the APIC subsystem is configured in mixed mode with 1270 * Virtual Wire mode implemented through the local APIC, an 1271 * interrupt vector of 0Fh (Intel reserved encoding) may be 1272 * generated by the local APIC (Int 15). This vector may be 1273 * generated upon receipt of a spurious interrupt (an interrupt 1274 * which is removed before the system receives the INTA sequence) 1275 * instead of the programmed 8259 spurious interrupt vector. 1276 * 1277 * IMPLICATION: The spurious interrupt vector programmed in the 1278 * 8259 is normally handled by an operating system's spurious 1279 * interrupt handler. However, a vector of 0Fh is unknown to some 1280 * operating systems, which would crash if this erratum occurred. 1281 * 1282 * In theory this could be limited to 32bit, but the handler is not 1283 * hurting and who knows which other CPUs suffer from this. 1284 */ 1285 } 1286 1287 static bool handle_xfd_event(struct pt_regs *regs) 1288 { 1289 u64 xfd_err; 1290 int err; 1291 1292 if (!IS_ENABLED(CONFIG_X86_64) || !cpu_feature_enabled(X86_FEATURE_XFD)) 1293 return false; 1294 1295 rdmsrl(MSR_IA32_XFD_ERR, xfd_err); 1296 if (!xfd_err) 1297 return false; 1298 1299 wrmsrl(MSR_IA32_XFD_ERR, 0); 1300 1301 /* Die if that happens in kernel space */ 1302 if (WARN_ON(!user_mode(regs))) 1303 return false; 1304 1305 local_irq_enable(); 1306 1307 err = xfd_enable_feature(xfd_err); 1308 1309 switch (err) { 1310 case -EPERM: 1311 force_sig_fault(SIGILL, ILL_ILLOPC, error_get_trap_addr(regs)); 1312 break; 1313 case -EFAULT: 1314 force_sig(SIGSEGV); 1315 break; 1316 } 1317 1318 local_irq_disable(); 1319 return true; 1320 } 1321 1322 DEFINE_IDTENTRY(exc_device_not_available) 1323 { 1324 unsigned long cr0 = read_cr0(); 1325 1326 if (handle_xfd_event(regs)) 1327 return; 1328 1329 #ifdef CONFIG_MATH_EMULATION 1330 if (!boot_cpu_has(X86_FEATURE_FPU) && (cr0 & X86_CR0_EM)) { 1331 struct math_emu_info info = { }; 1332 1333 cond_local_irq_enable(regs); 1334 1335 info.regs = regs; 1336 math_emulate(&info); 1337 1338 cond_local_irq_disable(regs); 1339 return; 1340 } 1341 #endif 1342 1343 /* This should not happen. */ 1344 if (WARN(cr0 & X86_CR0_TS, "CR0.TS was set")) { 1345 /* Try to fix it up and carry on. */ 1346 write_cr0(cr0 & ~X86_CR0_TS); 1347 } else { 1348 /* 1349 * Something terrible happened, and we're better off trying 1350 * to kill the task than getting stuck in a never-ending 1351 * loop of #NM faults. 1352 */ 1353 die("unexpected #NM exception", regs, 0); 1354 } 1355 } 1356 1357 #ifdef CONFIG_INTEL_TDX_GUEST 1358 1359 #define VE_FAULT_STR "VE fault" 1360 1361 static void ve_raise_fault(struct pt_regs *regs, long error_code, 1362 unsigned long address) 1363 { 1364 if (user_mode(regs)) { 1365 gp_user_force_sig_segv(regs, X86_TRAP_VE, error_code, VE_FAULT_STR); 1366 return; 1367 } 1368 1369 if (gp_try_fixup_and_notify(regs, X86_TRAP_VE, error_code, 1370 VE_FAULT_STR, address)) { 1371 return; 1372 } 1373 1374 die_addr(VE_FAULT_STR, regs, error_code, address); 1375 } 1376 1377 /* 1378 * Virtualization Exceptions (#VE) are delivered to TDX guests due to 1379 * specific guest actions which may happen in either user space or the 1380 * kernel: 1381 * 1382 * * Specific instructions (WBINVD, for example) 1383 * * Specific MSR accesses 1384 * * Specific CPUID leaf accesses 1385 * * Access to specific guest physical addresses 1386 * 1387 * In the settings that Linux will run in, virtualization exceptions are 1388 * never generated on accesses to normal, TD-private memory that has been 1389 * accepted (by BIOS or with tdx_enc_status_changed()). 1390 * 1391 * Syscall entry code has a critical window where the kernel stack is not 1392 * yet set up. Any exception in this window leads to hard to debug issues 1393 * and can be exploited for privilege escalation. Exceptions in the NMI 1394 * entry code also cause issues. Returning from the exception handler with 1395 * IRET will re-enable NMIs and nested NMI will corrupt the NMI stack. 1396 * 1397 * For these reasons, the kernel avoids #VEs during the syscall gap and 1398 * the NMI entry code. Entry code paths do not access TD-shared memory, 1399 * MMIO regions, use #VE triggering MSRs, instructions, or CPUID leaves 1400 * that might generate #VE. VMM can remove memory from TD at any point, 1401 * but access to unaccepted (or missing) private memory leads to VM 1402 * termination, not to #VE. 1403 * 1404 * Similarly to page faults and breakpoints, #VEs are allowed in NMI 1405 * handlers once the kernel is ready to deal with nested NMIs. 1406 * 1407 * During #VE delivery, all interrupts, including NMIs, are blocked until 1408 * TDGETVEINFO is called. It prevents #VE nesting until the kernel reads 1409 * the VE info. 1410 * 1411 * If a guest kernel action which would normally cause a #VE occurs in 1412 * the interrupt-disabled region before TDGETVEINFO, a #DF (fault 1413 * exception) is delivered to the guest which will result in an oops. 1414 * 1415 * The entry code has been audited carefully for following these expectations. 1416 * Changes in the entry code have to be audited for correctness vs. this 1417 * aspect. Similarly to #PF, #VE in these places will expose kernel to 1418 * privilege escalation or may lead to random crashes. 1419 */ 1420 DEFINE_IDTENTRY(exc_virtualization_exception) 1421 { 1422 struct ve_info ve; 1423 1424 /* 1425 * NMIs/Machine-checks/Interrupts will be in a disabled state 1426 * till TDGETVEINFO TDCALL is executed. This ensures that VE 1427 * info cannot be overwritten by a nested #VE. 1428 */ 1429 tdx_get_ve_info(&ve); 1430 1431 cond_local_irq_enable(regs); 1432 1433 /* 1434 * If tdx_handle_virt_exception() could not process 1435 * it successfully, treat it as #GP(0) and handle it. 1436 */ 1437 if (!tdx_handle_virt_exception(regs, &ve)) 1438 ve_raise_fault(regs, 0, ve.gla); 1439 1440 cond_local_irq_disable(regs); 1441 } 1442 1443 #endif 1444 1445 #ifdef CONFIG_X86_32 1446 DEFINE_IDTENTRY_SW(iret_error) 1447 { 1448 local_irq_enable(); 1449 if (notify_die(DIE_TRAP, "iret exception", regs, 0, 1450 X86_TRAP_IRET, SIGILL) != NOTIFY_STOP) { 1451 do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, 0, 1452 ILL_BADSTK, (void __user *)NULL); 1453 } 1454 local_irq_disable(); 1455 } 1456 #endif 1457 1458 void __init trap_init(void) 1459 { 1460 /* Init cpu_entry_area before IST entries are set up */ 1461 setup_cpu_entry_areas(); 1462 1463 /* Init GHCB memory pages when running as an SEV-ES guest */ 1464 sev_es_init_vc_handling(); 1465 1466 /* Initialize TSS before setting up traps so ISTs work */ 1467 cpu_init_exception_handling(); 1468 /* Setup traps as cpu_init() might #GP */ 1469 idt_setup_traps(); 1470 cpu_init(); 1471 } 1472