1 /* 2 * Copyright (C) 1991, 1992 Linus Torvalds 3 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs 4 * 5 * Pentium III FXSR, SSE support 6 * Gareth Hughes <gareth@valinux.com>, May 2000 7 */ 8 9 /* 10 * Handle hardware traps and faults. 11 */ 12 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 15 #include <linux/context_tracking.h> 16 #include <linux/interrupt.h> 17 #include <linux/kallsyms.h> 18 #include <linux/spinlock.h> 19 #include <linux/kprobes.h> 20 #include <linux/uaccess.h> 21 #include <linux/kdebug.h> 22 #include <linux/kgdb.h> 23 #include <linux/kernel.h> 24 #include <linux/export.h> 25 #include <linux/ptrace.h> 26 #include <linux/uprobes.h> 27 #include <linux/string.h> 28 #include <linux/delay.h> 29 #include <linux/errno.h> 30 #include <linux/kexec.h> 31 #include <linux/sched.h> 32 #include <linux/sched/task_stack.h> 33 #include <linux/timer.h> 34 #include <linux/init.h> 35 #include <linux/bug.h> 36 #include <linux/nmi.h> 37 #include <linux/mm.h> 38 #include <linux/smp.h> 39 #include <linux/io.h> 40 #include <linux/hardirq.h> 41 #include <linux/atomic.h> 42 43 #include <asm/stacktrace.h> 44 #include <asm/processor.h> 45 #include <asm/debugreg.h> 46 #include <asm/text-patching.h> 47 #include <asm/ftrace.h> 48 #include <asm/traps.h> 49 #include <asm/desc.h> 50 #include <asm/fpu/internal.h> 51 #include <asm/cpu.h> 52 #include <asm/cpu_entry_area.h> 53 #include <asm/mce.h> 54 #include <asm/fixmap.h> 55 #include <asm/mach_traps.h> 56 #include <asm/alternative.h> 57 #include <asm/fpu/xstate.h> 58 #include <asm/vm86.h> 59 #include <asm/umip.h> 60 #include <asm/insn.h> 61 #include <asm/insn-eval.h> 62 63 #ifdef CONFIG_X86_64 64 #include <asm/x86_init.h> 65 #include <asm/proto.h> 66 #else 67 #include <asm/processor-flags.h> 68 #include <asm/setup.h> 69 #include <asm/proto.h> 70 #endif 71 72 DECLARE_BITMAP(system_vectors, NR_VECTORS); 73 74 static inline void cond_local_irq_enable(struct pt_regs *regs) 75 { 76 if (regs->flags & X86_EFLAGS_IF) 77 local_irq_enable(); 78 } 79 80 static inline void cond_local_irq_disable(struct pt_regs *regs) 81 { 82 if (regs->flags & X86_EFLAGS_IF) 83 local_irq_disable(); 84 } 85 86 __always_inline int is_valid_bugaddr(unsigned long addr) 87 { 88 if (addr < TASK_SIZE_MAX) 89 return 0; 90 91 /* 92 * We got #UD, if the text isn't readable we'd have gotten 93 * a different exception. 94 */ 95 return *(unsigned short *)addr == INSN_UD2; 96 } 97 98 static nokprobe_inline int 99 do_trap_no_signal(struct task_struct *tsk, int trapnr, const char *str, 100 struct pt_regs *regs, long error_code) 101 { 102 if (v8086_mode(regs)) { 103 /* 104 * Traps 0, 1, 3, 4, and 5 should be forwarded to vm86. 105 * On nmi (interrupt 2), do_trap should not be called. 106 */ 107 if (trapnr < X86_TRAP_UD) { 108 if (!handle_vm86_trap((struct kernel_vm86_regs *) regs, 109 error_code, trapnr)) 110 return 0; 111 } 112 } else if (!user_mode(regs)) { 113 if (fixup_exception(regs, trapnr, error_code, 0)) 114 return 0; 115 116 tsk->thread.error_code = error_code; 117 tsk->thread.trap_nr = trapnr; 118 die(str, regs, error_code); 119 } 120 121 /* 122 * We want error_code and trap_nr set for userspace faults and 123 * kernelspace faults which result in die(), but not 124 * kernelspace faults which are fixed up. die() gives the 125 * process no chance to handle the signal and notice the 126 * kernel fault information, so that won't result in polluting 127 * the information about previously queued, but not yet 128 * delivered, faults. See also exc_general_protection below. 129 */ 130 tsk->thread.error_code = error_code; 131 tsk->thread.trap_nr = trapnr; 132 133 return -1; 134 } 135 136 static void show_signal(struct task_struct *tsk, int signr, 137 const char *type, const char *desc, 138 struct pt_regs *regs, long error_code) 139 { 140 if (show_unhandled_signals && unhandled_signal(tsk, signr) && 141 printk_ratelimit()) { 142 pr_info("%s[%d] %s%s ip:%lx sp:%lx error:%lx", 143 tsk->comm, task_pid_nr(tsk), type, desc, 144 regs->ip, regs->sp, error_code); 145 print_vma_addr(KERN_CONT " in ", regs->ip); 146 pr_cont("\n"); 147 } 148 } 149 150 static void 151 do_trap(int trapnr, int signr, char *str, struct pt_regs *regs, 152 long error_code, int sicode, void __user *addr) 153 { 154 struct task_struct *tsk = current; 155 156 if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code)) 157 return; 158 159 show_signal(tsk, signr, "trap ", str, regs, error_code); 160 161 if (!sicode) 162 force_sig(signr); 163 else 164 force_sig_fault(signr, sicode, addr); 165 } 166 NOKPROBE_SYMBOL(do_trap); 167 168 static void do_error_trap(struct pt_regs *regs, long error_code, char *str, 169 unsigned long trapnr, int signr, int sicode, void __user *addr) 170 { 171 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); 172 173 if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) != 174 NOTIFY_STOP) { 175 cond_local_irq_enable(regs); 176 do_trap(trapnr, signr, str, regs, error_code, sicode, addr); 177 cond_local_irq_disable(regs); 178 } 179 } 180 181 /* 182 * Posix requires to provide the address of the faulting instruction for 183 * SIGILL (#UD) and SIGFPE (#DE) in the si_addr member of siginfo_t. 184 * 185 * This address is usually regs->ip, but when an uprobe moved the code out 186 * of line then regs->ip points to the XOL code which would confuse 187 * anything which analyzes the fault address vs. the unmodified binary. If 188 * a trap happened in XOL code then uprobe maps regs->ip back to the 189 * original instruction address. 190 */ 191 static __always_inline void __user *error_get_trap_addr(struct pt_regs *regs) 192 { 193 return (void __user *)uprobe_get_trap_addr(regs); 194 } 195 196 DEFINE_IDTENTRY(exc_divide_error) 197 { 198 do_error_trap(regs, 0, "divide error", X86_TRAP_DE, SIGFPE, 199 FPE_INTDIV, error_get_trap_addr(regs)); 200 } 201 202 DEFINE_IDTENTRY(exc_overflow) 203 { 204 do_error_trap(regs, 0, "overflow", X86_TRAP_OF, SIGSEGV, 0, NULL); 205 } 206 207 #ifdef CONFIG_X86_F00F_BUG 208 void handle_invalid_op(struct pt_regs *regs) 209 #else 210 static inline void handle_invalid_op(struct pt_regs *regs) 211 #endif 212 { 213 do_error_trap(regs, 0, "invalid opcode", X86_TRAP_UD, SIGILL, 214 ILL_ILLOPN, error_get_trap_addr(regs)); 215 } 216 217 static noinstr bool handle_bug(struct pt_regs *regs) 218 { 219 bool handled = false; 220 221 if (!is_valid_bugaddr(regs->ip)) 222 return handled; 223 224 /* 225 * All lies, just get the WARN/BUG out. 226 */ 227 instrumentation_begin(); 228 /* 229 * Since we're emulating a CALL with exceptions, restore the interrupt 230 * state to what it was at the exception site. 231 */ 232 if (regs->flags & X86_EFLAGS_IF) 233 raw_local_irq_enable(); 234 if (report_bug(regs->ip, regs) == BUG_TRAP_TYPE_WARN) { 235 regs->ip += LEN_UD2; 236 handled = true; 237 } 238 if (regs->flags & X86_EFLAGS_IF) 239 raw_local_irq_disable(); 240 instrumentation_end(); 241 242 return handled; 243 } 244 245 DEFINE_IDTENTRY_RAW(exc_invalid_op) 246 { 247 irqentry_state_t state; 248 249 /* 250 * We use UD2 as a short encoding for 'CALL __WARN', as such 251 * handle it before exception entry to avoid recursive WARN 252 * in case exception entry is the one triggering WARNs. 253 */ 254 if (!user_mode(regs) && handle_bug(regs)) 255 return; 256 257 state = irqentry_enter(regs); 258 instrumentation_begin(); 259 handle_invalid_op(regs); 260 instrumentation_end(); 261 irqentry_exit(regs, state); 262 } 263 264 DEFINE_IDTENTRY(exc_coproc_segment_overrun) 265 { 266 do_error_trap(regs, 0, "coprocessor segment overrun", 267 X86_TRAP_OLD_MF, SIGFPE, 0, NULL); 268 } 269 270 DEFINE_IDTENTRY_ERRORCODE(exc_invalid_tss) 271 { 272 do_error_trap(regs, error_code, "invalid TSS", X86_TRAP_TS, SIGSEGV, 273 0, NULL); 274 } 275 276 DEFINE_IDTENTRY_ERRORCODE(exc_segment_not_present) 277 { 278 do_error_trap(regs, error_code, "segment not present", X86_TRAP_NP, 279 SIGBUS, 0, NULL); 280 } 281 282 DEFINE_IDTENTRY_ERRORCODE(exc_stack_segment) 283 { 284 do_error_trap(regs, error_code, "stack segment", X86_TRAP_SS, SIGBUS, 285 0, NULL); 286 } 287 288 DEFINE_IDTENTRY_ERRORCODE(exc_alignment_check) 289 { 290 char *str = "alignment check"; 291 292 if (notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_AC, SIGBUS) == NOTIFY_STOP) 293 return; 294 295 if (!user_mode(regs)) 296 die("Split lock detected\n", regs, error_code); 297 298 local_irq_enable(); 299 300 if (handle_user_split_lock(regs, error_code)) 301 return; 302 303 do_trap(X86_TRAP_AC, SIGBUS, "alignment check", regs, 304 error_code, BUS_ADRALN, NULL); 305 306 local_irq_disable(); 307 } 308 309 #ifdef CONFIG_VMAP_STACK 310 __visible void __noreturn handle_stack_overflow(const char *message, 311 struct pt_regs *regs, 312 unsigned long fault_address) 313 { 314 printk(KERN_EMERG "BUG: stack guard page was hit at %p (stack is %p..%p)\n", 315 (void *)fault_address, current->stack, 316 (char *)current->stack + THREAD_SIZE - 1); 317 die(message, regs, 0); 318 319 /* Be absolutely certain we don't return. */ 320 panic("%s", message); 321 } 322 #endif 323 324 /* 325 * Runs on an IST stack for x86_64 and on a special task stack for x86_32. 326 * 327 * On x86_64, this is more or less a normal kernel entry. Notwithstanding the 328 * SDM's warnings about double faults being unrecoverable, returning works as 329 * expected. Presumably what the SDM actually means is that the CPU may get 330 * the register state wrong on entry, so returning could be a bad idea. 331 * 332 * Various CPU engineers have promised that double faults due to an IRET fault 333 * while the stack is read-only are, in fact, recoverable. 334 * 335 * On x86_32, this is entered through a task gate, and regs are synthesized 336 * from the TSS. Returning is, in principle, okay, but changes to regs will 337 * be lost. If, for some reason, we need to return to a context with modified 338 * regs, the shim code could be adjusted to synchronize the registers. 339 * 340 * The 32bit #DF shim provides CR2 already as an argument. On 64bit it needs 341 * to be read before doing anything else. 342 */ 343 DEFINE_IDTENTRY_DF(exc_double_fault) 344 { 345 static const char str[] = "double fault"; 346 struct task_struct *tsk = current; 347 348 #ifdef CONFIG_VMAP_STACK 349 unsigned long address = read_cr2(); 350 #endif 351 352 #ifdef CONFIG_X86_ESPFIX64 353 extern unsigned char native_irq_return_iret[]; 354 355 /* 356 * If IRET takes a non-IST fault on the espfix64 stack, then we 357 * end up promoting it to a doublefault. In that case, take 358 * advantage of the fact that we're not using the normal (TSS.sp0) 359 * stack right now. We can write a fake #GP(0) frame at TSS.sp0 360 * and then modify our own IRET frame so that, when we return, 361 * we land directly at the #GP(0) vector with the stack already 362 * set up according to its expectations. 363 * 364 * The net result is that our #GP handler will think that we 365 * entered from usermode with the bad user context. 366 * 367 * No need for nmi_enter() here because we don't use RCU. 368 */ 369 if (((long)regs->sp >> P4D_SHIFT) == ESPFIX_PGD_ENTRY && 370 regs->cs == __KERNEL_CS && 371 regs->ip == (unsigned long)native_irq_return_iret) 372 { 373 struct pt_regs *gpregs = (struct pt_regs *)this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1; 374 unsigned long *p = (unsigned long *)regs->sp; 375 376 /* 377 * regs->sp points to the failing IRET frame on the 378 * ESPFIX64 stack. Copy it to the entry stack. This fills 379 * in gpregs->ss through gpregs->ip. 380 * 381 */ 382 gpregs->ip = p[0]; 383 gpregs->cs = p[1]; 384 gpregs->flags = p[2]; 385 gpregs->sp = p[3]; 386 gpregs->ss = p[4]; 387 gpregs->orig_ax = 0; /* Missing (lost) #GP error code */ 388 389 /* 390 * Adjust our frame so that we return straight to the #GP 391 * vector with the expected RSP value. This is safe because 392 * we won't enable interupts or schedule before we invoke 393 * general_protection, so nothing will clobber the stack 394 * frame we just set up. 395 * 396 * We will enter general_protection with kernel GSBASE, 397 * which is what the stub expects, given that the faulting 398 * RIP will be the IRET instruction. 399 */ 400 regs->ip = (unsigned long)asm_exc_general_protection; 401 regs->sp = (unsigned long)&gpregs->orig_ax; 402 403 return; 404 } 405 #endif 406 407 idtentry_enter_nmi(regs); 408 instrumentation_begin(); 409 notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV); 410 411 tsk->thread.error_code = error_code; 412 tsk->thread.trap_nr = X86_TRAP_DF; 413 414 #ifdef CONFIG_VMAP_STACK 415 /* 416 * If we overflow the stack into a guard page, the CPU will fail 417 * to deliver #PF and will send #DF instead. Similarly, if we 418 * take any non-IST exception while too close to the bottom of 419 * the stack, the processor will get a page fault while 420 * delivering the exception and will generate a double fault. 421 * 422 * According to the SDM (footnote in 6.15 under "Interrupt 14 - 423 * Page-Fault Exception (#PF): 424 * 425 * Processors update CR2 whenever a page fault is detected. If a 426 * second page fault occurs while an earlier page fault is being 427 * delivered, the faulting linear address of the second fault will 428 * overwrite the contents of CR2 (replacing the previous 429 * address). These updates to CR2 occur even if the page fault 430 * results in a double fault or occurs during the delivery of a 431 * double fault. 432 * 433 * The logic below has a small possibility of incorrectly diagnosing 434 * some errors as stack overflows. For example, if the IDT or GDT 435 * gets corrupted such that #GP delivery fails due to a bad descriptor 436 * causing #GP and we hit this condition while CR2 coincidentally 437 * points to the stack guard page, we'll think we overflowed the 438 * stack. Given that we're going to panic one way or another 439 * if this happens, this isn't necessarily worth fixing. 440 * 441 * If necessary, we could improve the test by only diagnosing 442 * a stack overflow if the saved RSP points within 47 bytes of 443 * the bottom of the stack: if RSP == tsk_stack + 48 and we 444 * take an exception, the stack is already aligned and there 445 * will be enough room SS, RSP, RFLAGS, CS, RIP, and a 446 * possible error code, so a stack overflow would *not* double 447 * fault. With any less space left, exception delivery could 448 * fail, and, as a practical matter, we've overflowed the 449 * stack even if the actual trigger for the double fault was 450 * something else. 451 */ 452 if ((unsigned long)task_stack_page(tsk) - 1 - address < PAGE_SIZE) { 453 handle_stack_overflow("kernel stack overflow (double-fault)", 454 regs, address); 455 } 456 #endif 457 458 pr_emerg("PANIC: double fault, error_code: 0x%lx\n", error_code); 459 die("double fault", regs, error_code); 460 panic("Machine halted."); 461 instrumentation_end(); 462 } 463 464 DEFINE_IDTENTRY(exc_bounds) 465 { 466 if (notify_die(DIE_TRAP, "bounds", regs, 0, 467 X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP) 468 return; 469 cond_local_irq_enable(regs); 470 471 if (!user_mode(regs)) 472 die("bounds", regs, 0); 473 474 do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, 0, 0, NULL); 475 476 cond_local_irq_disable(regs); 477 } 478 479 enum kernel_gp_hint { 480 GP_NO_HINT, 481 GP_NON_CANONICAL, 482 GP_CANONICAL 483 }; 484 485 /* 486 * When an uncaught #GP occurs, try to determine the memory address accessed by 487 * the instruction and return that address to the caller. Also, try to figure 488 * out whether any part of the access to that address was non-canonical. 489 */ 490 static enum kernel_gp_hint get_kernel_gp_address(struct pt_regs *regs, 491 unsigned long *addr) 492 { 493 u8 insn_buf[MAX_INSN_SIZE]; 494 struct insn insn; 495 496 if (copy_from_kernel_nofault(insn_buf, (void *)regs->ip, 497 MAX_INSN_SIZE)) 498 return GP_NO_HINT; 499 500 kernel_insn_init(&insn, insn_buf, MAX_INSN_SIZE); 501 insn_get_modrm(&insn); 502 insn_get_sib(&insn); 503 504 *addr = (unsigned long)insn_get_addr_ref(&insn, regs); 505 if (*addr == -1UL) 506 return GP_NO_HINT; 507 508 #ifdef CONFIG_X86_64 509 /* 510 * Check that: 511 * - the operand is not in the kernel half 512 * - the last byte of the operand is not in the user canonical half 513 */ 514 if (*addr < ~__VIRTUAL_MASK && 515 *addr + insn.opnd_bytes - 1 > __VIRTUAL_MASK) 516 return GP_NON_CANONICAL; 517 #endif 518 519 return GP_CANONICAL; 520 } 521 522 #define GPFSTR "general protection fault" 523 524 DEFINE_IDTENTRY_ERRORCODE(exc_general_protection) 525 { 526 char desc[sizeof(GPFSTR) + 50 + 2*sizeof(unsigned long) + 1] = GPFSTR; 527 enum kernel_gp_hint hint = GP_NO_HINT; 528 struct task_struct *tsk; 529 unsigned long gp_addr; 530 int ret; 531 532 cond_local_irq_enable(regs); 533 534 if (static_cpu_has(X86_FEATURE_UMIP)) { 535 if (user_mode(regs) && fixup_umip_exception(regs)) 536 goto exit; 537 } 538 539 if (v8086_mode(regs)) { 540 local_irq_enable(); 541 handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code); 542 local_irq_disable(); 543 return; 544 } 545 546 tsk = current; 547 548 if (user_mode(regs)) { 549 tsk->thread.error_code = error_code; 550 tsk->thread.trap_nr = X86_TRAP_GP; 551 552 show_signal(tsk, SIGSEGV, "", desc, regs, error_code); 553 force_sig(SIGSEGV); 554 goto exit; 555 } 556 557 if (fixup_exception(regs, X86_TRAP_GP, error_code, 0)) 558 goto exit; 559 560 tsk->thread.error_code = error_code; 561 tsk->thread.trap_nr = X86_TRAP_GP; 562 563 /* 564 * To be potentially processing a kprobe fault and to trust the result 565 * from kprobe_running(), we have to be non-preemptible. 566 */ 567 if (!preemptible() && 568 kprobe_running() && 569 kprobe_fault_handler(regs, X86_TRAP_GP)) 570 goto exit; 571 572 ret = notify_die(DIE_GPF, desc, regs, error_code, X86_TRAP_GP, SIGSEGV); 573 if (ret == NOTIFY_STOP) 574 goto exit; 575 576 if (error_code) 577 snprintf(desc, sizeof(desc), "segment-related " GPFSTR); 578 else 579 hint = get_kernel_gp_address(regs, &gp_addr); 580 581 if (hint != GP_NO_HINT) 582 snprintf(desc, sizeof(desc), GPFSTR ", %s 0x%lx", 583 (hint == GP_NON_CANONICAL) ? "probably for non-canonical address" 584 : "maybe for address", 585 gp_addr); 586 587 /* 588 * KASAN is interested only in the non-canonical case, clear it 589 * otherwise. 590 */ 591 if (hint != GP_NON_CANONICAL) 592 gp_addr = 0; 593 594 die_addr(desc, regs, error_code, gp_addr); 595 596 exit: 597 cond_local_irq_disable(regs); 598 } 599 600 static bool do_int3(struct pt_regs *regs) 601 { 602 int res; 603 604 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP 605 if (kgdb_ll_trap(DIE_INT3, "int3", regs, 0, X86_TRAP_BP, 606 SIGTRAP) == NOTIFY_STOP) 607 return true; 608 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ 609 610 #ifdef CONFIG_KPROBES 611 if (kprobe_int3_handler(regs)) 612 return true; 613 #endif 614 res = notify_die(DIE_INT3, "int3", regs, 0, X86_TRAP_BP, SIGTRAP); 615 616 return res == NOTIFY_STOP; 617 } 618 619 static void do_int3_user(struct pt_regs *regs) 620 { 621 if (do_int3(regs)) 622 return; 623 624 cond_local_irq_enable(regs); 625 do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, 0, 0, NULL); 626 cond_local_irq_disable(regs); 627 } 628 629 DEFINE_IDTENTRY_RAW(exc_int3) 630 { 631 /* 632 * poke_int3_handler() is completely self contained code; it does (and 633 * must) *NOT* call out to anything, lest it hits upon yet another 634 * INT3. 635 */ 636 if (poke_int3_handler(regs)) 637 return; 638 639 /* 640 * irqentry_enter_from_user_mode() uses static_branch_{,un}likely() 641 * and therefore can trigger INT3, hence poke_int3_handler() must 642 * be done before. If the entry came from kernel mode, then use 643 * nmi_enter() because the INT3 could have been hit in any context 644 * including NMI. 645 */ 646 if (user_mode(regs)) { 647 irqentry_enter_from_user_mode(regs); 648 instrumentation_begin(); 649 do_int3_user(regs); 650 instrumentation_end(); 651 irqentry_exit_to_user_mode(regs); 652 } else { 653 bool irq_state = idtentry_enter_nmi(regs); 654 instrumentation_begin(); 655 if (!do_int3(regs)) 656 die("int3", regs, 0); 657 instrumentation_end(); 658 idtentry_exit_nmi(regs, irq_state); 659 } 660 } 661 662 #ifdef CONFIG_X86_64 663 /* 664 * Help handler running on a per-cpu (IST or entry trampoline) stack 665 * to switch to the normal thread stack if the interrupted code was in 666 * user mode. The actual stack switch is done in entry_64.S 667 */ 668 asmlinkage __visible noinstr struct pt_regs *sync_regs(struct pt_regs *eregs) 669 { 670 struct pt_regs *regs = (struct pt_regs *)this_cpu_read(cpu_current_top_of_stack) - 1; 671 if (regs != eregs) 672 *regs = *eregs; 673 return regs; 674 } 675 676 struct bad_iret_stack { 677 void *error_entry_ret; 678 struct pt_regs regs; 679 }; 680 681 asmlinkage __visible noinstr 682 struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s) 683 { 684 /* 685 * This is called from entry_64.S early in handling a fault 686 * caused by a bad iret to user mode. To handle the fault 687 * correctly, we want to move our stack frame to where it would 688 * be had we entered directly on the entry stack (rather than 689 * just below the IRET frame) and we want to pretend that the 690 * exception came from the IRET target. 691 */ 692 struct bad_iret_stack tmp, *new_stack = 693 (struct bad_iret_stack *)__this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1; 694 695 /* Copy the IRET target to the temporary storage. */ 696 __memcpy(&tmp.regs.ip, (void *)s->regs.sp, 5*8); 697 698 /* Copy the remainder of the stack from the current stack. */ 699 __memcpy(&tmp, s, offsetof(struct bad_iret_stack, regs.ip)); 700 701 /* Update the entry stack */ 702 __memcpy(new_stack, &tmp, sizeof(tmp)); 703 704 BUG_ON(!user_mode(&new_stack->regs)); 705 return new_stack; 706 } 707 #endif 708 709 static bool is_sysenter_singlestep(struct pt_regs *regs) 710 { 711 /* 712 * We don't try for precision here. If we're anywhere in the region of 713 * code that can be single-stepped in the SYSENTER entry path, then 714 * assume that this is a useless single-step trap due to SYSENTER 715 * being invoked with TF set. (We don't know in advance exactly 716 * which instructions will be hit because BTF could plausibly 717 * be set.) 718 */ 719 #ifdef CONFIG_X86_32 720 return (regs->ip - (unsigned long)__begin_SYSENTER_singlestep_region) < 721 (unsigned long)__end_SYSENTER_singlestep_region - 722 (unsigned long)__begin_SYSENTER_singlestep_region; 723 #elif defined(CONFIG_IA32_EMULATION) 724 return (regs->ip - (unsigned long)entry_SYSENTER_compat) < 725 (unsigned long)__end_entry_SYSENTER_compat - 726 (unsigned long)entry_SYSENTER_compat; 727 #else 728 return false; 729 #endif 730 } 731 732 static __always_inline unsigned long debug_read_clear_dr6(void) 733 { 734 unsigned long dr6; 735 736 /* 737 * The Intel SDM says: 738 * 739 * Certain debug exceptions may clear bits 0-3. The remaining 740 * contents of the DR6 register are never cleared by the 741 * processor. To avoid confusion in identifying debug 742 * exceptions, debug handlers should clear the register before 743 * returning to the interrupted task. 744 * 745 * Keep it simple: clear DR6 immediately. 746 */ 747 get_debugreg(dr6, 6); 748 set_debugreg(DR6_RESERVED, 6); 749 dr6 ^= DR6_RESERVED; /* Flip to positive polarity */ 750 751 /* 752 * Clear the virtual DR6 value, ptrace routines will set bits here for 753 * things we want signals for. 754 */ 755 current->thread.virtual_dr6 = 0; 756 757 /* 758 * The SDM says "The processor clears the BTF flag when it 759 * generates a debug exception." Clear TIF_BLOCKSTEP to keep 760 * TIF_BLOCKSTEP in sync with the hardware BTF flag. 761 */ 762 clear_thread_flag(TIF_BLOCKSTEP); 763 764 return dr6; 765 } 766 767 /* 768 * Our handling of the processor debug registers is non-trivial. 769 * We do not clear them on entry and exit from the kernel. Therefore 770 * it is possible to get a watchpoint trap here from inside the kernel. 771 * However, the code in ./ptrace.c has ensured that the user can 772 * only set watchpoints on userspace addresses. Therefore the in-kernel 773 * watchpoint trap can only occur in code which is reading/writing 774 * from user space. Such code must not hold kernel locks (since it 775 * can equally take a page fault), therefore it is safe to call 776 * force_sig_info even though that claims and releases locks. 777 * 778 * Code in ./signal.c ensures that the debug control register 779 * is restored before we deliver any signal, and therefore that 780 * user code runs with the correct debug control register even though 781 * we clear it here. 782 * 783 * Being careful here means that we don't have to be as careful in a 784 * lot of more complicated places (task switching can be a bit lazy 785 * about restoring all the debug state, and ptrace doesn't have to 786 * find every occurrence of the TF bit that could be saved away even 787 * by user code) 788 * 789 * May run on IST stack. 790 */ 791 792 static bool notify_debug(struct pt_regs *regs, unsigned long *dr6) 793 { 794 /* 795 * Notifiers will clear bits in @dr6 to indicate the event has been 796 * consumed - hw_breakpoint_handler(), single_stop_cont(). 797 * 798 * Notifiers will set bits in @virtual_dr6 to indicate the desire 799 * for signals - ptrace_triggered(), kgdb_hw_overflow_handler(). 800 */ 801 if (notify_die(DIE_DEBUG, "debug", regs, (long)dr6, 0, SIGTRAP) == NOTIFY_STOP) 802 return true; 803 804 return false; 805 } 806 807 static __always_inline void exc_debug_kernel(struct pt_regs *regs, 808 unsigned long dr6) 809 { 810 /* 811 * Disable breakpoints during exception handling; recursive exceptions 812 * are exceedingly 'fun'. 813 * 814 * Since this function is NOKPROBE, and that also applies to 815 * HW_BREAKPOINT_X, we can't hit a breakpoint before this (XXX except a 816 * HW_BREAKPOINT_W on our stack) 817 * 818 * Entry text is excluded for HW_BP_X and cpu_entry_area, which 819 * includes the entry stack is excluded for everything. 820 */ 821 unsigned long dr7 = local_db_save(); 822 bool irq_state = idtentry_enter_nmi(regs); 823 instrumentation_begin(); 824 825 /* 826 * If something gets miswired and we end up here for a user mode 827 * #DB, we will malfunction. 828 */ 829 WARN_ON_ONCE(user_mode(regs)); 830 831 /* 832 * Catch SYSENTER with TF set and clear DR_STEP. If this hit a 833 * watchpoint at the same time then that will still be handled. 834 */ 835 if ((dr6 & DR_STEP) && is_sysenter_singlestep(regs)) 836 dr6 &= ~DR_STEP; 837 838 if (kprobe_debug_handler(regs)) 839 goto out; 840 841 /* 842 * The kernel doesn't use INT1 843 */ 844 if (!dr6) 845 goto out; 846 847 if (notify_debug(regs, &dr6)) 848 goto out; 849 850 /* 851 * The kernel doesn't use TF single-step outside of: 852 * 853 * - Kprobes, consumed through kprobe_debug_handler() 854 * - KGDB, consumed through notify_debug() 855 * 856 * So if we get here with DR_STEP set, something is wonky. 857 * 858 * A known way to trigger this is through QEMU's GDB stub, 859 * which leaks #DB into the guest and causes IST recursion. 860 */ 861 if (WARN_ON_ONCE(dr6 & DR_STEP)) 862 regs->flags &= ~X86_EFLAGS_TF; 863 out: 864 instrumentation_end(); 865 idtentry_exit_nmi(regs, irq_state); 866 867 local_db_restore(dr7); 868 } 869 870 static __always_inline void exc_debug_user(struct pt_regs *regs, 871 unsigned long dr6) 872 { 873 bool icebp; 874 875 /* 876 * If something gets miswired and we end up here for a kernel mode 877 * #DB, we will malfunction. 878 */ 879 WARN_ON_ONCE(!user_mode(regs)); 880 881 /* 882 * NB: We can't easily clear DR7 here because 883 * idtentry_exit_to_usermode() can invoke ptrace, schedule, access 884 * user memory, etc. This means that a recursive #DB is possible. If 885 * this happens, that #DB will hit exc_debug_kernel() and clear DR7. 886 * Since we're not on the IST stack right now, everything will be 887 * fine. 888 */ 889 890 irqentry_enter_from_user_mode(regs); 891 instrumentation_begin(); 892 893 /* 894 * If dr6 has no reason to give us about the origin of this trap, 895 * then it's very likely the result of an icebp/int01 trap. 896 * User wants a sigtrap for that. 897 */ 898 icebp = !dr6; 899 900 if (notify_debug(regs, &dr6)) 901 goto out; 902 903 /* It's safe to allow irq's after DR6 has been saved */ 904 local_irq_enable(); 905 906 if (v8086_mode(regs)) { 907 handle_vm86_trap((struct kernel_vm86_regs *)regs, 0, X86_TRAP_DB); 908 goto out_irq; 909 } 910 911 /* Add the virtual_dr6 bits for signals. */ 912 dr6 |= current->thread.virtual_dr6; 913 if (dr6 & (DR_STEP | DR_TRAP_BITS) || icebp) 914 send_sigtrap(regs, 0, get_si_code(dr6)); 915 916 out_irq: 917 local_irq_disable(); 918 out: 919 instrumentation_end(); 920 irqentry_exit_to_user_mode(regs); 921 } 922 923 #ifdef CONFIG_X86_64 924 /* IST stack entry */ 925 DEFINE_IDTENTRY_DEBUG(exc_debug) 926 { 927 exc_debug_kernel(regs, debug_read_clear_dr6()); 928 } 929 930 /* User entry, runs on regular task stack */ 931 DEFINE_IDTENTRY_DEBUG_USER(exc_debug) 932 { 933 exc_debug_user(regs, debug_read_clear_dr6()); 934 } 935 #else 936 /* 32 bit does not have separate entry points. */ 937 DEFINE_IDTENTRY_RAW(exc_debug) 938 { 939 unsigned long dr6 = debug_read_clear_dr6(); 940 941 if (user_mode(regs)) 942 exc_debug_user(regs, dr6); 943 else 944 exc_debug_kernel(regs, dr6); 945 } 946 #endif 947 948 /* 949 * Note that we play around with the 'TS' bit in an attempt to get 950 * the correct behaviour even in the presence of the asynchronous 951 * IRQ13 behaviour 952 */ 953 static void math_error(struct pt_regs *regs, int trapnr) 954 { 955 struct task_struct *task = current; 956 struct fpu *fpu = &task->thread.fpu; 957 int si_code; 958 char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" : 959 "simd exception"; 960 961 cond_local_irq_enable(regs); 962 963 if (!user_mode(regs)) { 964 if (fixup_exception(regs, trapnr, 0, 0)) 965 goto exit; 966 967 task->thread.error_code = 0; 968 task->thread.trap_nr = trapnr; 969 970 if (notify_die(DIE_TRAP, str, regs, 0, trapnr, 971 SIGFPE) != NOTIFY_STOP) 972 die(str, regs, 0); 973 goto exit; 974 } 975 976 /* 977 * Save the info for the exception handler and clear the error. 978 */ 979 fpu__save(fpu); 980 981 task->thread.trap_nr = trapnr; 982 task->thread.error_code = 0; 983 984 si_code = fpu__exception_code(fpu, trapnr); 985 /* Retry when we get spurious exceptions: */ 986 if (!si_code) 987 goto exit; 988 989 force_sig_fault(SIGFPE, si_code, 990 (void __user *)uprobe_get_trap_addr(regs)); 991 exit: 992 cond_local_irq_disable(regs); 993 } 994 995 DEFINE_IDTENTRY(exc_coprocessor_error) 996 { 997 math_error(regs, X86_TRAP_MF); 998 } 999 1000 DEFINE_IDTENTRY(exc_simd_coprocessor_error) 1001 { 1002 if (IS_ENABLED(CONFIG_X86_INVD_BUG)) { 1003 /* AMD 486 bug: INVD in CPL 0 raises #XF instead of #GP */ 1004 if (!static_cpu_has(X86_FEATURE_XMM)) { 1005 __exc_general_protection(regs, 0); 1006 return; 1007 } 1008 } 1009 math_error(regs, X86_TRAP_XF); 1010 } 1011 1012 DEFINE_IDTENTRY(exc_spurious_interrupt_bug) 1013 { 1014 /* 1015 * This addresses a Pentium Pro Erratum: 1016 * 1017 * PROBLEM: If the APIC subsystem is configured in mixed mode with 1018 * Virtual Wire mode implemented through the local APIC, an 1019 * interrupt vector of 0Fh (Intel reserved encoding) may be 1020 * generated by the local APIC (Int 15). This vector may be 1021 * generated upon receipt of a spurious interrupt (an interrupt 1022 * which is removed before the system receives the INTA sequence) 1023 * instead of the programmed 8259 spurious interrupt vector. 1024 * 1025 * IMPLICATION: The spurious interrupt vector programmed in the 1026 * 8259 is normally handled by an operating system's spurious 1027 * interrupt handler. However, a vector of 0Fh is unknown to some 1028 * operating systems, which would crash if this erratum occurred. 1029 * 1030 * In theory this could be limited to 32bit, but the handler is not 1031 * hurting and who knows which other CPUs suffer from this. 1032 */ 1033 } 1034 1035 DEFINE_IDTENTRY(exc_device_not_available) 1036 { 1037 unsigned long cr0 = read_cr0(); 1038 1039 #ifdef CONFIG_MATH_EMULATION 1040 if (!boot_cpu_has(X86_FEATURE_FPU) && (cr0 & X86_CR0_EM)) { 1041 struct math_emu_info info = { }; 1042 1043 cond_local_irq_enable(regs); 1044 1045 info.regs = regs; 1046 math_emulate(&info); 1047 1048 cond_local_irq_disable(regs); 1049 return; 1050 } 1051 #endif 1052 1053 /* This should not happen. */ 1054 if (WARN(cr0 & X86_CR0_TS, "CR0.TS was set")) { 1055 /* Try to fix it up and carry on. */ 1056 write_cr0(cr0 & ~X86_CR0_TS); 1057 } else { 1058 /* 1059 * Something terrible happened, and we're better off trying 1060 * to kill the task than getting stuck in a never-ending 1061 * loop of #NM faults. 1062 */ 1063 die("unexpected #NM exception", regs, 0); 1064 } 1065 } 1066 1067 #ifdef CONFIG_X86_32 1068 DEFINE_IDTENTRY_SW(iret_error) 1069 { 1070 local_irq_enable(); 1071 if (notify_die(DIE_TRAP, "iret exception", regs, 0, 1072 X86_TRAP_IRET, SIGILL) != NOTIFY_STOP) { 1073 do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, 0, 1074 ILL_BADSTK, (void __user *)NULL); 1075 } 1076 local_irq_disable(); 1077 } 1078 #endif 1079 1080 void __init trap_init(void) 1081 { 1082 /* Init cpu_entry_area before IST entries are set up */ 1083 setup_cpu_entry_areas(); 1084 1085 idt_setup_traps(); 1086 1087 /* 1088 * Should be a barrier for any external CPU state: 1089 */ 1090 cpu_init(); 1091 1092 idt_setup_ist_traps(); 1093 } 1094