1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/module.h> 45 #include <linux/sched.h> 46 #include <linux/percpu.h> 47 #include <linux/bootmem.h> 48 #include <linux/err.h> 49 #include <linux/nmi.h> 50 #include <linux/tboot.h> 51 #include <linux/stackprotector.h> 52 #include <linux/gfp.h> 53 #include <linux/cpuidle.h> 54 55 #include <asm/acpi.h> 56 #include <asm/desc.h> 57 #include <asm/nmi.h> 58 #include <asm/irq.h> 59 #include <asm/idle.h> 60 #include <asm/trampoline.h> 61 #include <asm/cpu.h> 62 #include <asm/numa.h> 63 #include <asm/pgtable.h> 64 #include <asm/tlbflush.h> 65 #include <asm/mtrr.h> 66 #include <asm/mwait.h> 67 #include <asm/apic.h> 68 #include <asm/io_apic.h> 69 #include <asm/setup.h> 70 #include <asm/uv/uv.h> 71 #include <linux/mc146818rtc.h> 72 73 #include <asm/smpboot_hooks.h> 74 #include <asm/i8259.h> 75 76 /* State of each CPU */ 77 DEFINE_PER_CPU(int, cpu_state) = { 0 }; 78 79 #ifdef CONFIG_HOTPLUG_CPU 80 /* 81 * We need this for trampoline_base protection from concurrent accesses when 82 * off- and onlining cores wildly. 83 */ 84 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex); 85 86 void cpu_hotplug_driver_lock(void) 87 { 88 mutex_lock(&x86_cpu_hotplug_driver_mutex); 89 } 90 91 void cpu_hotplug_driver_unlock(void) 92 { 93 mutex_unlock(&x86_cpu_hotplug_driver_mutex); 94 } 95 96 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; } 97 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; } 98 #endif 99 100 /* Number of siblings per CPU package */ 101 int smp_num_siblings = 1; 102 EXPORT_SYMBOL(smp_num_siblings); 103 104 /* Last level cache ID of each logical CPU */ 105 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; 106 107 /* representing HT siblings of each logical CPU */ 108 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); 109 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 110 111 /* representing HT and core siblings of each logical CPU */ 112 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); 113 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 114 115 DEFINE_PER_CPU(cpumask_var_t, cpu_llc_shared_map); 116 117 /* Per CPU bogomips and other parameters */ 118 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 119 EXPORT_PER_CPU_SYMBOL(cpu_info); 120 121 atomic_t init_deasserted; 122 123 /* 124 * Report back to the Boot Processor. 125 * Running on AP. 126 */ 127 static void __cpuinit smp_callin(void) 128 { 129 int cpuid, phys_id; 130 unsigned long timeout; 131 132 /* 133 * If waken up by an INIT in an 82489DX configuration 134 * we may get here before an INIT-deassert IPI reaches 135 * our local APIC. We have to wait for the IPI or we'll 136 * lock up on an APIC access. 137 */ 138 if (apic->wait_for_init_deassert) 139 apic->wait_for_init_deassert(&init_deasserted); 140 141 /* 142 * (This works even if the APIC is not enabled.) 143 */ 144 phys_id = read_apic_id(); 145 cpuid = smp_processor_id(); 146 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { 147 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, 148 phys_id, cpuid); 149 } 150 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); 151 152 /* 153 * STARTUP IPIs are fragile beasts as they might sometimes 154 * trigger some glue motherboard logic. Complete APIC bus 155 * silence for 1 second, this overestimates the time the 156 * boot CPU is spending to send the up to 2 STARTUP IPIs 157 * by a factor of two. This should be enough. 158 */ 159 160 /* 161 * Waiting 2s total for startup (udelay is not yet working) 162 */ 163 timeout = jiffies + 2*HZ; 164 while (time_before(jiffies, timeout)) { 165 /* 166 * Has the boot CPU finished it's STARTUP sequence? 167 */ 168 if (cpumask_test_cpu(cpuid, cpu_callout_mask)) 169 break; 170 cpu_relax(); 171 } 172 173 if (!time_before(jiffies, timeout)) { 174 panic("%s: CPU%d started up but did not get a callout!\n", 175 __func__, cpuid); 176 } 177 178 /* 179 * the boot CPU has finished the init stage and is spinning 180 * on callin_map until we finish. We are free to set up this 181 * CPU, first the APIC. (this is probably redundant on most 182 * boards) 183 */ 184 185 pr_debug("CALLIN, before setup_local_APIC().\n"); 186 if (apic->smp_callin_clear_local_apic) 187 apic->smp_callin_clear_local_apic(); 188 setup_local_APIC(); 189 end_local_APIC_setup(); 190 191 /* 192 * Need to setup vector mappings before we enable interrupts. 193 */ 194 setup_vector_irq(smp_processor_id()); 195 196 /* 197 * Save our processor parameters. Note: this information 198 * is needed for clock calibration. 199 */ 200 smp_store_cpu_info(cpuid); 201 202 /* 203 * Get our bogomips. 204 * Update loops_per_jiffy in cpu_data. Previous call to 205 * smp_store_cpu_info() stored a value that is close but not as 206 * accurate as the value just calculated. 207 */ 208 calibrate_delay(); 209 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 210 pr_debug("Stack at about %p\n", &cpuid); 211 212 /* 213 * This must be done before setting cpu_online_mask 214 * or calling notify_cpu_starting. 215 */ 216 set_cpu_sibling_map(raw_smp_processor_id()); 217 wmb(); 218 219 notify_cpu_starting(cpuid); 220 221 /* 222 * Allow the master to continue. 223 */ 224 cpumask_set_cpu(cpuid, cpu_callin_mask); 225 } 226 227 /* 228 * Activate a secondary processor. 229 */ 230 notrace static void __cpuinit start_secondary(void *unused) 231 { 232 /* 233 * Don't put *anything* before cpu_init(), SMP booting is too 234 * fragile that we want to limit the things done here to the 235 * most necessary things. 236 */ 237 cpu_init(); 238 x86_cpuinit.early_percpu_clock_init(); 239 preempt_disable(); 240 smp_callin(); 241 242 #ifdef CONFIG_X86_32 243 /* switch away from the initial page table */ 244 load_cr3(swapper_pg_dir); 245 __flush_tlb_all(); 246 #endif 247 248 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 249 barrier(); 250 /* 251 * Check TSC synchronization with the BP: 252 */ 253 check_tsc_sync_target(); 254 255 /* 256 * We need to hold call_lock, so there is no inconsistency 257 * between the time smp_call_function() determines number of 258 * IPI recipients, and the time when the determination is made 259 * for which cpus receive the IPI. Holding this 260 * lock helps us to not include this cpu in a currently in progress 261 * smp_call_function(). 262 * 263 * We need to hold vector_lock so there the set of online cpus 264 * does not change while we are assigning vectors to cpus. Holding 265 * this lock ensures we don't half assign or remove an irq from a cpu. 266 */ 267 ipi_call_lock(); 268 lock_vector_lock(); 269 set_cpu_online(smp_processor_id(), true); 270 unlock_vector_lock(); 271 ipi_call_unlock(); 272 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; 273 x86_platform.nmi_init(); 274 275 /* enable local interrupts */ 276 local_irq_enable(); 277 278 /* to prevent fake stack check failure in clock setup */ 279 boot_init_stack_canary(); 280 281 x86_cpuinit.setup_percpu_clockev(); 282 283 wmb(); 284 cpu_idle(); 285 } 286 287 /* 288 * The bootstrap kernel entry code has set these up. Save them for 289 * a given CPU 290 */ 291 292 void __cpuinit smp_store_cpu_info(int id) 293 { 294 struct cpuinfo_x86 *c = &cpu_data(id); 295 296 *c = boot_cpu_data; 297 c->cpu_index = id; 298 if (id != 0) 299 identify_secondary_cpu(c); 300 } 301 302 static bool __cpuinit 303 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 304 { 305 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 306 307 return !WARN_ONCE(cpu_to_node(cpu1) != cpu_to_node(cpu2), 308 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 309 "[node: %d != %d]. Ignoring dependency.\n", 310 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 311 } 312 313 #define link_mask(_m, c1, c2) \ 314 do { \ 315 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \ 316 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \ 317 } while (0) 318 319 static bool __cpuinit match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 320 { 321 if (cpu_has(c, X86_FEATURE_TOPOEXT)) { 322 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 323 324 if (c->phys_proc_id == o->phys_proc_id && 325 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && 326 c->compute_unit_id == o->compute_unit_id) 327 return topology_sane(c, o, "smt"); 328 329 } else if (c->phys_proc_id == o->phys_proc_id && 330 c->cpu_core_id == o->cpu_core_id) { 331 return topology_sane(c, o, "smt"); 332 } 333 334 return false; 335 } 336 337 static bool __cpuinit match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 338 { 339 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 340 341 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && 342 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) 343 return topology_sane(c, o, "llc"); 344 345 return false; 346 } 347 348 static bool __cpuinit match_mc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 349 { 350 if (c->phys_proc_id == o->phys_proc_id) 351 return topology_sane(c, o, "mc"); 352 353 return false; 354 } 355 356 void __cpuinit set_cpu_sibling_map(int cpu) 357 { 358 bool has_mc = boot_cpu_data.x86_max_cores > 1; 359 bool has_smt = smp_num_siblings > 1; 360 struct cpuinfo_x86 *c = &cpu_data(cpu); 361 struct cpuinfo_x86 *o; 362 int i; 363 364 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 365 366 if (!has_smt && !has_mc) { 367 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); 368 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 369 cpumask_set_cpu(cpu, cpu_core_mask(cpu)); 370 c->booted_cores = 1; 371 return; 372 } 373 374 for_each_cpu(i, cpu_sibling_setup_mask) { 375 o = &cpu_data(i); 376 377 if ((i == cpu) || (has_smt && match_smt(c, o))) 378 link_mask(sibling, cpu, i); 379 380 if ((i == cpu) || (has_mc && match_llc(c, o))) 381 link_mask(llc_shared, cpu, i); 382 383 if ((i == cpu) || (has_mc && match_mc(c, o))) { 384 link_mask(core, cpu, i); 385 386 /* 387 * Does this new cpu bringup a new core? 388 */ 389 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { 390 /* 391 * for each core in package, increment 392 * the booted_cores for this new cpu 393 */ 394 if (cpumask_first(cpu_sibling_mask(i)) == i) 395 c->booted_cores++; 396 /* 397 * increment the core count for all 398 * the other cpus in this package 399 */ 400 if (i != cpu) 401 cpu_data(i).booted_cores++; 402 } else if (i != cpu && !c->booted_cores) 403 c->booted_cores = cpu_data(i).booted_cores; 404 } 405 } 406 } 407 408 /* maps the cpu to the sched domain representing multi-core */ 409 const struct cpumask *cpu_coregroup_mask(int cpu) 410 { 411 struct cpuinfo_x86 *c = &cpu_data(cpu); 412 /* 413 * For perf, we return last level cache shared map. 414 * And for power savings, we return cpu_core_map 415 */ 416 if (!(cpu_has(c, X86_FEATURE_AMD_DCM))) 417 return cpu_core_mask(cpu); 418 else 419 return cpu_llc_shared_mask(cpu); 420 } 421 422 static void impress_friends(void) 423 { 424 int cpu; 425 unsigned long bogosum = 0; 426 /* 427 * Allow the user to impress friends. 428 */ 429 pr_debug("Before bogomips.\n"); 430 for_each_possible_cpu(cpu) 431 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 432 bogosum += cpu_data(cpu).loops_per_jiffy; 433 printk(KERN_INFO 434 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", 435 num_online_cpus(), 436 bogosum/(500000/HZ), 437 (bogosum/(5000/HZ))%100); 438 439 pr_debug("Before bogocount - setting activated=1.\n"); 440 } 441 442 void __inquire_remote_apic(int apicid) 443 { 444 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 445 const char * const names[] = { "ID", "VERSION", "SPIV" }; 446 int timeout; 447 u32 status; 448 449 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); 450 451 for (i = 0; i < ARRAY_SIZE(regs); i++) { 452 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); 453 454 /* 455 * Wait for idle. 456 */ 457 status = safe_apic_wait_icr_idle(); 458 if (status) 459 printk(KERN_CONT 460 "a previous APIC delivery may have failed\n"); 461 462 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 463 464 timeout = 0; 465 do { 466 udelay(100); 467 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 468 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 469 470 switch (status) { 471 case APIC_ICR_RR_VALID: 472 status = apic_read(APIC_RRR); 473 printk(KERN_CONT "%08x\n", status); 474 break; 475 default: 476 printk(KERN_CONT "failed\n"); 477 } 478 } 479 } 480 481 /* 482 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 483 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 484 * won't ... remember to clear down the APIC, etc later. 485 */ 486 int __cpuinit 487 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) 488 { 489 unsigned long send_status, accept_status = 0; 490 int maxlvt; 491 492 /* Target chip */ 493 /* Boot on the stack */ 494 /* Kick the second */ 495 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); 496 497 pr_debug("Waiting for send to finish...\n"); 498 send_status = safe_apic_wait_icr_idle(); 499 500 /* 501 * Give the other CPU some time to accept the IPI. 502 */ 503 udelay(200); 504 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 505 maxlvt = lapic_get_maxlvt(); 506 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 507 apic_write(APIC_ESR, 0); 508 accept_status = (apic_read(APIC_ESR) & 0xEF); 509 } 510 pr_debug("NMI sent.\n"); 511 512 if (send_status) 513 printk(KERN_ERR "APIC never delivered???\n"); 514 if (accept_status) 515 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 516 517 return (send_status | accept_status); 518 } 519 520 static int __cpuinit 521 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 522 { 523 unsigned long send_status, accept_status = 0; 524 int maxlvt, num_starts, j; 525 526 maxlvt = lapic_get_maxlvt(); 527 528 /* 529 * Be paranoid about clearing APIC errors. 530 */ 531 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 532 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 533 apic_write(APIC_ESR, 0); 534 apic_read(APIC_ESR); 535 } 536 537 pr_debug("Asserting INIT.\n"); 538 539 /* 540 * Turn INIT on target chip 541 */ 542 /* 543 * Send IPI 544 */ 545 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 546 phys_apicid); 547 548 pr_debug("Waiting for send to finish...\n"); 549 send_status = safe_apic_wait_icr_idle(); 550 551 mdelay(10); 552 553 pr_debug("Deasserting INIT.\n"); 554 555 /* Target chip */ 556 /* Send IPI */ 557 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 558 559 pr_debug("Waiting for send to finish...\n"); 560 send_status = safe_apic_wait_icr_idle(); 561 562 mb(); 563 atomic_set(&init_deasserted, 1); 564 565 /* 566 * Should we send STARTUP IPIs ? 567 * 568 * Determine this based on the APIC version. 569 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 570 */ 571 if (APIC_INTEGRATED(apic_version[phys_apicid])) 572 num_starts = 2; 573 else 574 num_starts = 0; 575 576 /* 577 * Paravirt / VMI wants a startup IPI hook here to set up the 578 * target processor state. 579 */ 580 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, 581 stack_start); 582 583 /* 584 * Run STARTUP IPI loop. 585 */ 586 pr_debug("#startup loops: %d.\n", num_starts); 587 588 for (j = 1; j <= num_starts; j++) { 589 pr_debug("Sending STARTUP #%d.\n", j); 590 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 591 apic_write(APIC_ESR, 0); 592 apic_read(APIC_ESR); 593 pr_debug("After apic_write.\n"); 594 595 /* 596 * STARTUP IPI 597 */ 598 599 /* Target chip */ 600 /* Boot on the stack */ 601 /* Kick the second */ 602 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 603 phys_apicid); 604 605 /* 606 * Give the other CPU some time to accept the IPI. 607 */ 608 udelay(300); 609 610 pr_debug("Startup point 1.\n"); 611 612 pr_debug("Waiting for send to finish...\n"); 613 send_status = safe_apic_wait_icr_idle(); 614 615 /* 616 * Give the other CPU some time to accept the IPI. 617 */ 618 udelay(200); 619 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 620 apic_write(APIC_ESR, 0); 621 accept_status = (apic_read(APIC_ESR) & 0xEF); 622 if (send_status || accept_status) 623 break; 624 } 625 pr_debug("After Startup.\n"); 626 627 if (send_status) 628 printk(KERN_ERR "APIC never delivered???\n"); 629 if (accept_status) 630 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 631 632 return (send_status | accept_status); 633 } 634 635 /* reduce the number of lines printed when booting a large cpu count system */ 636 static void __cpuinit announce_cpu(int cpu, int apicid) 637 { 638 static int current_node = -1; 639 int node = early_cpu_to_node(cpu); 640 641 if (system_state == SYSTEM_BOOTING) { 642 if (node != current_node) { 643 if (current_node > (-1)) 644 pr_cont(" Ok.\n"); 645 current_node = node; 646 pr_info("Booting Node %3d, Processors ", node); 647 } 648 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : ""); 649 return; 650 } else 651 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 652 node, cpu, apicid); 653 } 654 655 /* 656 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 657 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 658 * Returns zero if CPU booted OK, else error code from 659 * ->wakeup_secondary_cpu. 660 */ 661 static int __cpuinit do_boot_cpu(int apicid, int cpu, struct task_struct *idle) 662 { 663 unsigned long boot_error = 0; 664 unsigned long start_ip; 665 int timeout; 666 667 alternatives_smp_switch(1); 668 669 idle->thread.sp = (unsigned long) (((struct pt_regs *) 670 (THREAD_SIZE + task_stack_page(idle))) - 1); 671 per_cpu(current_task, cpu) = idle; 672 673 #ifdef CONFIG_X86_32 674 /* Stack for startup_32 can be just as for start_secondary onwards */ 675 irq_ctx_init(cpu); 676 #else 677 clear_tsk_thread_flag(idle, TIF_FORK); 678 initial_gs = per_cpu_offset(cpu); 679 per_cpu(kernel_stack, cpu) = 680 (unsigned long)task_stack_page(idle) - 681 KERNEL_STACK_OFFSET + THREAD_SIZE; 682 #endif 683 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 684 initial_code = (unsigned long)start_secondary; 685 stack_start = idle->thread.sp; 686 687 /* start_ip had better be page-aligned! */ 688 start_ip = trampoline_address(); 689 690 /* So we see what's up */ 691 announce_cpu(cpu, apicid); 692 693 /* 694 * This grunge runs the startup process for 695 * the targeted processor. 696 */ 697 698 atomic_set(&init_deasserted, 0); 699 700 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 701 702 pr_debug("Setting warm reset code and vector.\n"); 703 704 smpboot_setup_warm_reset_vector(start_ip); 705 /* 706 * Be paranoid about clearing APIC errors. 707 */ 708 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 709 apic_write(APIC_ESR, 0); 710 apic_read(APIC_ESR); 711 } 712 } 713 714 /* 715 * Kick the secondary CPU. Use the method in the APIC driver 716 * if it's defined - or use an INIT boot APIC message otherwise: 717 */ 718 if (apic->wakeup_secondary_cpu) 719 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 720 else 721 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 722 723 if (!boot_error) { 724 /* 725 * allow APs to start initializing. 726 */ 727 pr_debug("Before Callout %d.\n", cpu); 728 cpumask_set_cpu(cpu, cpu_callout_mask); 729 pr_debug("After Callout %d.\n", cpu); 730 731 /* 732 * Wait 5s total for a response 733 */ 734 for (timeout = 0; timeout < 50000; timeout++) { 735 if (cpumask_test_cpu(cpu, cpu_callin_mask)) 736 break; /* It has booted */ 737 udelay(100); 738 /* 739 * Allow other tasks to run while we wait for the 740 * AP to come online. This also gives a chance 741 * for the MTRR work(triggered by the AP coming online) 742 * to be completed in the stop machine context. 743 */ 744 schedule(); 745 } 746 747 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 748 print_cpu_msr(&cpu_data(cpu)); 749 pr_debug("CPU%d: has booted.\n", cpu); 750 } else { 751 boot_error = 1; 752 if (*(volatile u32 *)TRAMPOLINE_SYM(trampoline_status) 753 == 0xA5A5A5A5) 754 /* trampoline started but...? */ 755 pr_err("CPU%d: Stuck ??\n", cpu); 756 else 757 /* trampoline code not run */ 758 pr_err("CPU%d: Not responding.\n", cpu); 759 if (apic->inquire_remote_apic) 760 apic->inquire_remote_apic(apicid); 761 } 762 } 763 764 if (boot_error) { 765 /* Try to put things back the way they were before ... */ 766 numa_remove_cpu(cpu); /* was set by numa_add_cpu */ 767 768 /* was set by do_boot_cpu() */ 769 cpumask_clear_cpu(cpu, cpu_callout_mask); 770 771 /* was set by cpu_init() */ 772 cpumask_clear_cpu(cpu, cpu_initialized_mask); 773 774 set_cpu_present(cpu, false); 775 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; 776 } 777 778 /* mark "stuck" area as not stuck */ 779 *(volatile u32 *)TRAMPOLINE_SYM(trampoline_status) = 0; 780 781 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 782 /* 783 * Cleanup possible dangling ends... 784 */ 785 smpboot_restore_warm_reset_vector(); 786 } 787 return boot_error; 788 } 789 790 int __cpuinit native_cpu_up(unsigned int cpu, struct task_struct *tidle) 791 { 792 int apicid = apic->cpu_present_to_apicid(cpu); 793 unsigned long flags; 794 int err; 795 796 WARN_ON(irqs_disabled()); 797 798 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 799 800 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || 801 !physid_isset(apicid, phys_cpu_present_map) || 802 !apic->apic_id_valid(apicid)) { 803 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); 804 return -EINVAL; 805 } 806 807 /* 808 * Already booted CPU? 809 */ 810 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 811 pr_debug("do_boot_cpu %d Already started\n", cpu); 812 return -ENOSYS; 813 } 814 815 /* 816 * Save current MTRR state in case it was changed since early boot 817 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 818 */ 819 mtrr_save_state(); 820 821 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; 822 823 err = do_boot_cpu(apicid, cpu, tidle); 824 if (err) { 825 pr_debug("do_boot_cpu failed %d\n", err); 826 return -EIO; 827 } 828 829 /* 830 * Check TSC synchronization with the AP (keep irqs disabled 831 * while doing so): 832 */ 833 local_irq_save(flags); 834 check_tsc_sync_source(cpu); 835 local_irq_restore(flags); 836 837 while (!cpu_online(cpu)) { 838 cpu_relax(); 839 touch_nmi_watchdog(); 840 } 841 842 return 0; 843 } 844 845 /** 846 * arch_disable_smp_support() - disables SMP support for x86 at runtime 847 */ 848 void arch_disable_smp_support(void) 849 { 850 disable_ioapic_support(); 851 } 852 853 /* 854 * Fall back to non SMP mode after errors. 855 * 856 * RED-PEN audit/test this more. I bet there is more state messed up here. 857 */ 858 static __init void disable_smp(void) 859 { 860 init_cpu_present(cpumask_of(0)); 861 init_cpu_possible(cpumask_of(0)); 862 smpboot_clear_io_apic_irqs(); 863 864 if (smp_found_config) 865 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 866 else 867 physid_set_mask_of_physid(0, &phys_cpu_present_map); 868 cpumask_set_cpu(0, cpu_sibling_mask(0)); 869 cpumask_set_cpu(0, cpu_core_mask(0)); 870 } 871 872 /* 873 * Various sanity checks. 874 */ 875 static int __init smp_sanity_check(unsigned max_cpus) 876 { 877 preempt_disable(); 878 879 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 880 if (def_to_bigsmp && nr_cpu_ids > 8) { 881 unsigned int cpu; 882 unsigned nr; 883 884 printk(KERN_WARNING 885 "More than 8 CPUs detected - skipping them.\n" 886 "Use CONFIG_X86_BIGSMP.\n"); 887 888 nr = 0; 889 for_each_present_cpu(cpu) { 890 if (nr >= 8) 891 set_cpu_present(cpu, false); 892 nr++; 893 } 894 895 nr = 0; 896 for_each_possible_cpu(cpu) { 897 if (nr >= 8) 898 set_cpu_possible(cpu, false); 899 nr++; 900 } 901 902 nr_cpu_ids = 8; 903 } 904 #endif 905 906 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 907 printk(KERN_WARNING 908 "weird, boot CPU (#%d) not listed by the BIOS.\n", 909 hard_smp_processor_id()); 910 911 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 912 } 913 914 /* 915 * If we couldn't find an SMP configuration at boot time, 916 * get out of here now! 917 */ 918 if (!smp_found_config && !acpi_lapic) { 919 preempt_enable(); 920 printk(KERN_NOTICE "SMP motherboard not detected.\n"); 921 disable_smp(); 922 if (APIC_init_uniprocessor()) 923 printk(KERN_NOTICE "Local APIC not detected." 924 " Using dummy APIC emulation.\n"); 925 return -1; 926 } 927 928 /* 929 * Should not be necessary because the MP table should list the boot 930 * CPU too, but we do it for the sake of robustness anyway. 931 */ 932 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 933 printk(KERN_NOTICE 934 "weird, boot CPU (#%d) not listed by the BIOS.\n", 935 boot_cpu_physical_apicid); 936 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 937 } 938 preempt_enable(); 939 940 /* 941 * If we couldn't find a local APIC, then get out of here now! 942 */ 943 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 944 !cpu_has_apic) { 945 if (!disable_apic) { 946 pr_err("BIOS bug, local APIC #%d not detected!...\n", 947 boot_cpu_physical_apicid); 948 pr_err("... forcing use of dummy APIC emulation." 949 "(tell your hw vendor)\n"); 950 } 951 smpboot_clear_io_apic(); 952 disable_ioapic_support(); 953 return -1; 954 } 955 956 verify_local_APIC(); 957 958 /* 959 * If SMP should be disabled, then really disable it! 960 */ 961 if (!max_cpus) { 962 printk(KERN_INFO "SMP mode deactivated.\n"); 963 smpboot_clear_io_apic(); 964 965 connect_bsp_APIC(); 966 setup_local_APIC(); 967 bsp_end_local_APIC_setup(); 968 return -1; 969 } 970 971 return 0; 972 } 973 974 static void __init smp_cpu_index_default(void) 975 { 976 int i; 977 struct cpuinfo_x86 *c; 978 979 for_each_possible_cpu(i) { 980 c = &cpu_data(i); 981 /* mark all to hotplug */ 982 c->cpu_index = nr_cpu_ids; 983 } 984 } 985 986 /* 987 * Prepare for SMP bootup. The MP table or ACPI has been read 988 * earlier. Just do some sanity checking here and enable APIC mode. 989 */ 990 void __init native_smp_prepare_cpus(unsigned int max_cpus) 991 { 992 unsigned int i; 993 994 preempt_disable(); 995 smp_cpu_index_default(); 996 997 /* 998 * Setup boot CPU information 999 */ 1000 smp_store_cpu_info(0); /* Final full version of the data */ 1001 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1002 mb(); 1003 1004 current_thread_info()->cpu = 0; /* needed? */ 1005 for_each_possible_cpu(i) { 1006 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1007 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1008 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1009 } 1010 set_cpu_sibling_map(0); 1011 1012 1013 if (smp_sanity_check(max_cpus) < 0) { 1014 printk(KERN_INFO "SMP disabled\n"); 1015 disable_smp(); 1016 goto out; 1017 } 1018 1019 default_setup_apic_routing(); 1020 1021 preempt_disable(); 1022 if (read_apic_id() != boot_cpu_physical_apicid) { 1023 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1024 read_apic_id(), boot_cpu_physical_apicid); 1025 /* Or can we switch back to PIC here? */ 1026 } 1027 preempt_enable(); 1028 1029 connect_bsp_APIC(); 1030 1031 /* 1032 * Switch from PIC to APIC mode. 1033 */ 1034 setup_local_APIC(); 1035 1036 /* 1037 * Enable IO APIC before setting up error vector 1038 */ 1039 if (!skip_ioapic_setup && nr_ioapics) 1040 enable_IO_APIC(); 1041 1042 bsp_end_local_APIC_setup(); 1043 1044 if (apic->setup_portio_remap) 1045 apic->setup_portio_remap(); 1046 1047 smpboot_setup_io_apic(); 1048 /* 1049 * Set up local APIC timer on boot CPU. 1050 */ 1051 1052 printk(KERN_INFO "CPU%d: ", 0); 1053 print_cpu_info(&cpu_data(0)); 1054 x86_init.timers.setup_percpu_clockev(); 1055 1056 if (is_uv_system()) 1057 uv_system_init(); 1058 1059 set_mtrr_aps_delayed_init(); 1060 out: 1061 preempt_enable(); 1062 } 1063 1064 void arch_disable_nonboot_cpus_begin(void) 1065 { 1066 /* 1067 * Avoid the smp alternatives switch during the disable_nonboot_cpus(). 1068 * In the suspend path, we will be back in the SMP mode shortly anyways. 1069 */ 1070 skip_smp_alternatives = true; 1071 } 1072 1073 void arch_disable_nonboot_cpus_end(void) 1074 { 1075 skip_smp_alternatives = false; 1076 } 1077 1078 void arch_enable_nonboot_cpus_begin(void) 1079 { 1080 set_mtrr_aps_delayed_init(); 1081 } 1082 1083 void arch_enable_nonboot_cpus_end(void) 1084 { 1085 mtrr_aps_init(); 1086 } 1087 1088 /* 1089 * Early setup to make printk work. 1090 */ 1091 void __init native_smp_prepare_boot_cpu(void) 1092 { 1093 int me = smp_processor_id(); 1094 switch_to_new_gdt(me); 1095 /* already set me in cpu_online_mask in boot_cpu_init() */ 1096 cpumask_set_cpu(me, cpu_callout_mask); 1097 per_cpu(cpu_state, me) = CPU_ONLINE; 1098 } 1099 1100 void __init native_smp_cpus_done(unsigned int max_cpus) 1101 { 1102 pr_debug("Boot done.\n"); 1103 1104 nmi_selftest(); 1105 impress_friends(); 1106 #ifdef CONFIG_X86_IO_APIC 1107 setup_ioapic_dest(); 1108 #endif 1109 mtrr_aps_init(); 1110 } 1111 1112 static int __initdata setup_possible_cpus = -1; 1113 static int __init _setup_possible_cpus(char *str) 1114 { 1115 get_option(&str, &setup_possible_cpus); 1116 return 0; 1117 } 1118 early_param("possible_cpus", _setup_possible_cpus); 1119 1120 1121 /* 1122 * cpu_possible_mask should be static, it cannot change as cpu's 1123 * are onlined, or offlined. The reason is per-cpu data-structures 1124 * are allocated by some modules at init time, and dont expect to 1125 * do this dynamically on cpu arrival/departure. 1126 * cpu_present_mask on the other hand can change dynamically. 1127 * In case when cpu_hotplug is not compiled, then we resort to current 1128 * behaviour, which is cpu_possible == cpu_present. 1129 * - Ashok Raj 1130 * 1131 * Three ways to find out the number of additional hotplug CPUs: 1132 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1133 * - The user can overwrite it with possible_cpus=NUM 1134 * - Otherwise don't reserve additional CPUs. 1135 * We do this because additional CPUs waste a lot of memory. 1136 * -AK 1137 */ 1138 __init void prefill_possible_map(void) 1139 { 1140 int i, possible; 1141 1142 /* no processor from mptable or madt */ 1143 if (!num_processors) 1144 num_processors = 1; 1145 1146 i = setup_max_cpus ?: 1; 1147 if (setup_possible_cpus == -1) { 1148 possible = num_processors; 1149 #ifdef CONFIG_HOTPLUG_CPU 1150 if (setup_max_cpus) 1151 possible += disabled_cpus; 1152 #else 1153 if (possible > i) 1154 possible = i; 1155 #endif 1156 } else 1157 possible = setup_possible_cpus; 1158 1159 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1160 1161 /* nr_cpu_ids could be reduced via nr_cpus= */ 1162 if (possible > nr_cpu_ids) { 1163 printk(KERN_WARNING 1164 "%d Processors exceeds NR_CPUS limit of %d\n", 1165 possible, nr_cpu_ids); 1166 possible = nr_cpu_ids; 1167 } 1168 1169 #ifdef CONFIG_HOTPLUG_CPU 1170 if (!setup_max_cpus) 1171 #endif 1172 if (possible > i) { 1173 printk(KERN_WARNING 1174 "%d Processors exceeds max_cpus limit of %u\n", 1175 possible, setup_max_cpus); 1176 possible = i; 1177 } 1178 1179 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", 1180 possible, max_t(int, possible - num_processors, 0)); 1181 1182 for (i = 0; i < possible; i++) 1183 set_cpu_possible(i, true); 1184 for (; i < NR_CPUS; i++) 1185 set_cpu_possible(i, false); 1186 1187 nr_cpu_ids = possible; 1188 } 1189 1190 #ifdef CONFIG_HOTPLUG_CPU 1191 1192 static void remove_siblinginfo(int cpu) 1193 { 1194 int sibling; 1195 struct cpuinfo_x86 *c = &cpu_data(cpu); 1196 1197 for_each_cpu(sibling, cpu_core_mask(cpu)) { 1198 cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); 1199 /*/ 1200 * last thread sibling in this cpu core going down 1201 */ 1202 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) 1203 cpu_data(sibling).booted_cores--; 1204 } 1205 1206 for_each_cpu(sibling, cpu_sibling_mask(cpu)) 1207 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); 1208 cpumask_clear(cpu_sibling_mask(cpu)); 1209 cpumask_clear(cpu_core_mask(cpu)); 1210 c->phys_proc_id = 0; 1211 c->cpu_core_id = 0; 1212 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1213 } 1214 1215 static void __ref remove_cpu_from_maps(int cpu) 1216 { 1217 set_cpu_online(cpu, false); 1218 cpumask_clear_cpu(cpu, cpu_callout_mask); 1219 cpumask_clear_cpu(cpu, cpu_callin_mask); 1220 /* was set by cpu_init() */ 1221 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1222 numa_remove_cpu(cpu); 1223 } 1224 1225 void cpu_disable_common(void) 1226 { 1227 int cpu = smp_processor_id(); 1228 1229 remove_siblinginfo(cpu); 1230 1231 /* It's now safe to remove this processor from the online map */ 1232 lock_vector_lock(); 1233 remove_cpu_from_maps(cpu); 1234 unlock_vector_lock(); 1235 fixup_irqs(); 1236 } 1237 1238 int native_cpu_disable(void) 1239 { 1240 int cpu = smp_processor_id(); 1241 1242 /* 1243 * Perhaps use cpufreq to drop frequency, but that could go 1244 * into generic code. 1245 * 1246 * We won't take down the boot processor on i386 due to some 1247 * interrupts only being able to be serviced by the BSP. 1248 * Especially so if we're not using an IOAPIC -zwane 1249 */ 1250 if (cpu == 0) 1251 return -EBUSY; 1252 1253 clear_local_APIC(); 1254 1255 cpu_disable_common(); 1256 return 0; 1257 } 1258 1259 void native_cpu_die(unsigned int cpu) 1260 { 1261 /* We don't do anything here: idle task is faking death itself. */ 1262 unsigned int i; 1263 1264 for (i = 0; i < 10; i++) { 1265 /* They ack this in play_dead by setting CPU_DEAD */ 1266 if (per_cpu(cpu_state, cpu) == CPU_DEAD) { 1267 if (system_state == SYSTEM_RUNNING) 1268 pr_info("CPU %u is now offline\n", cpu); 1269 1270 if (1 == num_online_cpus()) 1271 alternatives_smp_switch(0); 1272 return; 1273 } 1274 msleep(100); 1275 } 1276 pr_err("CPU %u didn't die...\n", cpu); 1277 } 1278 1279 void play_dead_common(void) 1280 { 1281 idle_task_exit(); 1282 reset_lazy_tlbstate(); 1283 amd_e400_remove_cpu(raw_smp_processor_id()); 1284 1285 mb(); 1286 /* Ack it */ 1287 __this_cpu_write(cpu_state, CPU_DEAD); 1288 1289 /* 1290 * With physical CPU hotplug, we should halt the cpu 1291 */ 1292 local_irq_disable(); 1293 } 1294 1295 /* 1296 * We need to flush the caches before going to sleep, lest we have 1297 * dirty data in our caches when we come back up. 1298 */ 1299 static inline void mwait_play_dead(void) 1300 { 1301 unsigned int eax, ebx, ecx, edx; 1302 unsigned int highest_cstate = 0; 1303 unsigned int highest_subcstate = 0; 1304 int i; 1305 void *mwait_ptr; 1306 struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info); 1307 1308 if (!(this_cpu_has(X86_FEATURE_MWAIT) && mwait_usable(c))) 1309 return; 1310 if (!this_cpu_has(X86_FEATURE_CLFLSH)) 1311 return; 1312 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1313 return; 1314 1315 eax = CPUID_MWAIT_LEAF; 1316 ecx = 0; 1317 native_cpuid(&eax, &ebx, &ecx, &edx); 1318 1319 /* 1320 * eax will be 0 if EDX enumeration is not valid. 1321 * Initialized below to cstate, sub_cstate value when EDX is valid. 1322 */ 1323 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1324 eax = 0; 1325 } else { 1326 edx >>= MWAIT_SUBSTATE_SIZE; 1327 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1328 if (edx & MWAIT_SUBSTATE_MASK) { 1329 highest_cstate = i; 1330 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1331 } 1332 } 1333 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1334 (highest_subcstate - 1); 1335 } 1336 1337 /* 1338 * This should be a memory location in a cache line which is 1339 * unlikely to be touched by other processors. The actual 1340 * content is immaterial as it is not actually modified in any way. 1341 */ 1342 mwait_ptr = ¤t_thread_info()->flags; 1343 1344 wbinvd(); 1345 1346 while (1) { 1347 /* 1348 * The CLFLUSH is a workaround for erratum AAI65 for 1349 * the Xeon 7400 series. It's not clear it is actually 1350 * needed, but it should be harmless in either case. 1351 * The WBINVD is insufficient due to the spurious-wakeup 1352 * case where we return around the loop. 1353 */ 1354 clflush(mwait_ptr); 1355 __monitor(mwait_ptr, 0, 0); 1356 mb(); 1357 __mwait(eax, 0); 1358 } 1359 } 1360 1361 static inline void hlt_play_dead(void) 1362 { 1363 if (__this_cpu_read(cpu_info.x86) >= 4) 1364 wbinvd(); 1365 1366 while (1) { 1367 native_halt(); 1368 } 1369 } 1370 1371 void native_play_dead(void) 1372 { 1373 play_dead_common(); 1374 tboot_shutdown(TB_SHUTDOWN_WFS); 1375 1376 mwait_play_dead(); /* Only returns on failure */ 1377 if (cpuidle_play_dead()) 1378 hlt_play_dead(); 1379 } 1380 1381 #else /* ... !CONFIG_HOTPLUG_CPU */ 1382 int native_cpu_disable(void) 1383 { 1384 return -ENOSYS; 1385 } 1386 1387 void native_cpu_die(unsigned int cpu) 1388 { 1389 /* We said "no" in __cpu_disable */ 1390 BUG(); 1391 } 1392 1393 void native_play_dead(void) 1394 { 1395 BUG(); 1396 } 1397 1398 #endif 1399