1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/module.h> 45 #include <linux/sched.h> 46 #include <linux/percpu.h> 47 #include <linux/bootmem.h> 48 #include <linux/err.h> 49 #include <linux/nmi.h> 50 #include <linux/tboot.h> 51 #include <linux/stackprotector.h> 52 #include <linux/gfp.h> 53 54 #include <asm/acpi.h> 55 #include <asm/desc.h> 56 #include <asm/nmi.h> 57 #include <asm/irq.h> 58 #include <asm/idle.h> 59 #include <asm/trampoline.h> 60 #include <asm/cpu.h> 61 #include <asm/numa.h> 62 #include <asm/pgtable.h> 63 #include <asm/tlbflush.h> 64 #include <asm/mtrr.h> 65 #include <asm/mwait.h> 66 #include <asm/apic.h> 67 #include <asm/setup.h> 68 #include <asm/uv/uv.h> 69 #include <linux/mc146818rtc.h> 70 71 #include <asm/smpboot_hooks.h> 72 #include <asm/i8259.h> 73 74 #ifdef CONFIG_X86_32 75 u8 apicid_2_node[MAX_APICID]; 76 #endif 77 78 /* State of each CPU */ 79 DEFINE_PER_CPU(int, cpu_state) = { 0 }; 80 81 /* Store all idle threads, this can be reused instead of creating 82 * a new thread. Also avoids complicated thread destroy functionality 83 * for idle threads. 84 */ 85 #ifdef CONFIG_HOTPLUG_CPU 86 /* 87 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is 88 * removed after init for !CONFIG_HOTPLUG_CPU. 89 */ 90 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); 91 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) 92 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) 93 94 /* 95 * We need this for trampoline_base protection from concurrent accesses when 96 * off- and onlining cores wildly. 97 */ 98 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex); 99 100 void cpu_hotplug_driver_lock() 101 { 102 mutex_lock(&x86_cpu_hotplug_driver_mutex); 103 } 104 105 void cpu_hotplug_driver_unlock() 106 { 107 mutex_unlock(&x86_cpu_hotplug_driver_mutex); 108 } 109 110 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; } 111 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; } 112 #else 113 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; 114 #define get_idle_for_cpu(x) (idle_thread_array[(x)]) 115 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) 116 #endif 117 118 /* Number of siblings per CPU package */ 119 int smp_num_siblings = 1; 120 EXPORT_SYMBOL(smp_num_siblings); 121 122 /* Last level cache ID of each logical CPU */ 123 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; 124 125 /* representing HT siblings of each logical CPU */ 126 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); 127 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 128 129 /* representing HT and core siblings of each logical CPU */ 130 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); 131 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 132 133 /* Per CPU bogomips and other parameters */ 134 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 135 EXPORT_PER_CPU_SYMBOL(cpu_info); 136 137 atomic_t init_deasserted; 138 139 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) 140 /* which node each logical CPU is on */ 141 int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; 142 EXPORT_SYMBOL(cpu_to_node_map); 143 144 /* set up a mapping between cpu and node. */ 145 static void map_cpu_to_node(int cpu, int node) 146 { 147 printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); 148 cpumask_set_cpu(cpu, node_to_cpumask_map[node]); 149 cpu_to_node_map[cpu] = node; 150 } 151 152 /* undo a mapping between cpu and node. */ 153 static void unmap_cpu_to_node(int cpu) 154 { 155 int node; 156 157 printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); 158 for (node = 0; node < MAX_NUMNODES; node++) 159 cpumask_clear_cpu(cpu, node_to_cpumask_map[node]); 160 cpu_to_node_map[cpu] = 0; 161 } 162 #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ 163 #define map_cpu_to_node(cpu, node) ({}) 164 #define unmap_cpu_to_node(cpu) ({}) 165 #endif 166 167 #ifdef CONFIG_X86_32 168 static int boot_cpu_logical_apicid; 169 170 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = 171 { [0 ... NR_CPUS-1] = BAD_APICID }; 172 173 static void map_cpu_to_logical_apicid(void) 174 { 175 int cpu = smp_processor_id(); 176 int apicid = logical_smp_processor_id(); 177 int node = apic->apicid_to_node(apicid); 178 179 if (!node_online(node)) 180 node = first_online_node; 181 182 cpu_2_logical_apicid[cpu] = apicid; 183 map_cpu_to_node(cpu, node); 184 } 185 186 void numa_remove_cpu(int cpu) 187 { 188 cpu_2_logical_apicid[cpu] = BAD_APICID; 189 unmap_cpu_to_node(cpu); 190 } 191 #else 192 #define map_cpu_to_logical_apicid() do {} while (0) 193 #endif 194 195 /* 196 * Report back to the Boot Processor. 197 * Running on AP. 198 */ 199 static void __cpuinit smp_callin(void) 200 { 201 int cpuid, phys_id; 202 unsigned long timeout; 203 204 /* 205 * If waken up by an INIT in an 82489DX configuration 206 * we may get here before an INIT-deassert IPI reaches 207 * our local APIC. We have to wait for the IPI or we'll 208 * lock up on an APIC access. 209 */ 210 if (apic->wait_for_init_deassert) 211 apic->wait_for_init_deassert(&init_deasserted); 212 213 /* 214 * (This works even if the APIC is not enabled.) 215 */ 216 phys_id = read_apic_id(); 217 cpuid = smp_processor_id(); 218 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { 219 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, 220 phys_id, cpuid); 221 } 222 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); 223 224 /* 225 * STARTUP IPIs are fragile beasts as they might sometimes 226 * trigger some glue motherboard logic. Complete APIC bus 227 * silence for 1 second, this overestimates the time the 228 * boot CPU is spending to send the up to 2 STARTUP IPIs 229 * by a factor of two. This should be enough. 230 */ 231 232 /* 233 * Waiting 2s total for startup (udelay is not yet working) 234 */ 235 timeout = jiffies + 2*HZ; 236 while (time_before(jiffies, timeout)) { 237 /* 238 * Has the boot CPU finished it's STARTUP sequence? 239 */ 240 if (cpumask_test_cpu(cpuid, cpu_callout_mask)) 241 break; 242 cpu_relax(); 243 } 244 245 if (!time_before(jiffies, timeout)) { 246 panic("%s: CPU%d started up but did not get a callout!\n", 247 __func__, cpuid); 248 } 249 250 /* 251 * the boot CPU has finished the init stage and is spinning 252 * on callin_map until we finish. We are free to set up this 253 * CPU, first the APIC. (this is probably redundant on most 254 * boards) 255 */ 256 257 pr_debug("CALLIN, before setup_local_APIC().\n"); 258 if (apic->smp_callin_clear_local_apic) 259 apic->smp_callin_clear_local_apic(); 260 setup_local_APIC(); 261 end_local_APIC_setup(); 262 map_cpu_to_logical_apicid(); 263 264 /* 265 * Need to setup vector mappings before we enable interrupts. 266 */ 267 setup_vector_irq(smp_processor_id()); 268 /* 269 * Get our bogomips. 270 * 271 * Need to enable IRQs because it can take longer and then 272 * the NMI watchdog might kill us. 273 */ 274 local_irq_enable(); 275 calibrate_delay(); 276 local_irq_disable(); 277 pr_debug("Stack at about %p\n", &cpuid); 278 279 /* 280 * Save our processor parameters 281 */ 282 smp_store_cpu_info(cpuid); 283 284 notify_cpu_starting(cpuid); 285 286 /* 287 * Allow the master to continue. 288 */ 289 cpumask_set_cpu(cpuid, cpu_callin_mask); 290 } 291 292 /* 293 * Activate a secondary processor. 294 */ 295 notrace static void __cpuinit start_secondary(void *unused) 296 { 297 /* 298 * Don't put *anything* before cpu_init(), SMP booting is too 299 * fragile that we want to limit the things done here to the 300 * most necessary things. 301 */ 302 cpu_init(); 303 preempt_disable(); 304 smp_callin(); 305 306 #ifdef CONFIG_X86_32 307 /* switch away from the initial page table */ 308 load_cr3(swapper_pg_dir); 309 __flush_tlb_all(); 310 #endif 311 312 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 313 barrier(); 314 /* 315 * Check TSC synchronization with the BP: 316 */ 317 check_tsc_sync_target(); 318 319 if (nmi_watchdog == NMI_IO_APIC) { 320 legacy_pic->mask(0); 321 enable_NMI_through_LVT0(); 322 legacy_pic->unmask(0); 323 } 324 325 /* This must be done before setting cpu_online_mask */ 326 set_cpu_sibling_map(raw_smp_processor_id()); 327 wmb(); 328 329 /* 330 * We need to hold call_lock, so there is no inconsistency 331 * between the time smp_call_function() determines number of 332 * IPI recipients, and the time when the determination is made 333 * for which cpus receive the IPI. Holding this 334 * lock helps us to not include this cpu in a currently in progress 335 * smp_call_function(). 336 * 337 * We need to hold vector_lock so there the set of online cpus 338 * does not change while we are assigning vectors to cpus. Holding 339 * this lock ensures we don't half assign or remove an irq from a cpu. 340 */ 341 ipi_call_lock(); 342 lock_vector_lock(); 343 set_cpu_online(smp_processor_id(), true); 344 unlock_vector_lock(); 345 ipi_call_unlock(); 346 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; 347 x86_platform.nmi_init(); 348 349 /* enable local interrupts */ 350 local_irq_enable(); 351 352 /* to prevent fake stack check failure in clock setup */ 353 boot_init_stack_canary(); 354 355 x86_cpuinit.setup_percpu_clockev(); 356 357 wmb(); 358 cpu_idle(); 359 } 360 361 #ifdef CONFIG_CPUMASK_OFFSTACK 362 /* In this case, llc_shared_map is a pointer to a cpumask. */ 363 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, 364 const struct cpuinfo_x86 *src) 365 { 366 struct cpumask *llc = dst->llc_shared_map; 367 *dst = *src; 368 dst->llc_shared_map = llc; 369 } 370 #else 371 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, 372 const struct cpuinfo_x86 *src) 373 { 374 *dst = *src; 375 } 376 #endif /* CONFIG_CPUMASK_OFFSTACK */ 377 378 /* 379 * The bootstrap kernel entry code has set these up. Save them for 380 * a given CPU 381 */ 382 383 void __cpuinit smp_store_cpu_info(int id) 384 { 385 struct cpuinfo_x86 *c = &cpu_data(id); 386 387 copy_cpuinfo_x86(c, &boot_cpu_data); 388 c->cpu_index = id; 389 if (id != 0) 390 identify_secondary_cpu(c); 391 } 392 393 static void __cpuinit link_thread_siblings(int cpu1, int cpu2) 394 { 395 struct cpuinfo_x86 *c1 = &cpu_data(cpu1); 396 struct cpuinfo_x86 *c2 = &cpu_data(cpu2); 397 398 cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2)); 399 cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1)); 400 cpumask_set_cpu(cpu1, cpu_core_mask(cpu2)); 401 cpumask_set_cpu(cpu2, cpu_core_mask(cpu1)); 402 cpumask_set_cpu(cpu1, c2->llc_shared_map); 403 cpumask_set_cpu(cpu2, c1->llc_shared_map); 404 } 405 406 407 void __cpuinit set_cpu_sibling_map(int cpu) 408 { 409 int i; 410 struct cpuinfo_x86 *c = &cpu_data(cpu); 411 412 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 413 414 if (smp_num_siblings > 1) { 415 for_each_cpu(i, cpu_sibling_setup_mask) { 416 struct cpuinfo_x86 *o = &cpu_data(i); 417 418 if (cpu_has(c, X86_FEATURE_TOPOEXT)) { 419 if (c->phys_proc_id == o->phys_proc_id && 420 c->compute_unit_id == o->compute_unit_id) 421 link_thread_siblings(cpu, i); 422 } else if (c->phys_proc_id == o->phys_proc_id && 423 c->cpu_core_id == o->cpu_core_id) { 424 link_thread_siblings(cpu, i); 425 } 426 } 427 } else { 428 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); 429 } 430 431 cpumask_set_cpu(cpu, c->llc_shared_map); 432 433 if (current_cpu_data.x86_max_cores == 1) { 434 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); 435 c->booted_cores = 1; 436 return; 437 } 438 439 for_each_cpu(i, cpu_sibling_setup_mask) { 440 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && 441 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { 442 cpumask_set_cpu(i, c->llc_shared_map); 443 cpumask_set_cpu(cpu, cpu_data(i).llc_shared_map); 444 } 445 if (c->phys_proc_id == cpu_data(i).phys_proc_id) { 446 cpumask_set_cpu(i, cpu_core_mask(cpu)); 447 cpumask_set_cpu(cpu, cpu_core_mask(i)); 448 /* 449 * Does this new cpu bringup a new core? 450 */ 451 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { 452 /* 453 * for each core in package, increment 454 * the booted_cores for this new cpu 455 */ 456 if (cpumask_first(cpu_sibling_mask(i)) == i) 457 c->booted_cores++; 458 /* 459 * increment the core count for all 460 * the other cpus in this package 461 */ 462 if (i != cpu) 463 cpu_data(i).booted_cores++; 464 } else if (i != cpu && !c->booted_cores) 465 c->booted_cores = cpu_data(i).booted_cores; 466 } 467 } 468 } 469 470 /* maps the cpu to the sched domain representing multi-core */ 471 const struct cpumask *cpu_coregroup_mask(int cpu) 472 { 473 struct cpuinfo_x86 *c = &cpu_data(cpu); 474 /* 475 * For perf, we return last level cache shared map. 476 * And for power savings, we return cpu_core_map 477 */ 478 if ((sched_mc_power_savings || sched_smt_power_savings) && 479 !(cpu_has(c, X86_FEATURE_AMD_DCM))) 480 return cpu_core_mask(cpu); 481 else 482 return c->llc_shared_map; 483 } 484 485 static void impress_friends(void) 486 { 487 int cpu; 488 unsigned long bogosum = 0; 489 /* 490 * Allow the user to impress friends. 491 */ 492 pr_debug("Before bogomips.\n"); 493 for_each_possible_cpu(cpu) 494 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 495 bogosum += cpu_data(cpu).loops_per_jiffy; 496 printk(KERN_INFO 497 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", 498 num_online_cpus(), 499 bogosum/(500000/HZ), 500 (bogosum/(5000/HZ))%100); 501 502 pr_debug("Before bogocount - setting activated=1.\n"); 503 } 504 505 void __inquire_remote_apic(int apicid) 506 { 507 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 508 char *names[] = { "ID", "VERSION", "SPIV" }; 509 int timeout; 510 u32 status; 511 512 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); 513 514 for (i = 0; i < ARRAY_SIZE(regs); i++) { 515 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); 516 517 /* 518 * Wait for idle. 519 */ 520 status = safe_apic_wait_icr_idle(); 521 if (status) 522 printk(KERN_CONT 523 "a previous APIC delivery may have failed\n"); 524 525 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 526 527 timeout = 0; 528 do { 529 udelay(100); 530 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 531 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 532 533 switch (status) { 534 case APIC_ICR_RR_VALID: 535 status = apic_read(APIC_RRR); 536 printk(KERN_CONT "%08x\n", status); 537 break; 538 default: 539 printk(KERN_CONT "failed\n"); 540 } 541 } 542 } 543 544 /* 545 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 546 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 547 * won't ... remember to clear down the APIC, etc later. 548 */ 549 int __cpuinit 550 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) 551 { 552 unsigned long send_status, accept_status = 0; 553 int maxlvt; 554 555 /* Target chip */ 556 /* Boot on the stack */ 557 /* Kick the second */ 558 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); 559 560 pr_debug("Waiting for send to finish...\n"); 561 send_status = safe_apic_wait_icr_idle(); 562 563 /* 564 * Give the other CPU some time to accept the IPI. 565 */ 566 udelay(200); 567 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 568 maxlvt = lapic_get_maxlvt(); 569 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 570 apic_write(APIC_ESR, 0); 571 accept_status = (apic_read(APIC_ESR) & 0xEF); 572 } 573 pr_debug("NMI sent.\n"); 574 575 if (send_status) 576 printk(KERN_ERR "APIC never delivered???\n"); 577 if (accept_status) 578 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 579 580 return (send_status | accept_status); 581 } 582 583 static int __cpuinit 584 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 585 { 586 unsigned long send_status, accept_status = 0; 587 int maxlvt, num_starts, j; 588 589 maxlvt = lapic_get_maxlvt(); 590 591 /* 592 * Be paranoid about clearing APIC errors. 593 */ 594 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 595 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 596 apic_write(APIC_ESR, 0); 597 apic_read(APIC_ESR); 598 } 599 600 pr_debug("Asserting INIT.\n"); 601 602 /* 603 * Turn INIT on target chip 604 */ 605 /* 606 * Send IPI 607 */ 608 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 609 phys_apicid); 610 611 pr_debug("Waiting for send to finish...\n"); 612 send_status = safe_apic_wait_icr_idle(); 613 614 mdelay(10); 615 616 pr_debug("Deasserting INIT.\n"); 617 618 /* Target chip */ 619 /* Send IPI */ 620 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 621 622 pr_debug("Waiting for send to finish...\n"); 623 send_status = safe_apic_wait_icr_idle(); 624 625 mb(); 626 atomic_set(&init_deasserted, 1); 627 628 /* 629 * Should we send STARTUP IPIs ? 630 * 631 * Determine this based on the APIC version. 632 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 633 */ 634 if (APIC_INTEGRATED(apic_version[phys_apicid])) 635 num_starts = 2; 636 else 637 num_starts = 0; 638 639 /* 640 * Paravirt / VMI wants a startup IPI hook here to set up the 641 * target processor state. 642 */ 643 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, 644 (unsigned long)stack_start.sp); 645 646 /* 647 * Run STARTUP IPI loop. 648 */ 649 pr_debug("#startup loops: %d.\n", num_starts); 650 651 for (j = 1; j <= num_starts; j++) { 652 pr_debug("Sending STARTUP #%d.\n", j); 653 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 654 apic_write(APIC_ESR, 0); 655 apic_read(APIC_ESR); 656 pr_debug("After apic_write.\n"); 657 658 /* 659 * STARTUP IPI 660 */ 661 662 /* Target chip */ 663 /* Boot on the stack */ 664 /* Kick the second */ 665 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 666 phys_apicid); 667 668 /* 669 * Give the other CPU some time to accept the IPI. 670 */ 671 udelay(300); 672 673 pr_debug("Startup point 1.\n"); 674 675 pr_debug("Waiting for send to finish...\n"); 676 send_status = safe_apic_wait_icr_idle(); 677 678 /* 679 * Give the other CPU some time to accept the IPI. 680 */ 681 udelay(200); 682 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 683 apic_write(APIC_ESR, 0); 684 accept_status = (apic_read(APIC_ESR) & 0xEF); 685 if (send_status || accept_status) 686 break; 687 } 688 pr_debug("After Startup.\n"); 689 690 if (send_status) 691 printk(KERN_ERR "APIC never delivered???\n"); 692 if (accept_status) 693 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 694 695 return (send_status | accept_status); 696 } 697 698 struct create_idle { 699 struct work_struct work; 700 struct task_struct *idle; 701 struct completion done; 702 int cpu; 703 }; 704 705 static void __cpuinit do_fork_idle(struct work_struct *work) 706 { 707 struct create_idle *c_idle = 708 container_of(work, struct create_idle, work); 709 710 c_idle->idle = fork_idle(c_idle->cpu); 711 complete(&c_idle->done); 712 } 713 714 /* reduce the number of lines printed when booting a large cpu count system */ 715 static void __cpuinit announce_cpu(int cpu, int apicid) 716 { 717 static int current_node = -1; 718 int node = early_cpu_to_node(cpu); 719 720 if (system_state == SYSTEM_BOOTING) { 721 if (node != current_node) { 722 if (current_node > (-1)) 723 pr_cont(" Ok.\n"); 724 current_node = node; 725 pr_info("Booting Node %3d, Processors ", node); 726 } 727 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : ""); 728 return; 729 } else 730 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 731 node, cpu, apicid); 732 } 733 734 /* 735 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 736 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 737 * Returns zero if CPU booted OK, else error code from 738 * ->wakeup_secondary_cpu. 739 */ 740 static int __cpuinit do_boot_cpu(int apicid, int cpu) 741 { 742 unsigned long boot_error = 0; 743 unsigned long start_ip; 744 int timeout; 745 struct create_idle c_idle = { 746 .cpu = cpu, 747 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), 748 }; 749 750 INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle); 751 752 alternatives_smp_switch(1); 753 754 c_idle.idle = get_idle_for_cpu(cpu); 755 756 /* 757 * We can't use kernel_thread since we must avoid to 758 * reschedule the child. 759 */ 760 if (c_idle.idle) { 761 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) 762 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); 763 init_idle(c_idle.idle, cpu); 764 goto do_rest; 765 } 766 767 schedule_work(&c_idle.work); 768 wait_for_completion(&c_idle.done); 769 770 if (IS_ERR(c_idle.idle)) { 771 printk("failed fork for CPU %d\n", cpu); 772 destroy_work_on_stack(&c_idle.work); 773 return PTR_ERR(c_idle.idle); 774 } 775 776 set_idle_for_cpu(cpu, c_idle.idle); 777 do_rest: 778 per_cpu(current_task, cpu) = c_idle.idle; 779 #ifdef CONFIG_X86_32 780 /* Stack for startup_32 can be just as for start_secondary onwards */ 781 irq_ctx_init(cpu); 782 #else 783 clear_tsk_thread_flag(c_idle.idle, TIF_FORK); 784 initial_gs = per_cpu_offset(cpu); 785 per_cpu(kernel_stack, cpu) = 786 (unsigned long)task_stack_page(c_idle.idle) - 787 KERNEL_STACK_OFFSET + THREAD_SIZE; 788 #endif 789 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 790 initial_code = (unsigned long)start_secondary; 791 stack_start.sp = (void *) c_idle.idle->thread.sp; 792 793 /* start_ip had better be page-aligned! */ 794 start_ip = setup_trampoline(); 795 796 /* So we see what's up */ 797 announce_cpu(cpu, apicid); 798 799 /* 800 * This grunge runs the startup process for 801 * the targeted processor. 802 */ 803 804 atomic_set(&init_deasserted, 0); 805 806 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 807 808 pr_debug("Setting warm reset code and vector.\n"); 809 810 smpboot_setup_warm_reset_vector(start_ip); 811 /* 812 * Be paranoid about clearing APIC errors. 813 */ 814 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 815 apic_write(APIC_ESR, 0); 816 apic_read(APIC_ESR); 817 } 818 } 819 820 /* 821 * Kick the secondary CPU. Use the method in the APIC driver 822 * if it's defined - or use an INIT boot APIC message otherwise: 823 */ 824 if (apic->wakeup_secondary_cpu) 825 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 826 else 827 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 828 829 if (!boot_error) { 830 /* 831 * allow APs to start initializing. 832 */ 833 pr_debug("Before Callout %d.\n", cpu); 834 cpumask_set_cpu(cpu, cpu_callout_mask); 835 pr_debug("After Callout %d.\n", cpu); 836 837 /* 838 * Wait 5s total for a response 839 */ 840 for (timeout = 0; timeout < 50000; timeout++) { 841 if (cpumask_test_cpu(cpu, cpu_callin_mask)) 842 break; /* It has booted */ 843 udelay(100); 844 /* 845 * Allow other tasks to run while we wait for the 846 * AP to come online. This also gives a chance 847 * for the MTRR work(triggered by the AP coming online) 848 * to be completed in the stop machine context. 849 */ 850 schedule(); 851 } 852 853 if (cpumask_test_cpu(cpu, cpu_callin_mask)) 854 pr_debug("CPU%d: has booted.\n", cpu); 855 else { 856 boot_error = 1; 857 if (*((volatile unsigned char *)trampoline_base) 858 == 0xA5) 859 /* trampoline started but...? */ 860 pr_err("CPU%d: Stuck ??\n", cpu); 861 else 862 /* trampoline code not run */ 863 pr_err("CPU%d: Not responding.\n", cpu); 864 if (apic->inquire_remote_apic) 865 apic->inquire_remote_apic(apicid); 866 } 867 } 868 869 if (boot_error) { 870 /* Try to put things back the way they were before ... */ 871 numa_remove_cpu(cpu); /* was set by numa_add_cpu */ 872 873 /* was set by do_boot_cpu() */ 874 cpumask_clear_cpu(cpu, cpu_callout_mask); 875 876 /* was set by cpu_init() */ 877 cpumask_clear_cpu(cpu, cpu_initialized_mask); 878 879 set_cpu_present(cpu, false); 880 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; 881 } 882 883 /* mark "stuck" area as not stuck */ 884 *((volatile unsigned long *)trampoline_base) = 0; 885 886 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 887 /* 888 * Cleanup possible dangling ends... 889 */ 890 smpboot_restore_warm_reset_vector(); 891 } 892 893 destroy_work_on_stack(&c_idle.work); 894 return boot_error; 895 } 896 897 int __cpuinit native_cpu_up(unsigned int cpu) 898 { 899 int apicid = apic->cpu_present_to_apicid(cpu); 900 unsigned long flags; 901 int err; 902 903 WARN_ON(irqs_disabled()); 904 905 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 906 907 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || 908 !physid_isset(apicid, phys_cpu_present_map)) { 909 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); 910 return -EINVAL; 911 } 912 913 /* 914 * Already booted CPU? 915 */ 916 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 917 pr_debug("do_boot_cpu %d Already started\n", cpu); 918 return -ENOSYS; 919 } 920 921 /* 922 * Save current MTRR state in case it was changed since early boot 923 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 924 */ 925 mtrr_save_state(); 926 927 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; 928 929 err = do_boot_cpu(apicid, cpu); 930 if (err) { 931 pr_debug("do_boot_cpu failed %d\n", err); 932 return -EIO; 933 } 934 935 /* 936 * Check TSC synchronization with the AP (keep irqs disabled 937 * while doing so): 938 */ 939 local_irq_save(flags); 940 check_tsc_sync_source(cpu); 941 local_irq_restore(flags); 942 943 while (!cpu_online(cpu)) { 944 cpu_relax(); 945 touch_nmi_watchdog(); 946 } 947 948 return 0; 949 } 950 951 /* 952 * Fall back to non SMP mode after errors. 953 * 954 * RED-PEN audit/test this more. I bet there is more state messed up here. 955 */ 956 static __init void disable_smp(void) 957 { 958 init_cpu_present(cpumask_of(0)); 959 init_cpu_possible(cpumask_of(0)); 960 smpboot_clear_io_apic_irqs(); 961 962 if (smp_found_config) 963 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 964 else 965 physid_set_mask_of_physid(0, &phys_cpu_present_map); 966 map_cpu_to_logical_apicid(); 967 cpumask_set_cpu(0, cpu_sibling_mask(0)); 968 cpumask_set_cpu(0, cpu_core_mask(0)); 969 } 970 971 /* 972 * Various sanity checks. 973 */ 974 static int __init smp_sanity_check(unsigned max_cpus) 975 { 976 preempt_disable(); 977 978 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 979 if (def_to_bigsmp && nr_cpu_ids > 8) { 980 unsigned int cpu; 981 unsigned nr; 982 983 printk(KERN_WARNING 984 "More than 8 CPUs detected - skipping them.\n" 985 "Use CONFIG_X86_BIGSMP.\n"); 986 987 nr = 0; 988 for_each_present_cpu(cpu) { 989 if (nr >= 8) 990 set_cpu_present(cpu, false); 991 nr++; 992 } 993 994 nr = 0; 995 for_each_possible_cpu(cpu) { 996 if (nr >= 8) 997 set_cpu_possible(cpu, false); 998 nr++; 999 } 1000 1001 nr_cpu_ids = 8; 1002 } 1003 #endif 1004 1005 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1006 printk(KERN_WARNING 1007 "weird, boot CPU (#%d) not listed by the BIOS.\n", 1008 hard_smp_processor_id()); 1009 1010 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1011 } 1012 1013 /* 1014 * If we couldn't find an SMP configuration at boot time, 1015 * get out of here now! 1016 */ 1017 if (!smp_found_config && !acpi_lapic) { 1018 preempt_enable(); 1019 printk(KERN_NOTICE "SMP motherboard not detected.\n"); 1020 disable_smp(); 1021 if (APIC_init_uniprocessor()) 1022 printk(KERN_NOTICE "Local APIC not detected." 1023 " Using dummy APIC emulation.\n"); 1024 return -1; 1025 } 1026 1027 /* 1028 * Should not be necessary because the MP table should list the boot 1029 * CPU too, but we do it for the sake of robustness anyway. 1030 */ 1031 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1032 printk(KERN_NOTICE 1033 "weird, boot CPU (#%d) not listed by the BIOS.\n", 1034 boot_cpu_physical_apicid); 1035 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1036 } 1037 preempt_enable(); 1038 1039 /* 1040 * If we couldn't find a local APIC, then get out of here now! 1041 */ 1042 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 1043 !cpu_has_apic) { 1044 if (!disable_apic) { 1045 pr_err("BIOS bug, local APIC #%d not detected!...\n", 1046 boot_cpu_physical_apicid); 1047 pr_err("... forcing use of dummy APIC emulation." 1048 "(tell your hw vendor)\n"); 1049 } 1050 smpboot_clear_io_apic(); 1051 arch_disable_smp_support(); 1052 return -1; 1053 } 1054 1055 verify_local_APIC(); 1056 1057 /* 1058 * If SMP should be disabled, then really disable it! 1059 */ 1060 if (!max_cpus) { 1061 printk(KERN_INFO "SMP mode deactivated.\n"); 1062 smpboot_clear_io_apic(); 1063 1064 localise_nmi_watchdog(); 1065 1066 connect_bsp_APIC(); 1067 setup_local_APIC(); 1068 end_local_APIC_setup(); 1069 return -1; 1070 } 1071 1072 return 0; 1073 } 1074 1075 static void __init smp_cpu_index_default(void) 1076 { 1077 int i; 1078 struct cpuinfo_x86 *c; 1079 1080 for_each_possible_cpu(i) { 1081 c = &cpu_data(i); 1082 /* mark all to hotplug */ 1083 c->cpu_index = nr_cpu_ids; 1084 } 1085 } 1086 1087 /* 1088 * Prepare for SMP bootup. The MP table or ACPI has been read 1089 * earlier. Just do some sanity checking here and enable APIC mode. 1090 */ 1091 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1092 { 1093 unsigned int i; 1094 1095 preempt_disable(); 1096 smp_cpu_index_default(); 1097 current_cpu_data = boot_cpu_data; 1098 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1099 mb(); 1100 /* 1101 * Setup boot CPU information 1102 */ 1103 smp_store_cpu_info(0); /* Final full version of the data */ 1104 #ifdef CONFIG_X86_32 1105 boot_cpu_logical_apicid = logical_smp_processor_id(); 1106 #endif 1107 current_thread_info()->cpu = 0; /* needed? */ 1108 for_each_possible_cpu(i) { 1109 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1110 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1111 zalloc_cpumask_var(&cpu_data(i).llc_shared_map, GFP_KERNEL); 1112 } 1113 set_cpu_sibling_map(0); 1114 1115 1116 if (smp_sanity_check(max_cpus) < 0) { 1117 printk(KERN_INFO "SMP disabled\n"); 1118 disable_smp(); 1119 goto out; 1120 } 1121 1122 default_setup_apic_routing(); 1123 1124 preempt_disable(); 1125 if (read_apic_id() != boot_cpu_physical_apicid) { 1126 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1127 read_apic_id(), boot_cpu_physical_apicid); 1128 /* Or can we switch back to PIC here? */ 1129 } 1130 preempt_enable(); 1131 1132 connect_bsp_APIC(); 1133 1134 /* 1135 * Switch from PIC to APIC mode. 1136 */ 1137 setup_local_APIC(); 1138 1139 /* 1140 * Enable IO APIC before setting up error vector 1141 */ 1142 if (!skip_ioapic_setup && nr_ioapics) 1143 enable_IO_APIC(); 1144 1145 end_local_APIC_setup(); 1146 1147 map_cpu_to_logical_apicid(); 1148 1149 if (apic->setup_portio_remap) 1150 apic->setup_portio_remap(); 1151 1152 smpboot_setup_io_apic(); 1153 /* 1154 * Set up local APIC timer on boot CPU. 1155 */ 1156 1157 printk(KERN_INFO "CPU%d: ", 0); 1158 print_cpu_info(&cpu_data(0)); 1159 x86_init.timers.setup_percpu_clockev(); 1160 1161 if (is_uv_system()) 1162 uv_system_init(); 1163 1164 set_mtrr_aps_delayed_init(); 1165 out: 1166 preempt_enable(); 1167 } 1168 1169 void arch_enable_nonboot_cpus_begin(void) 1170 { 1171 set_mtrr_aps_delayed_init(); 1172 } 1173 1174 void arch_enable_nonboot_cpus_end(void) 1175 { 1176 mtrr_aps_init(); 1177 } 1178 1179 /* 1180 * Early setup to make printk work. 1181 */ 1182 void __init native_smp_prepare_boot_cpu(void) 1183 { 1184 int me = smp_processor_id(); 1185 switch_to_new_gdt(me); 1186 /* already set me in cpu_online_mask in boot_cpu_init() */ 1187 cpumask_set_cpu(me, cpu_callout_mask); 1188 per_cpu(cpu_state, me) = CPU_ONLINE; 1189 } 1190 1191 void __init native_smp_cpus_done(unsigned int max_cpus) 1192 { 1193 pr_debug("Boot done.\n"); 1194 1195 impress_friends(); 1196 #ifdef CONFIG_X86_IO_APIC 1197 setup_ioapic_dest(); 1198 #endif 1199 check_nmi_watchdog(); 1200 mtrr_aps_init(); 1201 } 1202 1203 static int __initdata setup_possible_cpus = -1; 1204 static int __init _setup_possible_cpus(char *str) 1205 { 1206 get_option(&str, &setup_possible_cpus); 1207 return 0; 1208 } 1209 early_param("possible_cpus", _setup_possible_cpus); 1210 1211 1212 /* 1213 * cpu_possible_mask should be static, it cannot change as cpu's 1214 * are onlined, or offlined. The reason is per-cpu data-structures 1215 * are allocated by some modules at init time, and dont expect to 1216 * do this dynamically on cpu arrival/departure. 1217 * cpu_present_mask on the other hand can change dynamically. 1218 * In case when cpu_hotplug is not compiled, then we resort to current 1219 * behaviour, which is cpu_possible == cpu_present. 1220 * - Ashok Raj 1221 * 1222 * Three ways to find out the number of additional hotplug CPUs: 1223 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1224 * - The user can overwrite it with possible_cpus=NUM 1225 * - Otherwise don't reserve additional CPUs. 1226 * We do this because additional CPUs waste a lot of memory. 1227 * -AK 1228 */ 1229 __init void prefill_possible_map(void) 1230 { 1231 int i, possible; 1232 1233 /* no processor from mptable or madt */ 1234 if (!num_processors) 1235 num_processors = 1; 1236 1237 i = setup_max_cpus ?: 1; 1238 if (setup_possible_cpus == -1) { 1239 possible = num_processors; 1240 #ifdef CONFIG_HOTPLUG_CPU 1241 if (setup_max_cpus) 1242 possible += disabled_cpus; 1243 #else 1244 if (possible > i) 1245 possible = i; 1246 #endif 1247 } else 1248 possible = setup_possible_cpus; 1249 1250 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1251 1252 /* nr_cpu_ids could be reduced via nr_cpus= */ 1253 if (possible > nr_cpu_ids) { 1254 printk(KERN_WARNING 1255 "%d Processors exceeds NR_CPUS limit of %d\n", 1256 possible, nr_cpu_ids); 1257 possible = nr_cpu_ids; 1258 } 1259 1260 #ifdef CONFIG_HOTPLUG_CPU 1261 if (!setup_max_cpus) 1262 #endif 1263 if (possible > i) { 1264 printk(KERN_WARNING 1265 "%d Processors exceeds max_cpus limit of %u\n", 1266 possible, setup_max_cpus); 1267 possible = i; 1268 } 1269 1270 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", 1271 possible, max_t(int, possible - num_processors, 0)); 1272 1273 for (i = 0; i < possible; i++) 1274 set_cpu_possible(i, true); 1275 for (; i < NR_CPUS; i++) 1276 set_cpu_possible(i, false); 1277 1278 nr_cpu_ids = possible; 1279 } 1280 1281 #ifdef CONFIG_HOTPLUG_CPU 1282 1283 static void remove_siblinginfo(int cpu) 1284 { 1285 int sibling; 1286 struct cpuinfo_x86 *c = &cpu_data(cpu); 1287 1288 for_each_cpu(sibling, cpu_core_mask(cpu)) { 1289 cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); 1290 /*/ 1291 * last thread sibling in this cpu core going down 1292 */ 1293 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) 1294 cpu_data(sibling).booted_cores--; 1295 } 1296 1297 for_each_cpu(sibling, cpu_sibling_mask(cpu)) 1298 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); 1299 cpumask_clear(cpu_sibling_mask(cpu)); 1300 cpumask_clear(cpu_core_mask(cpu)); 1301 c->phys_proc_id = 0; 1302 c->cpu_core_id = 0; 1303 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1304 } 1305 1306 static void __ref remove_cpu_from_maps(int cpu) 1307 { 1308 set_cpu_online(cpu, false); 1309 cpumask_clear_cpu(cpu, cpu_callout_mask); 1310 cpumask_clear_cpu(cpu, cpu_callin_mask); 1311 /* was set by cpu_init() */ 1312 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1313 numa_remove_cpu(cpu); 1314 } 1315 1316 void cpu_disable_common(void) 1317 { 1318 int cpu = smp_processor_id(); 1319 1320 remove_siblinginfo(cpu); 1321 1322 /* It's now safe to remove this processor from the online map */ 1323 lock_vector_lock(); 1324 remove_cpu_from_maps(cpu); 1325 unlock_vector_lock(); 1326 fixup_irqs(); 1327 } 1328 1329 int native_cpu_disable(void) 1330 { 1331 int cpu = smp_processor_id(); 1332 1333 /* 1334 * Perhaps use cpufreq to drop frequency, but that could go 1335 * into generic code. 1336 * 1337 * We won't take down the boot processor on i386 due to some 1338 * interrupts only being able to be serviced by the BSP. 1339 * Especially so if we're not using an IOAPIC -zwane 1340 */ 1341 if (cpu == 0) 1342 return -EBUSY; 1343 1344 if (nmi_watchdog == NMI_LOCAL_APIC) 1345 stop_apic_nmi_watchdog(NULL); 1346 clear_local_APIC(); 1347 1348 cpu_disable_common(); 1349 return 0; 1350 } 1351 1352 void native_cpu_die(unsigned int cpu) 1353 { 1354 /* We don't do anything here: idle task is faking death itself. */ 1355 unsigned int i; 1356 1357 for (i = 0; i < 10; i++) { 1358 /* They ack this in play_dead by setting CPU_DEAD */ 1359 if (per_cpu(cpu_state, cpu) == CPU_DEAD) { 1360 if (system_state == SYSTEM_RUNNING) 1361 pr_info("CPU %u is now offline\n", cpu); 1362 1363 if (1 == num_online_cpus()) 1364 alternatives_smp_switch(0); 1365 return; 1366 } 1367 msleep(100); 1368 } 1369 pr_err("CPU %u didn't die...\n", cpu); 1370 } 1371 1372 void play_dead_common(void) 1373 { 1374 idle_task_exit(); 1375 reset_lazy_tlbstate(); 1376 irq_ctx_exit(raw_smp_processor_id()); 1377 c1e_remove_cpu(raw_smp_processor_id()); 1378 1379 mb(); 1380 /* Ack it */ 1381 __get_cpu_var(cpu_state) = CPU_DEAD; 1382 1383 /* 1384 * With physical CPU hotplug, we should halt the cpu 1385 */ 1386 local_irq_disable(); 1387 } 1388 1389 /* 1390 * We need to flush the caches before going to sleep, lest we have 1391 * dirty data in our caches when we come back up. 1392 */ 1393 static inline void mwait_play_dead(void) 1394 { 1395 unsigned int eax, ebx, ecx, edx; 1396 unsigned int highest_cstate = 0; 1397 unsigned int highest_subcstate = 0; 1398 int i; 1399 void *mwait_ptr; 1400 1401 if (!cpu_has(¤t_cpu_data, X86_FEATURE_MWAIT)) 1402 return; 1403 if (!cpu_has(¤t_cpu_data, X86_FEATURE_CLFLSH)) 1404 return; 1405 if (current_cpu_data.cpuid_level < CPUID_MWAIT_LEAF) 1406 return; 1407 1408 eax = CPUID_MWAIT_LEAF; 1409 ecx = 0; 1410 native_cpuid(&eax, &ebx, &ecx, &edx); 1411 1412 /* 1413 * eax will be 0 if EDX enumeration is not valid. 1414 * Initialized below to cstate, sub_cstate value when EDX is valid. 1415 */ 1416 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1417 eax = 0; 1418 } else { 1419 edx >>= MWAIT_SUBSTATE_SIZE; 1420 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1421 if (edx & MWAIT_SUBSTATE_MASK) { 1422 highest_cstate = i; 1423 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1424 } 1425 } 1426 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1427 (highest_subcstate - 1); 1428 } 1429 1430 /* 1431 * This should be a memory location in a cache line which is 1432 * unlikely to be touched by other processors. The actual 1433 * content is immaterial as it is not actually modified in any way. 1434 */ 1435 mwait_ptr = ¤t_thread_info()->flags; 1436 1437 wbinvd(); 1438 1439 while (1) { 1440 /* 1441 * The CLFLUSH is a workaround for erratum AAI65 for 1442 * the Xeon 7400 series. It's not clear it is actually 1443 * needed, but it should be harmless in either case. 1444 * The WBINVD is insufficient due to the spurious-wakeup 1445 * case where we return around the loop. 1446 */ 1447 clflush(mwait_ptr); 1448 __monitor(mwait_ptr, 0, 0); 1449 mb(); 1450 __mwait(eax, 0); 1451 } 1452 } 1453 1454 static inline void hlt_play_dead(void) 1455 { 1456 if (current_cpu_data.x86 >= 4) 1457 wbinvd(); 1458 1459 while (1) { 1460 native_halt(); 1461 } 1462 } 1463 1464 void native_play_dead(void) 1465 { 1466 play_dead_common(); 1467 tboot_shutdown(TB_SHUTDOWN_WFS); 1468 1469 mwait_play_dead(); /* Only returns on failure */ 1470 hlt_play_dead(); 1471 } 1472 1473 #else /* ... !CONFIG_HOTPLUG_CPU */ 1474 int native_cpu_disable(void) 1475 { 1476 return -ENOSYS; 1477 } 1478 1479 void native_cpu_die(unsigned int cpu) 1480 { 1481 /* We said "no" in __cpu_disable */ 1482 BUG(); 1483 } 1484 1485 void native_play_dead(void) 1486 { 1487 BUG(); 1488 } 1489 1490 #endif 1491