1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 43 44 #include <linux/init.h> 45 #include <linux/smp.h> 46 #include <linux/module.h> 47 #include <linux/sched.h> 48 #include <linux/percpu.h> 49 #include <linux/bootmem.h> 50 #include <linux/err.h> 51 #include <linux/nmi.h> 52 #include <linux/tboot.h> 53 #include <linux/stackprotector.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 57 #include <asm/acpi.h> 58 #include <asm/desc.h> 59 #include <asm/nmi.h> 60 #include <asm/irq.h> 61 #include <asm/idle.h> 62 #include <asm/realmode.h> 63 #include <asm/cpu.h> 64 #include <asm/numa.h> 65 #include <asm/pgtable.h> 66 #include <asm/tlbflush.h> 67 #include <asm/mtrr.h> 68 #include <asm/mwait.h> 69 #include <asm/apic.h> 70 #include <asm/io_apic.h> 71 #include <asm/fpu/internal.h> 72 #include <asm/setup.h> 73 #include <asm/uv/uv.h> 74 #include <linux/mc146818rtc.h> 75 #include <asm/i8259.h> 76 #include <asm/realmode.h> 77 #include <asm/misc.h> 78 79 /* Number of siblings per CPU package */ 80 int smp_num_siblings = 1; 81 EXPORT_SYMBOL(smp_num_siblings); 82 83 /* Last level cache ID of each logical CPU */ 84 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 85 86 /* representing HT siblings of each logical CPU */ 87 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 88 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 89 90 /* representing HT and core siblings of each logical CPU */ 91 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 92 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 93 94 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); 95 96 /* Per CPU bogomips and other parameters */ 97 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 98 EXPORT_PER_CPU_SYMBOL(cpu_info); 99 100 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 101 { 102 unsigned long flags; 103 104 spin_lock_irqsave(&rtc_lock, flags); 105 CMOS_WRITE(0xa, 0xf); 106 spin_unlock_irqrestore(&rtc_lock, flags); 107 local_flush_tlb(); 108 pr_debug("1.\n"); 109 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = 110 start_eip >> 4; 111 pr_debug("2.\n"); 112 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 113 start_eip & 0xf; 114 pr_debug("3.\n"); 115 } 116 117 static inline void smpboot_restore_warm_reset_vector(void) 118 { 119 unsigned long flags; 120 121 /* 122 * Install writable page 0 entry to set BIOS data area. 123 */ 124 local_flush_tlb(); 125 126 /* 127 * Paranoid: Set warm reset code and vector here back 128 * to default values. 129 */ 130 spin_lock_irqsave(&rtc_lock, flags); 131 CMOS_WRITE(0, 0xf); 132 spin_unlock_irqrestore(&rtc_lock, flags); 133 134 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 135 } 136 137 /* 138 * Report back to the Boot Processor during boot time or to the caller processor 139 * during CPU online. 140 */ 141 static void smp_callin(void) 142 { 143 int cpuid, phys_id; 144 145 /* 146 * If waken up by an INIT in an 82489DX configuration 147 * cpu_callout_mask guarantees we don't get here before 148 * an INIT_deassert IPI reaches our local APIC, so it is 149 * now safe to touch our local APIC. 150 */ 151 cpuid = smp_processor_id(); 152 153 /* 154 * (This works even if the APIC is not enabled.) 155 */ 156 phys_id = read_apic_id(); 157 158 /* 159 * the boot CPU has finished the init stage and is spinning 160 * on callin_map until we finish. We are free to set up this 161 * CPU, first the APIC. (this is probably redundant on most 162 * boards) 163 */ 164 apic_ap_setup(); 165 166 /* 167 * Save our processor parameters. Note: this information 168 * is needed for clock calibration. 169 */ 170 smp_store_cpu_info(cpuid); 171 172 /* 173 * Get our bogomips. 174 * Update loops_per_jiffy in cpu_data. Previous call to 175 * smp_store_cpu_info() stored a value that is close but not as 176 * accurate as the value just calculated. 177 */ 178 calibrate_delay(); 179 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 180 pr_debug("Stack at about %p\n", &cpuid); 181 182 /* 183 * This must be done before setting cpu_online_mask 184 * or calling notify_cpu_starting. 185 */ 186 set_cpu_sibling_map(raw_smp_processor_id()); 187 wmb(); 188 189 notify_cpu_starting(cpuid); 190 191 /* 192 * Allow the master to continue. 193 */ 194 cpumask_set_cpu(cpuid, cpu_callin_mask); 195 } 196 197 static int cpu0_logical_apicid; 198 static int enable_start_cpu0; 199 /* 200 * Activate a secondary processor. 201 */ 202 static void notrace start_secondary(void *unused) 203 { 204 /* 205 * Don't put *anything* before cpu_init(), SMP booting is too 206 * fragile that we want to limit the things done here to the 207 * most necessary things. 208 */ 209 cpu_init(); 210 x86_cpuinit.early_percpu_clock_init(); 211 preempt_disable(); 212 smp_callin(); 213 214 enable_start_cpu0 = 0; 215 216 #ifdef CONFIG_X86_32 217 /* switch away from the initial page table */ 218 load_cr3(swapper_pg_dir); 219 __flush_tlb_all(); 220 #endif 221 222 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 223 barrier(); 224 /* 225 * Check TSC synchronization with the BP: 226 */ 227 check_tsc_sync_target(); 228 229 /* 230 * Lock vector_lock and initialize the vectors on this cpu 231 * before setting the cpu online. We must set it online with 232 * vector_lock held to prevent a concurrent setup/teardown 233 * from seeing a half valid vector space. 234 */ 235 lock_vector_lock(); 236 setup_vector_irq(smp_processor_id()); 237 set_cpu_online(smp_processor_id(), true); 238 unlock_vector_lock(); 239 cpu_set_state_online(smp_processor_id()); 240 x86_platform.nmi_init(); 241 242 /* enable local interrupts */ 243 local_irq_enable(); 244 245 /* to prevent fake stack check failure in clock setup */ 246 boot_init_stack_canary(); 247 248 x86_cpuinit.setup_percpu_clockev(); 249 250 wmb(); 251 cpu_startup_entry(CPUHP_ONLINE); 252 } 253 254 void __init smp_store_boot_cpu_info(void) 255 { 256 int id = 0; /* CPU 0 */ 257 struct cpuinfo_x86 *c = &cpu_data(id); 258 259 *c = boot_cpu_data; 260 c->cpu_index = id; 261 } 262 263 /* 264 * The bootstrap kernel entry code has set these up. Save them for 265 * a given CPU 266 */ 267 void smp_store_cpu_info(int id) 268 { 269 struct cpuinfo_x86 *c = &cpu_data(id); 270 271 *c = boot_cpu_data; 272 c->cpu_index = id; 273 /* 274 * During boot time, CPU0 has this setup already. Save the info when 275 * bringing up AP or offlined CPU0. 276 */ 277 identify_secondary_cpu(c); 278 } 279 280 static bool 281 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 282 { 283 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 284 285 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 286 } 287 288 static bool 289 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 290 { 291 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 292 293 return !WARN_ONCE(!topology_same_node(c, o), 294 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 295 "[node: %d != %d]. Ignoring dependency.\n", 296 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 297 } 298 299 #define link_mask(mfunc, c1, c2) \ 300 do { \ 301 cpumask_set_cpu((c1), mfunc(c2)); \ 302 cpumask_set_cpu((c2), mfunc(c1)); \ 303 } while (0) 304 305 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 306 { 307 if (cpu_has_topoext) { 308 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 309 310 if (c->phys_proc_id == o->phys_proc_id && 311 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && 312 c->compute_unit_id == o->compute_unit_id) 313 return topology_sane(c, o, "smt"); 314 315 } else if (c->phys_proc_id == o->phys_proc_id && 316 c->cpu_core_id == o->cpu_core_id) { 317 return topology_sane(c, o, "smt"); 318 } 319 320 return false; 321 } 322 323 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 324 { 325 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 326 327 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && 328 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) 329 return topology_sane(c, o, "llc"); 330 331 return false; 332 } 333 334 /* 335 * Unlike the other levels, we do not enforce keeping a 336 * multicore group inside a NUMA node. If this happens, we will 337 * discard the MC level of the topology later. 338 */ 339 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 340 { 341 if (c->phys_proc_id == o->phys_proc_id) 342 return true; 343 return false; 344 } 345 346 static struct sched_domain_topology_level numa_inside_package_topology[] = { 347 #ifdef CONFIG_SCHED_SMT 348 { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) }, 349 #endif 350 #ifdef CONFIG_SCHED_MC 351 { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) }, 352 #endif 353 { NULL, }, 354 }; 355 /* 356 * set_sched_topology() sets the topology internal to a CPU. The 357 * NUMA topologies are layered on top of it to build the full 358 * system topology. 359 * 360 * If NUMA nodes are observed to occur within a CPU package, this 361 * function should be called. It forces the sched domain code to 362 * only use the SMT level for the CPU portion of the topology. 363 * This essentially falls back to relying on NUMA information 364 * from the SRAT table to describe the entire system topology 365 * (except for hyperthreads). 366 */ 367 static void primarily_use_numa_for_topology(void) 368 { 369 set_sched_topology(numa_inside_package_topology); 370 } 371 372 void set_cpu_sibling_map(int cpu) 373 { 374 bool has_smt = smp_num_siblings > 1; 375 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 376 struct cpuinfo_x86 *c = &cpu_data(cpu); 377 struct cpuinfo_x86 *o; 378 int i; 379 380 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 381 382 if (!has_mp) { 383 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 384 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 385 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 386 c->booted_cores = 1; 387 return; 388 } 389 390 for_each_cpu(i, cpu_sibling_setup_mask) { 391 o = &cpu_data(i); 392 393 if ((i == cpu) || (has_smt && match_smt(c, o))) 394 link_mask(topology_sibling_cpumask, cpu, i); 395 396 if ((i == cpu) || (has_mp && match_llc(c, o))) 397 link_mask(cpu_llc_shared_mask, cpu, i); 398 399 } 400 401 /* 402 * This needs a separate iteration over the cpus because we rely on all 403 * topology_sibling_cpumask links to be set-up. 404 */ 405 for_each_cpu(i, cpu_sibling_setup_mask) { 406 o = &cpu_data(i); 407 408 if ((i == cpu) || (has_mp && match_die(c, o))) { 409 link_mask(topology_core_cpumask, cpu, i); 410 411 /* 412 * Does this new cpu bringup a new core? 413 */ 414 if (cpumask_weight( 415 topology_sibling_cpumask(cpu)) == 1) { 416 /* 417 * for each core in package, increment 418 * the booted_cores for this new cpu 419 */ 420 if (cpumask_first( 421 topology_sibling_cpumask(i)) == i) 422 c->booted_cores++; 423 /* 424 * increment the core count for all 425 * the other cpus in this package 426 */ 427 if (i != cpu) 428 cpu_data(i).booted_cores++; 429 } else if (i != cpu && !c->booted_cores) 430 c->booted_cores = cpu_data(i).booted_cores; 431 } 432 if (match_die(c, o) && !topology_same_node(c, o)) 433 primarily_use_numa_for_topology(); 434 } 435 } 436 437 /* maps the cpu to the sched domain representing multi-core */ 438 const struct cpumask *cpu_coregroup_mask(int cpu) 439 { 440 return cpu_llc_shared_mask(cpu); 441 } 442 443 static void impress_friends(void) 444 { 445 int cpu; 446 unsigned long bogosum = 0; 447 /* 448 * Allow the user to impress friends. 449 */ 450 pr_debug("Before bogomips\n"); 451 for_each_possible_cpu(cpu) 452 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 453 bogosum += cpu_data(cpu).loops_per_jiffy; 454 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 455 num_online_cpus(), 456 bogosum/(500000/HZ), 457 (bogosum/(5000/HZ))%100); 458 459 pr_debug("Before bogocount - setting activated=1\n"); 460 } 461 462 void __inquire_remote_apic(int apicid) 463 { 464 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 465 const char * const names[] = { "ID", "VERSION", "SPIV" }; 466 int timeout; 467 u32 status; 468 469 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 470 471 for (i = 0; i < ARRAY_SIZE(regs); i++) { 472 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 473 474 /* 475 * Wait for idle. 476 */ 477 status = safe_apic_wait_icr_idle(); 478 if (status) 479 pr_cont("a previous APIC delivery may have failed\n"); 480 481 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 482 483 timeout = 0; 484 do { 485 udelay(100); 486 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 487 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 488 489 switch (status) { 490 case APIC_ICR_RR_VALID: 491 status = apic_read(APIC_RRR); 492 pr_cont("%08x\n", status); 493 break; 494 default: 495 pr_cont("failed\n"); 496 } 497 } 498 } 499 500 /* 501 * The Multiprocessor Specification 1.4 (1997) example code suggests 502 * that there should be a 10ms delay between the BSP asserting INIT 503 * and de-asserting INIT, when starting a remote processor. 504 * But that slows boot and resume on modern processors, which include 505 * many cores and don't require that delay. 506 * 507 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 508 * Modern processor families are quirked to remove the delay entirely. 509 */ 510 #define UDELAY_10MS_DEFAULT 10000 511 512 static unsigned int init_udelay = INT_MAX; 513 514 static int __init cpu_init_udelay(char *str) 515 { 516 get_option(&str, &init_udelay); 517 518 return 0; 519 } 520 early_param("cpu_init_udelay", cpu_init_udelay); 521 522 static void __init smp_quirk_init_udelay(void) 523 { 524 /* if cmdline changed it from default, leave it alone */ 525 if (init_udelay != INT_MAX) 526 return; 527 528 /* if modern processor, use no delay */ 529 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 530 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) 531 init_udelay = 0; 532 533 /* else, use legacy delay */ 534 init_udelay = UDELAY_10MS_DEFAULT; 535 } 536 537 /* 538 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 539 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 540 * won't ... remember to clear down the APIC, etc later. 541 */ 542 int 543 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 544 { 545 unsigned long send_status, accept_status = 0; 546 int maxlvt; 547 548 /* Target chip */ 549 /* Boot on the stack */ 550 /* Kick the second */ 551 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); 552 553 pr_debug("Waiting for send to finish...\n"); 554 send_status = safe_apic_wait_icr_idle(); 555 556 /* 557 * Give the other CPU some time to accept the IPI. 558 */ 559 udelay(200); 560 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 561 maxlvt = lapic_get_maxlvt(); 562 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 563 apic_write(APIC_ESR, 0); 564 accept_status = (apic_read(APIC_ESR) & 0xEF); 565 } 566 pr_debug("NMI sent\n"); 567 568 if (send_status) 569 pr_err("APIC never delivered???\n"); 570 if (accept_status) 571 pr_err("APIC delivery error (%lx)\n", accept_status); 572 573 return (send_status | accept_status); 574 } 575 576 static int 577 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 578 { 579 unsigned long send_status = 0, accept_status = 0; 580 int maxlvt, num_starts, j; 581 582 maxlvt = lapic_get_maxlvt(); 583 584 /* 585 * Be paranoid about clearing APIC errors. 586 */ 587 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 588 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 589 apic_write(APIC_ESR, 0); 590 apic_read(APIC_ESR); 591 } 592 593 pr_debug("Asserting INIT\n"); 594 595 /* 596 * Turn INIT on target chip 597 */ 598 /* 599 * Send IPI 600 */ 601 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 602 phys_apicid); 603 604 pr_debug("Waiting for send to finish...\n"); 605 send_status = safe_apic_wait_icr_idle(); 606 607 udelay(init_udelay); 608 609 pr_debug("Deasserting INIT\n"); 610 611 /* Target chip */ 612 /* Send IPI */ 613 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 614 615 pr_debug("Waiting for send to finish...\n"); 616 send_status = safe_apic_wait_icr_idle(); 617 618 mb(); 619 620 /* 621 * Should we send STARTUP IPIs ? 622 * 623 * Determine this based on the APIC version. 624 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 625 */ 626 if (APIC_INTEGRATED(apic_version[phys_apicid])) 627 num_starts = 2; 628 else 629 num_starts = 0; 630 631 /* 632 * Paravirt / VMI wants a startup IPI hook here to set up the 633 * target processor state. 634 */ 635 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, 636 stack_start); 637 638 /* 639 * Run STARTUP IPI loop. 640 */ 641 pr_debug("#startup loops: %d\n", num_starts); 642 643 for (j = 1; j <= num_starts; j++) { 644 pr_debug("Sending STARTUP #%d\n", j); 645 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 646 apic_write(APIC_ESR, 0); 647 apic_read(APIC_ESR); 648 pr_debug("After apic_write\n"); 649 650 /* 651 * STARTUP IPI 652 */ 653 654 /* Target chip */ 655 /* Boot on the stack */ 656 /* Kick the second */ 657 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 658 phys_apicid); 659 660 /* 661 * Give the other CPU some time to accept the IPI. 662 */ 663 if (init_udelay == 0) 664 udelay(10); 665 else 666 udelay(300); 667 668 pr_debug("Startup point 1\n"); 669 670 pr_debug("Waiting for send to finish...\n"); 671 send_status = safe_apic_wait_icr_idle(); 672 673 /* 674 * Give the other CPU some time to accept the IPI. 675 */ 676 if (init_udelay == 0) 677 udelay(10); 678 else 679 udelay(200); 680 681 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 682 apic_write(APIC_ESR, 0); 683 accept_status = (apic_read(APIC_ESR) & 0xEF); 684 if (send_status || accept_status) 685 break; 686 } 687 pr_debug("After Startup\n"); 688 689 if (send_status) 690 pr_err("APIC never delivered???\n"); 691 if (accept_status) 692 pr_err("APIC delivery error (%lx)\n", accept_status); 693 694 return (send_status | accept_status); 695 } 696 697 void smp_announce(void) 698 { 699 int num_nodes = num_online_nodes(); 700 701 printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n", 702 num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus()); 703 } 704 705 /* reduce the number of lines printed when booting a large cpu count system */ 706 static void announce_cpu(int cpu, int apicid) 707 { 708 static int current_node = -1; 709 int node = early_cpu_to_node(cpu); 710 static int width, node_width; 711 712 if (!width) 713 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 714 715 if (!node_width) 716 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 717 718 if (cpu == 1) 719 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 720 721 if (system_state == SYSTEM_BOOTING) { 722 if (node != current_node) { 723 if (current_node > (-1)) 724 pr_cont("\n"); 725 current_node = node; 726 727 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 728 node_width - num_digits(node), " ", node); 729 } 730 731 /* Add padding for the BSP */ 732 if (cpu == 1) 733 pr_cont("%*s", width + 1, " "); 734 735 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 736 737 } else 738 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 739 node, cpu, apicid); 740 } 741 742 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 743 { 744 int cpu; 745 746 cpu = smp_processor_id(); 747 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 748 return NMI_HANDLED; 749 750 return NMI_DONE; 751 } 752 753 /* 754 * Wake up AP by INIT, INIT, STARTUP sequence. 755 * 756 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 757 * boot-strap code which is not a desired behavior for waking up BSP. To 758 * void the boot-strap code, wake up CPU0 by NMI instead. 759 * 760 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 761 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 762 * We'll change this code in the future to wake up hard offlined CPU0 if 763 * real platform and request are available. 764 */ 765 static int 766 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 767 int *cpu0_nmi_registered) 768 { 769 int id; 770 int boot_error; 771 772 preempt_disable(); 773 774 /* 775 * Wake up AP by INIT, INIT, STARTUP sequence. 776 */ 777 if (cpu) { 778 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 779 goto out; 780 } 781 782 /* 783 * Wake up BSP by nmi. 784 * 785 * Register a NMI handler to help wake up CPU0. 786 */ 787 boot_error = register_nmi_handler(NMI_LOCAL, 788 wakeup_cpu0_nmi, 0, "wake_cpu0"); 789 790 if (!boot_error) { 791 enable_start_cpu0 = 1; 792 *cpu0_nmi_registered = 1; 793 if (apic->dest_logical == APIC_DEST_LOGICAL) 794 id = cpu0_logical_apicid; 795 else 796 id = apicid; 797 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 798 } 799 800 out: 801 preempt_enable(); 802 803 return boot_error; 804 } 805 806 void common_cpu_up(unsigned int cpu, struct task_struct *idle) 807 { 808 /* Just in case we booted with a single CPU. */ 809 alternatives_enable_smp(); 810 811 per_cpu(current_task, cpu) = idle; 812 813 #ifdef CONFIG_X86_32 814 /* Stack for startup_32 can be just as for start_secondary onwards */ 815 irq_ctx_init(cpu); 816 per_cpu(cpu_current_top_of_stack, cpu) = 817 (unsigned long)task_stack_page(idle) + THREAD_SIZE; 818 #else 819 clear_tsk_thread_flag(idle, TIF_FORK); 820 initial_gs = per_cpu_offset(cpu); 821 #endif 822 } 823 824 /* 825 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 826 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 827 * Returns zero if CPU booted OK, else error code from 828 * ->wakeup_secondary_cpu. 829 */ 830 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) 831 { 832 volatile u32 *trampoline_status = 833 (volatile u32 *) __va(real_mode_header->trampoline_status); 834 /* start_ip had better be page-aligned! */ 835 unsigned long start_ip = real_mode_header->trampoline_start; 836 837 unsigned long boot_error = 0; 838 int cpu0_nmi_registered = 0; 839 unsigned long timeout; 840 841 idle->thread.sp = (unsigned long) (((struct pt_regs *) 842 (THREAD_SIZE + task_stack_page(idle))) - 1); 843 844 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 845 initial_code = (unsigned long)start_secondary; 846 stack_start = idle->thread.sp; 847 848 /* 849 * Enable the espfix hack for this CPU 850 */ 851 #ifdef CONFIG_X86_ESPFIX64 852 init_espfix_ap(cpu); 853 #endif 854 855 /* So we see what's up */ 856 announce_cpu(cpu, apicid); 857 858 /* 859 * This grunge runs the startup process for 860 * the targeted processor. 861 */ 862 863 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 864 865 pr_debug("Setting warm reset code and vector.\n"); 866 867 smpboot_setup_warm_reset_vector(start_ip); 868 /* 869 * Be paranoid about clearing APIC errors. 870 */ 871 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 872 apic_write(APIC_ESR, 0); 873 apic_read(APIC_ESR); 874 } 875 } 876 877 /* 878 * AP might wait on cpu_callout_mask in cpu_init() with 879 * cpu_initialized_mask set if previous attempt to online 880 * it timed-out. Clear cpu_initialized_mask so that after 881 * INIT/SIPI it could start with a clean state. 882 */ 883 cpumask_clear_cpu(cpu, cpu_initialized_mask); 884 smp_mb(); 885 886 /* 887 * Wake up a CPU in difference cases: 888 * - Use the method in the APIC driver if it's defined 889 * Otherwise, 890 * - Use an INIT boot APIC message for APs or NMI for BSP. 891 */ 892 if (apic->wakeup_secondary_cpu) 893 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 894 else 895 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 896 &cpu0_nmi_registered); 897 898 if (!boot_error) { 899 /* 900 * Wait 10s total for first sign of life from AP 901 */ 902 boot_error = -1; 903 timeout = jiffies + 10*HZ; 904 while (time_before(jiffies, timeout)) { 905 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 906 /* 907 * Tell AP to proceed with initialization 908 */ 909 cpumask_set_cpu(cpu, cpu_callout_mask); 910 boot_error = 0; 911 break; 912 } 913 schedule(); 914 } 915 } 916 917 if (!boot_error) { 918 /* 919 * Wait till AP completes initial initialization 920 */ 921 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 922 /* 923 * Allow other tasks to run while we wait for the 924 * AP to come online. This also gives a chance 925 * for the MTRR work(triggered by the AP coming online) 926 * to be completed in the stop machine context. 927 */ 928 schedule(); 929 } 930 } 931 932 /* mark "stuck" area as not stuck */ 933 *trampoline_status = 0; 934 935 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 936 /* 937 * Cleanup possible dangling ends... 938 */ 939 smpboot_restore_warm_reset_vector(); 940 } 941 /* 942 * Clean up the nmi handler. Do this after the callin and callout sync 943 * to avoid impact of possible long unregister time. 944 */ 945 if (cpu0_nmi_registered) 946 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 947 948 return boot_error; 949 } 950 951 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 952 { 953 int apicid = apic->cpu_present_to_apicid(cpu); 954 unsigned long flags; 955 int err; 956 957 WARN_ON(irqs_disabled()); 958 959 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 960 961 if (apicid == BAD_APICID || 962 !physid_isset(apicid, phys_cpu_present_map) || 963 !apic->apic_id_valid(apicid)) { 964 pr_err("%s: bad cpu %d\n", __func__, cpu); 965 return -EINVAL; 966 } 967 968 /* 969 * Already booted CPU? 970 */ 971 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 972 pr_debug("do_boot_cpu %d Already started\n", cpu); 973 return -ENOSYS; 974 } 975 976 /* 977 * Save current MTRR state in case it was changed since early boot 978 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 979 */ 980 mtrr_save_state(); 981 982 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 983 err = cpu_check_up_prepare(cpu); 984 if (err && err != -EBUSY) 985 return err; 986 987 /* the FPU context is blank, nobody can own it */ 988 __cpu_disable_lazy_restore(cpu); 989 990 common_cpu_up(cpu, tidle); 991 992 /* 993 * We have to walk the irq descriptors to setup the vector 994 * space for the cpu which comes online. Prevent irq 995 * alloc/free across the bringup. 996 */ 997 irq_lock_sparse(); 998 999 err = do_boot_cpu(apicid, cpu, tidle); 1000 1001 if (err) { 1002 irq_unlock_sparse(); 1003 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1004 return -EIO; 1005 } 1006 1007 /* 1008 * Check TSC synchronization with the AP (keep irqs disabled 1009 * while doing so): 1010 */ 1011 local_irq_save(flags); 1012 check_tsc_sync_source(cpu); 1013 local_irq_restore(flags); 1014 1015 while (!cpu_online(cpu)) { 1016 cpu_relax(); 1017 touch_nmi_watchdog(); 1018 } 1019 1020 irq_unlock_sparse(); 1021 1022 return 0; 1023 } 1024 1025 /** 1026 * arch_disable_smp_support() - disables SMP support for x86 at runtime 1027 */ 1028 void arch_disable_smp_support(void) 1029 { 1030 disable_ioapic_support(); 1031 } 1032 1033 /* 1034 * Fall back to non SMP mode after errors. 1035 * 1036 * RED-PEN audit/test this more. I bet there is more state messed up here. 1037 */ 1038 static __init void disable_smp(void) 1039 { 1040 pr_info("SMP disabled\n"); 1041 1042 disable_ioapic_support(); 1043 1044 init_cpu_present(cpumask_of(0)); 1045 init_cpu_possible(cpumask_of(0)); 1046 1047 if (smp_found_config) 1048 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1049 else 1050 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1051 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1052 cpumask_set_cpu(0, topology_core_cpumask(0)); 1053 } 1054 1055 enum { 1056 SMP_OK, 1057 SMP_NO_CONFIG, 1058 SMP_NO_APIC, 1059 SMP_FORCE_UP, 1060 }; 1061 1062 /* 1063 * Various sanity checks. 1064 */ 1065 static int __init smp_sanity_check(unsigned max_cpus) 1066 { 1067 preempt_disable(); 1068 1069 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1070 if (def_to_bigsmp && nr_cpu_ids > 8) { 1071 unsigned int cpu; 1072 unsigned nr; 1073 1074 pr_warn("More than 8 CPUs detected - skipping them\n" 1075 "Use CONFIG_X86_BIGSMP\n"); 1076 1077 nr = 0; 1078 for_each_present_cpu(cpu) { 1079 if (nr >= 8) 1080 set_cpu_present(cpu, false); 1081 nr++; 1082 } 1083 1084 nr = 0; 1085 for_each_possible_cpu(cpu) { 1086 if (nr >= 8) 1087 set_cpu_possible(cpu, false); 1088 nr++; 1089 } 1090 1091 nr_cpu_ids = 8; 1092 } 1093 #endif 1094 1095 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1096 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1097 hard_smp_processor_id()); 1098 1099 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1100 } 1101 1102 /* 1103 * If we couldn't find an SMP configuration at boot time, 1104 * get out of here now! 1105 */ 1106 if (!smp_found_config && !acpi_lapic) { 1107 preempt_enable(); 1108 pr_notice("SMP motherboard not detected\n"); 1109 return SMP_NO_CONFIG; 1110 } 1111 1112 /* 1113 * Should not be necessary because the MP table should list the boot 1114 * CPU too, but we do it for the sake of robustness anyway. 1115 */ 1116 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1117 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1118 boot_cpu_physical_apicid); 1119 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1120 } 1121 preempt_enable(); 1122 1123 /* 1124 * If we couldn't find a local APIC, then get out of here now! 1125 */ 1126 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 1127 !cpu_has_apic) { 1128 if (!disable_apic) { 1129 pr_err("BIOS bug, local APIC #%d not detected!...\n", 1130 boot_cpu_physical_apicid); 1131 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); 1132 } 1133 return SMP_NO_APIC; 1134 } 1135 1136 /* 1137 * If SMP should be disabled, then really disable it! 1138 */ 1139 if (!max_cpus) { 1140 pr_info("SMP mode deactivated\n"); 1141 return SMP_FORCE_UP; 1142 } 1143 1144 return SMP_OK; 1145 } 1146 1147 static void __init smp_cpu_index_default(void) 1148 { 1149 int i; 1150 struct cpuinfo_x86 *c; 1151 1152 for_each_possible_cpu(i) { 1153 c = &cpu_data(i); 1154 /* mark all to hotplug */ 1155 c->cpu_index = nr_cpu_ids; 1156 } 1157 } 1158 1159 /* 1160 * Prepare for SMP bootup. The MP table or ACPI has been read 1161 * earlier. Just do some sanity checking here and enable APIC mode. 1162 */ 1163 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1164 { 1165 unsigned int i; 1166 1167 smp_cpu_index_default(); 1168 1169 /* 1170 * Setup boot CPU information 1171 */ 1172 smp_store_boot_cpu_info(); /* Final full version of the data */ 1173 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1174 mb(); 1175 1176 current_thread_info()->cpu = 0; /* needed? */ 1177 for_each_possible_cpu(i) { 1178 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1179 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1180 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1181 } 1182 set_cpu_sibling_map(0); 1183 1184 switch (smp_sanity_check(max_cpus)) { 1185 case SMP_NO_CONFIG: 1186 disable_smp(); 1187 if (APIC_init_uniprocessor()) 1188 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); 1189 return; 1190 case SMP_NO_APIC: 1191 disable_smp(); 1192 return; 1193 case SMP_FORCE_UP: 1194 disable_smp(); 1195 apic_bsp_setup(false); 1196 return; 1197 case SMP_OK: 1198 break; 1199 } 1200 1201 default_setup_apic_routing(); 1202 1203 if (read_apic_id() != boot_cpu_physical_apicid) { 1204 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1205 read_apic_id(), boot_cpu_physical_apicid); 1206 /* Or can we switch back to PIC here? */ 1207 } 1208 1209 cpu0_logical_apicid = apic_bsp_setup(false); 1210 1211 pr_info("CPU%d: ", 0); 1212 print_cpu_info(&cpu_data(0)); 1213 1214 if (is_uv_system()) 1215 uv_system_init(); 1216 1217 set_mtrr_aps_delayed_init(); 1218 1219 smp_quirk_init_udelay(); 1220 } 1221 1222 void arch_enable_nonboot_cpus_begin(void) 1223 { 1224 set_mtrr_aps_delayed_init(); 1225 } 1226 1227 void arch_enable_nonboot_cpus_end(void) 1228 { 1229 mtrr_aps_init(); 1230 } 1231 1232 /* 1233 * Early setup to make printk work. 1234 */ 1235 void __init native_smp_prepare_boot_cpu(void) 1236 { 1237 int me = smp_processor_id(); 1238 switch_to_new_gdt(me); 1239 /* already set me in cpu_online_mask in boot_cpu_init() */ 1240 cpumask_set_cpu(me, cpu_callout_mask); 1241 cpu_set_state_online(me); 1242 } 1243 1244 void __init native_smp_cpus_done(unsigned int max_cpus) 1245 { 1246 pr_debug("Boot done\n"); 1247 1248 nmi_selftest(); 1249 impress_friends(); 1250 setup_ioapic_dest(); 1251 mtrr_aps_init(); 1252 } 1253 1254 static int __initdata setup_possible_cpus = -1; 1255 static int __init _setup_possible_cpus(char *str) 1256 { 1257 get_option(&str, &setup_possible_cpus); 1258 return 0; 1259 } 1260 early_param("possible_cpus", _setup_possible_cpus); 1261 1262 1263 /* 1264 * cpu_possible_mask should be static, it cannot change as cpu's 1265 * are onlined, or offlined. The reason is per-cpu data-structures 1266 * are allocated by some modules at init time, and dont expect to 1267 * do this dynamically on cpu arrival/departure. 1268 * cpu_present_mask on the other hand can change dynamically. 1269 * In case when cpu_hotplug is not compiled, then we resort to current 1270 * behaviour, which is cpu_possible == cpu_present. 1271 * - Ashok Raj 1272 * 1273 * Three ways to find out the number of additional hotplug CPUs: 1274 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1275 * - The user can overwrite it with possible_cpus=NUM 1276 * - Otherwise don't reserve additional CPUs. 1277 * We do this because additional CPUs waste a lot of memory. 1278 * -AK 1279 */ 1280 __init void prefill_possible_map(void) 1281 { 1282 int i, possible; 1283 1284 /* no processor from mptable or madt */ 1285 if (!num_processors) 1286 num_processors = 1; 1287 1288 i = setup_max_cpus ?: 1; 1289 if (setup_possible_cpus == -1) { 1290 possible = num_processors; 1291 #ifdef CONFIG_HOTPLUG_CPU 1292 if (setup_max_cpus) 1293 possible += disabled_cpus; 1294 #else 1295 if (possible > i) 1296 possible = i; 1297 #endif 1298 } else 1299 possible = setup_possible_cpus; 1300 1301 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1302 1303 /* nr_cpu_ids could be reduced via nr_cpus= */ 1304 if (possible > nr_cpu_ids) { 1305 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", 1306 possible, nr_cpu_ids); 1307 possible = nr_cpu_ids; 1308 } 1309 1310 #ifdef CONFIG_HOTPLUG_CPU 1311 if (!setup_max_cpus) 1312 #endif 1313 if (possible > i) { 1314 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1315 possible, setup_max_cpus); 1316 possible = i; 1317 } 1318 1319 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1320 possible, max_t(int, possible - num_processors, 0)); 1321 1322 for (i = 0; i < possible; i++) 1323 set_cpu_possible(i, true); 1324 for (; i < NR_CPUS; i++) 1325 set_cpu_possible(i, false); 1326 1327 nr_cpu_ids = possible; 1328 } 1329 1330 #ifdef CONFIG_HOTPLUG_CPU 1331 1332 static void remove_siblinginfo(int cpu) 1333 { 1334 int sibling; 1335 struct cpuinfo_x86 *c = &cpu_data(cpu); 1336 1337 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1338 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1339 /*/ 1340 * last thread sibling in this cpu core going down 1341 */ 1342 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1343 cpu_data(sibling).booted_cores--; 1344 } 1345 1346 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) 1347 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1348 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1349 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1350 cpumask_clear(cpu_llc_shared_mask(cpu)); 1351 cpumask_clear(topology_sibling_cpumask(cpu)); 1352 cpumask_clear(topology_core_cpumask(cpu)); 1353 c->phys_proc_id = 0; 1354 c->cpu_core_id = 0; 1355 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1356 } 1357 1358 static void remove_cpu_from_maps(int cpu) 1359 { 1360 set_cpu_online(cpu, false); 1361 cpumask_clear_cpu(cpu, cpu_callout_mask); 1362 cpumask_clear_cpu(cpu, cpu_callin_mask); 1363 /* was set by cpu_init() */ 1364 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1365 numa_remove_cpu(cpu); 1366 } 1367 1368 void cpu_disable_common(void) 1369 { 1370 int cpu = smp_processor_id(); 1371 1372 remove_siblinginfo(cpu); 1373 1374 /* It's now safe to remove this processor from the online map */ 1375 lock_vector_lock(); 1376 remove_cpu_from_maps(cpu); 1377 unlock_vector_lock(); 1378 fixup_irqs(); 1379 } 1380 1381 int native_cpu_disable(void) 1382 { 1383 int ret; 1384 1385 ret = check_irq_vectors_for_cpu_disable(); 1386 if (ret) 1387 return ret; 1388 1389 clear_local_APIC(); 1390 cpu_disable_common(); 1391 1392 return 0; 1393 } 1394 1395 int common_cpu_die(unsigned int cpu) 1396 { 1397 int ret = 0; 1398 1399 /* We don't do anything here: idle task is faking death itself. */ 1400 1401 /* They ack this in play_dead() by setting CPU_DEAD */ 1402 if (cpu_wait_death(cpu, 5)) { 1403 if (system_state == SYSTEM_RUNNING) 1404 pr_info("CPU %u is now offline\n", cpu); 1405 } else { 1406 pr_err("CPU %u didn't die...\n", cpu); 1407 ret = -1; 1408 } 1409 1410 return ret; 1411 } 1412 1413 void native_cpu_die(unsigned int cpu) 1414 { 1415 common_cpu_die(cpu); 1416 } 1417 1418 void play_dead_common(void) 1419 { 1420 idle_task_exit(); 1421 reset_lazy_tlbstate(); 1422 amd_e400_remove_cpu(raw_smp_processor_id()); 1423 1424 /* Ack it */ 1425 (void)cpu_report_death(); 1426 1427 /* 1428 * With physical CPU hotplug, we should halt the cpu 1429 */ 1430 local_irq_disable(); 1431 } 1432 1433 static bool wakeup_cpu0(void) 1434 { 1435 if (smp_processor_id() == 0 && enable_start_cpu0) 1436 return true; 1437 1438 return false; 1439 } 1440 1441 /* 1442 * We need to flush the caches before going to sleep, lest we have 1443 * dirty data in our caches when we come back up. 1444 */ 1445 static inline void mwait_play_dead(void) 1446 { 1447 unsigned int eax, ebx, ecx, edx; 1448 unsigned int highest_cstate = 0; 1449 unsigned int highest_subcstate = 0; 1450 void *mwait_ptr; 1451 int i; 1452 1453 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1454 return; 1455 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1456 return; 1457 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1458 return; 1459 1460 eax = CPUID_MWAIT_LEAF; 1461 ecx = 0; 1462 native_cpuid(&eax, &ebx, &ecx, &edx); 1463 1464 /* 1465 * eax will be 0 if EDX enumeration is not valid. 1466 * Initialized below to cstate, sub_cstate value when EDX is valid. 1467 */ 1468 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1469 eax = 0; 1470 } else { 1471 edx >>= MWAIT_SUBSTATE_SIZE; 1472 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1473 if (edx & MWAIT_SUBSTATE_MASK) { 1474 highest_cstate = i; 1475 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1476 } 1477 } 1478 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1479 (highest_subcstate - 1); 1480 } 1481 1482 /* 1483 * This should be a memory location in a cache line which is 1484 * unlikely to be touched by other processors. The actual 1485 * content is immaterial as it is not actually modified in any way. 1486 */ 1487 mwait_ptr = ¤t_thread_info()->flags; 1488 1489 wbinvd(); 1490 1491 while (1) { 1492 /* 1493 * The CLFLUSH is a workaround for erratum AAI65 for 1494 * the Xeon 7400 series. It's not clear it is actually 1495 * needed, but it should be harmless in either case. 1496 * The WBINVD is insufficient due to the spurious-wakeup 1497 * case where we return around the loop. 1498 */ 1499 mb(); 1500 clflush(mwait_ptr); 1501 mb(); 1502 __monitor(mwait_ptr, 0, 0); 1503 mb(); 1504 __mwait(eax, 0); 1505 /* 1506 * If NMI wants to wake up CPU0, start CPU0. 1507 */ 1508 if (wakeup_cpu0()) 1509 start_cpu0(); 1510 } 1511 } 1512 1513 static inline void hlt_play_dead(void) 1514 { 1515 if (__this_cpu_read(cpu_info.x86) >= 4) 1516 wbinvd(); 1517 1518 while (1) { 1519 native_halt(); 1520 /* 1521 * If NMI wants to wake up CPU0, start CPU0. 1522 */ 1523 if (wakeup_cpu0()) 1524 start_cpu0(); 1525 } 1526 } 1527 1528 void native_play_dead(void) 1529 { 1530 play_dead_common(); 1531 tboot_shutdown(TB_SHUTDOWN_WFS); 1532 1533 mwait_play_dead(); /* Only returns on failure */ 1534 if (cpuidle_play_dead()) 1535 hlt_play_dead(); 1536 } 1537 1538 #else /* ... !CONFIG_HOTPLUG_CPU */ 1539 int native_cpu_disable(void) 1540 { 1541 return -ENOSYS; 1542 } 1543 1544 void native_cpu_die(unsigned int cpu) 1545 { 1546 /* We said "no" in __cpu_disable */ 1547 BUG(); 1548 } 1549 1550 void native_play_dead(void) 1551 { 1552 BUG(); 1553 } 1554 1555 #endif 1556