1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * x86 SMP booting functions 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 7 * Copyright 2001 Andi Kleen, SuSE Labs. 8 * 9 * Much of the core SMP work is based on previous work by Thomas Radke, to 10 * whom a great many thanks are extended. 11 * 12 * Thanks to Intel for making available several different Pentium, 13 * Pentium Pro and Pentium-II/Xeon MP machines. 14 * Original development of Linux SMP code supported by Caldera. 15 * 16 * Fixes 17 * Felix Koop : NR_CPUS used properly 18 * Jose Renau : Handle single CPU case. 19 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 20 * Greg Wright : Fix for kernel stacks panic. 21 * Erich Boleyn : MP v1.4 and additional changes. 22 * Matthias Sattler : Changes for 2.1 kernel map. 23 * Michel Lespinasse : Changes for 2.1 kernel map. 24 * Michael Chastain : Change trampoline.S to gnu as. 25 * Alan Cox : Dumb bug: 'B' step PPro's are fine 26 * Ingo Molnar : Added APIC timers, based on code 27 * from Jose Renau 28 * Ingo Molnar : various cleanups and rewrites 29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 31 * Andi Kleen : Changed for SMP boot into long mode. 32 * Martin J. Bligh : Added support for multi-quad systems 33 * Dave Jones : Report invalid combinations of Athlon CPUs. 34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 35 * Andi Kleen : Converted to new state machine. 36 * Ashok Raj : CPU hotplug support 37 * Glauber Costa : i386 and x86_64 integration 38 */ 39 40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/export.h> 45 #include <linux/sched.h> 46 #include <linux/sched/topology.h> 47 #include <linux/sched/hotplug.h> 48 #include <linux/sched/task_stack.h> 49 #include <linux/percpu.h> 50 #include <linux/memblock.h> 51 #include <linux/err.h> 52 #include <linux/nmi.h> 53 #include <linux/tboot.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 #include <linux/kexec.h> 57 #include <linux/numa.h> 58 #include <linux/pgtable.h> 59 #include <linux/overflow.h> 60 #include <linux/stackprotector.h> 61 #include <linux/cpuhotplug.h> 62 #include <linux/mc146818rtc.h> 63 64 #include <asm/acpi.h> 65 #include <asm/cacheinfo.h> 66 #include <asm/desc.h> 67 #include <asm/nmi.h> 68 #include <asm/irq.h> 69 #include <asm/realmode.h> 70 #include <asm/cpu.h> 71 #include <asm/numa.h> 72 #include <asm/tlbflush.h> 73 #include <asm/mtrr.h> 74 #include <asm/mwait.h> 75 #include <asm/apic.h> 76 #include <asm/io_apic.h> 77 #include <asm/fpu/api.h> 78 #include <asm/setup.h> 79 #include <asm/uv/uv.h> 80 #include <asm/microcode.h> 81 #include <asm/i8259.h> 82 #include <asm/misc.h> 83 #include <asm/qspinlock.h> 84 #include <asm/intel-family.h> 85 #include <asm/cpu_device_id.h> 86 #include <asm/spec-ctrl.h> 87 #include <asm/hw_irq.h> 88 #include <asm/stackprotector.h> 89 #include <asm/sev.h> 90 91 /* representing HT siblings of each logical CPU */ 92 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 93 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 94 95 /* representing HT and core siblings of each logical CPU */ 96 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 97 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 98 99 /* representing HT, core, and die siblings of each logical CPU */ 100 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); 101 EXPORT_PER_CPU_SYMBOL(cpu_die_map); 102 103 /* Per CPU bogomips and other parameters */ 104 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 105 EXPORT_PER_CPU_SYMBOL(cpu_info); 106 107 /* CPUs which are the primary SMT threads */ 108 struct cpumask __cpu_primary_thread_mask __read_mostly; 109 110 /* Representing CPUs for which sibling maps can be computed */ 111 static cpumask_var_t cpu_sibling_setup_mask; 112 113 struct mwait_cpu_dead { 114 unsigned int control; 115 unsigned int status; 116 }; 117 118 #define CPUDEAD_MWAIT_WAIT 0xDEADBEEF 119 #define CPUDEAD_MWAIT_KEXEC_HLT 0x4A17DEAD 120 121 /* 122 * Cache line aligned data for mwait_play_dead(). Separate on purpose so 123 * that it's unlikely to be touched by other CPUs. 124 */ 125 static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead); 126 127 /* Logical package management. We might want to allocate that dynamically */ 128 unsigned int __max_logical_packages __read_mostly; 129 EXPORT_SYMBOL(__max_logical_packages); 130 static unsigned int logical_packages __read_mostly; 131 static unsigned int logical_die __read_mostly; 132 133 /* Maximum number of SMT threads on any online core */ 134 int __read_mostly __max_smt_threads = 1; 135 136 /* Flag to indicate if a complete sched domain rebuild is required */ 137 bool x86_topology_update; 138 139 int arch_update_cpu_topology(void) 140 { 141 int retval = x86_topology_update; 142 143 x86_topology_update = false; 144 return retval; 145 } 146 147 static unsigned int smpboot_warm_reset_vector_count; 148 149 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 150 { 151 unsigned long flags; 152 153 spin_lock_irqsave(&rtc_lock, flags); 154 if (!smpboot_warm_reset_vector_count++) { 155 CMOS_WRITE(0xa, 0xf); 156 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = start_eip >> 4; 157 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = start_eip & 0xf; 158 } 159 spin_unlock_irqrestore(&rtc_lock, flags); 160 } 161 162 static inline void smpboot_restore_warm_reset_vector(void) 163 { 164 unsigned long flags; 165 166 /* 167 * Paranoid: Set warm reset code and vector here back 168 * to default values. 169 */ 170 spin_lock_irqsave(&rtc_lock, flags); 171 if (!--smpboot_warm_reset_vector_count) { 172 CMOS_WRITE(0, 0xf); 173 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 174 } 175 spin_unlock_irqrestore(&rtc_lock, flags); 176 177 } 178 179 /* Run the next set of setup steps for the upcoming CPU */ 180 static void ap_starting(void) 181 { 182 int cpuid = smp_processor_id(); 183 184 /* Mop up eventual mwait_play_dead() wreckage */ 185 this_cpu_write(mwait_cpu_dead.status, 0); 186 this_cpu_write(mwait_cpu_dead.control, 0); 187 188 /* 189 * If woken up by an INIT in an 82489DX configuration the alive 190 * synchronization guarantees that the CPU does not reach this 191 * point before an INIT_deassert IPI reaches the local APIC, so it 192 * is now safe to touch the local APIC. 193 * 194 * Set up this CPU, first the APIC, which is probably redundant on 195 * most boards. 196 */ 197 apic_ap_setup(); 198 199 /* Save the processor parameters. */ 200 smp_store_cpu_info(cpuid); 201 202 /* 203 * The topology information must be up to date before 204 * notify_cpu_starting(). 205 */ 206 set_cpu_sibling_map(cpuid); 207 208 ap_init_aperfmperf(); 209 210 pr_debug("Stack at about %p\n", &cpuid); 211 212 wmb(); 213 214 /* 215 * This runs the AP through all the cpuhp states to its target 216 * state CPUHP_ONLINE. 217 */ 218 notify_cpu_starting(cpuid); 219 } 220 221 static void ap_calibrate_delay(void) 222 { 223 /* 224 * Calibrate the delay loop and update loops_per_jiffy in cpu_data. 225 * smp_store_cpu_info() stored a value that is close but not as 226 * accurate as the value just calculated. 227 * 228 * As this is invoked after the TSC synchronization check, 229 * calibrate_delay_is_known() will skip the calibration routine 230 * when TSC is synchronized across sockets. 231 */ 232 calibrate_delay(); 233 cpu_data(smp_processor_id()).loops_per_jiffy = loops_per_jiffy; 234 } 235 236 /* 237 * Activate a secondary processor. 238 */ 239 static void notrace start_secondary(void *unused) 240 { 241 /* 242 * Don't put *anything* except direct CPU state initialization 243 * before cpu_init(), SMP booting is too fragile that we want to 244 * limit the things done here to the most necessary things. 245 */ 246 cr4_init(); 247 248 /* 249 * 32-bit specific. 64-bit reaches this code with the correct page 250 * table established. Yet another historical divergence. 251 */ 252 if (IS_ENABLED(CONFIG_X86_32)) { 253 /* switch away from the initial page table */ 254 load_cr3(swapper_pg_dir); 255 __flush_tlb_all(); 256 } 257 258 cpu_init_exception_handling(); 259 260 /* 261 * 32-bit systems load the microcode from the ASM startup code for 262 * historical reasons. 263 * 264 * On 64-bit systems load it before reaching the AP alive 265 * synchronization point below so it is not part of the full per 266 * CPU serialized bringup part when "parallel" bringup is enabled. 267 * 268 * That's even safe when hyperthreading is enabled in the CPU as 269 * the core code starts the primary threads first and leaves the 270 * secondary threads waiting for SIPI. Loading microcode on 271 * physical cores concurrently is a safe operation. 272 * 273 * This covers both the Intel specific issue that concurrent 274 * microcode loading on SMT siblings must be prohibited and the 275 * vendor independent issue`that microcode loading which changes 276 * CPUID, MSRs etc. must be strictly serialized to maintain 277 * software state correctness. 278 */ 279 if (IS_ENABLED(CONFIG_X86_64)) 280 load_ucode_ap(); 281 282 /* 283 * Synchronization point with the hotplug core. Sets this CPUs 284 * synchronization state to ALIVE and spin-waits for the control CPU to 285 * release this CPU for further bringup. 286 */ 287 cpuhp_ap_sync_alive(); 288 289 cpu_init(); 290 fpu__init_cpu(); 291 rcu_cpu_starting(raw_smp_processor_id()); 292 x86_cpuinit.early_percpu_clock_init(); 293 294 ap_starting(); 295 296 /* Check TSC synchronization with the control CPU. */ 297 check_tsc_sync_target(); 298 299 /* 300 * Calibrate the delay loop after the TSC synchronization check. 301 * This allows to skip the calibration when TSC is synchronized 302 * across sockets. 303 */ 304 ap_calibrate_delay(); 305 306 speculative_store_bypass_ht_init(); 307 308 /* 309 * Lock vector_lock, set CPU online and bring the vector 310 * allocator online. Online must be set with vector_lock held 311 * to prevent a concurrent irq setup/teardown from seeing a 312 * half valid vector space. 313 */ 314 lock_vector_lock(); 315 set_cpu_online(smp_processor_id(), true); 316 lapic_online(); 317 unlock_vector_lock(); 318 x86_platform.nmi_init(); 319 320 /* enable local interrupts */ 321 local_irq_enable(); 322 323 x86_cpuinit.setup_percpu_clockev(); 324 325 wmb(); 326 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 327 } 328 329 /** 330 * topology_smt_supported - Check whether SMT is supported by the CPUs 331 */ 332 bool topology_smt_supported(void) 333 { 334 return smp_num_siblings > 1; 335 } 336 337 /** 338 * topology_phys_to_logical_pkg - Map a physical package id to a logical 339 * @phys_pkg: The physical package id to map 340 * 341 * Returns logical package id or -1 if not found 342 */ 343 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 344 { 345 int cpu; 346 347 for_each_possible_cpu(cpu) { 348 struct cpuinfo_x86 *c = &cpu_data(cpu); 349 350 if (c->initialized && c->phys_proc_id == phys_pkg) 351 return c->logical_proc_id; 352 } 353 return -1; 354 } 355 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 356 357 /** 358 * topology_phys_to_logical_die - Map a physical die id to logical 359 * @die_id: The physical die id to map 360 * @cur_cpu: The CPU for which the mapping is done 361 * 362 * Returns logical die id or -1 if not found 363 */ 364 static int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu) 365 { 366 int cpu, proc_id = cpu_data(cur_cpu).phys_proc_id; 367 368 for_each_possible_cpu(cpu) { 369 struct cpuinfo_x86 *c = &cpu_data(cpu); 370 371 if (c->initialized && c->cpu_die_id == die_id && 372 c->phys_proc_id == proc_id) 373 return c->logical_die_id; 374 } 375 return -1; 376 } 377 378 /** 379 * topology_update_package_map - Update the physical to logical package map 380 * @pkg: The physical package id as retrieved via CPUID 381 * @cpu: The cpu for which this is updated 382 */ 383 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 384 { 385 int new; 386 387 /* Already available somewhere? */ 388 new = topology_phys_to_logical_pkg(pkg); 389 if (new >= 0) 390 goto found; 391 392 new = logical_packages++; 393 if (new != pkg) { 394 pr_info("CPU %u Converting physical %u to logical package %u\n", 395 cpu, pkg, new); 396 } 397 found: 398 cpu_data(cpu).logical_proc_id = new; 399 return 0; 400 } 401 /** 402 * topology_update_die_map - Update the physical to logical die map 403 * @die: The die id as retrieved via CPUID 404 * @cpu: The cpu for which this is updated 405 */ 406 int topology_update_die_map(unsigned int die, unsigned int cpu) 407 { 408 int new; 409 410 /* Already available somewhere? */ 411 new = topology_phys_to_logical_die(die, cpu); 412 if (new >= 0) 413 goto found; 414 415 new = logical_die++; 416 if (new != die) { 417 pr_info("CPU %u Converting physical %u to logical die %u\n", 418 cpu, die, new); 419 } 420 found: 421 cpu_data(cpu).logical_die_id = new; 422 return 0; 423 } 424 425 void __init smp_store_boot_cpu_info(void) 426 { 427 int id = 0; /* CPU 0 */ 428 struct cpuinfo_x86 *c = &cpu_data(id); 429 430 *c = boot_cpu_data; 431 c->cpu_index = id; 432 topology_update_package_map(c->phys_proc_id, id); 433 topology_update_die_map(c->cpu_die_id, id); 434 c->initialized = true; 435 } 436 437 /* 438 * The bootstrap kernel entry code has set these up. Save them for 439 * a given CPU 440 */ 441 void smp_store_cpu_info(int id) 442 { 443 struct cpuinfo_x86 *c = &cpu_data(id); 444 445 /* Copy boot_cpu_data only on the first bringup */ 446 if (!c->initialized) 447 *c = boot_cpu_data; 448 c->cpu_index = id; 449 /* 450 * During boot time, CPU0 has this setup already. Save the info when 451 * bringing up an AP. 452 */ 453 identify_secondary_cpu(c); 454 c->initialized = true; 455 } 456 457 static bool 458 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 459 { 460 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 461 462 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 463 } 464 465 static bool 466 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 467 { 468 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 469 470 return !WARN_ONCE(!topology_same_node(c, o), 471 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 472 "[node: %d != %d]. Ignoring dependency.\n", 473 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 474 } 475 476 #define link_mask(mfunc, c1, c2) \ 477 do { \ 478 cpumask_set_cpu((c1), mfunc(c2)); \ 479 cpumask_set_cpu((c2), mfunc(c1)); \ 480 } while (0) 481 482 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 483 { 484 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 485 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 486 487 if (c->phys_proc_id == o->phys_proc_id && 488 c->cpu_die_id == o->cpu_die_id && 489 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { 490 if (c->cpu_core_id == o->cpu_core_id) 491 return topology_sane(c, o, "smt"); 492 493 if ((c->cu_id != 0xff) && 494 (o->cu_id != 0xff) && 495 (c->cu_id == o->cu_id)) 496 return topology_sane(c, o, "smt"); 497 } 498 499 } else if (c->phys_proc_id == o->phys_proc_id && 500 c->cpu_die_id == o->cpu_die_id && 501 c->cpu_core_id == o->cpu_core_id) { 502 return topology_sane(c, o, "smt"); 503 } 504 505 return false; 506 } 507 508 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 509 { 510 if (c->phys_proc_id == o->phys_proc_id && 511 c->cpu_die_id == o->cpu_die_id) 512 return true; 513 return false; 514 } 515 516 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 517 { 518 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 519 520 /* If the arch didn't set up l2c_id, fall back to SMT */ 521 if (per_cpu(cpu_l2c_id, cpu1) == BAD_APICID) 522 return match_smt(c, o); 523 524 /* Do not match if L2 cache id does not match: */ 525 if (per_cpu(cpu_l2c_id, cpu1) != per_cpu(cpu_l2c_id, cpu2)) 526 return false; 527 528 return topology_sane(c, o, "l2c"); 529 } 530 531 /* 532 * Unlike the other levels, we do not enforce keeping a 533 * multicore group inside a NUMA node. If this happens, we will 534 * discard the MC level of the topology later. 535 */ 536 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 537 { 538 if (c->phys_proc_id == o->phys_proc_id) 539 return true; 540 return false; 541 } 542 543 /* 544 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs. 545 * 546 * Any Intel CPU that has multiple nodes per package and does not 547 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology. 548 * 549 * When in SNC mode, these CPUs enumerate an LLC that is shared 550 * by multiple NUMA nodes. The LLC is shared for off-package data 551 * access but private to the NUMA node (half of the package) for 552 * on-package access. CPUID (the source of the information about 553 * the LLC) can only enumerate the cache as shared or unshared, 554 * but not this particular configuration. 555 */ 556 557 static const struct x86_cpu_id intel_cod_cpu[] = { 558 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */ 559 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */ 560 X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */ 561 {} 562 }; 563 564 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 565 { 566 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu); 567 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 568 bool intel_snc = id && id->driver_data; 569 570 /* Do not match if we do not have a valid APICID for cpu: */ 571 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID) 572 return false; 573 574 /* Do not match if LLC id does not match: */ 575 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2)) 576 return false; 577 578 /* 579 * Allow the SNC topology without warning. Return of false 580 * means 'c' does not share the LLC of 'o'. This will be 581 * reflected to userspace. 582 */ 583 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc) 584 return false; 585 586 return topology_sane(c, o, "llc"); 587 } 588 589 590 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_CLUSTER) || defined(CONFIG_SCHED_MC) 591 static inline int x86_sched_itmt_flags(void) 592 { 593 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 594 } 595 596 #ifdef CONFIG_SCHED_MC 597 static int x86_core_flags(void) 598 { 599 return cpu_core_flags() | x86_sched_itmt_flags(); 600 } 601 #endif 602 #ifdef CONFIG_SCHED_SMT 603 static int x86_smt_flags(void) 604 { 605 return cpu_smt_flags() | x86_sched_itmt_flags(); 606 } 607 #endif 608 #ifdef CONFIG_SCHED_CLUSTER 609 static int x86_cluster_flags(void) 610 { 611 return cpu_cluster_flags() | x86_sched_itmt_flags(); 612 } 613 #endif 614 #endif 615 616 static struct sched_domain_topology_level x86_numa_in_package_topology[] = { 617 #ifdef CONFIG_SCHED_SMT 618 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 619 #endif 620 #ifdef CONFIG_SCHED_CLUSTER 621 { cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) }, 622 #endif 623 #ifdef CONFIG_SCHED_MC 624 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 625 #endif 626 { NULL, }, 627 }; 628 629 static struct sched_domain_topology_level x86_hybrid_topology[] = { 630 #ifdef CONFIG_SCHED_SMT 631 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 632 #endif 633 #ifdef CONFIG_SCHED_MC 634 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 635 #endif 636 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 637 { NULL, }, 638 }; 639 640 static struct sched_domain_topology_level x86_topology[] = { 641 #ifdef CONFIG_SCHED_SMT 642 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 643 #endif 644 #ifdef CONFIG_SCHED_CLUSTER 645 { cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) }, 646 #endif 647 #ifdef CONFIG_SCHED_MC 648 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 649 #endif 650 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 651 { NULL, }, 652 }; 653 654 /* 655 * Set if a package/die has multiple NUMA nodes inside. 656 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel 657 * Sub-NUMA Clustering have this. 658 */ 659 static bool x86_has_numa_in_package; 660 661 void set_cpu_sibling_map(int cpu) 662 { 663 bool has_smt = smp_num_siblings > 1; 664 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 665 struct cpuinfo_x86 *c = &cpu_data(cpu); 666 struct cpuinfo_x86 *o; 667 int i, threads; 668 669 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 670 671 if (!has_mp) { 672 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 673 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 674 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu)); 675 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 676 cpumask_set_cpu(cpu, topology_die_cpumask(cpu)); 677 c->booted_cores = 1; 678 return; 679 } 680 681 for_each_cpu(i, cpu_sibling_setup_mask) { 682 o = &cpu_data(i); 683 684 if (match_pkg(c, o) && !topology_same_node(c, o)) 685 x86_has_numa_in_package = true; 686 687 if ((i == cpu) || (has_smt && match_smt(c, o))) 688 link_mask(topology_sibling_cpumask, cpu, i); 689 690 if ((i == cpu) || (has_mp && match_llc(c, o))) 691 link_mask(cpu_llc_shared_mask, cpu, i); 692 693 if ((i == cpu) || (has_mp && match_l2c(c, o))) 694 link_mask(cpu_l2c_shared_mask, cpu, i); 695 696 if ((i == cpu) || (has_mp && match_die(c, o))) 697 link_mask(topology_die_cpumask, cpu, i); 698 } 699 700 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 701 if (threads > __max_smt_threads) 702 __max_smt_threads = threads; 703 704 for_each_cpu(i, topology_sibling_cpumask(cpu)) 705 cpu_data(i).smt_active = threads > 1; 706 707 /* 708 * This needs a separate iteration over the cpus because we rely on all 709 * topology_sibling_cpumask links to be set-up. 710 */ 711 for_each_cpu(i, cpu_sibling_setup_mask) { 712 o = &cpu_data(i); 713 714 if ((i == cpu) || (has_mp && match_pkg(c, o))) { 715 link_mask(topology_core_cpumask, cpu, i); 716 717 /* 718 * Does this new cpu bringup a new core? 719 */ 720 if (threads == 1) { 721 /* 722 * for each core in package, increment 723 * the booted_cores for this new cpu 724 */ 725 if (cpumask_first( 726 topology_sibling_cpumask(i)) == i) 727 c->booted_cores++; 728 /* 729 * increment the core count for all 730 * the other cpus in this package 731 */ 732 if (i != cpu) 733 cpu_data(i).booted_cores++; 734 } else if (i != cpu && !c->booted_cores) 735 c->booted_cores = cpu_data(i).booted_cores; 736 } 737 } 738 } 739 740 /* maps the cpu to the sched domain representing multi-core */ 741 const struct cpumask *cpu_coregroup_mask(int cpu) 742 { 743 return cpu_llc_shared_mask(cpu); 744 } 745 746 const struct cpumask *cpu_clustergroup_mask(int cpu) 747 { 748 return cpu_l2c_shared_mask(cpu); 749 } 750 751 static void impress_friends(void) 752 { 753 int cpu; 754 unsigned long bogosum = 0; 755 /* 756 * Allow the user to impress friends. 757 */ 758 pr_debug("Before bogomips\n"); 759 for_each_online_cpu(cpu) 760 bogosum += cpu_data(cpu).loops_per_jiffy; 761 762 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 763 num_online_cpus(), 764 bogosum/(500000/HZ), 765 (bogosum/(5000/HZ))%100); 766 767 pr_debug("Before bogocount - setting activated=1\n"); 768 } 769 770 void __inquire_remote_apic(int apicid) 771 { 772 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 773 const char * const names[] = { "ID", "VERSION", "SPIV" }; 774 int timeout; 775 u32 status; 776 777 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 778 779 for (i = 0; i < ARRAY_SIZE(regs); i++) { 780 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 781 782 /* 783 * Wait for idle. 784 */ 785 status = safe_apic_wait_icr_idle(); 786 if (status) 787 pr_cont("a previous APIC delivery may have failed\n"); 788 789 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 790 791 timeout = 0; 792 do { 793 udelay(100); 794 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 795 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 796 797 switch (status) { 798 case APIC_ICR_RR_VALID: 799 status = apic_read(APIC_RRR); 800 pr_cont("%08x\n", status); 801 break; 802 default: 803 pr_cont("failed\n"); 804 } 805 } 806 } 807 808 /* 809 * The Multiprocessor Specification 1.4 (1997) example code suggests 810 * that there should be a 10ms delay between the BSP asserting INIT 811 * and de-asserting INIT, when starting a remote processor. 812 * But that slows boot and resume on modern processors, which include 813 * many cores and don't require that delay. 814 * 815 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 816 * Modern processor families are quirked to remove the delay entirely. 817 */ 818 #define UDELAY_10MS_DEFAULT 10000 819 820 static unsigned int init_udelay = UINT_MAX; 821 822 static int __init cpu_init_udelay(char *str) 823 { 824 get_option(&str, &init_udelay); 825 826 return 0; 827 } 828 early_param("cpu_init_udelay", cpu_init_udelay); 829 830 static void __init smp_quirk_init_udelay(void) 831 { 832 /* if cmdline changed it from default, leave it alone */ 833 if (init_udelay != UINT_MAX) 834 return; 835 836 /* if modern processor, use no delay */ 837 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 838 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || 839 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 840 init_udelay = 0; 841 return; 842 } 843 /* else, use legacy delay */ 844 init_udelay = UDELAY_10MS_DEFAULT; 845 } 846 847 /* 848 * Wake up AP by INIT, INIT, STARTUP sequence. 849 */ 850 static void send_init_sequence(int phys_apicid) 851 { 852 int maxlvt = lapic_get_maxlvt(); 853 854 /* Be paranoid about clearing APIC errors. */ 855 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 856 /* Due to the Pentium erratum 3AP. */ 857 if (maxlvt > 3) 858 apic_write(APIC_ESR, 0); 859 apic_read(APIC_ESR); 860 } 861 862 /* Assert INIT on the target CPU */ 863 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, phys_apicid); 864 safe_apic_wait_icr_idle(); 865 866 udelay(init_udelay); 867 868 /* Deassert INIT on the target CPU */ 869 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 870 safe_apic_wait_icr_idle(); 871 } 872 873 /* 874 * Wake up AP by INIT, INIT, STARTUP sequence. 875 */ 876 static int wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 877 { 878 unsigned long send_status = 0, accept_status = 0; 879 int num_starts, j, maxlvt; 880 881 preempt_disable(); 882 maxlvt = lapic_get_maxlvt(); 883 send_init_sequence(phys_apicid); 884 885 mb(); 886 887 /* 888 * Should we send STARTUP IPIs ? 889 * 890 * Determine this based on the APIC version. 891 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 892 */ 893 if (APIC_INTEGRATED(boot_cpu_apic_version)) 894 num_starts = 2; 895 else 896 num_starts = 0; 897 898 /* 899 * Run STARTUP IPI loop. 900 */ 901 pr_debug("#startup loops: %d\n", num_starts); 902 903 for (j = 1; j <= num_starts; j++) { 904 pr_debug("Sending STARTUP #%d\n", j); 905 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 906 apic_write(APIC_ESR, 0); 907 apic_read(APIC_ESR); 908 pr_debug("After apic_write\n"); 909 910 /* 911 * STARTUP IPI 912 */ 913 914 /* Target chip */ 915 /* Boot on the stack */ 916 /* Kick the second */ 917 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 918 phys_apicid); 919 920 /* 921 * Give the other CPU some time to accept the IPI. 922 */ 923 if (init_udelay == 0) 924 udelay(10); 925 else 926 udelay(300); 927 928 pr_debug("Startup point 1\n"); 929 930 pr_debug("Waiting for send to finish...\n"); 931 send_status = safe_apic_wait_icr_idle(); 932 933 /* 934 * Give the other CPU some time to accept the IPI. 935 */ 936 if (init_udelay == 0) 937 udelay(10); 938 else 939 udelay(200); 940 941 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 942 apic_write(APIC_ESR, 0); 943 accept_status = (apic_read(APIC_ESR) & 0xEF); 944 if (send_status || accept_status) 945 break; 946 } 947 pr_debug("After Startup\n"); 948 949 if (send_status) 950 pr_err("APIC never delivered???\n"); 951 if (accept_status) 952 pr_err("APIC delivery error (%lx)\n", accept_status); 953 954 preempt_enable(); 955 return (send_status | accept_status); 956 } 957 958 /* reduce the number of lines printed when booting a large cpu count system */ 959 static void announce_cpu(int cpu, int apicid) 960 { 961 static int width, node_width, first = 1; 962 static int current_node = NUMA_NO_NODE; 963 int node = early_cpu_to_node(cpu); 964 965 if (!width) 966 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 967 968 if (!node_width) 969 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 970 971 if (system_state < SYSTEM_RUNNING) { 972 if (first) 973 pr_info("x86: Booting SMP configuration:\n"); 974 975 if (node != current_node) { 976 if (current_node > (-1)) 977 pr_cont("\n"); 978 current_node = node; 979 980 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 981 node_width - num_digits(node), " ", node); 982 } 983 984 /* Add padding for the BSP */ 985 if (first) 986 pr_cont("%*s", width + 1, " "); 987 first = 0; 988 989 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 990 } else 991 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 992 node, cpu, apicid); 993 } 994 995 int common_cpu_up(unsigned int cpu, struct task_struct *idle) 996 { 997 int ret; 998 999 /* Just in case we booted with a single CPU. */ 1000 alternatives_enable_smp(); 1001 1002 per_cpu(pcpu_hot.current_task, cpu) = idle; 1003 cpu_init_stack_canary(cpu, idle); 1004 1005 /* Initialize the interrupt stack(s) */ 1006 ret = irq_init_percpu_irqstack(cpu); 1007 if (ret) 1008 return ret; 1009 1010 #ifdef CONFIG_X86_32 1011 /* Stack for startup_32 can be just as for start_secondary onwards */ 1012 per_cpu(pcpu_hot.top_of_stack, cpu) = task_top_of_stack(idle); 1013 #endif 1014 return 0; 1015 } 1016 1017 /* 1018 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 1019 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 1020 * Returns zero if startup was successfully sent, else error code from 1021 * ->wakeup_secondary_cpu. 1022 */ 1023 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) 1024 { 1025 unsigned long start_ip = real_mode_header->trampoline_start; 1026 int ret; 1027 1028 #ifdef CONFIG_X86_64 1029 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */ 1030 if (apic->wakeup_secondary_cpu_64) 1031 start_ip = real_mode_header->trampoline_start64; 1032 #endif 1033 idle->thread.sp = (unsigned long)task_pt_regs(idle); 1034 initial_code = (unsigned long)start_secondary; 1035 1036 if (IS_ENABLED(CONFIG_X86_32)) { 1037 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 1038 initial_stack = idle->thread.sp; 1039 } else if (!(smpboot_control & STARTUP_PARALLEL_MASK)) { 1040 smpboot_control = cpu; 1041 } 1042 1043 /* Enable the espfix hack for this CPU */ 1044 init_espfix_ap(cpu); 1045 1046 /* So we see what's up */ 1047 announce_cpu(cpu, apicid); 1048 1049 /* 1050 * This grunge runs the startup process for 1051 * the targeted processor. 1052 */ 1053 if (x86_platform.legacy.warm_reset) { 1054 1055 pr_debug("Setting warm reset code and vector.\n"); 1056 1057 smpboot_setup_warm_reset_vector(start_ip); 1058 /* 1059 * Be paranoid about clearing APIC errors. 1060 */ 1061 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 1062 apic_write(APIC_ESR, 0); 1063 apic_read(APIC_ESR); 1064 } 1065 } 1066 1067 smp_mb(); 1068 1069 /* 1070 * Wake up a CPU in difference cases: 1071 * - Use a method from the APIC driver if one defined, with wakeup 1072 * straight to 64-bit mode preferred over wakeup to RM. 1073 * Otherwise, 1074 * - Use an INIT boot APIC message 1075 */ 1076 if (apic->wakeup_secondary_cpu_64) 1077 ret = apic->wakeup_secondary_cpu_64(apicid, start_ip); 1078 else if (apic->wakeup_secondary_cpu) 1079 ret = apic->wakeup_secondary_cpu(apicid, start_ip); 1080 else 1081 ret = wakeup_secondary_cpu_via_init(apicid, start_ip); 1082 1083 /* If the wakeup mechanism failed, cleanup the warm reset vector */ 1084 if (ret) 1085 arch_cpuhp_cleanup_kick_cpu(cpu); 1086 return ret; 1087 } 1088 1089 int native_kick_ap(unsigned int cpu, struct task_struct *tidle) 1090 { 1091 int apicid = apic->cpu_present_to_apicid(cpu); 1092 int err; 1093 1094 lockdep_assert_irqs_enabled(); 1095 1096 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1097 1098 if (apicid == BAD_APICID || 1099 !physid_isset(apicid, phys_cpu_present_map) || 1100 !apic->apic_id_valid(apicid)) { 1101 pr_err("%s: bad cpu %d\n", __func__, cpu); 1102 return -EINVAL; 1103 } 1104 1105 /* 1106 * Save current MTRR state in case it was changed since early boot 1107 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1108 */ 1109 mtrr_save_state(); 1110 1111 /* the FPU context is blank, nobody can own it */ 1112 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1113 1114 err = common_cpu_up(cpu, tidle); 1115 if (err) 1116 return err; 1117 1118 err = do_boot_cpu(apicid, cpu, tidle); 1119 if (err) 1120 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1121 1122 return err; 1123 } 1124 1125 int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *tidle) 1126 { 1127 return smp_ops.kick_ap_alive(cpu, tidle); 1128 } 1129 1130 void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu) 1131 { 1132 /* Cleanup possible dangling ends... */ 1133 if (smp_ops.kick_ap_alive == native_kick_ap && x86_platform.legacy.warm_reset) 1134 smpboot_restore_warm_reset_vector(); 1135 } 1136 1137 void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu) 1138 { 1139 if (smp_ops.cleanup_dead_cpu) 1140 smp_ops.cleanup_dead_cpu(cpu); 1141 1142 if (system_state == SYSTEM_RUNNING) 1143 pr_info("CPU %u is now offline\n", cpu); 1144 } 1145 1146 void arch_cpuhp_sync_state_poll(void) 1147 { 1148 if (smp_ops.poll_sync_state) 1149 smp_ops.poll_sync_state(); 1150 } 1151 1152 /** 1153 * arch_disable_smp_support() - Disables SMP support for x86 at boottime 1154 */ 1155 void __init arch_disable_smp_support(void) 1156 { 1157 disable_ioapic_support(); 1158 } 1159 1160 /* 1161 * Fall back to non SMP mode after errors. 1162 * 1163 * RED-PEN audit/test this more. I bet there is more state messed up here. 1164 */ 1165 static __init void disable_smp(void) 1166 { 1167 pr_info("SMP disabled\n"); 1168 1169 disable_ioapic_support(); 1170 1171 init_cpu_present(cpumask_of(0)); 1172 init_cpu_possible(cpumask_of(0)); 1173 1174 if (smp_found_config) 1175 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1176 else 1177 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1178 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1179 cpumask_set_cpu(0, topology_core_cpumask(0)); 1180 cpumask_set_cpu(0, topology_die_cpumask(0)); 1181 } 1182 1183 /* 1184 * Various sanity checks. 1185 */ 1186 static void __init smp_sanity_check(void) 1187 { 1188 preempt_disable(); 1189 1190 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1191 if (def_to_bigsmp && nr_cpu_ids > 8) { 1192 unsigned int cpu; 1193 unsigned nr; 1194 1195 pr_warn("More than 8 CPUs detected - skipping them\n" 1196 "Use CONFIG_X86_BIGSMP\n"); 1197 1198 nr = 0; 1199 for_each_present_cpu(cpu) { 1200 if (nr >= 8) 1201 set_cpu_present(cpu, false); 1202 nr++; 1203 } 1204 1205 nr = 0; 1206 for_each_possible_cpu(cpu) { 1207 if (nr >= 8) 1208 set_cpu_possible(cpu, false); 1209 nr++; 1210 } 1211 1212 set_nr_cpu_ids(8); 1213 } 1214 #endif 1215 1216 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1217 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1218 hard_smp_processor_id()); 1219 1220 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1221 } 1222 1223 /* 1224 * Should not be necessary because the MP table should list the boot 1225 * CPU too, but we do it for the sake of robustness anyway. 1226 */ 1227 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1228 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1229 boot_cpu_physical_apicid); 1230 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1231 } 1232 preempt_enable(); 1233 } 1234 1235 static void __init smp_cpu_index_default(void) 1236 { 1237 int i; 1238 struct cpuinfo_x86 *c; 1239 1240 for_each_possible_cpu(i) { 1241 c = &cpu_data(i); 1242 /* mark all to hotplug */ 1243 c->cpu_index = nr_cpu_ids; 1244 } 1245 } 1246 1247 void __init smp_prepare_cpus_common(void) 1248 { 1249 unsigned int i; 1250 1251 smp_cpu_index_default(); 1252 1253 /* 1254 * Setup boot CPU information 1255 */ 1256 smp_store_boot_cpu_info(); /* Final full version of the data */ 1257 mb(); 1258 1259 for_each_possible_cpu(i) { 1260 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1261 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1262 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL); 1263 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1264 zalloc_cpumask_var(&per_cpu(cpu_l2c_shared_map, i), GFP_KERNEL); 1265 } 1266 1267 /* 1268 * Set 'default' x86 topology, this matches default_topology() in that 1269 * it has NUMA nodes as a topology level. See also 1270 * native_smp_cpus_done(). 1271 * 1272 * Must be done before set_cpus_sibling_map() is ran. 1273 */ 1274 set_sched_topology(x86_topology); 1275 1276 set_cpu_sibling_map(0); 1277 } 1278 1279 #ifdef CONFIG_X86_64 1280 /* Establish whether parallel bringup can be supported. */ 1281 bool __init arch_cpuhp_init_parallel_bringup(void) 1282 { 1283 if (!x86_cpuinit.parallel_bringup) { 1284 pr_info("Parallel CPU startup disabled by the platform\n"); 1285 return false; 1286 } 1287 1288 smpboot_control = STARTUP_READ_APICID; 1289 pr_debug("Parallel CPU startup enabled: 0x%08x\n", smpboot_control); 1290 return true; 1291 } 1292 #endif 1293 1294 /* 1295 * Prepare for SMP bootup. 1296 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1297 * for common interface support. 1298 */ 1299 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1300 { 1301 smp_prepare_cpus_common(); 1302 1303 smp_sanity_check(); 1304 1305 switch (apic_intr_mode) { 1306 case APIC_PIC: 1307 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1308 disable_smp(); 1309 return; 1310 case APIC_SYMMETRIC_IO_NO_ROUTING: 1311 disable_smp(); 1312 /* Setup local timer */ 1313 x86_init.timers.setup_percpu_clockev(); 1314 return; 1315 case APIC_VIRTUAL_WIRE: 1316 case APIC_SYMMETRIC_IO: 1317 break; 1318 } 1319 1320 /* Setup local timer */ 1321 x86_init.timers.setup_percpu_clockev(); 1322 1323 pr_info("CPU0: "); 1324 print_cpu_info(&cpu_data(0)); 1325 1326 uv_system_init(); 1327 1328 smp_quirk_init_udelay(); 1329 1330 speculative_store_bypass_ht_init(); 1331 1332 snp_set_wakeup_secondary_cpu(); 1333 } 1334 1335 void arch_thaw_secondary_cpus_begin(void) 1336 { 1337 set_cache_aps_delayed_init(true); 1338 } 1339 1340 void arch_thaw_secondary_cpus_end(void) 1341 { 1342 cache_aps_init(); 1343 } 1344 1345 bool smp_park_other_cpus_in_init(void) 1346 { 1347 unsigned int cpu, this_cpu = smp_processor_id(); 1348 unsigned int apicid; 1349 1350 if (apic->wakeup_secondary_cpu_64 || apic->wakeup_secondary_cpu) 1351 return false; 1352 1353 for_each_present_cpu(cpu) { 1354 if (cpu == this_cpu) 1355 continue; 1356 apicid = apic->cpu_present_to_apicid(cpu); 1357 if (apicid == BAD_APICID) 1358 continue; 1359 send_init_sequence(apicid); 1360 } 1361 return true; 1362 } 1363 1364 /* 1365 * Early setup to make printk work. 1366 */ 1367 void __init native_smp_prepare_boot_cpu(void) 1368 { 1369 int me = smp_processor_id(); 1370 1371 /* SMP handles this from setup_per_cpu_areas() */ 1372 if (!IS_ENABLED(CONFIG_SMP)) 1373 switch_gdt_and_percpu_base(me); 1374 1375 native_pv_lock_init(); 1376 } 1377 1378 void __init calculate_max_logical_packages(void) 1379 { 1380 int ncpus; 1381 1382 /* 1383 * Today neither Intel nor AMD support heterogeneous systems so 1384 * extrapolate the boot cpu's data to all packages. 1385 */ 1386 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); 1387 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); 1388 pr_info("Max logical packages: %u\n", __max_logical_packages); 1389 } 1390 1391 void __init native_smp_cpus_done(unsigned int max_cpus) 1392 { 1393 pr_debug("Boot done\n"); 1394 1395 calculate_max_logical_packages(); 1396 1397 /* XXX for now assume numa-in-package and hybrid don't overlap */ 1398 if (x86_has_numa_in_package) 1399 set_sched_topology(x86_numa_in_package_topology); 1400 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) 1401 set_sched_topology(x86_hybrid_topology); 1402 1403 nmi_selftest(); 1404 impress_friends(); 1405 cache_aps_init(); 1406 } 1407 1408 static int __initdata setup_possible_cpus = -1; 1409 static int __init _setup_possible_cpus(char *str) 1410 { 1411 get_option(&str, &setup_possible_cpus); 1412 return 0; 1413 } 1414 early_param("possible_cpus", _setup_possible_cpus); 1415 1416 1417 /* 1418 * cpu_possible_mask should be static, it cannot change as cpu's 1419 * are onlined, or offlined. The reason is per-cpu data-structures 1420 * are allocated by some modules at init time, and don't expect to 1421 * do this dynamically on cpu arrival/departure. 1422 * cpu_present_mask on the other hand can change dynamically. 1423 * In case when cpu_hotplug is not compiled, then we resort to current 1424 * behaviour, which is cpu_possible == cpu_present. 1425 * - Ashok Raj 1426 * 1427 * Three ways to find out the number of additional hotplug CPUs: 1428 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1429 * - The user can overwrite it with possible_cpus=NUM 1430 * - Otherwise don't reserve additional CPUs. 1431 * We do this because additional CPUs waste a lot of memory. 1432 * -AK 1433 */ 1434 __init void prefill_possible_map(void) 1435 { 1436 int i, possible; 1437 1438 /* No boot processor was found in mptable or ACPI MADT */ 1439 if (!num_processors) { 1440 if (boot_cpu_has(X86_FEATURE_APIC)) { 1441 int apicid = boot_cpu_physical_apicid; 1442 int cpu = hard_smp_processor_id(); 1443 1444 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); 1445 1446 /* Make sure boot cpu is enumerated */ 1447 if (apic->cpu_present_to_apicid(0) == BAD_APICID && 1448 apic->apic_id_valid(apicid)) 1449 generic_processor_info(apicid, boot_cpu_apic_version); 1450 } 1451 1452 if (!num_processors) 1453 num_processors = 1; 1454 } 1455 1456 i = setup_max_cpus ?: 1; 1457 if (setup_possible_cpus == -1) { 1458 possible = num_processors; 1459 #ifdef CONFIG_HOTPLUG_CPU 1460 if (setup_max_cpus) 1461 possible += disabled_cpus; 1462 #else 1463 if (possible > i) 1464 possible = i; 1465 #endif 1466 } else 1467 possible = setup_possible_cpus; 1468 1469 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1470 1471 /* nr_cpu_ids could be reduced via nr_cpus= */ 1472 if (possible > nr_cpu_ids) { 1473 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", 1474 possible, nr_cpu_ids); 1475 possible = nr_cpu_ids; 1476 } 1477 1478 #ifdef CONFIG_HOTPLUG_CPU 1479 if (!setup_max_cpus) 1480 #endif 1481 if (possible > i) { 1482 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1483 possible, setup_max_cpus); 1484 possible = i; 1485 } 1486 1487 set_nr_cpu_ids(possible); 1488 1489 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1490 possible, max_t(int, possible - num_processors, 0)); 1491 1492 reset_cpu_possible_mask(); 1493 1494 for (i = 0; i < possible; i++) 1495 set_cpu_possible(i, true); 1496 } 1497 1498 /* correctly size the local cpu masks */ 1499 void __init setup_cpu_local_masks(void) 1500 { 1501 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 1502 } 1503 1504 #ifdef CONFIG_HOTPLUG_CPU 1505 1506 /* Recompute SMT state for all CPUs on offline */ 1507 static void recompute_smt_state(void) 1508 { 1509 int max_threads, cpu; 1510 1511 max_threads = 0; 1512 for_each_online_cpu (cpu) { 1513 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1514 1515 if (threads > max_threads) 1516 max_threads = threads; 1517 } 1518 __max_smt_threads = max_threads; 1519 } 1520 1521 static void remove_siblinginfo(int cpu) 1522 { 1523 int sibling; 1524 struct cpuinfo_x86 *c = &cpu_data(cpu); 1525 1526 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1527 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1528 /*/ 1529 * last thread sibling in this cpu core going down 1530 */ 1531 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1532 cpu_data(sibling).booted_cores--; 1533 } 1534 1535 for_each_cpu(sibling, topology_die_cpumask(cpu)) 1536 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling)); 1537 1538 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) { 1539 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1540 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1) 1541 cpu_data(sibling).smt_active = false; 1542 } 1543 1544 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1545 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1546 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu)) 1547 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling)); 1548 cpumask_clear(cpu_llc_shared_mask(cpu)); 1549 cpumask_clear(cpu_l2c_shared_mask(cpu)); 1550 cpumask_clear(topology_sibling_cpumask(cpu)); 1551 cpumask_clear(topology_core_cpumask(cpu)); 1552 cpumask_clear(topology_die_cpumask(cpu)); 1553 c->cpu_core_id = 0; 1554 c->booted_cores = 0; 1555 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1556 recompute_smt_state(); 1557 } 1558 1559 static void remove_cpu_from_maps(int cpu) 1560 { 1561 set_cpu_online(cpu, false); 1562 numa_remove_cpu(cpu); 1563 } 1564 1565 void cpu_disable_common(void) 1566 { 1567 int cpu = smp_processor_id(); 1568 1569 remove_siblinginfo(cpu); 1570 1571 /* It's now safe to remove this processor from the online map */ 1572 lock_vector_lock(); 1573 remove_cpu_from_maps(cpu); 1574 unlock_vector_lock(); 1575 fixup_irqs(); 1576 lapic_offline(); 1577 } 1578 1579 int native_cpu_disable(void) 1580 { 1581 int ret; 1582 1583 ret = lapic_can_unplug_cpu(); 1584 if (ret) 1585 return ret; 1586 1587 cpu_disable_common(); 1588 1589 /* 1590 * Disable the local APIC. Otherwise IPI broadcasts will reach 1591 * it. It still responds normally to INIT, NMI, SMI, and SIPI 1592 * messages. 1593 * 1594 * Disabling the APIC must happen after cpu_disable_common() 1595 * which invokes fixup_irqs(). 1596 * 1597 * Disabling the APIC preserves already set bits in IRR, but 1598 * an interrupt arriving after disabling the local APIC does not 1599 * set the corresponding IRR bit. 1600 * 1601 * fixup_irqs() scans IRR for set bits so it can raise a not 1602 * yet handled interrupt on the new destination CPU via an IPI 1603 * but obviously it can't do so for IRR bits which are not set. 1604 * IOW, interrupts arriving after disabling the local APIC will 1605 * be lost. 1606 */ 1607 apic_soft_disable(); 1608 1609 return 0; 1610 } 1611 1612 void play_dead_common(void) 1613 { 1614 idle_task_exit(); 1615 1616 cpuhp_ap_report_dead(); 1617 /* 1618 * With physical CPU hotplug, we should halt the cpu 1619 */ 1620 local_irq_disable(); 1621 } 1622 1623 /* 1624 * We need to flush the caches before going to sleep, lest we have 1625 * dirty data in our caches when we come back up. 1626 */ 1627 static inline void mwait_play_dead(void) 1628 { 1629 struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead); 1630 unsigned int eax, ebx, ecx, edx; 1631 unsigned int highest_cstate = 0; 1632 unsigned int highest_subcstate = 0; 1633 int i; 1634 1635 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1636 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 1637 return; 1638 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1639 return; 1640 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1641 return; 1642 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1643 return; 1644 1645 eax = CPUID_MWAIT_LEAF; 1646 ecx = 0; 1647 native_cpuid(&eax, &ebx, &ecx, &edx); 1648 1649 /* 1650 * eax will be 0 if EDX enumeration is not valid. 1651 * Initialized below to cstate, sub_cstate value when EDX is valid. 1652 */ 1653 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1654 eax = 0; 1655 } else { 1656 edx >>= MWAIT_SUBSTATE_SIZE; 1657 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1658 if (edx & MWAIT_SUBSTATE_MASK) { 1659 highest_cstate = i; 1660 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1661 } 1662 } 1663 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1664 (highest_subcstate - 1); 1665 } 1666 1667 /* Set up state for the kexec() hack below */ 1668 md->status = CPUDEAD_MWAIT_WAIT; 1669 md->control = CPUDEAD_MWAIT_WAIT; 1670 1671 wbinvd(); 1672 1673 while (1) { 1674 /* 1675 * The CLFLUSH is a workaround for erratum AAI65 for 1676 * the Xeon 7400 series. It's not clear it is actually 1677 * needed, but it should be harmless in either case. 1678 * The WBINVD is insufficient due to the spurious-wakeup 1679 * case where we return around the loop. 1680 */ 1681 mb(); 1682 clflush(md); 1683 mb(); 1684 __monitor(md, 0, 0); 1685 mb(); 1686 __mwait(eax, 0); 1687 1688 if (READ_ONCE(md->control) == CPUDEAD_MWAIT_KEXEC_HLT) { 1689 /* 1690 * Kexec is about to happen. Don't go back into mwait() as 1691 * the kexec kernel might overwrite text and data including 1692 * page tables and stack. So mwait() would resume when the 1693 * monitor cache line is written to and then the CPU goes 1694 * south due to overwritten text, page tables and stack. 1695 * 1696 * Note: This does _NOT_ protect against a stray MCE, NMI, 1697 * SMI. They will resume execution at the instruction 1698 * following the HLT instruction and run into the problem 1699 * which this is trying to prevent. 1700 */ 1701 WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT); 1702 while(1) 1703 native_halt(); 1704 } 1705 } 1706 } 1707 1708 /* 1709 * Kick all "offline" CPUs out of mwait on kexec(). See comment in 1710 * mwait_play_dead(). 1711 */ 1712 void smp_kick_mwait_play_dead(void) 1713 { 1714 u32 newstate = CPUDEAD_MWAIT_KEXEC_HLT; 1715 struct mwait_cpu_dead *md; 1716 unsigned int cpu, i; 1717 1718 for_each_cpu_andnot(cpu, cpu_present_mask, cpu_online_mask) { 1719 md = per_cpu_ptr(&mwait_cpu_dead, cpu); 1720 1721 /* Does it sit in mwait_play_dead() ? */ 1722 if (READ_ONCE(md->status) != CPUDEAD_MWAIT_WAIT) 1723 continue; 1724 1725 /* Wait up to 5ms */ 1726 for (i = 0; READ_ONCE(md->status) != newstate && i < 1000; i++) { 1727 /* Bring it out of mwait */ 1728 WRITE_ONCE(md->control, newstate); 1729 udelay(5); 1730 } 1731 1732 if (READ_ONCE(md->status) != newstate) 1733 pr_err_once("CPU%u is stuck in mwait_play_dead()\n", cpu); 1734 } 1735 } 1736 1737 void __noreturn hlt_play_dead(void) 1738 { 1739 if (__this_cpu_read(cpu_info.x86) >= 4) 1740 wbinvd(); 1741 1742 while (1) 1743 native_halt(); 1744 } 1745 1746 void native_play_dead(void) 1747 { 1748 play_dead_common(); 1749 tboot_shutdown(TB_SHUTDOWN_WFS); 1750 1751 mwait_play_dead(); 1752 if (cpuidle_play_dead()) 1753 hlt_play_dead(); 1754 } 1755 1756 #else /* ... !CONFIG_HOTPLUG_CPU */ 1757 int native_cpu_disable(void) 1758 { 1759 return -ENOSYS; 1760 } 1761 1762 void native_play_dead(void) 1763 { 1764 BUG(); 1765 } 1766 1767 #endif 1768