1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * x86 SMP booting functions 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 7 * Copyright 2001 Andi Kleen, SuSE Labs. 8 * 9 * Much of the core SMP work is based on previous work by Thomas Radke, to 10 * whom a great many thanks are extended. 11 * 12 * Thanks to Intel for making available several different Pentium, 13 * Pentium Pro and Pentium-II/Xeon MP machines. 14 * Original development of Linux SMP code supported by Caldera. 15 * 16 * Fixes 17 * Felix Koop : NR_CPUS used properly 18 * Jose Renau : Handle single CPU case. 19 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 20 * Greg Wright : Fix for kernel stacks panic. 21 * Erich Boleyn : MP v1.4 and additional changes. 22 * Matthias Sattler : Changes for 2.1 kernel map. 23 * Michel Lespinasse : Changes for 2.1 kernel map. 24 * Michael Chastain : Change trampoline.S to gnu as. 25 * Alan Cox : Dumb bug: 'B' step PPro's are fine 26 * Ingo Molnar : Added APIC timers, based on code 27 * from Jose Renau 28 * Ingo Molnar : various cleanups and rewrites 29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 31 * Andi Kleen : Changed for SMP boot into long mode. 32 * Martin J. Bligh : Added support for multi-quad systems 33 * Dave Jones : Report invalid combinations of Athlon CPUs. 34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 35 * Andi Kleen : Converted to new state machine. 36 * Ashok Raj : CPU hotplug support 37 * Glauber Costa : i386 and x86_64 integration 38 */ 39 40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/export.h> 45 #include <linux/sched.h> 46 #include <linux/sched/topology.h> 47 #include <linux/sched/hotplug.h> 48 #include <linux/sched/task_stack.h> 49 #include <linux/percpu.h> 50 #include <linux/memblock.h> 51 #include <linux/err.h> 52 #include <linux/nmi.h> 53 #include <linux/tboot.h> 54 #include <linux/stackprotector.h> 55 #include <linux/gfp.h> 56 #include <linux/cpuidle.h> 57 #include <linux/numa.h> 58 #include <linux/pgtable.h> 59 60 #include <asm/acpi.h> 61 #include <asm/desc.h> 62 #include <asm/nmi.h> 63 #include <asm/irq.h> 64 #include <asm/realmode.h> 65 #include <asm/cpu.h> 66 #include <asm/numa.h> 67 #include <asm/tlbflush.h> 68 #include <asm/mtrr.h> 69 #include <asm/mwait.h> 70 #include <asm/apic.h> 71 #include <asm/io_apic.h> 72 #include <asm/fpu/internal.h> 73 #include <asm/setup.h> 74 #include <asm/uv/uv.h> 75 #include <linux/mc146818rtc.h> 76 #include <asm/i8259.h> 77 #include <asm/misc.h> 78 #include <asm/qspinlock.h> 79 #include <asm/intel-family.h> 80 #include <asm/cpu_device_id.h> 81 #include <asm/spec-ctrl.h> 82 #include <asm/hw_irq.h> 83 84 /* representing HT siblings of each logical CPU */ 85 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 86 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 87 88 /* representing HT and core siblings of each logical CPU */ 89 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 90 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 91 92 /* representing HT, core, and die siblings of each logical CPU */ 93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); 94 EXPORT_PER_CPU_SYMBOL(cpu_die_map); 95 96 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); 97 98 /* Per CPU bogomips and other parameters */ 99 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 100 EXPORT_PER_CPU_SYMBOL(cpu_info); 101 102 /* Logical package management. We might want to allocate that dynamically */ 103 unsigned int __max_logical_packages __read_mostly; 104 EXPORT_SYMBOL(__max_logical_packages); 105 static unsigned int logical_packages __read_mostly; 106 static unsigned int logical_die __read_mostly; 107 108 /* Maximum number of SMT threads on any online core */ 109 int __read_mostly __max_smt_threads = 1; 110 111 /* Flag to indicate if a complete sched domain rebuild is required */ 112 bool x86_topology_update; 113 114 int arch_update_cpu_topology(void) 115 { 116 int retval = x86_topology_update; 117 118 x86_topology_update = false; 119 return retval; 120 } 121 122 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 123 { 124 unsigned long flags; 125 126 spin_lock_irqsave(&rtc_lock, flags); 127 CMOS_WRITE(0xa, 0xf); 128 spin_unlock_irqrestore(&rtc_lock, flags); 129 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = 130 start_eip >> 4; 131 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 132 start_eip & 0xf; 133 } 134 135 static inline void smpboot_restore_warm_reset_vector(void) 136 { 137 unsigned long flags; 138 139 /* 140 * Paranoid: Set warm reset code and vector here back 141 * to default values. 142 */ 143 spin_lock_irqsave(&rtc_lock, flags); 144 CMOS_WRITE(0, 0xf); 145 spin_unlock_irqrestore(&rtc_lock, flags); 146 147 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 148 } 149 150 static void init_freq_invariance(bool secondary); 151 152 /* 153 * Report back to the Boot Processor during boot time or to the caller processor 154 * during CPU online. 155 */ 156 static void smp_callin(void) 157 { 158 int cpuid; 159 160 /* 161 * If waken up by an INIT in an 82489DX configuration 162 * cpu_callout_mask guarantees we don't get here before 163 * an INIT_deassert IPI reaches our local APIC, so it is 164 * now safe to touch our local APIC. 165 */ 166 cpuid = smp_processor_id(); 167 168 /* 169 * the boot CPU has finished the init stage and is spinning 170 * on callin_map until we finish. We are free to set up this 171 * CPU, first the APIC. (this is probably redundant on most 172 * boards) 173 */ 174 apic_ap_setup(); 175 176 /* 177 * Save our processor parameters. Note: this information 178 * is needed for clock calibration. 179 */ 180 smp_store_cpu_info(cpuid); 181 182 /* 183 * The topology information must be up to date before 184 * calibrate_delay() and notify_cpu_starting(). 185 */ 186 set_cpu_sibling_map(raw_smp_processor_id()); 187 188 init_freq_invariance(true); 189 190 /* 191 * Get our bogomips. 192 * Update loops_per_jiffy in cpu_data. Previous call to 193 * smp_store_cpu_info() stored a value that is close but not as 194 * accurate as the value just calculated. 195 */ 196 calibrate_delay(); 197 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 198 pr_debug("Stack at about %p\n", &cpuid); 199 200 wmb(); 201 202 notify_cpu_starting(cpuid); 203 204 /* 205 * Allow the master to continue. 206 */ 207 cpumask_set_cpu(cpuid, cpu_callin_mask); 208 } 209 210 static int cpu0_logical_apicid; 211 static int enable_start_cpu0; 212 /* 213 * Activate a secondary processor. 214 */ 215 static void notrace start_secondary(void *unused) 216 { 217 /* 218 * Don't put *anything* except direct CPU state initialization 219 * before cpu_init(), SMP booting is too fragile that we want to 220 * limit the things done here to the most necessary things. 221 */ 222 cr4_init(); 223 224 #ifdef CONFIG_X86_32 225 /* switch away from the initial page table */ 226 load_cr3(swapper_pg_dir); 227 __flush_tlb_all(); 228 #endif 229 load_current_idt(); 230 cpu_init(); 231 x86_cpuinit.early_percpu_clock_init(); 232 preempt_disable(); 233 smp_callin(); 234 235 enable_start_cpu0 = 0; 236 237 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 238 barrier(); 239 /* 240 * Check TSC synchronization with the boot CPU: 241 */ 242 check_tsc_sync_target(); 243 244 speculative_store_bypass_ht_init(); 245 246 /* 247 * Lock vector_lock, set CPU online and bring the vector 248 * allocator online. Online must be set with vector_lock held 249 * to prevent a concurrent irq setup/teardown from seeing a 250 * half valid vector space. 251 */ 252 lock_vector_lock(); 253 set_cpu_online(smp_processor_id(), true); 254 lapic_online(); 255 unlock_vector_lock(); 256 cpu_set_state_online(smp_processor_id()); 257 x86_platform.nmi_init(); 258 259 /* enable local interrupts */ 260 local_irq_enable(); 261 262 /* to prevent fake stack check failure in clock setup */ 263 boot_init_stack_canary(); 264 265 x86_cpuinit.setup_percpu_clockev(); 266 267 wmb(); 268 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 269 270 /* 271 * Prevent tail call to cpu_startup_entry() because the stack protector 272 * guard has been changed a couple of function calls up, in 273 * boot_init_stack_canary() and must not be checked before tail calling 274 * another function. 275 */ 276 prevent_tail_call_optimization(); 277 } 278 279 /** 280 * topology_is_primary_thread - Check whether CPU is the primary SMT thread 281 * @cpu: CPU to check 282 */ 283 bool topology_is_primary_thread(unsigned int cpu) 284 { 285 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu)); 286 } 287 288 /** 289 * topology_smt_supported - Check whether SMT is supported by the CPUs 290 */ 291 bool topology_smt_supported(void) 292 { 293 return smp_num_siblings > 1; 294 } 295 296 /** 297 * topology_phys_to_logical_pkg - Map a physical package id to a logical 298 * 299 * Returns logical package id or -1 if not found 300 */ 301 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 302 { 303 int cpu; 304 305 for_each_possible_cpu(cpu) { 306 struct cpuinfo_x86 *c = &cpu_data(cpu); 307 308 if (c->initialized && c->phys_proc_id == phys_pkg) 309 return c->logical_proc_id; 310 } 311 return -1; 312 } 313 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 314 /** 315 * topology_phys_to_logical_die - Map a physical die id to logical 316 * 317 * Returns logical die id or -1 if not found 318 */ 319 int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu) 320 { 321 int cpu; 322 int proc_id = cpu_data(cur_cpu).phys_proc_id; 323 324 for_each_possible_cpu(cpu) { 325 struct cpuinfo_x86 *c = &cpu_data(cpu); 326 327 if (c->initialized && c->cpu_die_id == die_id && 328 c->phys_proc_id == proc_id) 329 return c->logical_die_id; 330 } 331 return -1; 332 } 333 EXPORT_SYMBOL(topology_phys_to_logical_die); 334 335 /** 336 * topology_update_package_map - Update the physical to logical package map 337 * @pkg: The physical package id as retrieved via CPUID 338 * @cpu: The cpu for which this is updated 339 */ 340 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 341 { 342 int new; 343 344 /* Already available somewhere? */ 345 new = topology_phys_to_logical_pkg(pkg); 346 if (new >= 0) 347 goto found; 348 349 new = logical_packages++; 350 if (new != pkg) { 351 pr_info("CPU %u Converting physical %u to logical package %u\n", 352 cpu, pkg, new); 353 } 354 found: 355 cpu_data(cpu).logical_proc_id = new; 356 return 0; 357 } 358 /** 359 * topology_update_die_map - Update the physical to logical die map 360 * @die: The die id as retrieved via CPUID 361 * @cpu: The cpu for which this is updated 362 */ 363 int topology_update_die_map(unsigned int die, unsigned int cpu) 364 { 365 int new; 366 367 /* Already available somewhere? */ 368 new = topology_phys_to_logical_die(die, cpu); 369 if (new >= 0) 370 goto found; 371 372 new = logical_die++; 373 if (new != die) { 374 pr_info("CPU %u Converting physical %u to logical die %u\n", 375 cpu, die, new); 376 } 377 found: 378 cpu_data(cpu).logical_die_id = new; 379 return 0; 380 } 381 382 void __init smp_store_boot_cpu_info(void) 383 { 384 int id = 0; /* CPU 0 */ 385 struct cpuinfo_x86 *c = &cpu_data(id); 386 387 *c = boot_cpu_data; 388 c->cpu_index = id; 389 topology_update_package_map(c->phys_proc_id, id); 390 topology_update_die_map(c->cpu_die_id, id); 391 c->initialized = true; 392 } 393 394 /* 395 * The bootstrap kernel entry code has set these up. Save them for 396 * a given CPU 397 */ 398 void smp_store_cpu_info(int id) 399 { 400 struct cpuinfo_x86 *c = &cpu_data(id); 401 402 /* Copy boot_cpu_data only on the first bringup */ 403 if (!c->initialized) 404 *c = boot_cpu_data; 405 c->cpu_index = id; 406 /* 407 * During boot time, CPU0 has this setup already. Save the info when 408 * bringing up AP or offlined CPU0. 409 */ 410 identify_secondary_cpu(c); 411 c->initialized = true; 412 } 413 414 static bool 415 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 416 { 417 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 418 419 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 420 } 421 422 static bool 423 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 424 { 425 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 426 427 return !WARN_ONCE(!topology_same_node(c, o), 428 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 429 "[node: %d != %d]. Ignoring dependency.\n", 430 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 431 } 432 433 #define link_mask(mfunc, c1, c2) \ 434 do { \ 435 cpumask_set_cpu((c1), mfunc(c2)); \ 436 cpumask_set_cpu((c2), mfunc(c1)); \ 437 } while (0) 438 439 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 440 { 441 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 442 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 443 444 if (c->phys_proc_id == o->phys_proc_id && 445 c->cpu_die_id == o->cpu_die_id && 446 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { 447 if (c->cpu_core_id == o->cpu_core_id) 448 return topology_sane(c, o, "smt"); 449 450 if ((c->cu_id != 0xff) && 451 (o->cu_id != 0xff) && 452 (c->cu_id == o->cu_id)) 453 return topology_sane(c, o, "smt"); 454 } 455 456 } else if (c->phys_proc_id == o->phys_proc_id && 457 c->cpu_die_id == o->cpu_die_id && 458 c->cpu_core_id == o->cpu_core_id) { 459 return topology_sane(c, o, "smt"); 460 } 461 462 return false; 463 } 464 465 /* 466 * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs. 467 * 468 * These are Intel CPUs that enumerate an LLC that is shared by 469 * multiple NUMA nodes. The LLC on these systems is shared for 470 * off-package data access but private to the NUMA node (half 471 * of the package) for on-package access. 472 * 473 * CPUID (the source of the information about the LLC) can only 474 * enumerate the cache as being shared *or* unshared, but not 475 * this particular configuration. The CPU in this case enumerates 476 * the cache to be shared across the entire package (spanning both 477 * NUMA nodes). 478 */ 479 480 static const struct x86_cpu_id snc_cpu[] = { 481 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, NULL), 482 {} 483 }; 484 485 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 486 { 487 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 488 489 /* Do not match if we do not have a valid APICID for cpu: */ 490 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID) 491 return false; 492 493 /* Do not match if LLC id does not match: */ 494 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2)) 495 return false; 496 497 /* 498 * Allow the SNC topology without warning. Return of false 499 * means 'c' does not share the LLC of 'o'. This will be 500 * reflected to userspace. 501 */ 502 if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu)) 503 return false; 504 505 return topology_sane(c, o, "llc"); 506 } 507 508 /* 509 * Unlike the other levels, we do not enforce keeping a 510 * multicore group inside a NUMA node. If this happens, we will 511 * discard the MC level of the topology later. 512 */ 513 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 514 { 515 if (c->phys_proc_id == o->phys_proc_id) 516 return true; 517 return false; 518 } 519 520 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 521 { 522 if ((c->phys_proc_id == o->phys_proc_id) && 523 (c->cpu_die_id == o->cpu_die_id)) 524 return true; 525 return false; 526 } 527 528 529 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC) 530 static inline int x86_sched_itmt_flags(void) 531 { 532 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 533 } 534 535 #ifdef CONFIG_SCHED_MC 536 static int x86_core_flags(void) 537 { 538 return cpu_core_flags() | x86_sched_itmt_flags(); 539 } 540 #endif 541 #ifdef CONFIG_SCHED_SMT 542 static int x86_smt_flags(void) 543 { 544 return cpu_smt_flags() | x86_sched_itmt_flags(); 545 } 546 #endif 547 #endif 548 549 static struct sched_domain_topology_level x86_numa_in_package_topology[] = { 550 #ifdef CONFIG_SCHED_SMT 551 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 552 #endif 553 #ifdef CONFIG_SCHED_MC 554 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 555 #endif 556 { NULL, }, 557 }; 558 559 static struct sched_domain_topology_level x86_topology[] = { 560 #ifdef CONFIG_SCHED_SMT 561 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 562 #endif 563 #ifdef CONFIG_SCHED_MC 564 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 565 #endif 566 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 567 { NULL, }, 568 }; 569 570 /* 571 * Set if a package/die has multiple NUMA nodes inside. 572 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel 573 * Sub-NUMA Clustering have this. 574 */ 575 static bool x86_has_numa_in_package; 576 577 void set_cpu_sibling_map(int cpu) 578 { 579 bool has_smt = smp_num_siblings > 1; 580 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 581 struct cpuinfo_x86 *c = &cpu_data(cpu); 582 struct cpuinfo_x86 *o; 583 int i, threads; 584 585 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 586 587 if (!has_mp) { 588 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 589 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 590 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 591 cpumask_set_cpu(cpu, topology_die_cpumask(cpu)); 592 c->booted_cores = 1; 593 return; 594 } 595 596 for_each_cpu(i, cpu_sibling_setup_mask) { 597 o = &cpu_data(i); 598 599 if ((i == cpu) || (has_smt && match_smt(c, o))) 600 link_mask(topology_sibling_cpumask, cpu, i); 601 602 if ((i == cpu) || (has_mp && match_llc(c, o))) 603 link_mask(cpu_llc_shared_mask, cpu, i); 604 605 } 606 607 /* 608 * This needs a separate iteration over the cpus because we rely on all 609 * topology_sibling_cpumask links to be set-up. 610 */ 611 for_each_cpu(i, cpu_sibling_setup_mask) { 612 o = &cpu_data(i); 613 614 if ((i == cpu) || (has_mp && match_pkg(c, o))) { 615 link_mask(topology_core_cpumask, cpu, i); 616 617 /* 618 * Does this new cpu bringup a new core? 619 */ 620 if (cpumask_weight( 621 topology_sibling_cpumask(cpu)) == 1) { 622 /* 623 * for each core in package, increment 624 * the booted_cores for this new cpu 625 */ 626 if (cpumask_first( 627 topology_sibling_cpumask(i)) == i) 628 c->booted_cores++; 629 /* 630 * increment the core count for all 631 * the other cpus in this package 632 */ 633 if (i != cpu) 634 cpu_data(i).booted_cores++; 635 } else if (i != cpu && !c->booted_cores) 636 c->booted_cores = cpu_data(i).booted_cores; 637 } 638 if (match_pkg(c, o) && !topology_same_node(c, o)) 639 x86_has_numa_in_package = true; 640 641 if ((i == cpu) || (has_mp && match_die(c, o))) 642 link_mask(topology_die_cpumask, cpu, i); 643 } 644 645 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 646 if (threads > __max_smt_threads) 647 __max_smt_threads = threads; 648 } 649 650 /* maps the cpu to the sched domain representing multi-core */ 651 const struct cpumask *cpu_coregroup_mask(int cpu) 652 { 653 return cpu_llc_shared_mask(cpu); 654 } 655 656 static void impress_friends(void) 657 { 658 int cpu; 659 unsigned long bogosum = 0; 660 /* 661 * Allow the user to impress friends. 662 */ 663 pr_debug("Before bogomips\n"); 664 for_each_possible_cpu(cpu) 665 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 666 bogosum += cpu_data(cpu).loops_per_jiffy; 667 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 668 num_online_cpus(), 669 bogosum/(500000/HZ), 670 (bogosum/(5000/HZ))%100); 671 672 pr_debug("Before bogocount - setting activated=1\n"); 673 } 674 675 void __inquire_remote_apic(int apicid) 676 { 677 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 678 const char * const names[] = { "ID", "VERSION", "SPIV" }; 679 int timeout; 680 u32 status; 681 682 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 683 684 for (i = 0; i < ARRAY_SIZE(regs); i++) { 685 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 686 687 /* 688 * Wait for idle. 689 */ 690 status = safe_apic_wait_icr_idle(); 691 if (status) 692 pr_cont("a previous APIC delivery may have failed\n"); 693 694 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 695 696 timeout = 0; 697 do { 698 udelay(100); 699 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 700 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 701 702 switch (status) { 703 case APIC_ICR_RR_VALID: 704 status = apic_read(APIC_RRR); 705 pr_cont("%08x\n", status); 706 break; 707 default: 708 pr_cont("failed\n"); 709 } 710 } 711 } 712 713 /* 714 * The Multiprocessor Specification 1.4 (1997) example code suggests 715 * that there should be a 10ms delay between the BSP asserting INIT 716 * and de-asserting INIT, when starting a remote processor. 717 * But that slows boot and resume on modern processors, which include 718 * many cores and don't require that delay. 719 * 720 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 721 * Modern processor families are quirked to remove the delay entirely. 722 */ 723 #define UDELAY_10MS_DEFAULT 10000 724 725 static unsigned int init_udelay = UINT_MAX; 726 727 static int __init cpu_init_udelay(char *str) 728 { 729 get_option(&str, &init_udelay); 730 731 return 0; 732 } 733 early_param("cpu_init_udelay", cpu_init_udelay); 734 735 static void __init smp_quirk_init_udelay(void) 736 { 737 /* if cmdline changed it from default, leave it alone */ 738 if (init_udelay != UINT_MAX) 739 return; 740 741 /* if modern processor, use no delay */ 742 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 743 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || 744 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 745 init_udelay = 0; 746 return; 747 } 748 /* else, use legacy delay */ 749 init_udelay = UDELAY_10MS_DEFAULT; 750 } 751 752 /* 753 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 754 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 755 * won't ... remember to clear down the APIC, etc later. 756 */ 757 int 758 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 759 { 760 unsigned long send_status, accept_status = 0; 761 int maxlvt; 762 763 /* Target chip */ 764 /* Boot on the stack */ 765 /* Kick the second */ 766 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); 767 768 pr_debug("Waiting for send to finish...\n"); 769 send_status = safe_apic_wait_icr_idle(); 770 771 /* 772 * Give the other CPU some time to accept the IPI. 773 */ 774 udelay(200); 775 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 776 maxlvt = lapic_get_maxlvt(); 777 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 778 apic_write(APIC_ESR, 0); 779 accept_status = (apic_read(APIC_ESR) & 0xEF); 780 } 781 pr_debug("NMI sent\n"); 782 783 if (send_status) 784 pr_err("APIC never delivered???\n"); 785 if (accept_status) 786 pr_err("APIC delivery error (%lx)\n", accept_status); 787 788 return (send_status | accept_status); 789 } 790 791 static int 792 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 793 { 794 unsigned long send_status = 0, accept_status = 0; 795 int maxlvt, num_starts, j; 796 797 maxlvt = lapic_get_maxlvt(); 798 799 /* 800 * Be paranoid about clearing APIC errors. 801 */ 802 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 803 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 804 apic_write(APIC_ESR, 0); 805 apic_read(APIC_ESR); 806 } 807 808 pr_debug("Asserting INIT\n"); 809 810 /* 811 * Turn INIT on target chip 812 */ 813 /* 814 * Send IPI 815 */ 816 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 817 phys_apicid); 818 819 pr_debug("Waiting for send to finish...\n"); 820 send_status = safe_apic_wait_icr_idle(); 821 822 udelay(init_udelay); 823 824 pr_debug("Deasserting INIT\n"); 825 826 /* Target chip */ 827 /* Send IPI */ 828 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 829 830 pr_debug("Waiting for send to finish...\n"); 831 send_status = safe_apic_wait_icr_idle(); 832 833 mb(); 834 835 /* 836 * Should we send STARTUP IPIs ? 837 * 838 * Determine this based on the APIC version. 839 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 840 */ 841 if (APIC_INTEGRATED(boot_cpu_apic_version)) 842 num_starts = 2; 843 else 844 num_starts = 0; 845 846 /* 847 * Run STARTUP IPI loop. 848 */ 849 pr_debug("#startup loops: %d\n", num_starts); 850 851 for (j = 1; j <= num_starts; j++) { 852 pr_debug("Sending STARTUP #%d\n", j); 853 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 854 apic_write(APIC_ESR, 0); 855 apic_read(APIC_ESR); 856 pr_debug("After apic_write\n"); 857 858 /* 859 * STARTUP IPI 860 */ 861 862 /* Target chip */ 863 /* Boot on the stack */ 864 /* Kick the second */ 865 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 866 phys_apicid); 867 868 /* 869 * Give the other CPU some time to accept the IPI. 870 */ 871 if (init_udelay == 0) 872 udelay(10); 873 else 874 udelay(300); 875 876 pr_debug("Startup point 1\n"); 877 878 pr_debug("Waiting for send to finish...\n"); 879 send_status = safe_apic_wait_icr_idle(); 880 881 /* 882 * Give the other CPU some time to accept the IPI. 883 */ 884 if (init_udelay == 0) 885 udelay(10); 886 else 887 udelay(200); 888 889 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 890 apic_write(APIC_ESR, 0); 891 accept_status = (apic_read(APIC_ESR) & 0xEF); 892 if (send_status || accept_status) 893 break; 894 } 895 pr_debug("After Startup\n"); 896 897 if (send_status) 898 pr_err("APIC never delivered???\n"); 899 if (accept_status) 900 pr_err("APIC delivery error (%lx)\n", accept_status); 901 902 return (send_status | accept_status); 903 } 904 905 /* reduce the number of lines printed when booting a large cpu count system */ 906 static void announce_cpu(int cpu, int apicid) 907 { 908 static int current_node = NUMA_NO_NODE; 909 int node = early_cpu_to_node(cpu); 910 static int width, node_width; 911 912 if (!width) 913 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 914 915 if (!node_width) 916 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 917 918 if (cpu == 1) 919 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 920 921 if (system_state < SYSTEM_RUNNING) { 922 if (node != current_node) { 923 if (current_node > (-1)) 924 pr_cont("\n"); 925 current_node = node; 926 927 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 928 node_width - num_digits(node), " ", node); 929 } 930 931 /* Add padding for the BSP */ 932 if (cpu == 1) 933 pr_cont("%*s", width + 1, " "); 934 935 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 936 937 } else 938 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 939 node, cpu, apicid); 940 } 941 942 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 943 { 944 int cpu; 945 946 cpu = smp_processor_id(); 947 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 948 return NMI_HANDLED; 949 950 return NMI_DONE; 951 } 952 953 /* 954 * Wake up AP by INIT, INIT, STARTUP sequence. 955 * 956 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 957 * boot-strap code which is not a desired behavior for waking up BSP. To 958 * void the boot-strap code, wake up CPU0 by NMI instead. 959 * 960 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 961 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 962 * We'll change this code in the future to wake up hard offlined CPU0 if 963 * real platform and request are available. 964 */ 965 static int 966 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 967 int *cpu0_nmi_registered) 968 { 969 int id; 970 int boot_error; 971 972 preempt_disable(); 973 974 /* 975 * Wake up AP by INIT, INIT, STARTUP sequence. 976 */ 977 if (cpu) { 978 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 979 goto out; 980 } 981 982 /* 983 * Wake up BSP by nmi. 984 * 985 * Register a NMI handler to help wake up CPU0. 986 */ 987 boot_error = register_nmi_handler(NMI_LOCAL, 988 wakeup_cpu0_nmi, 0, "wake_cpu0"); 989 990 if (!boot_error) { 991 enable_start_cpu0 = 1; 992 *cpu0_nmi_registered = 1; 993 if (apic->dest_logical == APIC_DEST_LOGICAL) 994 id = cpu0_logical_apicid; 995 else 996 id = apicid; 997 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 998 } 999 1000 out: 1001 preempt_enable(); 1002 1003 return boot_error; 1004 } 1005 1006 int common_cpu_up(unsigned int cpu, struct task_struct *idle) 1007 { 1008 int ret; 1009 1010 /* Just in case we booted with a single CPU. */ 1011 alternatives_enable_smp(); 1012 1013 per_cpu(current_task, cpu) = idle; 1014 1015 /* Initialize the interrupt stack(s) */ 1016 ret = irq_init_percpu_irqstack(cpu); 1017 if (ret) 1018 return ret; 1019 1020 #ifdef CONFIG_X86_32 1021 /* Stack for startup_32 can be just as for start_secondary onwards */ 1022 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle); 1023 #else 1024 initial_gs = per_cpu_offset(cpu); 1025 #endif 1026 return 0; 1027 } 1028 1029 /* 1030 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 1031 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 1032 * Returns zero if CPU booted OK, else error code from 1033 * ->wakeup_secondary_cpu. 1034 */ 1035 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle, 1036 int *cpu0_nmi_registered) 1037 { 1038 /* start_ip had better be page-aligned! */ 1039 unsigned long start_ip = real_mode_header->trampoline_start; 1040 1041 unsigned long boot_error = 0; 1042 unsigned long timeout; 1043 1044 idle->thread.sp = (unsigned long)task_pt_regs(idle); 1045 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 1046 initial_code = (unsigned long)start_secondary; 1047 initial_stack = idle->thread.sp; 1048 1049 /* Enable the espfix hack for this CPU */ 1050 init_espfix_ap(cpu); 1051 1052 /* So we see what's up */ 1053 announce_cpu(cpu, apicid); 1054 1055 /* 1056 * This grunge runs the startup process for 1057 * the targeted processor. 1058 */ 1059 1060 if (x86_platform.legacy.warm_reset) { 1061 1062 pr_debug("Setting warm reset code and vector.\n"); 1063 1064 smpboot_setup_warm_reset_vector(start_ip); 1065 /* 1066 * Be paranoid about clearing APIC errors. 1067 */ 1068 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 1069 apic_write(APIC_ESR, 0); 1070 apic_read(APIC_ESR); 1071 } 1072 } 1073 1074 /* 1075 * AP might wait on cpu_callout_mask in cpu_init() with 1076 * cpu_initialized_mask set if previous attempt to online 1077 * it timed-out. Clear cpu_initialized_mask so that after 1078 * INIT/SIPI it could start with a clean state. 1079 */ 1080 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1081 smp_mb(); 1082 1083 /* 1084 * Wake up a CPU in difference cases: 1085 * - Use the method in the APIC driver if it's defined 1086 * Otherwise, 1087 * - Use an INIT boot APIC message for APs or NMI for BSP. 1088 */ 1089 if (apic->wakeup_secondary_cpu) 1090 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 1091 else 1092 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 1093 cpu0_nmi_registered); 1094 1095 if (!boot_error) { 1096 /* 1097 * Wait 10s total for first sign of life from AP 1098 */ 1099 boot_error = -1; 1100 timeout = jiffies + 10*HZ; 1101 while (time_before(jiffies, timeout)) { 1102 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 1103 /* 1104 * Tell AP to proceed with initialization 1105 */ 1106 cpumask_set_cpu(cpu, cpu_callout_mask); 1107 boot_error = 0; 1108 break; 1109 } 1110 schedule(); 1111 } 1112 } 1113 1114 if (!boot_error) { 1115 /* 1116 * Wait till AP completes initial initialization 1117 */ 1118 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 1119 /* 1120 * Allow other tasks to run while we wait for the 1121 * AP to come online. This also gives a chance 1122 * for the MTRR work(triggered by the AP coming online) 1123 * to be completed in the stop machine context. 1124 */ 1125 schedule(); 1126 } 1127 } 1128 1129 if (x86_platform.legacy.warm_reset) { 1130 /* 1131 * Cleanup possible dangling ends... 1132 */ 1133 smpboot_restore_warm_reset_vector(); 1134 } 1135 1136 return boot_error; 1137 } 1138 1139 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 1140 { 1141 int apicid = apic->cpu_present_to_apicid(cpu); 1142 int cpu0_nmi_registered = 0; 1143 unsigned long flags; 1144 int err, ret = 0; 1145 1146 lockdep_assert_irqs_enabled(); 1147 1148 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1149 1150 if (apicid == BAD_APICID || 1151 !physid_isset(apicid, phys_cpu_present_map) || 1152 !apic->apic_id_valid(apicid)) { 1153 pr_err("%s: bad cpu %d\n", __func__, cpu); 1154 return -EINVAL; 1155 } 1156 1157 /* 1158 * Already booted CPU? 1159 */ 1160 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 1161 pr_debug("do_boot_cpu %d Already started\n", cpu); 1162 return -ENOSYS; 1163 } 1164 1165 /* 1166 * Save current MTRR state in case it was changed since early boot 1167 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1168 */ 1169 mtrr_save_state(); 1170 1171 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 1172 err = cpu_check_up_prepare(cpu); 1173 if (err && err != -EBUSY) 1174 return err; 1175 1176 /* the FPU context is blank, nobody can own it */ 1177 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1178 1179 err = common_cpu_up(cpu, tidle); 1180 if (err) 1181 return err; 1182 1183 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered); 1184 if (err) { 1185 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1186 ret = -EIO; 1187 goto unreg_nmi; 1188 } 1189 1190 /* 1191 * Check TSC synchronization with the AP (keep irqs disabled 1192 * while doing so): 1193 */ 1194 local_irq_save(flags); 1195 check_tsc_sync_source(cpu); 1196 local_irq_restore(flags); 1197 1198 while (!cpu_online(cpu)) { 1199 cpu_relax(); 1200 touch_nmi_watchdog(); 1201 } 1202 1203 unreg_nmi: 1204 /* 1205 * Clean up the nmi handler. Do this after the callin and callout sync 1206 * to avoid impact of possible long unregister time. 1207 */ 1208 if (cpu0_nmi_registered) 1209 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 1210 1211 return ret; 1212 } 1213 1214 /** 1215 * arch_disable_smp_support() - disables SMP support for x86 at runtime 1216 */ 1217 void arch_disable_smp_support(void) 1218 { 1219 disable_ioapic_support(); 1220 } 1221 1222 /* 1223 * Fall back to non SMP mode after errors. 1224 * 1225 * RED-PEN audit/test this more. I bet there is more state messed up here. 1226 */ 1227 static __init void disable_smp(void) 1228 { 1229 pr_info("SMP disabled\n"); 1230 1231 disable_ioapic_support(); 1232 1233 init_cpu_present(cpumask_of(0)); 1234 init_cpu_possible(cpumask_of(0)); 1235 1236 if (smp_found_config) 1237 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1238 else 1239 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1240 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1241 cpumask_set_cpu(0, topology_core_cpumask(0)); 1242 cpumask_set_cpu(0, topology_die_cpumask(0)); 1243 } 1244 1245 /* 1246 * Various sanity checks. 1247 */ 1248 static void __init smp_sanity_check(void) 1249 { 1250 preempt_disable(); 1251 1252 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1253 if (def_to_bigsmp && nr_cpu_ids > 8) { 1254 unsigned int cpu; 1255 unsigned nr; 1256 1257 pr_warn("More than 8 CPUs detected - skipping them\n" 1258 "Use CONFIG_X86_BIGSMP\n"); 1259 1260 nr = 0; 1261 for_each_present_cpu(cpu) { 1262 if (nr >= 8) 1263 set_cpu_present(cpu, false); 1264 nr++; 1265 } 1266 1267 nr = 0; 1268 for_each_possible_cpu(cpu) { 1269 if (nr >= 8) 1270 set_cpu_possible(cpu, false); 1271 nr++; 1272 } 1273 1274 nr_cpu_ids = 8; 1275 } 1276 #endif 1277 1278 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1279 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1280 hard_smp_processor_id()); 1281 1282 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1283 } 1284 1285 /* 1286 * Should not be necessary because the MP table should list the boot 1287 * CPU too, but we do it for the sake of robustness anyway. 1288 */ 1289 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1290 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1291 boot_cpu_physical_apicid); 1292 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1293 } 1294 preempt_enable(); 1295 } 1296 1297 static void __init smp_cpu_index_default(void) 1298 { 1299 int i; 1300 struct cpuinfo_x86 *c; 1301 1302 for_each_possible_cpu(i) { 1303 c = &cpu_data(i); 1304 /* mark all to hotplug */ 1305 c->cpu_index = nr_cpu_ids; 1306 } 1307 } 1308 1309 static void __init smp_get_logical_apicid(void) 1310 { 1311 if (x2apic_mode) 1312 cpu0_logical_apicid = apic_read(APIC_LDR); 1313 else 1314 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1315 } 1316 1317 /* 1318 * Prepare for SMP bootup. 1319 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1320 * for common interface support. 1321 */ 1322 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1323 { 1324 unsigned int i; 1325 1326 smp_cpu_index_default(); 1327 1328 /* 1329 * Setup boot CPU information 1330 */ 1331 smp_store_boot_cpu_info(); /* Final full version of the data */ 1332 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1333 mb(); 1334 1335 for_each_possible_cpu(i) { 1336 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1337 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1338 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL); 1339 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1340 } 1341 1342 /* 1343 * Set 'default' x86 topology, this matches default_topology() in that 1344 * it has NUMA nodes as a topology level. See also 1345 * native_smp_cpus_done(). 1346 * 1347 * Must be done before set_cpus_sibling_map() is ran. 1348 */ 1349 set_sched_topology(x86_topology); 1350 1351 set_cpu_sibling_map(0); 1352 init_freq_invariance(false); 1353 smp_sanity_check(); 1354 1355 switch (apic_intr_mode) { 1356 case APIC_PIC: 1357 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1358 disable_smp(); 1359 return; 1360 case APIC_SYMMETRIC_IO_NO_ROUTING: 1361 disable_smp(); 1362 /* Setup local timer */ 1363 x86_init.timers.setup_percpu_clockev(); 1364 return; 1365 case APIC_VIRTUAL_WIRE: 1366 case APIC_SYMMETRIC_IO: 1367 break; 1368 } 1369 1370 /* Setup local timer */ 1371 x86_init.timers.setup_percpu_clockev(); 1372 1373 smp_get_logical_apicid(); 1374 1375 pr_info("CPU0: "); 1376 print_cpu_info(&cpu_data(0)); 1377 1378 uv_system_init(); 1379 1380 set_mtrr_aps_delayed_init(); 1381 1382 smp_quirk_init_udelay(); 1383 1384 speculative_store_bypass_ht_init(); 1385 } 1386 1387 void arch_thaw_secondary_cpus_begin(void) 1388 { 1389 set_mtrr_aps_delayed_init(); 1390 } 1391 1392 void arch_thaw_secondary_cpus_end(void) 1393 { 1394 mtrr_aps_init(); 1395 } 1396 1397 /* 1398 * Early setup to make printk work. 1399 */ 1400 void __init native_smp_prepare_boot_cpu(void) 1401 { 1402 int me = smp_processor_id(); 1403 switch_to_new_gdt(me); 1404 /* already set me in cpu_online_mask in boot_cpu_init() */ 1405 cpumask_set_cpu(me, cpu_callout_mask); 1406 cpu_set_state_online(me); 1407 native_pv_lock_init(); 1408 } 1409 1410 void __init calculate_max_logical_packages(void) 1411 { 1412 int ncpus; 1413 1414 /* 1415 * Today neither Intel nor AMD support heterogenous systems so 1416 * extrapolate the boot cpu's data to all packages. 1417 */ 1418 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); 1419 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); 1420 pr_info("Max logical packages: %u\n", __max_logical_packages); 1421 } 1422 1423 void __init native_smp_cpus_done(unsigned int max_cpus) 1424 { 1425 pr_debug("Boot done\n"); 1426 1427 calculate_max_logical_packages(); 1428 1429 if (x86_has_numa_in_package) 1430 set_sched_topology(x86_numa_in_package_topology); 1431 1432 nmi_selftest(); 1433 impress_friends(); 1434 mtrr_aps_init(); 1435 } 1436 1437 static int __initdata setup_possible_cpus = -1; 1438 static int __init _setup_possible_cpus(char *str) 1439 { 1440 get_option(&str, &setup_possible_cpus); 1441 return 0; 1442 } 1443 early_param("possible_cpus", _setup_possible_cpus); 1444 1445 1446 /* 1447 * cpu_possible_mask should be static, it cannot change as cpu's 1448 * are onlined, or offlined. The reason is per-cpu data-structures 1449 * are allocated by some modules at init time, and don't expect to 1450 * do this dynamically on cpu arrival/departure. 1451 * cpu_present_mask on the other hand can change dynamically. 1452 * In case when cpu_hotplug is not compiled, then we resort to current 1453 * behaviour, which is cpu_possible == cpu_present. 1454 * - Ashok Raj 1455 * 1456 * Three ways to find out the number of additional hotplug CPUs: 1457 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1458 * - The user can overwrite it with possible_cpus=NUM 1459 * - Otherwise don't reserve additional CPUs. 1460 * We do this because additional CPUs waste a lot of memory. 1461 * -AK 1462 */ 1463 __init void prefill_possible_map(void) 1464 { 1465 int i, possible; 1466 1467 /* No boot processor was found in mptable or ACPI MADT */ 1468 if (!num_processors) { 1469 if (boot_cpu_has(X86_FEATURE_APIC)) { 1470 int apicid = boot_cpu_physical_apicid; 1471 int cpu = hard_smp_processor_id(); 1472 1473 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); 1474 1475 /* Make sure boot cpu is enumerated */ 1476 if (apic->cpu_present_to_apicid(0) == BAD_APICID && 1477 apic->apic_id_valid(apicid)) 1478 generic_processor_info(apicid, boot_cpu_apic_version); 1479 } 1480 1481 if (!num_processors) 1482 num_processors = 1; 1483 } 1484 1485 i = setup_max_cpus ?: 1; 1486 if (setup_possible_cpus == -1) { 1487 possible = num_processors; 1488 #ifdef CONFIG_HOTPLUG_CPU 1489 if (setup_max_cpus) 1490 possible += disabled_cpus; 1491 #else 1492 if (possible > i) 1493 possible = i; 1494 #endif 1495 } else 1496 possible = setup_possible_cpus; 1497 1498 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1499 1500 /* nr_cpu_ids could be reduced via nr_cpus= */ 1501 if (possible > nr_cpu_ids) { 1502 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", 1503 possible, nr_cpu_ids); 1504 possible = nr_cpu_ids; 1505 } 1506 1507 #ifdef CONFIG_HOTPLUG_CPU 1508 if (!setup_max_cpus) 1509 #endif 1510 if (possible > i) { 1511 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1512 possible, setup_max_cpus); 1513 possible = i; 1514 } 1515 1516 nr_cpu_ids = possible; 1517 1518 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1519 possible, max_t(int, possible - num_processors, 0)); 1520 1521 reset_cpu_possible_mask(); 1522 1523 for (i = 0; i < possible; i++) 1524 set_cpu_possible(i, true); 1525 } 1526 1527 #ifdef CONFIG_HOTPLUG_CPU 1528 1529 /* Recompute SMT state for all CPUs on offline */ 1530 static void recompute_smt_state(void) 1531 { 1532 int max_threads, cpu; 1533 1534 max_threads = 0; 1535 for_each_online_cpu (cpu) { 1536 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1537 1538 if (threads > max_threads) 1539 max_threads = threads; 1540 } 1541 __max_smt_threads = max_threads; 1542 } 1543 1544 static void remove_siblinginfo(int cpu) 1545 { 1546 int sibling; 1547 struct cpuinfo_x86 *c = &cpu_data(cpu); 1548 1549 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1550 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1551 /*/ 1552 * last thread sibling in this cpu core going down 1553 */ 1554 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1555 cpu_data(sibling).booted_cores--; 1556 } 1557 1558 for_each_cpu(sibling, topology_die_cpumask(cpu)) 1559 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling)); 1560 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) 1561 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1562 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1563 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1564 cpumask_clear(cpu_llc_shared_mask(cpu)); 1565 cpumask_clear(topology_sibling_cpumask(cpu)); 1566 cpumask_clear(topology_core_cpumask(cpu)); 1567 cpumask_clear(topology_die_cpumask(cpu)); 1568 c->cpu_core_id = 0; 1569 c->booted_cores = 0; 1570 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1571 recompute_smt_state(); 1572 } 1573 1574 static void remove_cpu_from_maps(int cpu) 1575 { 1576 set_cpu_online(cpu, false); 1577 cpumask_clear_cpu(cpu, cpu_callout_mask); 1578 cpumask_clear_cpu(cpu, cpu_callin_mask); 1579 /* was set by cpu_init() */ 1580 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1581 numa_remove_cpu(cpu); 1582 } 1583 1584 void cpu_disable_common(void) 1585 { 1586 int cpu = smp_processor_id(); 1587 1588 remove_siblinginfo(cpu); 1589 1590 /* It's now safe to remove this processor from the online map */ 1591 lock_vector_lock(); 1592 remove_cpu_from_maps(cpu); 1593 unlock_vector_lock(); 1594 fixup_irqs(); 1595 lapic_offline(); 1596 } 1597 1598 int native_cpu_disable(void) 1599 { 1600 int ret; 1601 1602 ret = lapic_can_unplug_cpu(); 1603 if (ret) 1604 return ret; 1605 1606 /* 1607 * Disable the local APIC. Otherwise IPI broadcasts will reach 1608 * it. It still responds normally to INIT, NMI, SMI, and SIPI 1609 * messages. 1610 */ 1611 apic_soft_disable(); 1612 cpu_disable_common(); 1613 1614 return 0; 1615 } 1616 1617 int common_cpu_die(unsigned int cpu) 1618 { 1619 int ret = 0; 1620 1621 /* We don't do anything here: idle task is faking death itself. */ 1622 1623 /* They ack this in play_dead() by setting CPU_DEAD */ 1624 if (cpu_wait_death(cpu, 5)) { 1625 if (system_state == SYSTEM_RUNNING) 1626 pr_info("CPU %u is now offline\n", cpu); 1627 } else { 1628 pr_err("CPU %u didn't die...\n", cpu); 1629 ret = -1; 1630 } 1631 1632 return ret; 1633 } 1634 1635 void native_cpu_die(unsigned int cpu) 1636 { 1637 common_cpu_die(cpu); 1638 } 1639 1640 void play_dead_common(void) 1641 { 1642 idle_task_exit(); 1643 1644 /* Ack it */ 1645 (void)cpu_report_death(); 1646 1647 /* 1648 * With physical CPU hotplug, we should halt the cpu 1649 */ 1650 local_irq_disable(); 1651 } 1652 1653 static bool wakeup_cpu0(void) 1654 { 1655 if (smp_processor_id() == 0 && enable_start_cpu0) 1656 return true; 1657 1658 return false; 1659 } 1660 1661 /* 1662 * We need to flush the caches before going to sleep, lest we have 1663 * dirty data in our caches when we come back up. 1664 */ 1665 static inline void mwait_play_dead(void) 1666 { 1667 unsigned int eax, ebx, ecx, edx; 1668 unsigned int highest_cstate = 0; 1669 unsigned int highest_subcstate = 0; 1670 void *mwait_ptr; 1671 int i; 1672 1673 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1674 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 1675 return; 1676 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1677 return; 1678 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1679 return; 1680 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1681 return; 1682 1683 eax = CPUID_MWAIT_LEAF; 1684 ecx = 0; 1685 native_cpuid(&eax, &ebx, &ecx, &edx); 1686 1687 /* 1688 * eax will be 0 if EDX enumeration is not valid. 1689 * Initialized below to cstate, sub_cstate value when EDX is valid. 1690 */ 1691 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1692 eax = 0; 1693 } else { 1694 edx >>= MWAIT_SUBSTATE_SIZE; 1695 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1696 if (edx & MWAIT_SUBSTATE_MASK) { 1697 highest_cstate = i; 1698 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1699 } 1700 } 1701 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1702 (highest_subcstate - 1); 1703 } 1704 1705 /* 1706 * This should be a memory location in a cache line which is 1707 * unlikely to be touched by other processors. The actual 1708 * content is immaterial as it is not actually modified in any way. 1709 */ 1710 mwait_ptr = ¤t_thread_info()->flags; 1711 1712 wbinvd(); 1713 1714 while (1) { 1715 /* 1716 * The CLFLUSH is a workaround for erratum AAI65 for 1717 * the Xeon 7400 series. It's not clear it is actually 1718 * needed, but it should be harmless in either case. 1719 * The WBINVD is insufficient due to the spurious-wakeup 1720 * case where we return around the loop. 1721 */ 1722 mb(); 1723 clflush(mwait_ptr); 1724 mb(); 1725 __monitor(mwait_ptr, 0, 0); 1726 mb(); 1727 __mwait(eax, 0); 1728 /* 1729 * If NMI wants to wake up CPU0, start CPU0. 1730 */ 1731 if (wakeup_cpu0()) 1732 start_cpu0(); 1733 } 1734 } 1735 1736 void hlt_play_dead(void) 1737 { 1738 if (__this_cpu_read(cpu_info.x86) >= 4) 1739 wbinvd(); 1740 1741 while (1) { 1742 native_halt(); 1743 /* 1744 * If NMI wants to wake up CPU0, start CPU0. 1745 */ 1746 if (wakeup_cpu0()) 1747 start_cpu0(); 1748 } 1749 } 1750 1751 void native_play_dead(void) 1752 { 1753 play_dead_common(); 1754 tboot_shutdown(TB_SHUTDOWN_WFS); 1755 1756 mwait_play_dead(); /* Only returns on failure */ 1757 if (cpuidle_play_dead()) 1758 hlt_play_dead(); 1759 } 1760 1761 #else /* ... !CONFIG_HOTPLUG_CPU */ 1762 int native_cpu_disable(void) 1763 { 1764 return -ENOSYS; 1765 } 1766 1767 void native_cpu_die(unsigned int cpu) 1768 { 1769 /* We said "no" in __cpu_disable */ 1770 BUG(); 1771 } 1772 1773 void native_play_dead(void) 1774 { 1775 BUG(); 1776 } 1777 1778 #endif 1779 1780 /* 1781 * APERF/MPERF frequency ratio computation. 1782 * 1783 * The scheduler wants to do frequency invariant accounting and needs a <1 1784 * ratio to account for the 'current' frequency, corresponding to 1785 * freq_curr / freq_max. 1786 * 1787 * Since the frequency freq_curr on x86 is controlled by micro-controller and 1788 * our P-state setting is little more than a request/hint, we need to observe 1789 * the effective frequency 'BusyMHz', i.e. the average frequency over a time 1790 * interval after discarding idle time. This is given by: 1791 * 1792 * BusyMHz = delta_APERF / delta_MPERF * freq_base 1793 * 1794 * where freq_base is the max non-turbo P-state. 1795 * 1796 * The freq_max term has to be set to a somewhat arbitrary value, because we 1797 * can't know which turbo states will be available at a given point in time: 1798 * it all depends on the thermal headroom of the entire package. We set it to 1799 * the turbo level with 4 cores active. 1800 * 1801 * Benchmarks show that's a good compromise between the 1C turbo ratio 1802 * (freq_curr/freq_max would rarely reach 1) and something close to freq_base, 1803 * which would ignore the entire turbo range (a conspicuous part, making 1804 * freq_curr/freq_max always maxed out). 1805 * 1806 * An exception to the heuristic above is the Atom uarch, where we choose the 1807 * highest turbo level for freq_max since Atom's are generally oriented towards 1808 * power efficiency. 1809 * 1810 * Setting freq_max to anything less than the 1C turbo ratio makes the ratio 1811 * freq_curr / freq_max to eventually grow >1, in which case we clip it to 1. 1812 */ 1813 1814 DEFINE_STATIC_KEY_FALSE(arch_scale_freq_key); 1815 1816 static DEFINE_PER_CPU(u64, arch_prev_aperf); 1817 static DEFINE_PER_CPU(u64, arch_prev_mperf); 1818 static u64 arch_turbo_freq_ratio = SCHED_CAPACITY_SCALE; 1819 static u64 arch_max_freq_ratio = SCHED_CAPACITY_SCALE; 1820 1821 void arch_set_max_freq_ratio(bool turbo_disabled) 1822 { 1823 arch_max_freq_ratio = turbo_disabled ? SCHED_CAPACITY_SCALE : 1824 arch_turbo_freq_ratio; 1825 } 1826 1827 static bool turbo_disabled(void) 1828 { 1829 u64 misc_en; 1830 int err; 1831 1832 err = rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_en); 1833 if (err) 1834 return false; 1835 1836 return (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); 1837 } 1838 1839 static bool slv_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq) 1840 { 1841 int err; 1842 1843 err = rdmsrl_safe(MSR_ATOM_CORE_RATIOS, base_freq); 1844 if (err) 1845 return false; 1846 1847 err = rdmsrl_safe(MSR_ATOM_CORE_TURBO_RATIOS, turbo_freq); 1848 if (err) 1849 return false; 1850 1851 *base_freq = (*base_freq >> 16) & 0x3F; /* max P state */ 1852 *turbo_freq = *turbo_freq & 0x3F; /* 1C turbo */ 1853 1854 return true; 1855 } 1856 1857 #include <asm/cpu_device_id.h> 1858 #include <asm/intel-family.h> 1859 1860 #define X86_MATCH(model) \ 1861 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, \ 1862 INTEL_FAM6_##model, X86_FEATURE_APERFMPERF, NULL) 1863 1864 static const struct x86_cpu_id has_knl_turbo_ratio_limits[] = { 1865 X86_MATCH(XEON_PHI_KNL), 1866 X86_MATCH(XEON_PHI_KNM), 1867 {} 1868 }; 1869 1870 static const struct x86_cpu_id has_skx_turbo_ratio_limits[] = { 1871 X86_MATCH(SKYLAKE_X), 1872 {} 1873 }; 1874 1875 static const struct x86_cpu_id has_glm_turbo_ratio_limits[] = { 1876 X86_MATCH(ATOM_GOLDMONT), 1877 X86_MATCH(ATOM_GOLDMONT_D), 1878 X86_MATCH(ATOM_GOLDMONT_PLUS), 1879 {} 1880 }; 1881 1882 static bool knl_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq, 1883 int num_delta_fratio) 1884 { 1885 int fratio, delta_fratio, found; 1886 int err, i; 1887 u64 msr; 1888 1889 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); 1890 if (err) 1891 return false; 1892 1893 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */ 1894 1895 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr); 1896 if (err) 1897 return false; 1898 1899 fratio = (msr >> 8) & 0xFF; 1900 i = 16; 1901 found = 0; 1902 do { 1903 if (found >= num_delta_fratio) { 1904 *turbo_freq = fratio; 1905 return true; 1906 } 1907 1908 delta_fratio = (msr >> (i + 5)) & 0x7; 1909 1910 if (delta_fratio) { 1911 found += 1; 1912 fratio -= delta_fratio; 1913 } 1914 1915 i += 8; 1916 } while (i < 64); 1917 1918 return true; 1919 } 1920 1921 static bool skx_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq, int size) 1922 { 1923 u64 ratios, counts; 1924 u32 group_size; 1925 int err, i; 1926 1927 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); 1928 if (err) 1929 return false; 1930 1931 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */ 1932 1933 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &ratios); 1934 if (err) 1935 return false; 1936 1937 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT1, &counts); 1938 if (err) 1939 return false; 1940 1941 for (i = 0; i < 64; i += 8) { 1942 group_size = (counts >> i) & 0xFF; 1943 if (group_size >= size) { 1944 *turbo_freq = (ratios >> i) & 0xFF; 1945 return true; 1946 } 1947 } 1948 1949 return false; 1950 } 1951 1952 static bool core_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq) 1953 { 1954 u64 msr; 1955 int err; 1956 1957 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); 1958 if (err) 1959 return false; 1960 1961 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr); 1962 if (err) 1963 return false; 1964 1965 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */ 1966 *turbo_freq = (msr >> 24) & 0xFF; /* 4C turbo */ 1967 1968 /* The CPU may have less than 4 cores */ 1969 if (!*turbo_freq) 1970 *turbo_freq = msr & 0xFF; /* 1C turbo */ 1971 1972 return true; 1973 } 1974 1975 static bool intel_set_max_freq_ratio(void) 1976 { 1977 u64 base_freq, turbo_freq; 1978 1979 if (slv_set_max_freq_ratio(&base_freq, &turbo_freq)) 1980 goto out; 1981 1982 if (x86_match_cpu(has_glm_turbo_ratio_limits) && 1983 skx_set_max_freq_ratio(&base_freq, &turbo_freq, 1)) 1984 goto out; 1985 1986 if (x86_match_cpu(has_knl_turbo_ratio_limits) && 1987 knl_set_max_freq_ratio(&base_freq, &turbo_freq, 1)) 1988 goto out; 1989 1990 if (x86_match_cpu(has_skx_turbo_ratio_limits) && 1991 skx_set_max_freq_ratio(&base_freq, &turbo_freq, 4)) 1992 goto out; 1993 1994 if (core_set_max_freq_ratio(&base_freq, &turbo_freq)) 1995 goto out; 1996 1997 return false; 1998 1999 out: 2000 /* 2001 * Some hypervisors advertise X86_FEATURE_APERFMPERF 2002 * but then fill all MSR's with zeroes. 2003 */ 2004 if (!base_freq) { 2005 pr_debug("Couldn't determine cpu base frequency, necessary for scale-invariant accounting.\n"); 2006 return false; 2007 } 2008 2009 arch_turbo_freq_ratio = div_u64(turbo_freq * SCHED_CAPACITY_SCALE, 2010 base_freq); 2011 arch_set_max_freq_ratio(turbo_disabled()); 2012 return true; 2013 } 2014 2015 static void init_counter_refs(void) 2016 { 2017 u64 aperf, mperf; 2018 2019 rdmsrl(MSR_IA32_APERF, aperf); 2020 rdmsrl(MSR_IA32_MPERF, mperf); 2021 2022 this_cpu_write(arch_prev_aperf, aperf); 2023 this_cpu_write(arch_prev_mperf, mperf); 2024 } 2025 2026 static void init_freq_invariance(bool secondary) 2027 { 2028 bool ret = false; 2029 2030 if (!boot_cpu_has(X86_FEATURE_APERFMPERF)) 2031 return; 2032 2033 if (secondary) { 2034 if (static_branch_likely(&arch_scale_freq_key)) { 2035 init_counter_refs(); 2036 } 2037 return; 2038 } 2039 2040 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 2041 ret = intel_set_max_freq_ratio(); 2042 2043 if (ret) { 2044 init_counter_refs(); 2045 static_branch_enable(&arch_scale_freq_key); 2046 } else { 2047 pr_debug("Couldn't determine max cpu frequency, necessary for scale-invariant accounting.\n"); 2048 } 2049 } 2050 2051 DEFINE_PER_CPU(unsigned long, arch_freq_scale) = SCHED_CAPACITY_SCALE; 2052 2053 void arch_scale_freq_tick(void) 2054 { 2055 u64 freq_scale; 2056 u64 aperf, mperf; 2057 u64 acnt, mcnt; 2058 2059 if (!arch_scale_freq_invariant()) 2060 return; 2061 2062 rdmsrl(MSR_IA32_APERF, aperf); 2063 rdmsrl(MSR_IA32_MPERF, mperf); 2064 2065 acnt = aperf - this_cpu_read(arch_prev_aperf); 2066 mcnt = mperf - this_cpu_read(arch_prev_mperf); 2067 if (!mcnt) 2068 return; 2069 2070 this_cpu_write(arch_prev_aperf, aperf); 2071 this_cpu_write(arch_prev_mperf, mperf); 2072 2073 acnt <<= 2*SCHED_CAPACITY_SHIFT; 2074 mcnt *= arch_max_freq_ratio; 2075 2076 freq_scale = div64_u64(acnt, mcnt); 2077 2078 if (freq_scale > SCHED_CAPACITY_SCALE) 2079 freq_scale = SCHED_CAPACITY_SCALE; 2080 2081 this_cpu_write(arch_freq_scale, freq_scale); 2082 } 2083