1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> 5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/module.h> 45 #include <linux/sched.h> 46 #include <linux/percpu.h> 47 #include <linux/bootmem.h> 48 #include <linux/err.h> 49 #include <linux/nmi.h> 50 51 #include <asm/acpi.h> 52 #include <asm/desc.h> 53 #include <asm/nmi.h> 54 #include <asm/irq.h> 55 #include <asm/idle.h> 56 #include <asm/smp.h> 57 #include <asm/trampoline.h> 58 #include <asm/cpu.h> 59 #include <asm/numa.h> 60 #include <asm/pgtable.h> 61 #include <asm/tlbflush.h> 62 #include <asm/mtrr.h> 63 #include <asm/vmi.h> 64 #include <asm/genapic.h> 65 #include <linux/mc146818rtc.h> 66 67 #include <mach_apic.h> 68 #include <mach_wakecpu.h> 69 #include <smpboot_hooks.h> 70 71 #ifdef CONFIG_X86_32 72 u8 apicid_2_node[MAX_APICID]; 73 static int low_mappings; 74 #endif 75 76 /* State of each CPU */ 77 DEFINE_PER_CPU(int, cpu_state) = { 0 }; 78 79 /* Store all idle threads, this can be reused instead of creating 80 * a new thread. Also avoids complicated thread destroy functionality 81 * for idle threads. 82 */ 83 #ifdef CONFIG_HOTPLUG_CPU 84 /* 85 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is 86 * removed after init for !CONFIG_HOTPLUG_CPU. 87 */ 88 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); 89 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) 90 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) 91 #else 92 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; 93 #define get_idle_for_cpu(x) (idle_thread_array[(x)]) 94 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) 95 #endif 96 97 /* Number of siblings per CPU package */ 98 int smp_num_siblings = 1; 99 EXPORT_SYMBOL(smp_num_siblings); 100 101 /* Last level cache ID of each logical CPU */ 102 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; 103 104 /* bitmap of online cpus */ 105 cpumask_t cpu_online_map __read_mostly; 106 EXPORT_SYMBOL(cpu_online_map); 107 108 cpumask_t cpu_callin_map; 109 cpumask_t cpu_callout_map; 110 cpumask_t cpu_possible_map; 111 EXPORT_SYMBOL(cpu_possible_map); 112 113 /* representing HT siblings of each logical CPU */ 114 DEFINE_PER_CPU(cpumask_t, cpu_sibling_map); 115 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 116 117 /* representing HT and core siblings of each logical CPU */ 118 DEFINE_PER_CPU(cpumask_t, cpu_core_map); 119 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 120 121 /* Per CPU bogomips and other parameters */ 122 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 123 EXPORT_PER_CPU_SYMBOL(cpu_info); 124 125 static atomic_t init_deasserted; 126 127 128 /* representing cpus for which sibling maps can be computed */ 129 static cpumask_t cpu_sibling_setup_map; 130 131 /* Set if we find a B stepping CPU */ 132 static int __cpuinitdata smp_b_stepping; 133 134 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) 135 136 /* which logical CPUs are on which nodes */ 137 cpumask_t node_to_cpumask_map[MAX_NUMNODES] __read_mostly = 138 { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE }; 139 EXPORT_SYMBOL(node_to_cpumask_map); 140 /* which node each logical CPU is on */ 141 int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; 142 EXPORT_SYMBOL(cpu_to_node_map); 143 144 /* set up a mapping between cpu and node. */ 145 static void map_cpu_to_node(int cpu, int node) 146 { 147 printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); 148 cpu_set(cpu, node_to_cpumask_map[node]); 149 cpu_to_node_map[cpu] = node; 150 } 151 152 /* undo a mapping between cpu and node. */ 153 static void unmap_cpu_to_node(int cpu) 154 { 155 int node; 156 157 printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); 158 for (node = 0; node < MAX_NUMNODES; node++) 159 cpu_clear(cpu, node_to_cpumask_map[node]); 160 cpu_to_node_map[cpu] = 0; 161 } 162 #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ 163 #define map_cpu_to_node(cpu, node) ({}) 164 #define unmap_cpu_to_node(cpu) ({}) 165 #endif 166 167 #ifdef CONFIG_X86_32 168 static int boot_cpu_logical_apicid; 169 170 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = 171 { [0 ... NR_CPUS-1] = BAD_APICID }; 172 173 static void map_cpu_to_logical_apicid(void) 174 { 175 int cpu = smp_processor_id(); 176 int apicid = logical_smp_processor_id(); 177 int node = apicid_to_node(apicid); 178 179 if (!node_online(node)) 180 node = first_online_node; 181 182 cpu_2_logical_apicid[cpu] = apicid; 183 map_cpu_to_node(cpu, node); 184 } 185 186 void numa_remove_cpu(int cpu) 187 { 188 cpu_2_logical_apicid[cpu] = BAD_APICID; 189 unmap_cpu_to_node(cpu); 190 } 191 #else 192 #define map_cpu_to_logical_apicid() do {} while (0) 193 #endif 194 195 /* 196 * Report back to the Boot Processor. 197 * Running on AP. 198 */ 199 static void __cpuinit smp_callin(void) 200 { 201 int cpuid, phys_id; 202 unsigned long timeout; 203 204 /* 205 * If waken up by an INIT in an 82489DX configuration 206 * we may get here before an INIT-deassert IPI reaches 207 * our local APIC. We have to wait for the IPI or we'll 208 * lock up on an APIC access. 209 */ 210 wait_for_init_deassert(&init_deasserted); 211 212 /* 213 * (This works even if the APIC is not enabled.) 214 */ 215 phys_id = read_apic_id(); 216 cpuid = smp_processor_id(); 217 if (cpu_isset(cpuid, cpu_callin_map)) { 218 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, 219 phys_id, cpuid); 220 } 221 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); 222 223 /* 224 * STARTUP IPIs are fragile beasts as they might sometimes 225 * trigger some glue motherboard logic. Complete APIC bus 226 * silence for 1 second, this overestimates the time the 227 * boot CPU is spending to send the up to 2 STARTUP IPIs 228 * by a factor of two. This should be enough. 229 */ 230 231 /* 232 * Waiting 2s total for startup (udelay is not yet working) 233 */ 234 timeout = jiffies + 2*HZ; 235 while (time_before(jiffies, timeout)) { 236 /* 237 * Has the boot CPU finished it's STARTUP sequence? 238 */ 239 if (cpu_isset(cpuid, cpu_callout_map)) 240 break; 241 cpu_relax(); 242 } 243 244 if (!time_before(jiffies, timeout)) { 245 panic("%s: CPU%d started up but did not get a callout!\n", 246 __func__, cpuid); 247 } 248 249 /* 250 * the boot CPU has finished the init stage and is spinning 251 * on callin_map until we finish. We are free to set up this 252 * CPU, first the APIC. (this is probably redundant on most 253 * boards) 254 */ 255 256 pr_debug("CALLIN, before setup_local_APIC().\n"); 257 smp_callin_clear_local_apic(); 258 setup_local_APIC(); 259 end_local_APIC_setup(); 260 map_cpu_to_logical_apicid(); 261 262 notify_cpu_starting(cpuid); 263 /* 264 * Get our bogomips. 265 * 266 * Need to enable IRQs because it can take longer and then 267 * the NMI watchdog might kill us. 268 */ 269 local_irq_enable(); 270 calibrate_delay(); 271 local_irq_disable(); 272 pr_debug("Stack at about %p\n", &cpuid); 273 274 /* 275 * Save our processor parameters 276 */ 277 smp_store_cpu_info(cpuid); 278 279 /* 280 * Allow the master to continue. 281 */ 282 cpu_set(cpuid, cpu_callin_map); 283 } 284 285 /* 286 * Activate a secondary processor. 287 */ 288 static void __cpuinit start_secondary(void *unused) 289 { 290 /* 291 * Don't put *anything* before cpu_init(), SMP booting is too 292 * fragile that we want to limit the things done here to the 293 * most necessary things. 294 */ 295 #ifdef CONFIG_VMI 296 vmi_bringup(); 297 #endif 298 cpu_init(); 299 preempt_disable(); 300 smp_callin(); 301 302 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 303 barrier(); 304 /* 305 * Check TSC synchronization with the BP: 306 */ 307 check_tsc_sync_target(); 308 309 if (nmi_watchdog == NMI_IO_APIC) { 310 disable_8259A_irq(0); 311 enable_NMI_through_LVT0(); 312 enable_8259A_irq(0); 313 } 314 315 #ifdef CONFIG_X86_32 316 while (low_mappings) 317 cpu_relax(); 318 __flush_tlb_all(); 319 #endif 320 321 /* This must be done before setting cpu_online_map */ 322 set_cpu_sibling_map(raw_smp_processor_id()); 323 wmb(); 324 325 /* 326 * We need to hold call_lock, so there is no inconsistency 327 * between the time smp_call_function() determines number of 328 * IPI recipients, and the time when the determination is made 329 * for which cpus receive the IPI. Holding this 330 * lock helps us to not include this cpu in a currently in progress 331 * smp_call_function(). 332 * 333 * We need to hold vector_lock so there the set of online cpus 334 * does not change while we are assigning vectors to cpus. Holding 335 * this lock ensures we don't half assign or remove an irq from a cpu. 336 */ 337 ipi_call_lock(); 338 lock_vector_lock(); 339 __setup_vector_irq(smp_processor_id()); 340 cpu_set(smp_processor_id(), cpu_online_map); 341 unlock_vector_lock(); 342 ipi_call_unlock(); 343 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; 344 345 /* enable local interrupts */ 346 local_irq_enable(); 347 348 setup_secondary_clock(); 349 350 wmb(); 351 cpu_idle(); 352 } 353 354 static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c) 355 { 356 /* 357 * Mask B, Pentium, but not Pentium MMX 358 */ 359 if (c->x86_vendor == X86_VENDOR_INTEL && 360 c->x86 == 5 && 361 c->x86_mask >= 1 && c->x86_mask <= 4 && 362 c->x86_model <= 3) 363 /* 364 * Remember we have B step Pentia with bugs 365 */ 366 smp_b_stepping = 1; 367 368 /* 369 * Certain Athlons might work (for various values of 'work') in SMP 370 * but they are not certified as MP capable. 371 */ 372 if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) { 373 374 if (num_possible_cpus() == 1) 375 goto valid_k7; 376 377 /* Athlon 660/661 is valid. */ 378 if ((c->x86_model == 6) && ((c->x86_mask == 0) || 379 (c->x86_mask == 1))) 380 goto valid_k7; 381 382 /* Duron 670 is valid */ 383 if ((c->x86_model == 7) && (c->x86_mask == 0)) 384 goto valid_k7; 385 386 /* 387 * Athlon 662, Duron 671, and Athlon >model 7 have capability 388 * bit. It's worth noting that the A5 stepping (662) of some 389 * Athlon XP's have the MP bit set. 390 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 391 * more. 392 */ 393 if (((c->x86_model == 6) && (c->x86_mask >= 2)) || 394 ((c->x86_model == 7) && (c->x86_mask >= 1)) || 395 (c->x86_model > 7)) 396 if (cpu_has_mp) 397 goto valid_k7; 398 399 /* If we get here, not a certified SMP capable AMD system. */ 400 add_taint(TAINT_UNSAFE_SMP); 401 } 402 403 valid_k7: 404 ; 405 } 406 407 static void __cpuinit smp_checks(void) 408 { 409 if (smp_b_stepping) 410 printk(KERN_WARNING "WARNING: SMP operation may be unreliable" 411 "with B stepping processors.\n"); 412 413 /* 414 * Don't taint if we are running SMP kernel on a single non-MP 415 * approved Athlon 416 */ 417 if (tainted & TAINT_UNSAFE_SMP) { 418 if (num_online_cpus()) 419 printk(KERN_INFO "WARNING: This combination of AMD" 420 "processors is not suitable for SMP.\n"); 421 else 422 tainted &= ~TAINT_UNSAFE_SMP; 423 } 424 } 425 426 /* 427 * The bootstrap kernel entry code has set these up. Save them for 428 * a given CPU 429 */ 430 431 void __cpuinit smp_store_cpu_info(int id) 432 { 433 struct cpuinfo_x86 *c = &cpu_data(id); 434 435 *c = boot_cpu_data; 436 c->cpu_index = id; 437 if (id != 0) 438 identify_secondary_cpu(c); 439 smp_apply_quirks(c); 440 } 441 442 443 void __cpuinit set_cpu_sibling_map(int cpu) 444 { 445 int i; 446 struct cpuinfo_x86 *c = &cpu_data(cpu); 447 448 cpu_set(cpu, cpu_sibling_setup_map); 449 450 if (smp_num_siblings > 1) { 451 for_each_cpu_mask_nr(i, cpu_sibling_setup_map) { 452 if (c->phys_proc_id == cpu_data(i).phys_proc_id && 453 c->cpu_core_id == cpu_data(i).cpu_core_id) { 454 cpu_set(i, per_cpu(cpu_sibling_map, cpu)); 455 cpu_set(cpu, per_cpu(cpu_sibling_map, i)); 456 cpu_set(i, per_cpu(cpu_core_map, cpu)); 457 cpu_set(cpu, per_cpu(cpu_core_map, i)); 458 cpu_set(i, c->llc_shared_map); 459 cpu_set(cpu, cpu_data(i).llc_shared_map); 460 } 461 } 462 } else { 463 cpu_set(cpu, per_cpu(cpu_sibling_map, cpu)); 464 } 465 466 cpu_set(cpu, c->llc_shared_map); 467 468 if (current_cpu_data.x86_max_cores == 1) { 469 per_cpu(cpu_core_map, cpu) = per_cpu(cpu_sibling_map, cpu); 470 c->booted_cores = 1; 471 return; 472 } 473 474 for_each_cpu_mask_nr(i, cpu_sibling_setup_map) { 475 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && 476 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { 477 cpu_set(i, c->llc_shared_map); 478 cpu_set(cpu, cpu_data(i).llc_shared_map); 479 } 480 if (c->phys_proc_id == cpu_data(i).phys_proc_id) { 481 cpu_set(i, per_cpu(cpu_core_map, cpu)); 482 cpu_set(cpu, per_cpu(cpu_core_map, i)); 483 /* 484 * Does this new cpu bringup a new core? 485 */ 486 if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) { 487 /* 488 * for each core in package, increment 489 * the booted_cores for this new cpu 490 */ 491 if (first_cpu(per_cpu(cpu_sibling_map, i)) == i) 492 c->booted_cores++; 493 /* 494 * increment the core count for all 495 * the other cpus in this package 496 */ 497 if (i != cpu) 498 cpu_data(i).booted_cores++; 499 } else if (i != cpu && !c->booted_cores) 500 c->booted_cores = cpu_data(i).booted_cores; 501 } 502 } 503 } 504 505 /* maps the cpu to the sched domain representing multi-core */ 506 cpumask_t cpu_coregroup_map(int cpu) 507 { 508 struct cpuinfo_x86 *c = &cpu_data(cpu); 509 /* 510 * For perf, we return last level cache shared map. 511 * And for power savings, we return cpu_core_map 512 */ 513 if (sched_mc_power_savings || sched_smt_power_savings) 514 return per_cpu(cpu_core_map, cpu); 515 else 516 return c->llc_shared_map; 517 } 518 519 static void impress_friends(void) 520 { 521 int cpu; 522 unsigned long bogosum = 0; 523 /* 524 * Allow the user to impress friends. 525 */ 526 pr_debug("Before bogomips.\n"); 527 for_each_possible_cpu(cpu) 528 if (cpu_isset(cpu, cpu_callout_map)) 529 bogosum += cpu_data(cpu).loops_per_jiffy; 530 printk(KERN_INFO 531 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", 532 num_online_cpus(), 533 bogosum/(500000/HZ), 534 (bogosum/(5000/HZ))%100); 535 536 pr_debug("Before bogocount - setting activated=1.\n"); 537 } 538 539 static inline void __inquire_remote_apic(int apicid) 540 { 541 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 542 char *names[] = { "ID", "VERSION", "SPIV" }; 543 int timeout; 544 u32 status; 545 546 printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid); 547 548 for (i = 0; i < ARRAY_SIZE(regs); i++) { 549 printk(KERN_INFO "... APIC #%d %s: ", apicid, names[i]); 550 551 /* 552 * Wait for idle. 553 */ 554 status = safe_apic_wait_icr_idle(); 555 if (status) 556 printk(KERN_CONT 557 "a previous APIC delivery may have failed\n"); 558 559 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 560 561 timeout = 0; 562 do { 563 udelay(100); 564 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 565 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 566 567 switch (status) { 568 case APIC_ICR_RR_VALID: 569 status = apic_read(APIC_RRR); 570 printk(KERN_CONT "%08x\n", status); 571 break; 572 default: 573 printk(KERN_CONT "failed\n"); 574 } 575 } 576 } 577 578 #ifdef WAKE_SECONDARY_VIA_NMI 579 /* 580 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 581 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 582 * won't ... remember to clear down the APIC, etc later. 583 */ 584 static int __devinit 585 wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip) 586 { 587 unsigned long send_status, accept_status = 0; 588 int maxlvt; 589 590 /* Target chip */ 591 /* Boot on the stack */ 592 /* Kick the second */ 593 apic_icr_write(APIC_DM_NMI | APIC_DEST_LOGICAL, logical_apicid); 594 595 pr_debug("Waiting for send to finish...\n"); 596 send_status = safe_apic_wait_icr_idle(); 597 598 /* 599 * Give the other CPU some time to accept the IPI. 600 */ 601 udelay(200); 602 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 603 maxlvt = lapic_get_maxlvt(); 604 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 605 apic_write(APIC_ESR, 0); 606 accept_status = (apic_read(APIC_ESR) & 0xEF); 607 } 608 pr_debug("NMI sent.\n"); 609 610 if (send_status) 611 printk(KERN_ERR "APIC never delivered???\n"); 612 if (accept_status) 613 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 614 615 return (send_status | accept_status); 616 } 617 #endif /* WAKE_SECONDARY_VIA_NMI */ 618 619 #ifdef WAKE_SECONDARY_VIA_INIT 620 static int __devinit 621 wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip) 622 { 623 unsigned long send_status, accept_status = 0; 624 int maxlvt, num_starts, j; 625 626 if (get_uv_system_type() == UV_NON_UNIQUE_APIC) { 627 send_status = uv_wakeup_secondary(phys_apicid, start_eip); 628 atomic_set(&init_deasserted, 1); 629 return send_status; 630 } 631 632 maxlvt = lapic_get_maxlvt(); 633 634 /* 635 * Be paranoid about clearing APIC errors. 636 */ 637 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 638 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 639 apic_write(APIC_ESR, 0); 640 apic_read(APIC_ESR); 641 } 642 643 pr_debug("Asserting INIT.\n"); 644 645 /* 646 * Turn INIT on target chip 647 */ 648 /* 649 * Send IPI 650 */ 651 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 652 phys_apicid); 653 654 pr_debug("Waiting for send to finish...\n"); 655 send_status = safe_apic_wait_icr_idle(); 656 657 mdelay(10); 658 659 pr_debug("Deasserting INIT.\n"); 660 661 /* Target chip */ 662 /* Send IPI */ 663 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 664 665 pr_debug("Waiting for send to finish...\n"); 666 send_status = safe_apic_wait_icr_idle(); 667 668 mb(); 669 atomic_set(&init_deasserted, 1); 670 671 /* 672 * Should we send STARTUP IPIs ? 673 * 674 * Determine this based on the APIC version. 675 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 676 */ 677 if (APIC_INTEGRATED(apic_version[phys_apicid])) 678 num_starts = 2; 679 else 680 num_starts = 0; 681 682 /* 683 * Paravirt / VMI wants a startup IPI hook here to set up the 684 * target processor state. 685 */ 686 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, 687 (unsigned long)stack_start.sp); 688 689 /* 690 * Run STARTUP IPI loop. 691 */ 692 pr_debug("#startup loops: %d.\n", num_starts); 693 694 for (j = 1; j <= num_starts; j++) { 695 pr_debug("Sending STARTUP #%d.\n", j); 696 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 697 apic_write(APIC_ESR, 0); 698 apic_read(APIC_ESR); 699 pr_debug("After apic_write.\n"); 700 701 /* 702 * STARTUP IPI 703 */ 704 705 /* Target chip */ 706 /* Boot on the stack */ 707 /* Kick the second */ 708 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 709 phys_apicid); 710 711 /* 712 * Give the other CPU some time to accept the IPI. 713 */ 714 udelay(300); 715 716 pr_debug("Startup point 1.\n"); 717 718 pr_debug("Waiting for send to finish...\n"); 719 send_status = safe_apic_wait_icr_idle(); 720 721 /* 722 * Give the other CPU some time to accept the IPI. 723 */ 724 udelay(200); 725 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 726 apic_write(APIC_ESR, 0); 727 accept_status = (apic_read(APIC_ESR) & 0xEF); 728 if (send_status || accept_status) 729 break; 730 } 731 pr_debug("After Startup.\n"); 732 733 if (send_status) 734 printk(KERN_ERR "APIC never delivered???\n"); 735 if (accept_status) 736 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 737 738 return (send_status | accept_status); 739 } 740 #endif /* WAKE_SECONDARY_VIA_INIT */ 741 742 struct create_idle { 743 struct work_struct work; 744 struct task_struct *idle; 745 struct completion done; 746 int cpu; 747 }; 748 749 static void __cpuinit do_fork_idle(struct work_struct *work) 750 { 751 struct create_idle *c_idle = 752 container_of(work, struct create_idle, work); 753 754 c_idle->idle = fork_idle(c_idle->cpu); 755 complete(&c_idle->done); 756 } 757 758 #ifdef CONFIG_X86_64 759 760 /* __ref because it's safe to call free_bootmem when after_bootmem == 0. */ 761 static void __ref free_bootmem_pda(struct x8664_pda *oldpda) 762 { 763 if (!after_bootmem) 764 free_bootmem((unsigned long)oldpda, sizeof(*oldpda)); 765 } 766 767 /* 768 * Allocate node local memory for the AP pda. 769 * 770 * Must be called after the _cpu_pda pointer table is initialized. 771 */ 772 int __cpuinit get_local_pda(int cpu) 773 { 774 struct x8664_pda *oldpda, *newpda; 775 unsigned long size = sizeof(struct x8664_pda); 776 int node = cpu_to_node(cpu); 777 778 if (cpu_pda(cpu) && !cpu_pda(cpu)->in_bootmem) 779 return 0; 780 781 oldpda = cpu_pda(cpu); 782 newpda = kmalloc_node(size, GFP_ATOMIC, node); 783 if (!newpda) { 784 printk(KERN_ERR "Could not allocate node local PDA " 785 "for CPU %d on node %d\n", cpu, node); 786 787 if (oldpda) 788 return 0; /* have a usable pda */ 789 else 790 return -1; 791 } 792 793 if (oldpda) { 794 memcpy(newpda, oldpda, size); 795 free_bootmem_pda(oldpda); 796 } 797 798 newpda->in_bootmem = 0; 799 cpu_pda(cpu) = newpda; 800 return 0; 801 } 802 #endif /* CONFIG_X86_64 */ 803 804 static int __cpuinit do_boot_cpu(int apicid, int cpu) 805 /* 806 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 807 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 808 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu. 809 */ 810 { 811 unsigned long boot_error = 0; 812 int timeout; 813 unsigned long start_ip; 814 unsigned short nmi_high = 0, nmi_low = 0; 815 struct create_idle c_idle = { 816 .cpu = cpu, 817 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), 818 }; 819 INIT_WORK(&c_idle.work, do_fork_idle); 820 821 #ifdef CONFIG_X86_64 822 /* Allocate node local memory for AP pdas */ 823 if (cpu > 0) { 824 boot_error = get_local_pda(cpu); 825 if (boot_error) 826 goto restore_state; 827 /* if can't get pda memory, can't start cpu */ 828 } 829 #endif 830 831 alternatives_smp_switch(1); 832 833 c_idle.idle = get_idle_for_cpu(cpu); 834 835 /* 836 * We can't use kernel_thread since we must avoid to 837 * reschedule the child. 838 */ 839 if (c_idle.idle) { 840 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) 841 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); 842 init_idle(c_idle.idle, cpu); 843 goto do_rest; 844 } 845 846 if (!keventd_up() || current_is_keventd()) 847 c_idle.work.func(&c_idle.work); 848 else { 849 schedule_work(&c_idle.work); 850 wait_for_completion(&c_idle.done); 851 } 852 853 if (IS_ERR(c_idle.idle)) { 854 printk("failed fork for CPU %d\n", cpu); 855 return PTR_ERR(c_idle.idle); 856 } 857 858 set_idle_for_cpu(cpu, c_idle.idle); 859 do_rest: 860 #ifdef CONFIG_X86_32 861 per_cpu(current_task, cpu) = c_idle.idle; 862 init_gdt(cpu); 863 /* Stack for startup_32 can be just as for start_secondary onwards */ 864 irq_ctx_init(cpu); 865 #else 866 cpu_pda(cpu)->pcurrent = c_idle.idle; 867 clear_tsk_thread_flag(c_idle.idle, TIF_FORK); 868 #endif 869 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 870 initial_code = (unsigned long)start_secondary; 871 stack_start.sp = (void *) c_idle.idle->thread.sp; 872 873 /* start_ip had better be page-aligned! */ 874 start_ip = setup_trampoline(); 875 876 /* So we see what's up */ 877 printk(KERN_INFO "Booting processor %d/%d ip %lx\n", 878 cpu, apicid, start_ip); 879 880 /* 881 * This grunge runs the startup process for 882 * the targeted processor. 883 */ 884 885 atomic_set(&init_deasserted, 0); 886 887 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 888 889 pr_debug("Setting warm reset code and vector.\n"); 890 891 store_NMI_vector(&nmi_high, &nmi_low); 892 893 smpboot_setup_warm_reset_vector(start_ip); 894 /* 895 * Be paranoid about clearing APIC errors. 896 */ 897 apic_write(APIC_ESR, 0); 898 apic_read(APIC_ESR); 899 } 900 901 /* 902 * Starting actual IPI sequence... 903 */ 904 boot_error = wakeup_secondary_cpu(apicid, start_ip); 905 906 if (!boot_error) { 907 /* 908 * allow APs to start initializing. 909 */ 910 pr_debug("Before Callout %d.\n", cpu); 911 cpu_set(cpu, cpu_callout_map); 912 pr_debug("After Callout %d.\n", cpu); 913 914 /* 915 * Wait 5s total for a response 916 */ 917 for (timeout = 0; timeout < 50000; timeout++) { 918 if (cpu_isset(cpu, cpu_callin_map)) 919 break; /* It has booted */ 920 udelay(100); 921 } 922 923 if (cpu_isset(cpu, cpu_callin_map)) { 924 /* number CPUs logically, starting from 1 (BSP is 0) */ 925 pr_debug("OK.\n"); 926 printk(KERN_INFO "CPU%d: ", cpu); 927 print_cpu_info(&cpu_data(cpu)); 928 pr_debug("CPU has booted.\n"); 929 } else { 930 boot_error = 1; 931 if (*((volatile unsigned char *)trampoline_base) 932 == 0xA5) 933 /* trampoline started but...? */ 934 printk(KERN_ERR "Stuck ??\n"); 935 else 936 /* trampoline code not run */ 937 printk(KERN_ERR "Not responding.\n"); 938 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) 939 inquire_remote_apic(apicid); 940 } 941 } 942 #ifdef CONFIG_X86_64 943 restore_state: 944 #endif 945 if (boot_error) { 946 /* Try to put things back the way they were before ... */ 947 numa_remove_cpu(cpu); /* was set by numa_add_cpu */ 948 cpu_clear(cpu, cpu_callout_map); /* was set by do_boot_cpu() */ 949 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */ 950 cpu_clear(cpu, cpu_present_map); 951 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; 952 } 953 954 /* mark "stuck" area as not stuck */ 955 *((volatile unsigned long *)trampoline_base) = 0; 956 957 /* 958 * Cleanup possible dangling ends... 959 */ 960 smpboot_restore_warm_reset_vector(); 961 962 return boot_error; 963 } 964 965 int __cpuinit native_cpu_up(unsigned int cpu) 966 { 967 int apicid = cpu_present_to_apicid(cpu); 968 unsigned long flags; 969 int err; 970 971 WARN_ON(irqs_disabled()); 972 973 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 974 975 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || 976 !physid_isset(apicid, phys_cpu_present_map)) { 977 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); 978 return -EINVAL; 979 } 980 981 /* 982 * Already booted CPU? 983 */ 984 if (cpu_isset(cpu, cpu_callin_map)) { 985 pr_debug("do_boot_cpu %d Already started\n", cpu); 986 return -ENOSYS; 987 } 988 989 /* 990 * Save current MTRR state in case it was changed since early boot 991 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 992 */ 993 mtrr_save_state(); 994 995 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; 996 997 #ifdef CONFIG_X86_32 998 /* init low mem mapping */ 999 clone_pgd_range(swapper_pg_dir, swapper_pg_dir + KERNEL_PGD_BOUNDARY, 1000 min_t(unsigned long, KERNEL_PGD_PTRS, KERNEL_PGD_BOUNDARY)); 1001 flush_tlb_all(); 1002 low_mappings = 1; 1003 1004 err = do_boot_cpu(apicid, cpu); 1005 1006 zap_low_mappings(); 1007 low_mappings = 0; 1008 #else 1009 err = do_boot_cpu(apicid, cpu); 1010 #endif 1011 if (err) { 1012 pr_debug("do_boot_cpu failed %d\n", err); 1013 return -EIO; 1014 } 1015 1016 /* 1017 * Check TSC synchronization with the AP (keep irqs disabled 1018 * while doing so): 1019 */ 1020 local_irq_save(flags); 1021 check_tsc_sync_source(cpu); 1022 local_irq_restore(flags); 1023 1024 while (!cpu_online(cpu)) { 1025 cpu_relax(); 1026 touch_nmi_watchdog(); 1027 } 1028 1029 return 0; 1030 } 1031 1032 /* 1033 * Fall back to non SMP mode after errors. 1034 * 1035 * RED-PEN audit/test this more. I bet there is more state messed up here. 1036 */ 1037 static __init void disable_smp(void) 1038 { 1039 cpu_present_map = cpumask_of_cpu(0); 1040 cpu_possible_map = cpumask_of_cpu(0); 1041 smpboot_clear_io_apic_irqs(); 1042 1043 if (smp_found_config) 1044 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1045 else 1046 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1047 map_cpu_to_logical_apicid(); 1048 cpu_set(0, per_cpu(cpu_sibling_map, 0)); 1049 cpu_set(0, per_cpu(cpu_core_map, 0)); 1050 } 1051 1052 /* 1053 * Various sanity checks. 1054 */ 1055 static int __init smp_sanity_check(unsigned max_cpus) 1056 { 1057 preempt_disable(); 1058 1059 #if defined(CONFIG_X86_PC) && defined(CONFIG_X86_32) 1060 if (def_to_bigsmp && nr_cpu_ids > 8) { 1061 unsigned int cpu; 1062 unsigned nr; 1063 1064 printk(KERN_WARNING 1065 "More than 8 CPUs detected - skipping them.\n" 1066 "Use CONFIG_X86_GENERICARCH and CONFIG_X86_BIGSMP.\n"); 1067 1068 nr = 0; 1069 for_each_present_cpu(cpu) { 1070 if (nr >= 8) 1071 cpu_clear(cpu, cpu_present_map); 1072 nr++; 1073 } 1074 1075 nr = 0; 1076 for_each_possible_cpu(cpu) { 1077 if (nr >= 8) 1078 cpu_clear(cpu, cpu_possible_map); 1079 nr++; 1080 } 1081 1082 nr_cpu_ids = 8; 1083 } 1084 #endif 1085 1086 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1087 printk(KERN_WARNING "weird, boot CPU (#%d) not listed" 1088 "by the BIOS.\n", hard_smp_processor_id()); 1089 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1090 } 1091 1092 /* 1093 * If we couldn't find an SMP configuration at boot time, 1094 * get out of here now! 1095 */ 1096 if (!smp_found_config && !acpi_lapic) { 1097 preempt_enable(); 1098 printk(KERN_NOTICE "SMP motherboard not detected.\n"); 1099 disable_smp(); 1100 if (APIC_init_uniprocessor()) 1101 printk(KERN_NOTICE "Local APIC not detected." 1102 " Using dummy APIC emulation.\n"); 1103 return -1; 1104 } 1105 1106 /* 1107 * Should not be necessary because the MP table should list the boot 1108 * CPU too, but we do it for the sake of robustness anyway. 1109 */ 1110 if (!check_phys_apicid_present(boot_cpu_physical_apicid)) { 1111 printk(KERN_NOTICE 1112 "weird, boot CPU (#%d) not listed by the BIOS.\n", 1113 boot_cpu_physical_apicid); 1114 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1115 } 1116 preempt_enable(); 1117 1118 /* 1119 * If we couldn't find a local APIC, then get out of here now! 1120 */ 1121 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 1122 !cpu_has_apic) { 1123 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", 1124 boot_cpu_physical_apicid); 1125 printk(KERN_ERR "... forcing use of dummy APIC emulation." 1126 "(tell your hw vendor)\n"); 1127 smpboot_clear_io_apic(); 1128 return -1; 1129 } 1130 1131 verify_local_APIC(); 1132 1133 /* 1134 * If SMP should be disabled, then really disable it! 1135 */ 1136 if (!max_cpus) { 1137 printk(KERN_INFO "SMP mode deactivated.\n"); 1138 smpboot_clear_io_apic(); 1139 1140 localise_nmi_watchdog(); 1141 1142 connect_bsp_APIC(); 1143 setup_local_APIC(); 1144 end_local_APIC_setup(); 1145 return -1; 1146 } 1147 1148 return 0; 1149 } 1150 1151 static void __init smp_cpu_index_default(void) 1152 { 1153 int i; 1154 struct cpuinfo_x86 *c; 1155 1156 for_each_possible_cpu(i) { 1157 c = &cpu_data(i); 1158 /* mark all to hotplug */ 1159 c->cpu_index = NR_CPUS; 1160 } 1161 } 1162 1163 /* 1164 * Prepare for SMP bootup. The MP table or ACPI has been read 1165 * earlier. Just do some sanity checking here and enable APIC mode. 1166 */ 1167 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1168 { 1169 preempt_disable(); 1170 smp_cpu_index_default(); 1171 current_cpu_data = boot_cpu_data; 1172 cpu_callin_map = cpumask_of_cpu(0); 1173 mb(); 1174 /* 1175 * Setup boot CPU information 1176 */ 1177 smp_store_cpu_info(0); /* Final full version of the data */ 1178 #ifdef CONFIG_X86_32 1179 boot_cpu_logical_apicid = logical_smp_processor_id(); 1180 #endif 1181 current_thread_info()->cpu = 0; /* needed? */ 1182 set_cpu_sibling_map(0); 1183 1184 #ifdef CONFIG_X86_64 1185 enable_IR_x2apic(); 1186 setup_apic_routing(); 1187 #endif 1188 1189 if (smp_sanity_check(max_cpus) < 0) { 1190 printk(KERN_INFO "SMP disabled\n"); 1191 disable_smp(); 1192 goto out; 1193 } 1194 1195 preempt_disable(); 1196 if (read_apic_id() != boot_cpu_physical_apicid) { 1197 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1198 read_apic_id(), boot_cpu_physical_apicid); 1199 /* Or can we switch back to PIC here? */ 1200 } 1201 preempt_enable(); 1202 1203 connect_bsp_APIC(); 1204 1205 /* 1206 * Switch from PIC to APIC mode. 1207 */ 1208 setup_local_APIC(); 1209 1210 #ifdef CONFIG_X86_64 1211 /* 1212 * Enable IO APIC before setting up error vector 1213 */ 1214 if (!skip_ioapic_setup && nr_ioapics) 1215 enable_IO_APIC(); 1216 #endif 1217 end_local_APIC_setup(); 1218 1219 map_cpu_to_logical_apicid(); 1220 1221 setup_portio_remap(); 1222 1223 smpboot_setup_io_apic(); 1224 /* 1225 * Set up local APIC timer on boot CPU. 1226 */ 1227 1228 printk(KERN_INFO "CPU%d: ", 0); 1229 print_cpu_info(&cpu_data(0)); 1230 setup_boot_clock(); 1231 1232 if (is_uv_system()) 1233 uv_system_init(); 1234 out: 1235 preempt_enable(); 1236 } 1237 /* 1238 * Early setup to make printk work. 1239 */ 1240 void __init native_smp_prepare_boot_cpu(void) 1241 { 1242 int me = smp_processor_id(); 1243 #ifdef CONFIG_X86_32 1244 init_gdt(me); 1245 #endif 1246 switch_to_new_gdt(); 1247 /* already set me in cpu_online_map in boot_cpu_init() */ 1248 cpu_set(me, cpu_callout_map); 1249 per_cpu(cpu_state, me) = CPU_ONLINE; 1250 } 1251 1252 void __init native_smp_cpus_done(unsigned int max_cpus) 1253 { 1254 pr_debug("Boot done.\n"); 1255 1256 impress_friends(); 1257 smp_checks(); 1258 #ifdef CONFIG_X86_IO_APIC 1259 setup_ioapic_dest(); 1260 #endif 1261 check_nmi_watchdog(); 1262 } 1263 1264 /* 1265 * cpu_possible_map should be static, it cannot change as cpu's 1266 * are onlined, or offlined. The reason is per-cpu data-structures 1267 * are allocated by some modules at init time, and dont expect to 1268 * do this dynamically on cpu arrival/departure. 1269 * cpu_present_map on the other hand can change dynamically. 1270 * In case when cpu_hotplug is not compiled, then we resort to current 1271 * behaviour, which is cpu_possible == cpu_present. 1272 * - Ashok Raj 1273 * 1274 * Three ways to find out the number of additional hotplug CPUs: 1275 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1276 * - The user can overwrite it with additional_cpus=NUM 1277 * - Otherwise don't reserve additional CPUs. 1278 * We do this because additional CPUs waste a lot of memory. 1279 * -AK 1280 */ 1281 __init void prefill_possible_map(void) 1282 { 1283 int i, possible; 1284 1285 /* no processor from mptable or madt */ 1286 if (!num_processors) 1287 num_processors = 1; 1288 1289 possible = num_processors + disabled_cpus; 1290 if (possible > NR_CPUS) 1291 possible = NR_CPUS; 1292 1293 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", 1294 possible, max_t(int, possible - num_processors, 0)); 1295 1296 for (i = 0; i < possible; i++) 1297 cpu_set(i, cpu_possible_map); 1298 1299 nr_cpu_ids = possible; 1300 } 1301 1302 #ifdef CONFIG_HOTPLUG_CPU 1303 1304 static void remove_siblinginfo(int cpu) 1305 { 1306 int sibling; 1307 struct cpuinfo_x86 *c = &cpu_data(cpu); 1308 1309 for_each_cpu_mask_nr(sibling, per_cpu(cpu_core_map, cpu)) { 1310 cpu_clear(cpu, per_cpu(cpu_core_map, sibling)); 1311 /*/ 1312 * last thread sibling in this cpu core going down 1313 */ 1314 if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) 1315 cpu_data(sibling).booted_cores--; 1316 } 1317 1318 for_each_cpu_mask_nr(sibling, per_cpu(cpu_sibling_map, cpu)) 1319 cpu_clear(cpu, per_cpu(cpu_sibling_map, sibling)); 1320 cpus_clear(per_cpu(cpu_sibling_map, cpu)); 1321 cpus_clear(per_cpu(cpu_core_map, cpu)); 1322 c->phys_proc_id = 0; 1323 c->cpu_core_id = 0; 1324 cpu_clear(cpu, cpu_sibling_setup_map); 1325 } 1326 1327 static void __ref remove_cpu_from_maps(int cpu) 1328 { 1329 cpu_clear(cpu, cpu_online_map); 1330 cpu_clear(cpu, cpu_callout_map); 1331 cpu_clear(cpu, cpu_callin_map); 1332 /* was set by cpu_init() */ 1333 cpu_clear(cpu, cpu_initialized); 1334 numa_remove_cpu(cpu); 1335 } 1336 1337 void cpu_disable_common(void) 1338 { 1339 int cpu = smp_processor_id(); 1340 /* 1341 * HACK: 1342 * Allow any queued timer interrupts to get serviced 1343 * This is only a temporary solution until we cleanup 1344 * fixup_irqs as we do for IA64. 1345 */ 1346 local_irq_enable(); 1347 mdelay(1); 1348 1349 local_irq_disable(); 1350 remove_siblinginfo(cpu); 1351 1352 /* It's now safe to remove this processor from the online map */ 1353 lock_vector_lock(); 1354 remove_cpu_from_maps(cpu); 1355 unlock_vector_lock(); 1356 fixup_irqs(cpu_online_map); 1357 } 1358 1359 int native_cpu_disable(void) 1360 { 1361 int cpu = smp_processor_id(); 1362 1363 /* 1364 * Perhaps use cpufreq to drop frequency, but that could go 1365 * into generic code. 1366 * 1367 * We won't take down the boot processor on i386 due to some 1368 * interrupts only being able to be serviced by the BSP. 1369 * Especially so if we're not using an IOAPIC -zwane 1370 */ 1371 if (cpu == 0) 1372 return -EBUSY; 1373 1374 if (nmi_watchdog == NMI_LOCAL_APIC) 1375 stop_apic_nmi_watchdog(NULL); 1376 clear_local_APIC(); 1377 1378 cpu_disable_common(); 1379 return 0; 1380 } 1381 1382 void native_cpu_die(unsigned int cpu) 1383 { 1384 /* We don't do anything here: idle task is faking death itself. */ 1385 unsigned int i; 1386 1387 for (i = 0; i < 10; i++) { 1388 /* They ack this in play_dead by setting CPU_DEAD */ 1389 if (per_cpu(cpu_state, cpu) == CPU_DEAD) { 1390 printk(KERN_INFO "CPU %d is now offline\n", cpu); 1391 if (1 == num_online_cpus()) 1392 alternatives_smp_switch(0); 1393 return; 1394 } 1395 msleep(100); 1396 } 1397 printk(KERN_ERR "CPU %u didn't die...\n", cpu); 1398 } 1399 1400 void play_dead_common(void) 1401 { 1402 idle_task_exit(); 1403 reset_lazy_tlbstate(); 1404 irq_ctx_exit(raw_smp_processor_id()); 1405 c1e_remove_cpu(raw_smp_processor_id()); 1406 1407 mb(); 1408 /* Ack it */ 1409 __get_cpu_var(cpu_state) = CPU_DEAD; 1410 1411 /* 1412 * With physical CPU hotplug, we should halt the cpu 1413 */ 1414 local_irq_disable(); 1415 } 1416 1417 void native_play_dead(void) 1418 { 1419 play_dead_common(); 1420 wbinvd_halt(); 1421 } 1422 1423 #else /* ... !CONFIG_HOTPLUG_CPU */ 1424 int native_cpu_disable(void) 1425 { 1426 return -ENOSYS; 1427 } 1428 1429 void native_cpu_die(unsigned int cpu) 1430 { 1431 /* We said "no" in __cpu_disable */ 1432 BUG(); 1433 } 1434 1435 void native_play_dead(void) 1436 { 1437 BUG(); 1438 } 1439 1440 #endif 1441