1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/module.h> 45 #include <linux/sched.h> 46 #include <linux/percpu.h> 47 #include <linux/bootmem.h> 48 #include <linux/err.h> 49 #include <linux/nmi.h> 50 #include <linux/tboot.h> 51 #include <linux/stackprotector.h> 52 #include <linux/gfp.h> 53 54 #include <asm/acpi.h> 55 #include <asm/desc.h> 56 #include <asm/nmi.h> 57 #include <asm/irq.h> 58 #include <asm/idle.h> 59 #include <asm/trampoline.h> 60 #include <asm/cpu.h> 61 #include <asm/numa.h> 62 #include <asm/pgtable.h> 63 #include <asm/tlbflush.h> 64 #include <asm/mtrr.h> 65 #include <asm/vmi.h> 66 #include <asm/apic.h> 67 #include <asm/setup.h> 68 #include <asm/uv/uv.h> 69 #include <linux/mc146818rtc.h> 70 71 #include <asm/smpboot_hooks.h> 72 #include <asm/i8259.h> 73 74 #ifdef CONFIG_X86_32 75 u8 apicid_2_node[MAX_APICID]; 76 static int low_mappings; 77 #endif 78 79 /* State of each CPU */ 80 DEFINE_PER_CPU(int, cpu_state) = { 0 }; 81 82 /* Store all idle threads, this can be reused instead of creating 83 * a new thread. Also avoids complicated thread destroy functionality 84 * for idle threads. 85 */ 86 #ifdef CONFIG_HOTPLUG_CPU 87 /* 88 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is 89 * removed after init for !CONFIG_HOTPLUG_CPU. 90 */ 91 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); 92 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) 93 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) 94 #else 95 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; 96 #define get_idle_for_cpu(x) (idle_thread_array[(x)]) 97 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) 98 #endif 99 100 /* Number of siblings per CPU package */ 101 int smp_num_siblings = 1; 102 EXPORT_SYMBOL(smp_num_siblings); 103 104 /* Last level cache ID of each logical CPU */ 105 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; 106 107 /* representing HT siblings of each logical CPU */ 108 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); 109 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 110 111 /* representing HT and core siblings of each logical CPU */ 112 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); 113 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 114 115 /* Per CPU bogomips and other parameters */ 116 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 117 EXPORT_PER_CPU_SYMBOL(cpu_info); 118 119 atomic_t init_deasserted; 120 121 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) 122 /* which node each logical CPU is on */ 123 int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; 124 EXPORT_SYMBOL(cpu_to_node_map); 125 126 /* set up a mapping between cpu and node. */ 127 static void map_cpu_to_node(int cpu, int node) 128 { 129 printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); 130 cpumask_set_cpu(cpu, node_to_cpumask_map[node]); 131 cpu_to_node_map[cpu] = node; 132 } 133 134 /* undo a mapping between cpu and node. */ 135 static void unmap_cpu_to_node(int cpu) 136 { 137 int node; 138 139 printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); 140 for (node = 0; node < MAX_NUMNODES; node++) 141 cpumask_clear_cpu(cpu, node_to_cpumask_map[node]); 142 cpu_to_node_map[cpu] = 0; 143 } 144 #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ 145 #define map_cpu_to_node(cpu, node) ({}) 146 #define unmap_cpu_to_node(cpu) ({}) 147 #endif 148 149 #ifdef CONFIG_X86_32 150 static int boot_cpu_logical_apicid; 151 152 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = 153 { [0 ... NR_CPUS-1] = BAD_APICID }; 154 155 static void map_cpu_to_logical_apicid(void) 156 { 157 int cpu = smp_processor_id(); 158 int apicid = logical_smp_processor_id(); 159 int node = apic->apicid_to_node(apicid); 160 161 if (!node_online(node)) 162 node = first_online_node; 163 164 cpu_2_logical_apicid[cpu] = apicid; 165 map_cpu_to_node(cpu, node); 166 } 167 168 void numa_remove_cpu(int cpu) 169 { 170 cpu_2_logical_apicid[cpu] = BAD_APICID; 171 unmap_cpu_to_node(cpu); 172 } 173 #else 174 #define map_cpu_to_logical_apicid() do {} while (0) 175 #endif 176 177 /* 178 * Report back to the Boot Processor. 179 * Running on AP. 180 */ 181 static void __cpuinit smp_callin(void) 182 { 183 int cpuid, phys_id; 184 unsigned long timeout; 185 186 /* 187 * If waken up by an INIT in an 82489DX configuration 188 * we may get here before an INIT-deassert IPI reaches 189 * our local APIC. We have to wait for the IPI or we'll 190 * lock up on an APIC access. 191 */ 192 if (apic->wait_for_init_deassert) 193 apic->wait_for_init_deassert(&init_deasserted); 194 195 /* 196 * (This works even if the APIC is not enabled.) 197 */ 198 phys_id = read_apic_id(); 199 cpuid = smp_processor_id(); 200 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { 201 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, 202 phys_id, cpuid); 203 } 204 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); 205 206 /* 207 * STARTUP IPIs are fragile beasts as they might sometimes 208 * trigger some glue motherboard logic. Complete APIC bus 209 * silence for 1 second, this overestimates the time the 210 * boot CPU is spending to send the up to 2 STARTUP IPIs 211 * by a factor of two. This should be enough. 212 */ 213 214 /* 215 * Waiting 2s total for startup (udelay is not yet working) 216 */ 217 timeout = jiffies + 2*HZ; 218 while (time_before(jiffies, timeout)) { 219 /* 220 * Has the boot CPU finished it's STARTUP sequence? 221 */ 222 if (cpumask_test_cpu(cpuid, cpu_callout_mask)) 223 break; 224 cpu_relax(); 225 } 226 227 if (!time_before(jiffies, timeout)) { 228 panic("%s: CPU%d started up but did not get a callout!\n", 229 __func__, cpuid); 230 } 231 232 /* 233 * the boot CPU has finished the init stage and is spinning 234 * on callin_map until we finish. We are free to set up this 235 * CPU, first the APIC. (this is probably redundant on most 236 * boards) 237 */ 238 239 pr_debug("CALLIN, before setup_local_APIC().\n"); 240 if (apic->smp_callin_clear_local_apic) 241 apic->smp_callin_clear_local_apic(); 242 setup_local_APIC(); 243 end_local_APIC_setup(); 244 map_cpu_to_logical_apicid(); 245 246 /* 247 * Need to setup vector mappings before we enable interrupts. 248 */ 249 setup_vector_irq(smp_processor_id()); 250 /* 251 * Get our bogomips. 252 * 253 * Need to enable IRQs because it can take longer and then 254 * the NMI watchdog might kill us. 255 */ 256 local_irq_enable(); 257 calibrate_delay(); 258 local_irq_disable(); 259 pr_debug("Stack at about %p\n", &cpuid); 260 261 /* 262 * Save our processor parameters 263 */ 264 smp_store_cpu_info(cpuid); 265 266 notify_cpu_starting(cpuid); 267 268 /* 269 * Allow the master to continue. 270 */ 271 cpumask_set_cpu(cpuid, cpu_callin_mask); 272 } 273 274 /* 275 * Activate a secondary processor. 276 */ 277 notrace static void __cpuinit start_secondary(void *unused) 278 { 279 /* 280 * Don't put *anything* before cpu_init(), SMP booting is too 281 * fragile that we want to limit the things done here to the 282 * most necessary things. 283 */ 284 vmi_bringup(); 285 cpu_init(); 286 preempt_disable(); 287 smp_callin(); 288 289 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 290 barrier(); 291 /* 292 * Check TSC synchronization with the BP: 293 */ 294 check_tsc_sync_target(); 295 296 if (nmi_watchdog == NMI_IO_APIC) { 297 legacy_pic->chip->mask(0); 298 enable_NMI_through_LVT0(); 299 legacy_pic->chip->unmask(0); 300 } 301 302 #ifdef CONFIG_X86_32 303 while (low_mappings) 304 cpu_relax(); 305 __flush_tlb_all(); 306 #endif 307 308 /* This must be done before setting cpu_online_mask */ 309 set_cpu_sibling_map(raw_smp_processor_id()); 310 wmb(); 311 312 /* 313 * We need to hold call_lock, so there is no inconsistency 314 * between the time smp_call_function() determines number of 315 * IPI recipients, and the time when the determination is made 316 * for which cpus receive the IPI. Holding this 317 * lock helps us to not include this cpu in a currently in progress 318 * smp_call_function(). 319 * 320 * We need to hold vector_lock so there the set of online cpus 321 * does not change while we are assigning vectors to cpus. Holding 322 * this lock ensures we don't half assign or remove an irq from a cpu. 323 */ 324 ipi_call_lock(); 325 lock_vector_lock(); 326 set_cpu_online(smp_processor_id(), true); 327 unlock_vector_lock(); 328 ipi_call_unlock(); 329 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; 330 x86_platform.nmi_init(); 331 332 /* enable local interrupts */ 333 local_irq_enable(); 334 335 /* to prevent fake stack check failure in clock setup */ 336 boot_init_stack_canary(); 337 338 x86_cpuinit.setup_percpu_clockev(); 339 340 wmb(); 341 cpu_idle(); 342 } 343 344 #ifdef CONFIG_CPUMASK_OFFSTACK 345 /* In this case, llc_shared_map is a pointer to a cpumask. */ 346 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, 347 const struct cpuinfo_x86 *src) 348 { 349 struct cpumask *llc = dst->llc_shared_map; 350 *dst = *src; 351 dst->llc_shared_map = llc; 352 } 353 #else 354 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, 355 const struct cpuinfo_x86 *src) 356 { 357 *dst = *src; 358 } 359 #endif /* CONFIG_CPUMASK_OFFSTACK */ 360 361 /* 362 * The bootstrap kernel entry code has set these up. Save them for 363 * a given CPU 364 */ 365 366 void __cpuinit smp_store_cpu_info(int id) 367 { 368 struct cpuinfo_x86 *c = &cpu_data(id); 369 370 copy_cpuinfo_x86(c, &boot_cpu_data); 371 c->cpu_index = id; 372 if (id != 0) 373 identify_secondary_cpu(c); 374 } 375 376 377 void __cpuinit set_cpu_sibling_map(int cpu) 378 { 379 int i; 380 struct cpuinfo_x86 *c = &cpu_data(cpu); 381 382 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 383 384 if (smp_num_siblings > 1) { 385 for_each_cpu(i, cpu_sibling_setup_mask) { 386 struct cpuinfo_x86 *o = &cpu_data(i); 387 388 if (c->phys_proc_id == o->phys_proc_id && 389 c->cpu_core_id == o->cpu_core_id) { 390 cpumask_set_cpu(i, cpu_sibling_mask(cpu)); 391 cpumask_set_cpu(cpu, cpu_sibling_mask(i)); 392 cpumask_set_cpu(i, cpu_core_mask(cpu)); 393 cpumask_set_cpu(cpu, cpu_core_mask(i)); 394 cpumask_set_cpu(i, c->llc_shared_map); 395 cpumask_set_cpu(cpu, o->llc_shared_map); 396 } 397 } 398 } else { 399 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); 400 } 401 402 cpumask_set_cpu(cpu, c->llc_shared_map); 403 404 if (current_cpu_data.x86_max_cores == 1) { 405 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); 406 c->booted_cores = 1; 407 return; 408 } 409 410 for_each_cpu(i, cpu_sibling_setup_mask) { 411 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && 412 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { 413 cpumask_set_cpu(i, c->llc_shared_map); 414 cpumask_set_cpu(cpu, cpu_data(i).llc_shared_map); 415 } 416 if (c->phys_proc_id == cpu_data(i).phys_proc_id) { 417 cpumask_set_cpu(i, cpu_core_mask(cpu)); 418 cpumask_set_cpu(cpu, cpu_core_mask(i)); 419 /* 420 * Does this new cpu bringup a new core? 421 */ 422 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { 423 /* 424 * for each core in package, increment 425 * the booted_cores for this new cpu 426 */ 427 if (cpumask_first(cpu_sibling_mask(i)) == i) 428 c->booted_cores++; 429 /* 430 * increment the core count for all 431 * the other cpus in this package 432 */ 433 if (i != cpu) 434 cpu_data(i).booted_cores++; 435 } else if (i != cpu && !c->booted_cores) 436 c->booted_cores = cpu_data(i).booted_cores; 437 } 438 } 439 } 440 441 /* maps the cpu to the sched domain representing multi-core */ 442 const struct cpumask *cpu_coregroup_mask(int cpu) 443 { 444 struct cpuinfo_x86 *c = &cpu_data(cpu); 445 /* 446 * For perf, we return last level cache shared map. 447 * And for power savings, we return cpu_core_map 448 */ 449 if ((sched_mc_power_savings || sched_smt_power_savings) && 450 !(cpu_has(c, X86_FEATURE_AMD_DCM))) 451 return cpu_core_mask(cpu); 452 else 453 return c->llc_shared_map; 454 } 455 456 static void impress_friends(void) 457 { 458 int cpu; 459 unsigned long bogosum = 0; 460 /* 461 * Allow the user to impress friends. 462 */ 463 pr_debug("Before bogomips.\n"); 464 for_each_possible_cpu(cpu) 465 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 466 bogosum += cpu_data(cpu).loops_per_jiffy; 467 printk(KERN_INFO 468 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", 469 num_online_cpus(), 470 bogosum/(500000/HZ), 471 (bogosum/(5000/HZ))%100); 472 473 pr_debug("Before bogocount - setting activated=1.\n"); 474 } 475 476 void __inquire_remote_apic(int apicid) 477 { 478 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 479 char *names[] = { "ID", "VERSION", "SPIV" }; 480 int timeout; 481 u32 status; 482 483 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); 484 485 for (i = 0; i < ARRAY_SIZE(regs); i++) { 486 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); 487 488 /* 489 * Wait for idle. 490 */ 491 status = safe_apic_wait_icr_idle(); 492 if (status) 493 printk(KERN_CONT 494 "a previous APIC delivery may have failed\n"); 495 496 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 497 498 timeout = 0; 499 do { 500 udelay(100); 501 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 502 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 503 504 switch (status) { 505 case APIC_ICR_RR_VALID: 506 status = apic_read(APIC_RRR); 507 printk(KERN_CONT "%08x\n", status); 508 break; 509 default: 510 printk(KERN_CONT "failed\n"); 511 } 512 } 513 } 514 515 /* 516 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 517 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 518 * won't ... remember to clear down the APIC, etc later. 519 */ 520 int __cpuinit 521 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) 522 { 523 unsigned long send_status, accept_status = 0; 524 int maxlvt; 525 526 /* Target chip */ 527 /* Boot on the stack */ 528 /* Kick the second */ 529 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); 530 531 pr_debug("Waiting for send to finish...\n"); 532 send_status = safe_apic_wait_icr_idle(); 533 534 /* 535 * Give the other CPU some time to accept the IPI. 536 */ 537 udelay(200); 538 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 539 maxlvt = lapic_get_maxlvt(); 540 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 541 apic_write(APIC_ESR, 0); 542 accept_status = (apic_read(APIC_ESR) & 0xEF); 543 } 544 pr_debug("NMI sent.\n"); 545 546 if (send_status) 547 printk(KERN_ERR "APIC never delivered???\n"); 548 if (accept_status) 549 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 550 551 return (send_status | accept_status); 552 } 553 554 static int __cpuinit 555 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 556 { 557 unsigned long send_status, accept_status = 0; 558 int maxlvt, num_starts, j; 559 560 maxlvt = lapic_get_maxlvt(); 561 562 /* 563 * Be paranoid about clearing APIC errors. 564 */ 565 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 566 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 567 apic_write(APIC_ESR, 0); 568 apic_read(APIC_ESR); 569 } 570 571 pr_debug("Asserting INIT.\n"); 572 573 /* 574 * Turn INIT on target chip 575 */ 576 /* 577 * Send IPI 578 */ 579 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 580 phys_apicid); 581 582 pr_debug("Waiting for send to finish...\n"); 583 send_status = safe_apic_wait_icr_idle(); 584 585 mdelay(10); 586 587 pr_debug("Deasserting INIT.\n"); 588 589 /* Target chip */ 590 /* Send IPI */ 591 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 592 593 pr_debug("Waiting for send to finish...\n"); 594 send_status = safe_apic_wait_icr_idle(); 595 596 mb(); 597 atomic_set(&init_deasserted, 1); 598 599 /* 600 * Should we send STARTUP IPIs ? 601 * 602 * Determine this based on the APIC version. 603 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 604 */ 605 if (APIC_INTEGRATED(apic_version[phys_apicid])) 606 num_starts = 2; 607 else 608 num_starts = 0; 609 610 /* 611 * Paravirt / VMI wants a startup IPI hook here to set up the 612 * target processor state. 613 */ 614 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, 615 (unsigned long)stack_start.sp); 616 617 /* 618 * Run STARTUP IPI loop. 619 */ 620 pr_debug("#startup loops: %d.\n", num_starts); 621 622 for (j = 1; j <= num_starts; j++) { 623 pr_debug("Sending STARTUP #%d.\n", j); 624 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 625 apic_write(APIC_ESR, 0); 626 apic_read(APIC_ESR); 627 pr_debug("After apic_write.\n"); 628 629 /* 630 * STARTUP IPI 631 */ 632 633 /* Target chip */ 634 /* Boot on the stack */ 635 /* Kick the second */ 636 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 637 phys_apicid); 638 639 /* 640 * Give the other CPU some time to accept the IPI. 641 */ 642 udelay(300); 643 644 pr_debug("Startup point 1.\n"); 645 646 pr_debug("Waiting for send to finish...\n"); 647 send_status = safe_apic_wait_icr_idle(); 648 649 /* 650 * Give the other CPU some time to accept the IPI. 651 */ 652 udelay(200); 653 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 654 apic_write(APIC_ESR, 0); 655 accept_status = (apic_read(APIC_ESR) & 0xEF); 656 if (send_status || accept_status) 657 break; 658 } 659 pr_debug("After Startup.\n"); 660 661 if (send_status) 662 printk(KERN_ERR "APIC never delivered???\n"); 663 if (accept_status) 664 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 665 666 return (send_status | accept_status); 667 } 668 669 struct create_idle { 670 struct work_struct work; 671 struct task_struct *idle; 672 struct completion done; 673 int cpu; 674 }; 675 676 static void __cpuinit do_fork_idle(struct work_struct *work) 677 { 678 struct create_idle *c_idle = 679 container_of(work, struct create_idle, work); 680 681 c_idle->idle = fork_idle(c_idle->cpu); 682 complete(&c_idle->done); 683 } 684 685 /* reduce the number of lines printed when booting a large cpu count system */ 686 static void __cpuinit announce_cpu(int cpu, int apicid) 687 { 688 static int current_node = -1; 689 int node = cpu_to_node(cpu); 690 691 if (system_state == SYSTEM_BOOTING) { 692 if (node != current_node) { 693 if (current_node > (-1)) 694 pr_cont(" Ok.\n"); 695 current_node = node; 696 pr_info("Booting Node %3d, Processors ", node); 697 } 698 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : ""); 699 return; 700 } else 701 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 702 node, cpu, apicid); 703 } 704 705 /* 706 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 707 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 708 * Returns zero if CPU booted OK, else error code from 709 * ->wakeup_secondary_cpu. 710 */ 711 static int __cpuinit do_boot_cpu(int apicid, int cpu) 712 { 713 unsigned long boot_error = 0; 714 unsigned long start_ip; 715 int timeout; 716 struct create_idle c_idle = { 717 .cpu = cpu, 718 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), 719 }; 720 721 INIT_WORK_ON_STACK(&c_idle.work, do_fork_idle); 722 723 alternatives_smp_switch(1); 724 725 c_idle.idle = get_idle_for_cpu(cpu); 726 727 /* 728 * We can't use kernel_thread since we must avoid to 729 * reschedule the child. 730 */ 731 if (c_idle.idle) { 732 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) 733 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); 734 init_idle(c_idle.idle, cpu); 735 goto do_rest; 736 } 737 738 if (!keventd_up() || current_is_keventd()) 739 c_idle.work.func(&c_idle.work); 740 else { 741 schedule_work(&c_idle.work); 742 wait_for_completion(&c_idle.done); 743 } 744 745 if (IS_ERR(c_idle.idle)) { 746 printk("failed fork for CPU %d\n", cpu); 747 destroy_work_on_stack(&c_idle.work); 748 return PTR_ERR(c_idle.idle); 749 } 750 751 set_idle_for_cpu(cpu, c_idle.idle); 752 do_rest: 753 per_cpu(current_task, cpu) = c_idle.idle; 754 #ifdef CONFIG_X86_32 755 /* Stack for startup_32 can be just as for start_secondary onwards */ 756 irq_ctx_init(cpu); 757 #else 758 clear_tsk_thread_flag(c_idle.idle, TIF_FORK); 759 initial_gs = per_cpu_offset(cpu); 760 per_cpu(kernel_stack, cpu) = 761 (unsigned long)task_stack_page(c_idle.idle) - 762 KERNEL_STACK_OFFSET + THREAD_SIZE; 763 #endif 764 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 765 initial_code = (unsigned long)start_secondary; 766 stack_start.sp = (void *) c_idle.idle->thread.sp; 767 768 /* start_ip had better be page-aligned! */ 769 start_ip = setup_trampoline(); 770 771 /* So we see what's up */ 772 announce_cpu(cpu, apicid); 773 774 /* 775 * This grunge runs the startup process for 776 * the targeted processor. 777 */ 778 779 atomic_set(&init_deasserted, 0); 780 781 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 782 783 pr_debug("Setting warm reset code and vector.\n"); 784 785 smpboot_setup_warm_reset_vector(start_ip); 786 /* 787 * Be paranoid about clearing APIC errors. 788 */ 789 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 790 apic_write(APIC_ESR, 0); 791 apic_read(APIC_ESR); 792 } 793 } 794 795 /* 796 * Kick the secondary CPU. Use the method in the APIC driver 797 * if it's defined - or use an INIT boot APIC message otherwise: 798 */ 799 if (apic->wakeup_secondary_cpu) 800 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 801 else 802 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 803 804 if (!boot_error) { 805 /* 806 * allow APs to start initializing. 807 */ 808 pr_debug("Before Callout %d.\n", cpu); 809 cpumask_set_cpu(cpu, cpu_callout_mask); 810 pr_debug("After Callout %d.\n", cpu); 811 812 /* 813 * Wait 5s total for a response 814 */ 815 for (timeout = 0; timeout < 50000; timeout++) { 816 if (cpumask_test_cpu(cpu, cpu_callin_mask)) 817 break; /* It has booted */ 818 udelay(100); 819 } 820 821 if (cpumask_test_cpu(cpu, cpu_callin_mask)) 822 pr_debug("CPU%d: has booted.\n", cpu); 823 else { 824 boot_error = 1; 825 if (*((volatile unsigned char *)trampoline_base) 826 == 0xA5) 827 /* trampoline started but...? */ 828 pr_err("CPU%d: Stuck ??\n", cpu); 829 else 830 /* trampoline code not run */ 831 pr_err("CPU%d: Not responding.\n", cpu); 832 if (apic->inquire_remote_apic) 833 apic->inquire_remote_apic(apicid); 834 } 835 } 836 837 if (boot_error) { 838 /* Try to put things back the way they were before ... */ 839 numa_remove_cpu(cpu); /* was set by numa_add_cpu */ 840 841 /* was set by do_boot_cpu() */ 842 cpumask_clear_cpu(cpu, cpu_callout_mask); 843 844 /* was set by cpu_init() */ 845 cpumask_clear_cpu(cpu, cpu_initialized_mask); 846 847 set_cpu_present(cpu, false); 848 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; 849 } 850 851 /* mark "stuck" area as not stuck */ 852 *((volatile unsigned long *)trampoline_base) = 0; 853 854 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 855 /* 856 * Cleanup possible dangling ends... 857 */ 858 smpboot_restore_warm_reset_vector(); 859 } 860 861 destroy_work_on_stack(&c_idle.work); 862 return boot_error; 863 } 864 865 int __cpuinit native_cpu_up(unsigned int cpu) 866 { 867 int apicid = apic->cpu_present_to_apicid(cpu); 868 unsigned long flags; 869 int err; 870 871 WARN_ON(irqs_disabled()); 872 873 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 874 875 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || 876 !physid_isset(apicid, phys_cpu_present_map)) { 877 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); 878 return -EINVAL; 879 } 880 881 /* 882 * Already booted CPU? 883 */ 884 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 885 pr_debug("do_boot_cpu %d Already started\n", cpu); 886 return -ENOSYS; 887 } 888 889 /* 890 * Save current MTRR state in case it was changed since early boot 891 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 892 */ 893 mtrr_save_state(); 894 895 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; 896 897 #ifdef CONFIG_X86_32 898 /* init low mem mapping */ 899 clone_pgd_range(swapper_pg_dir, swapper_pg_dir + KERNEL_PGD_BOUNDARY, 900 min_t(unsigned long, KERNEL_PGD_PTRS, KERNEL_PGD_BOUNDARY)); 901 flush_tlb_all(); 902 low_mappings = 1; 903 904 err = do_boot_cpu(apicid, cpu); 905 906 zap_low_mappings(false); 907 low_mappings = 0; 908 #else 909 err = do_boot_cpu(apicid, cpu); 910 #endif 911 if (err) { 912 pr_debug("do_boot_cpu failed %d\n", err); 913 return -EIO; 914 } 915 916 /* 917 * Check TSC synchronization with the AP (keep irqs disabled 918 * while doing so): 919 */ 920 local_irq_save(flags); 921 check_tsc_sync_source(cpu); 922 local_irq_restore(flags); 923 924 while (!cpu_online(cpu)) { 925 cpu_relax(); 926 touch_nmi_watchdog(); 927 } 928 929 return 0; 930 } 931 932 /* 933 * Fall back to non SMP mode after errors. 934 * 935 * RED-PEN audit/test this more. I bet there is more state messed up here. 936 */ 937 static __init void disable_smp(void) 938 { 939 init_cpu_present(cpumask_of(0)); 940 init_cpu_possible(cpumask_of(0)); 941 smpboot_clear_io_apic_irqs(); 942 943 if (smp_found_config) 944 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 945 else 946 physid_set_mask_of_physid(0, &phys_cpu_present_map); 947 map_cpu_to_logical_apicid(); 948 cpumask_set_cpu(0, cpu_sibling_mask(0)); 949 cpumask_set_cpu(0, cpu_core_mask(0)); 950 } 951 952 /* 953 * Various sanity checks. 954 */ 955 static int __init smp_sanity_check(unsigned max_cpus) 956 { 957 preempt_disable(); 958 959 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 960 if (def_to_bigsmp && nr_cpu_ids > 8) { 961 unsigned int cpu; 962 unsigned nr; 963 964 printk(KERN_WARNING 965 "More than 8 CPUs detected - skipping them.\n" 966 "Use CONFIG_X86_BIGSMP.\n"); 967 968 nr = 0; 969 for_each_present_cpu(cpu) { 970 if (nr >= 8) 971 set_cpu_present(cpu, false); 972 nr++; 973 } 974 975 nr = 0; 976 for_each_possible_cpu(cpu) { 977 if (nr >= 8) 978 set_cpu_possible(cpu, false); 979 nr++; 980 } 981 982 nr_cpu_ids = 8; 983 } 984 #endif 985 986 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 987 printk(KERN_WARNING 988 "weird, boot CPU (#%d) not listed by the BIOS.\n", 989 hard_smp_processor_id()); 990 991 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 992 } 993 994 /* 995 * If we couldn't find an SMP configuration at boot time, 996 * get out of here now! 997 */ 998 if (!smp_found_config && !acpi_lapic) { 999 preempt_enable(); 1000 printk(KERN_NOTICE "SMP motherboard not detected.\n"); 1001 disable_smp(); 1002 if (APIC_init_uniprocessor()) 1003 printk(KERN_NOTICE "Local APIC not detected." 1004 " Using dummy APIC emulation.\n"); 1005 return -1; 1006 } 1007 1008 /* 1009 * Should not be necessary because the MP table should list the boot 1010 * CPU too, but we do it for the sake of robustness anyway. 1011 */ 1012 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1013 printk(KERN_NOTICE 1014 "weird, boot CPU (#%d) not listed by the BIOS.\n", 1015 boot_cpu_physical_apicid); 1016 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1017 } 1018 preempt_enable(); 1019 1020 /* 1021 * If we couldn't find a local APIC, then get out of here now! 1022 */ 1023 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 1024 !cpu_has_apic) { 1025 if (!disable_apic) { 1026 pr_err("BIOS bug, local APIC #%d not detected!...\n", 1027 boot_cpu_physical_apicid); 1028 pr_err("... forcing use of dummy APIC emulation." 1029 "(tell your hw vendor)\n"); 1030 } 1031 smpboot_clear_io_apic(); 1032 arch_disable_smp_support(); 1033 return -1; 1034 } 1035 1036 verify_local_APIC(); 1037 1038 /* 1039 * If SMP should be disabled, then really disable it! 1040 */ 1041 if (!max_cpus) { 1042 printk(KERN_INFO "SMP mode deactivated.\n"); 1043 smpboot_clear_io_apic(); 1044 1045 localise_nmi_watchdog(); 1046 1047 connect_bsp_APIC(); 1048 setup_local_APIC(); 1049 end_local_APIC_setup(); 1050 return -1; 1051 } 1052 1053 return 0; 1054 } 1055 1056 static void __init smp_cpu_index_default(void) 1057 { 1058 int i; 1059 struct cpuinfo_x86 *c; 1060 1061 for_each_possible_cpu(i) { 1062 c = &cpu_data(i); 1063 /* mark all to hotplug */ 1064 c->cpu_index = nr_cpu_ids; 1065 } 1066 } 1067 1068 /* 1069 * Prepare for SMP bootup. The MP table or ACPI has been read 1070 * earlier. Just do some sanity checking here and enable APIC mode. 1071 */ 1072 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1073 { 1074 unsigned int i; 1075 1076 preempt_disable(); 1077 smp_cpu_index_default(); 1078 current_cpu_data = boot_cpu_data; 1079 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1080 mb(); 1081 /* 1082 * Setup boot CPU information 1083 */ 1084 smp_store_cpu_info(0); /* Final full version of the data */ 1085 #ifdef CONFIG_X86_32 1086 boot_cpu_logical_apicid = logical_smp_processor_id(); 1087 #endif 1088 current_thread_info()->cpu = 0; /* needed? */ 1089 for_each_possible_cpu(i) { 1090 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1091 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1092 zalloc_cpumask_var(&cpu_data(i).llc_shared_map, GFP_KERNEL); 1093 } 1094 set_cpu_sibling_map(0); 1095 1096 enable_IR_x2apic(); 1097 default_setup_apic_routing(); 1098 1099 if (smp_sanity_check(max_cpus) < 0) { 1100 printk(KERN_INFO "SMP disabled\n"); 1101 disable_smp(); 1102 goto out; 1103 } 1104 1105 preempt_disable(); 1106 if (read_apic_id() != boot_cpu_physical_apicid) { 1107 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1108 read_apic_id(), boot_cpu_physical_apicid); 1109 /* Or can we switch back to PIC here? */ 1110 } 1111 preempt_enable(); 1112 1113 connect_bsp_APIC(); 1114 1115 /* 1116 * Switch from PIC to APIC mode. 1117 */ 1118 setup_local_APIC(); 1119 1120 /* 1121 * Enable IO APIC before setting up error vector 1122 */ 1123 if (!skip_ioapic_setup && nr_ioapics) 1124 enable_IO_APIC(); 1125 1126 end_local_APIC_setup(); 1127 1128 map_cpu_to_logical_apicid(); 1129 1130 if (apic->setup_portio_remap) 1131 apic->setup_portio_remap(); 1132 1133 smpboot_setup_io_apic(); 1134 /* 1135 * Set up local APIC timer on boot CPU. 1136 */ 1137 1138 printk(KERN_INFO "CPU%d: ", 0); 1139 print_cpu_info(&cpu_data(0)); 1140 x86_init.timers.setup_percpu_clockev(); 1141 1142 if (is_uv_system()) 1143 uv_system_init(); 1144 1145 set_mtrr_aps_delayed_init(); 1146 out: 1147 preempt_enable(); 1148 } 1149 1150 void arch_enable_nonboot_cpus_begin(void) 1151 { 1152 set_mtrr_aps_delayed_init(); 1153 } 1154 1155 void arch_enable_nonboot_cpus_end(void) 1156 { 1157 mtrr_aps_init(); 1158 } 1159 1160 /* 1161 * Early setup to make printk work. 1162 */ 1163 void __init native_smp_prepare_boot_cpu(void) 1164 { 1165 int me = smp_processor_id(); 1166 switch_to_new_gdt(me); 1167 /* already set me in cpu_online_mask in boot_cpu_init() */ 1168 cpumask_set_cpu(me, cpu_callout_mask); 1169 per_cpu(cpu_state, me) = CPU_ONLINE; 1170 } 1171 1172 void __init native_smp_cpus_done(unsigned int max_cpus) 1173 { 1174 pr_debug("Boot done.\n"); 1175 1176 impress_friends(); 1177 #ifdef CONFIG_X86_IO_APIC 1178 setup_ioapic_dest(); 1179 #endif 1180 check_nmi_watchdog(); 1181 mtrr_aps_init(); 1182 } 1183 1184 static int __initdata setup_possible_cpus = -1; 1185 static int __init _setup_possible_cpus(char *str) 1186 { 1187 get_option(&str, &setup_possible_cpus); 1188 return 0; 1189 } 1190 early_param("possible_cpus", _setup_possible_cpus); 1191 1192 1193 /* 1194 * cpu_possible_mask should be static, it cannot change as cpu's 1195 * are onlined, or offlined. The reason is per-cpu data-structures 1196 * are allocated by some modules at init time, and dont expect to 1197 * do this dynamically on cpu arrival/departure. 1198 * cpu_present_mask on the other hand can change dynamically. 1199 * In case when cpu_hotplug is not compiled, then we resort to current 1200 * behaviour, which is cpu_possible == cpu_present. 1201 * - Ashok Raj 1202 * 1203 * Three ways to find out the number of additional hotplug CPUs: 1204 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1205 * - The user can overwrite it with possible_cpus=NUM 1206 * - Otherwise don't reserve additional CPUs. 1207 * We do this because additional CPUs waste a lot of memory. 1208 * -AK 1209 */ 1210 __init void prefill_possible_map(void) 1211 { 1212 int i, possible; 1213 1214 /* no processor from mptable or madt */ 1215 if (!num_processors) 1216 num_processors = 1; 1217 1218 if (setup_possible_cpus == -1) 1219 possible = num_processors + disabled_cpus; 1220 else 1221 possible = setup_possible_cpus; 1222 1223 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1224 1225 /* nr_cpu_ids could be reduced via nr_cpus= */ 1226 if (possible > nr_cpu_ids) { 1227 printk(KERN_WARNING 1228 "%d Processors exceeds NR_CPUS limit of %d\n", 1229 possible, nr_cpu_ids); 1230 possible = nr_cpu_ids; 1231 } 1232 1233 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", 1234 possible, max_t(int, possible - num_processors, 0)); 1235 1236 for (i = 0; i < possible; i++) 1237 set_cpu_possible(i, true); 1238 1239 nr_cpu_ids = possible; 1240 } 1241 1242 #ifdef CONFIG_HOTPLUG_CPU 1243 1244 static void remove_siblinginfo(int cpu) 1245 { 1246 int sibling; 1247 struct cpuinfo_x86 *c = &cpu_data(cpu); 1248 1249 for_each_cpu(sibling, cpu_core_mask(cpu)) { 1250 cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); 1251 /*/ 1252 * last thread sibling in this cpu core going down 1253 */ 1254 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) 1255 cpu_data(sibling).booted_cores--; 1256 } 1257 1258 for_each_cpu(sibling, cpu_sibling_mask(cpu)) 1259 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); 1260 cpumask_clear(cpu_sibling_mask(cpu)); 1261 cpumask_clear(cpu_core_mask(cpu)); 1262 c->phys_proc_id = 0; 1263 c->cpu_core_id = 0; 1264 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1265 } 1266 1267 static void __ref remove_cpu_from_maps(int cpu) 1268 { 1269 set_cpu_online(cpu, false); 1270 cpumask_clear_cpu(cpu, cpu_callout_mask); 1271 cpumask_clear_cpu(cpu, cpu_callin_mask); 1272 /* was set by cpu_init() */ 1273 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1274 numa_remove_cpu(cpu); 1275 } 1276 1277 void cpu_disable_common(void) 1278 { 1279 int cpu = smp_processor_id(); 1280 1281 remove_siblinginfo(cpu); 1282 1283 /* It's now safe to remove this processor from the online map */ 1284 lock_vector_lock(); 1285 remove_cpu_from_maps(cpu); 1286 unlock_vector_lock(); 1287 fixup_irqs(); 1288 } 1289 1290 int native_cpu_disable(void) 1291 { 1292 int cpu = smp_processor_id(); 1293 1294 /* 1295 * Perhaps use cpufreq to drop frequency, but that could go 1296 * into generic code. 1297 * 1298 * We won't take down the boot processor on i386 due to some 1299 * interrupts only being able to be serviced by the BSP. 1300 * Especially so if we're not using an IOAPIC -zwane 1301 */ 1302 if (cpu == 0) 1303 return -EBUSY; 1304 1305 if (nmi_watchdog == NMI_LOCAL_APIC) 1306 stop_apic_nmi_watchdog(NULL); 1307 clear_local_APIC(); 1308 1309 cpu_disable_common(); 1310 return 0; 1311 } 1312 1313 void native_cpu_die(unsigned int cpu) 1314 { 1315 /* We don't do anything here: idle task is faking death itself. */ 1316 unsigned int i; 1317 1318 for (i = 0; i < 10; i++) { 1319 /* They ack this in play_dead by setting CPU_DEAD */ 1320 if (per_cpu(cpu_state, cpu) == CPU_DEAD) { 1321 if (system_state == SYSTEM_RUNNING) 1322 pr_info("CPU %u is now offline\n", cpu); 1323 1324 if (1 == num_online_cpus()) 1325 alternatives_smp_switch(0); 1326 return; 1327 } 1328 msleep(100); 1329 } 1330 pr_err("CPU %u didn't die...\n", cpu); 1331 } 1332 1333 void play_dead_common(void) 1334 { 1335 idle_task_exit(); 1336 reset_lazy_tlbstate(); 1337 irq_ctx_exit(raw_smp_processor_id()); 1338 c1e_remove_cpu(raw_smp_processor_id()); 1339 1340 mb(); 1341 /* Ack it */ 1342 __get_cpu_var(cpu_state) = CPU_DEAD; 1343 1344 /* 1345 * With physical CPU hotplug, we should halt the cpu 1346 */ 1347 local_irq_disable(); 1348 } 1349 1350 void native_play_dead(void) 1351 { 1352 play_dead_common(); 1353 tboot_shutdown(TB_SHUTDOWN_WFS); 1354 wbinvd_halt(); 1355 } 1356 1357 #else /* ... !CONFIG_HOTPLUG_CPU */ 1358 int native_cpu_disable(void) 1359 { 1360 return -ENOSYS; 1361 } 1362 1363 void native_cpu_die(unsigned int cpu) 1364 { 1365 /* We said "no" in __cpu_disable */ 1366 BUG(); 1367 } 1368 1369 void native_play_dead(void) 1370 { 1371 BUG(); 1372 } 1373 1374 #endif 1375