1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/module.h> 45 #include <linux/sched.h> 46 #include <linux/percpu.h> 47 #include <linux/bootmem.h> 48 #include <linux/err.h> 49 #include <linux/nmi.h> 50 #include <linux/tboot.h> 51 #include <linux/stackprotector.h> 52 #include <linux/gfp.h> 53 54 #include <asm/acpi.h> 55 #include <asm/desc.h> 56 #include <asm/nmi.h> 57 #include <asm/irq.h> 58 #include <asm/idle.h> 59 #include <asm/trampoline.h> 60 #include <asm/cpu.h> 61 #include <asm/numa.h> 62 #include <asm/pgtable.h> 63 #include <asm/tlbflush.h> 64 #include <asm/mtrr.h> 65 #include <asm/mwait.h> 66 #include <asm/apic.h> 67 #include <asm/io_apic.h> 68 #include <asm/setup.h> 69 #include <asm/uv/uv.h> 70 #include <linux/mc146818rtc.h> 71 72 #include <asm/smpboot_hooks.h> 73 #include <asm/i8259.h> 74 75 /* State of each CPU */ 76 DEFINE_PER_CPU(int, cpu_state) = { 0 }; 77 78 /* Store all idle threads, this can be reused instead of creating 79 * a new thread. Also avoids complicated thread destroy functionality 80 * for idle threads. 81 */ 82 #ifdef CONFIG_HOTPLUG_CPU 83 /* 84 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is 85 * removed after init for !CONFIG_HOTPLUG_CPU. 86 */ 87 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); 88 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) 89 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) 90 91 /* 92 * We need this for trampoline_base protection from concurrent accesses when 93 * off- and onlining cores wildly. 94 */ 95 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex); 96 97 void cpu_hotplug_driver_lock(void) 98 { 99 mutex_lock(&x86_cpu_hotplug_driver_mutex); 100 } 101 102 void cpu_hotplug_driver_unlock(void) 103 { 104 mutex_unlock(&x86_cpu_hotplug_driver_mutex); 105 } 106 107 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; } 108 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; } 109 #else 110 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; 111 #define get_idle_for_cpu(x) (idle_thread_array[(x)]) 112 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) 113 #endif 114 115 /* Number of siblings per CPU package */ 116 int smp_num_siblings = 1; 117 EXPORT_SYMBOL(smp_num_siblings); 118 119 /* Last level cache ID of each logical CPU */ 120 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; 121 122 /* representing HT siblings of each logical CPU */ 123 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); 124 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 125 126 /* representing HT and core siblings of each logical CPU */ 127 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); 128 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 129 130 DEFINE_PER_CPU(cpumask_var_t, cpu_llc_shared_map); 131 132 /* Per CPU bogomips and other parameters */ 133 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 134 EXPORT_PER_CPU_SYMBOL(cpu_info); 135 136 atomic_t init_deasserted; 137 138 /* 139 * Report back to the Boot Processor. 140 * Running on AP. 141 */ 142 static void __cpuinit smp_callin(void) 143 { 144 int cpuid, phys_id; 145 unsigned long timeout; 146 147 /* 148 * If waken up by an INIT in an 82489DX configuration 149 * we may get here before an INIT-deassert IPI reaches 150 * our local APIC. We have to wait for the IPI or we'll 151 * lock up on an APIC access. 152 */ 153 if (apic->wait_for_init_deassert) 154 apic->wait_for_init_deassert(&init_deasserted); 155 156 /* 157 * (This works even if the APIC is not enabled.) 158 */ 159 phys_id = read_apic_id(); 160 cpuid = smp_processor_id(); 161 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { 162 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, 163 phys_id, cpuid); 164 } 165 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); 166 167 /* 168 * STARTUP IPIs are fragile beasts as they might sometimes 169 * trigger some glue motherboard logic. Complete APIC bus 170 * silence for 1 second, this overestimates the time the 171 * boot CPU is spending to send the up to 2 STARTUP IPIs 172 * by a factor of two. This should be enough. 173 */ 174 175 /* 176 * Waiting 2s total for startup (udelay is not yet working) 177 */ 178 timeout = jiffies + 2*HZ; 179 while (time_before(jiffies, timeout)) { 180 /* 181 * Has the boot CPU finished it's STARTUP sequence? 182 */ 183 if (cpumask_test_cpu(cpuid, cpu_callout_mask)) 184 break; 185 cpu_relax(); 186 } 187 188 if (!time_before(jiffies, timeout)) { 189 panic("%s: CPU%d started up but did not get a callout!\n", 190 __func__, cpuid); 191 } 192 193 /* 194 * the boot CPU has finished the init stage and is spinning 195 * on callin_map until we finish. We are free to set up this 196 * CPU, first the APIC. (this is probably redundant on most 197 * boards) 198 */ 199 200 pr_debug("CALLIN, before setup_local_APIC().\n"); 201 if (apic->smp_callin_clear_local_apic) 202 apic->smp_callin_clear_local_apic(); 203 setup_local_APIC(); 204 end_local_APIC_setup(); 205 206 /* 207 * Need to setup vector mappings before we enable interrupts. 208 */ 209 setup_vector_irq(smp_processor_id()); 210 211 /* 212 * Save our processor parameters. Note: this information 213 * is needed for clock calibration. 214 */ 215 smp_store_cpu_info(cpuid); 216 217 /* 218 * Get our bogomips. 219 * Update loops_per_jiffy in cpu_data. Previous call to 220 * smp_store_cpu_info() stored a value that is close but not as 221 * accurate as the value just calculated. 222 * 223 * Need to enable IRQs because it can take longer and then 224 * the NMI watchdog might kill us. 225 */ 226 local_irq_enable(); 227 calibrate_delay(); 228 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 229 local_irq_disable(); 230 pr_debug("Stack at about %p\n", &cpuid); 231 232 /* 233 * This must be done before setting cpu_online_mask 234 * or calling notify_cpu_starting. 235 */ 236 set_cpu_sibling_map(raw_smp_processor_id()); 237 wmb(); 238 239 notify_cpu_starting(cpuid); 240 241 /* 242 * Allow the master to continue. 243 */ 244 cpumask_set_cpu(cpuid, cpu_callin_mask); 245 } 246 247 /* 248 * Activate a secondary processor. 249 */ 250 notrace static void __cpuinit start_secondary(void *unused) 251 { 252 /* 253 * Don't put *anything* before cpu_init(), SMP booting is too 254 * fragile that we want to limit the things done here to the 255 * most necessary things. 256 */ 257 cpu_init(); 258 preempt_disable(); 259 smp_callin(); 260 261 #ifdef CONFIG_X86_32 262 /* switch away from the initial page table */ 263 load_cr3(swapper_pg_dir); 264 __flush_tlb_all(); 265 #endif 266 267 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 268 barrier(); 269 /* 270 * Check TSC synchronization with the BP: 271 */ 272 check_tsc_sync_target(); 273 274 /* 275 * We need to hold call_lock, so there is no inconsistency 276 * between the time smp_call_function() determines number of 277 * IPI recipients, and the time when the determination is made 278 * for which cpus receive the IPI. Holding this 279 * lock helps us to not include this cpu in a currently in progress 280 * smp_call_function(). 281 * 282 * We need to hold vector_lock so there the set of online cpus 283 * does not change while we are assigning vectors to cpus. Holding 284 * this lock ensures we don't half assign or remove an irq from a cpu. 285 */ 286 ipi_call_lock(); 287 lock_vector_lock(); 288 set_cpu_online(smp_processor_id(), true); 289 unlock_vector_lock(); 290 ipi_call_unlock(); 291 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; 292 x86_platform.nmi_init(); 293 294 /* enable local interrupts */ 295 local_irq_enable(); 296 297 /* to prevent fake stack check failure in clock setup */ 298 boot_init_stack_canary(); 299 300 x86_cpuinit.setup_percpu_clockev(); 301 302 wmb(); 303 cpu_idle(); 304 } 305 306 /* 307 * The bootstrap kernel entry code has set these up. Save them for 308 * a given CPU 309 */ 310 311 void __cpuinit smp_store_cpu_info(int id) 312 { 313 struct cpuinfo_x86 *c = &cpu_data(id); 314 315 *c = boot_cpu_data; 316 c->cpu_index = id; 317 if (id != 0) 318 identify_secondary_cpu(c); 319 } 320 321 static void __cpuinit link_thread_siblings(int cpu1, int cpu2) 322 { 323 cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2)); 324 cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1)); 325 cpumask_set_cpu(cpu1, cpu_core_mask(cpu2)); 326 cpumask_set_cpu(cpu2, cpu_core_mask(cpu1)); 327 cpumask_set_cpu(cpu1, cpu_llc_shared_mask(cpu2)); 328 cpumask_set_cpu(cpu2, cpu_llc_shared_mask(cpu1)); 329 } 330 331 332 void __cpuinit set_cpu_sibling_map(int cpu) 333 { 334 int i; 335 struct cpuinfo_x86 *c = &cpu_data(cpu); 336 337 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 338 339 if (smp_num_siblings > 1) { 340 for_each_cpu(i, cpu_sibling_setup_mask) { 341 struct cpuinfo_x86 *o = &cpu_data(i); 342 343 if (cpu_has(c, X86_FEATURE_TOPOEXT)) { 344 if (c->phys_proc_id == o->phys_proc_id && 345 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i) && 346 c->compute_unit_id == o->compute_unit_id) 347 link_thread_siblings(cpu, i); 348 } else if (c->phys_proc_id == o->phys_proc_id && 349 c->cpu_core_id == o->cpu_core_id) { 350 link_thread_siblings(cpu, i); 351 } 352 } 353 } else { 354 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); 355 } 356 357 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 358 359 if (__this_cpu_read(cpu_info.x86_max_cores) == 1) { 360 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); 361 c->booted_cores = 1; 362 return; 363 } 364 365 for_each_cpu(i, cpu_sibling_setup_mask) { 366 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && 367 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { 368 cpumask_set_cpu(i, cpu_llc_shared_mask(cpu)); 369 cpumask_set_cpu(cpu, cpu_llc_shared_mask(i)); 370 } 371 if (c->phys_proc_id == cpu_data(i).phys_proc_id) { 372 cpumask_set_cpu(i, cpu_core_mask(cpu)); 373 cpumask_set_cpu(cpu, cpu_core_mask(i)); 374 /* 375 * Does this new cpu bringup a new core? 376 */ 377 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { 378 /* 379 * for each core in package, increment 380 * the booted_cores for this new cpu 381 */ 382 if (cpumask_first(cpu_sibling_mask(i)) == i) 383 c->booted_cores++; 384 /* 385 * increment the core count for all 386 * the other cpus in this package 387 */ 388 if (i != cpu) 389 cpu_data(i).booted_cores++; 390 } else if (i != cpu && !c->booted_cores) 391 c->booted_cores = cpu_data(i).booted_cores; 392 } 393 } 394 } 395 396 /* maps the cpu to the sched domain representing multi-core */ 397 const struct cpumask *cpu_coregroup_mask(int cpu) 398 { 399 struct cpuinfo_x86 *c = &cpu_data(cpu); 400 /* 401 * For perf, we return last level cache shared map. 402 * And for power savings, we return cpu_core_map 403 */ 404 if ((sched_mc_power_savings || sched_smt_power_savings) && 405 !(cpu_has(c, X86_FEATURE_AMD_DCM))) 406 return cpu_core_mask(cpu); 407 else 408 return cpu_llc_shared_mask(cpu); 409 } 410 411 static void impress_friends(void) 412 { 413 int cpu; 414 unsigned long bogosum = 0; 415 /* 416 * Allow the user to impress friends. 417 */ 418 pr_debug("Before bogomips.\n"); 419 for_each_possible_cpu(cpu) 420 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 421 bogosum += cpu_data(cpu).loops_per_jiffy; 422 printk(KERN_INFO 423 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", 424 num_online_cpus(), 425 bogosum/(500000/HZ), 426 (bogosum/(5000/HZ))%100); 427 428 pr_debug("Before bogocount - setting activated=1.\n"); 429 } 430 431 void __inquire_remote_apic(int apicid) 432 { 433 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 434 const char * const names[] = { "ID", "VERSION", "SPIV" }; 435 int timeout; 436 u32 status; 437 438 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); 439 440 for (i = 0; i < ARRAY_SIZE(regs); i++) { 441 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); 442 443 /* 444 * Wait for idle. 445 */ 446 status = safe_apic_wait_icr_idle(); 447 if (status) 448 printk(KERN_CONT 449 "a previous APIC delivery may have failed\n"); 450 451 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 452 453 timeout = 0; 454 do { 455 udelay(100); 456 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 457 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 458 459 switch (status) { 460 case APIC_ICR_RR_VALID: 461 status = apic_read(APIC_RRR); 462 printk(KERN_CONT "%08x\n", status); 463 break; 464 default: 465 printk(KERN_CONT "failed\n"); 466 } 467 } 468 } 469 470 /* 471 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 472 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 473 * won't ... remember to clear down the APIC, etc later. 474 */ 475 int __cpuinit 476 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) 477 { 478 unsigned long send_status, accept_status = 0; 479 int maxlvt; 480 481 /* Target chip */ 482 /* Boot on the stack */ 483 /* Kick the second */ 484 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); 485 486 pr_debug("Waiting for send to finish...\n"); 487 send_status = safe_apic_wait_icr_idle(); 488 489 /* 490 * Give the other CPU some time to accept the IPI. 491 */ 492 udelay(200); 493 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 494 maxlvt = lapic_get_maxlvt(); 495 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 496 apic_write(APIC_ESR, 0); 497 accept_status = (apic_read(APIC_ESR) & 0xEF); 498 } 499 pr_debug("NMI sent.\n"); 500 501 if (send_status) 502 printk(KERN_ERR "APIC never delivered???\n"); 503 if (accept_status) 504 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 505 506 return (send_status | accept_status); 507 } 508 509 static int __cpuinit 510 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 511 { 512 unsigned long send_status, accept_status = 0; 513 int maxlvt, num_starts, j; 514 515 maxlvt = lapic_get_maxlvt(); 516 517 /* 518 * Be paranoid about clearing APIC errors. 519 */ 520 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 521 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 522 apic_write(APIC_ESR, 0); 523 apic_read(APIC_ESR); 524 } 525 526 pr_debug("Asserting INIT.\n"); 527 528 /* 529 * Turn INIT on target chip 530 */ 531 /* 532 * Send IPI 533 */ 534 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 535 phys_apicid); 536 537 pr_debug("Waiting for send to finish...\n"); 538 send_status = safe_apic_wait_icr_idle(); 539 540 mdelay(10); 541 542 pr_debug("Deasserting INIT.\n"); 543 544 /* Target chip */ 545 /* Send IPI */ 546 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 547 548 pr_debug("Waiting for send to finish...\n"); 549 send_status = safe_apic_wait_icr_idle(); 550 551 mb(); 552 atomic_set(&init_deasserted, 1); 553 554 /* 555 * Should we send STARTUP IPIs ? 556 * 557 * Determine this based on the APIC version. 558 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 559 */ 560 if (APIC_INTEGRATED(apic_version[phys_apicid])) 561 num_starts = 2; 562 else 563 num_starts = 0; 564 565 /* 566 * Paravirt / VMI wants a startup IPI hook here to set up the 567 * target processor state. 568 */ 569 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, 570 stack_start); 571 572 /* 573 * Run STARTUP IPI loop. 574 */ 575 pr_debug("#startup loops: %d.\n", num_starts); 576 577 for (j = 1; j <= num_starts; j++) { 578 pr_debug("Sending STARTUP #%d.\n", j); 579 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 580 apic_write(APIC_ESR, 0); 581 apic_read(APIC_ESR); 582 pr_debug("After apic_write.\n"); 583 584 /* 585 * STARTUP IPI 586 */ 587 588 /* Target chip */ 589 /* Boot on the stack */ 590 /* Kick the second */ 591 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 592 phys_apicid); 593 594 /* 595 * Give the other CPU some time to accept the IPI. 596 */ 597 udelay(300); 598 599 pr_debug("Startup point 1.\n"); 600 601 pr_debug("Waiting for send to finish...\n"); 602 send_status = safe_apic_wait_icr_idle(); 603 604 /* 605 * Give the other CPU some time to accept the IPI. 606 */ 607 udelay(200); 608 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 609 apic_write(APIC_ESR, 0); 610 accept_status = (apic_read(APIC_ESR) & 0xEF); 611 if (send_status || accept_status) 612 break; 613 } 614 pr_debug("After Startup.\n"); 615 616 if (send_status) 617 printk(KERN_ERR "APIC never delivered???\n"); 618 if (accept_status) 619 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 620 621 return (send_status | accept_status); 622 } 623 624 struct create_idle { 625 struct work_struct work; 626 struct task_struct *idle; 627 struct completion done; 628 int cpu; 629 }; 630 631 static void __cpuinit do_fork_idle(struct work_struct *work) 632 { 633 struct create_idle *c_idle = 634 container_of(work, struct create_idle, work); 635 636 c_idle->idle = fork_idle(c_idle->cpu); 637 complete(&c_idle->done); 638 } 639 640 /* reduce the number of lines printed when booting a large cpu count system */ 641 static void __cpuinit announce_cpu(int cpu, int apicid) 642 { 643 static int current_node = -1; 644 int node = early_cpu_to_node(cpu); 645 646 if (system_state == SYSTEM_BOOTING) { 647 if (node != current_node) { 648 if (current_node > (-1)) 649 pr_cont(" Ok.\n"); 650 current_node = node; 651 pr_info("Booting Node %3d, Processors ", node); 652 } 653 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : ""); 654 return; 655 } else 656 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 657 node, cpu, apicid); 658 } 659 660 /* 661 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 662 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 663 * Returns zero if CPU booted OK, else error code from 664 * ->wakeup_secondary_cpu. 665 */ 666 static int __cpuinit do_boot_cpu(int apicid, int cpu) 667 { 668 unsigned long boot_error = 0; 669 unsigned long start_ip; 670 int timeout; 671 struct create_idle c_idle = { 672 .cpu = cpu, 673 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), 674 }; 675 676 INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle); 677 678 alternatives_smp_switch(1); 679 680 c_idle.idle = get_idle_for_cpu(cpu); 681 682 /* 683 * We can't use kernel_thread since we must avoid to 684 * reschedule the child. 685 */ 686 if (c_idle.idle) { 687 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) 688 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); 689 init_idle(c_idle.idle, cpu); 690 goto do_rest; 691 } 692 693 schedule_work(&c_idle.work); 694 wait_for_completion(&c_idle.done); 695 696 if (IS_ERR(c_idle.idle)) { 697 printk("failed fork for CPU %d\n", cpu); 698 destroy_work_on_stack(&c_idle.work); 699 return PTR_ERR(c_idle.idle); 700 } 701 702 set_idle_for_cpu(cpu, c_idle.idle); 703 do_rest: 704 per_cpu(current_task, cpu) = c_idle.idle; 705 #ifdef CONFIG_X86_32 706 /* Stack for startup_32 can be just as for start_secondary onwards */ 707 irq_ctx_init(cpu); 708 #else 709 clear_tsk_thread_flag(c_idle.idle, TIF_FORK); 710 initial_gs = per_cpu_offset(cpu); 711 per_cpu(kernel_stack, cpu) = 712 (unsigned long)task_stack_page(c_idle.idle) - 713 KERNEL_STACK_OFFSET + THREAD_SIZE; 714 #endif 715 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 716 initial_code = (unsigned long)start_secondary; 717 stack_start = c_idle.idle->thread.sp; 718 719 /* start_ip had better be page-aligned! */ 720 start_ip = trampoline_address(); 721 722 /* So we see what's up */ 723 announce_cpu(cpu, apicid); 724 725 /* 726 * This grunge runs the startup process for 727 * the targeted processor. 728 */ 729 730 atomic_set(&init_deasserted, 0); 731 732 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 733 734 pr_debug("Setting warm reset code and vector.\n"); 735 736 smpboot_setup_warm_reset_vector(start_ip); 737 /* 738 * Be paranoid about clearing APIC errors. 739 */ 740 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 741 apic_write(APIC_ESR, 0); 742 apic_read(APIC_ESR); 743 } 744 } 745 746 /* 747 * Kick the secondary CPU. Use the method in the APIC driver 748 * if it's defined - or use an INIT boot APIC message otherwise: 749 */ 750 if (apic->wakeup_secondary_cpu) 751 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 752 else 753 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 754 755 if (!boot_error) { 756 /* 757 * allow APs to start initializing. 758 */ 759 pr_debug("Before Callout %d.\n", cpu); 760 cpumask_set_cpu(cpu, cpu_callout_mask); 761 pr_debug("After Callout %d.\n", cpu); 762 763 /* 764 * Wait 5s total for a response 765 */ 766 for (timeout = 0; timeout < 50000; timeout++) { 767 if (cpumask_test_cpu(cpu, cpu_callin_mask)) 768 break; /* It has booted */ 769 udelay(100); 770 /* 771 * Allow other tasks to run while we wait for the 772 * AP to come online. This also gives a chance 773 * for the MTRR work(triggered by the AP coming online) 774 * to be completed in the stop machine context. 775 */ 776 schedule(); 777 } 778 779 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 780 print_cpu_msr(&cpu_data(cpu)); 781 pr_debug("CPU%d: has booted.\n", cpu); 782 } else { 783 boot_error = 1; 784 if (*(volatile u32 *)TRAMPOLINE_SYM(trampoline_status) 785 == 0xA5A5A5A5) 786 /* trampoline started but...? */ 787 pr_err("CPU%d: Stuck ??\n", cpu); 788 else 789 /* trampoline code not run */ 790 pr_err("CPU%d: Not responding.\n", cpu); 791 if (apic->inquire_remote_apic) 792 apic->inquire_remote_apic(apicid); 793 } 794 } 795 796 if (boot_error) { 797 /* Try to put things back the way they were before ... */ 798 numa_remove_cpu(cpu); /* was set by numa_add_cpu */ 799 800 /* was set by do_boot_cpu() */ 801 cpumask_clear_cpu(cpu, cpu_callout_mask); 802 803 /* was set by cpu_init() */ 804 cpumask_clear_cpu(cpu, cpu_initialized_mask); 805 806 set_cpu_present(cpu, false); 807 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; 808 } 809 810 /* mark "stuck" area as not stuck */ 811 *(volatile u32 *)TRAMPOLINE_SYM(trampoline_status) = 0; 812 813 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 814 /* 815 * Cleanup possible dangling ends... 816 */ 817 smpboot_restore_warm_reset_vector(); 818 } 819 820 destroy_work_on_stack(&c_idle.work); 821 return boot_error; 822 } 823 824 int __cpuinit native_cpu_up(unsigned int cpu) 825 { 826 int apicid = apic->cpu_present_to_apicid(cpu); 827 unsigned long flags; 828 int err; 829 830 WARN_ON(irqs_disabled()); 831 832 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 833 834 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || 835 !physid_isset(apicid, phys_cpu_present_map) || 836 !apic->apic_id_valid(apicid)) { 837 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); 838 return -EINVAL; 839 } 840 841 /* 842 * Already booted CPU? 843 */ 844 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 845 pr_debug("do_boot_cpu %d Already started\n", cpu); 846 return -ENOSYS; 847 } 848 849 /* 850 * Save current MTRR state in case it was changed since early boot 851 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 852 */ 853 mtrr_save_state(); 854 855 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; 856 857 err = do_boot_cpu(apicid, cpu); 858 if (err) { 859 pr_debug("do_boot_cpu failed %d\n", err); 860 return -EIO; 861 } 862 863 /* 864 * Check TSC synchronization with the AP (keep irqs disabled 865 * while doing so): 866 */ 867 local_irq_save(flags); 868 check_tsc_sync_source(cpu); 869 local_irq_restore(flags); 870 871 while (!cpu_online(cpu)) { 872 cpu_relax(); 873 touch_nmi_watchdog(); 874 } 875 876 return 0; 877 } 878 879 /** 880 * arch_disable_smp_support() - disables SMP support for x86 at runtime 881 */ 882 void arch_disable_smp_support(void) 883 { 884 disable_ioapic_support(); 885 } 886 887 /* 888 * Fall back to non SMP mode after errors. 889 * 890 * RED-PEN audit/test this more. I bet there is more state messed up here. 891 */ 892 static __init void disable_smp(void) 893 { 894 init_cpu_present(cpumask_of(0)); 895 init_cpu_possible(cpumask_of(0)); 896 smpboot_clear_io_apic_irqs(); 897 898 if (smp_found_config) 899 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 900 else 901 physid_set_mask_of_physid(0, &phys_cpu_present_map); 902 cpumask_set_cpu(0, cpu_sibling_mask(0)); 903 cpumask_set_cpu(0, cpu_core_mask(0)); 904 } 905 906 /* 907 * Various sanity checks. 908 */ 909 static int __init smp_sanity_check(unsigned max_cpus) 910 { 911 preempt_disable(); 912 913 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 914 if (def_to_bigsmp && nr_cpu_ids > 8) { 915 unsigned int cpu; 916 unsigned nr; 917 918 printk(KERN_WARNING 919 "More than 8 CPUs detected - skipping them.\n" 920 "Use CONFIG_X86_BIGSMP.\n"); 921 922 nr = 0; 923 for_each_present_cpu(cpu) { 924 if (nr >= 8) 925 set_cpu_present(cpu, false); 926 nr++; 927 } 928 929 nr = 0; 930 for_each_possible_cpu(cpu) { 931 if (nr >= 8) 932 set_cpu_possible(cpu, false); 933 nr++; 934 } 935 936 nr_cpu_ids = 8; 937 } 938 #endif 939 940 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 941 printk(KERN_WARNING 942 "weird, boot CPU (#%d) not listed by the BIOS.\n", 943 hard_smp_processor_id()); 944 945 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 946 } 947 948 /* 949 * If we couldn't find an SMP configuration at boot time, 950 * get out of here now! 951 */ 952 if (!smp_found_config && !acpi_lapic) { 953 preempt_enable(); 954 printk(KERN_NOTICE "SMP motherboard not detected.\n"); 955 disable_smp(); 956 if (APIC_init_uniprocessor()) 957 printk(KERN_NOTICE "Local APIC not detected." 958 " Using dummy APIC emulation.\n"); 959 return -1; 960 } 961 962 /* 963 * Should not be necessary because the MP table should list the boot 964 * CPU too, but we do it for the sake of robustness anyway. 965 */ 966 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 967 printk(KERN_NOTICE 968 "weird, boot CPU (#%d) not listed by the BIOS.\n", 969 boot_cpu_physical_apicid); 970 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 971 } 972 preempt_enable(); 973 974 /* 975 * If we couldn't find a local APIC, then get out of here now! 976 */ 977 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 978 !cpu_has_apic) { 979 if (!disable_apic) { 980 pr_err("BIOS bug, local APIC #%d not detected!...\n", 981 boot_cpu_physical_apicid); 982 pr_err("... forcing use of dummy APIC emulation." 983 "(tell your hw vendor)\n"); 984 } 985 smpboot_clear_io_apic(); 986 disable_ioapic_support(); 987 return -1; 988 } 989 990 verify_local_APIC(); 991 992 /* 993 * If SMP should be disabled, then really disable it! 994 */ 995 if (!max_cpus) { 996 printk(KERN_INFO "SMP mode deactivated.\n"); 997 smpboot_clear_io_apic(); 998 999 connect_bsp_APIC(); 1000 setup_local_APIC(); 1001 bsp_end_local_APIC_setup(); 1002 return -1; 1003 } 1004 1005 return 0; 1006 } 1007 1008 static void __init smp_cpu_index_default(void) 1009 { 1010 int i; 1011 struct cpuinfo_x86 *c; 1012 1013 for_each_possible_cpu(i) { 1014 c = &cpu_data(i); 1015 /* mark all to hotplug */ 1016 c->cpu_index = nr_cpu_ids; 1017 } 1018 } 1019 1020 /* 1021 * Prepare for SMP bootup. The MP table or ACPI has been read 1022 * earlier. Just do some sanity checking here and enable APIC mode. 1023 */ 1024 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1025 { 1026 unsigned int i; 1027 1028 preempt_disable(); 1029 smp_cpu_index_default(); 1030 1031 /* 1032 * Setup boot CPU information 1033 */ 1034 smp_store_cpu_info(0); /* Final full version of the data */ 1035 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1036 mb(); 1037 1038 current_thread_info()->cpu = 0; /* needed? */ 1039 for_each_possible_cpu(i) { 1040 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1041 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1042 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1043 } 1044 set_cpu_sibling_map(0); 1045 1046 1047 if (smp_sanity_check(max_cpus) < 0) { 1048 printk(KERN_INFO "SMP disabled\n"); 1049 disable_smp(); 1050 goto out; 1051 } 1052 1053 default_setup_apic_routing(); 1054 1055 preempt_disable(); 1056 if (read_apic_id() != boot_cpu_physical_apicid) { 1057 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1058 read_apic_id(), boot_cpu_physical_apicid); 1059 /* Or can we switch back to PIC here? */ 1060 } 1061 preempt_enable(); 1062 1063 connect_bsp_APIC(); 1064 1065 /* 1066 * Switch from PIC to APIC mode. 1067 */ 1068 setup_local_APIC(); 1069 1070 /* 1071 * Enable IO APIC before setting up error vector 1072 */ 1073 if (!skip_ioapic_setup && nr_ioapics) 1074 enable_IO_APIC(); 1075 1076 bsp_end_local_APIC_setup(); 1077 1078 if (apic->setup_portio_remap) 1079 apic->setup_portio_remap(); 1080 1081 smpboot_setup_io_apic(); 1082 /* 1083 * Set up local APIC timer on boot CPU. 1084 */ 1085 1086 printk(KERN_INFO "CPU%d: ", 0); 1087 print_cpu_info(&cpu_data(0)); 1088 x86_init.timers.setup_percpu_clockev(); 1089 1090 if (is_uv_system()) 1091 uv_system_init(); 1092 1093 set_mtrr_aps_delayed_init(); 1094 out: 1095 preempt_enable(); 1096 } 1097 1098 void arch_disable_nonboot_cpus_begin(void) 1099 { 1100 /* 1101 * Avoid the smp alternatives switch during the disable_nonboot_cpus(). 1102 * In the suspend path, we will be back in the SMP mode shortly anyways. 1103 */ 1104 skip_smp_alternatives = true; 1105 } 1106 1107 void arch_disable_nonboot_cpus_end(void) 1108 { 1109 skip_smp_alternatives = false; 1110 } 1111 1112 void arch_enable_nonboot_cpus_begin(void) 1113 { 1114 set_mtrr_aps_delayed_init(); 1115 } 1116 1117 void arch_enable_nonboot_cpus_end(void) 1118 { 1119 mtrr_aps_init(); 1120 } 1121 1122 /* 1123 * Early setup to make printk work. 1124 */ 1125 void __init native_smp_prepare_boot_cpu(void) 1126 { 1127 int me = smp_processor_id(); 1128 switch_to_new_gdt(me); 1129 /* already set me in cpu_online_mask in boot_cpu_init() */ 1130 cpumask_set_cpu(me, cpu_callout_mask); 1131 per_cpu(cpu_state, me) = CPU_ONLINE; 1132 } 1133 1134 void __init native_smp_cpus_done(unsigned int max_cpus) 1135 { 1136 pr_debug("Boot done.\n"); 1137 1138 nmi_selftest(); 1139 impress_friends(); 1140 #ifdef CONFIG_X86_IO_APIC 1141 setup_ioapic_dest(); 1142 #endif 1143 mtrr_aps_init(); 1144 } 1145 1146 static int __initdata setup_possible_cpus = -1; 1147 static int __init _setup_possible_cpus(char *str) 1148 { 1149 get_option(&str, &setup_possible_cpus); 1150 return 0; 1151 } 1152 early_param("possible_cpus", _setup_possible_cpus); 1153 1154 1155 /* 1156 * cpu_possible_mask should be static, it cannot change as cpu's 1157 * are onlined, or offlined. The reason is per-cpu data-structures 1158 * are allocated by some modules at init time, and dont expect to 1159 * do this dynamically on cpu arrival/departure. 1160 * cpu_present_mask on the other hand can change dynamically. 1161 * In case when cpu_hotplug is not compiled, then we resort to current 1162 * behaviour, which is cpu_possible == cpu_present. 1163 * - Ashok Raj 1164 * 1165 * Three ways to find out the number of additional hotplug CPUs: 1166 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1167 * - The user can overwrite it with possible_cpus=NUM 1168 * - Otherwise don't reserve additional CPUs. 1169 * We do this because additional CPUs waste a lot of memory. 1170 * -AK 1171 */ 1172 __init void prefill_possible_map(void) 1173 { 1174 int i, possible; 1175 1176 /* no processor from mptable or madt */ 1177 if (!num_processors) 1178 num_processors = 1; 1179 1180 i = setup_max_cpus ?: 1; 1181 if (setup_possible_cpus == -1) { 1182 possible = num_processors; 1183 #ifdef CONFIG_HOTPLUG_CPU 1184 if (setup_max_cpus) 1185 possible += disabled_cpus; 1186 #else 1187 if (possible > i) 1188 possible = i; 1189 #endif 1190 } else 1191 possible = setup_possible_cpus; 1192 1193 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1194 1195 /* nr_cpu_ids could be reduced via nr_cpus= */ 1196 if (possible > nr_cpu_ids) { 1197 printk(KERN_WARNING 1198 "%d Processors exceeds NR_CPUS limit of %d\n", 1199 possible, nr_cpu_ids); 1200 possible = nr_cpu_ids; 1201 } 1202 1203 #ifdef CONFIG_HOTPLUG_CPU 1204 if (!setup_max_cpus) 1205 #endif 1206 if (possible > i) { 1207 printk(KERN_WARNING 1208 "%d Processors exceeds max_cpus limit of %u\n", 1209 possible, setup_max_cpus); 1210 possible = i; 1211 } 1212 1213 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", 1214 possible, max_t(int, possible - num_processors, 0)); 1215 1216 for (i = 0; i < possible; i++) 1217 set_cpu_possible(i, true); 1218 for (; i < NR_CPUS; i++) 1219 set_cpu_possible(i, false); 1220 1221 nr_cpu_ids = possible; 1222 } 1223 1224 #ifdef CONFIG_HOTPLUG_CPU 1225 1226 static void remove_siblinginfo(int cpu) 1227 { 1228 int sibling; 1229 struct cpuinfo_x86 *c = &cpu_data(cpu); 1230 1231 for_each_cpu(sibling, cpu_core_mask(cpu)) { 1232 cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); 1233 /*/ 1234 * last thread sibling in this cpu core going down 1235 */ 1236 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) 1237 cpu_data(sibling).booted_cores--; 1238 } 1239 1240 for_each_cpu(sibling, cpu_sibling_mask(cpu)) 1241 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); 1242 cpumask_clear(cpu_sibling_mask(cpu)); 1243 cpumask_clear(cpu_core_mask(cpu)); 1244 c->phys_proc_id = 0; 1245 c->cpu_core_id = 0; 1246 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1247 } 1248 1249 static void __ref remove_cpu_from_maps(int cpu) 1250 { 1251 set_cpu_online(cpu, false); 1252 cpumask_clear_cpu(cpu, cpu_callout_mask); 1253 cpumask_clear_cpu(cpu, cpu_callin_mask); 1254 /* was set by cpu_init() */ 1255 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1256 numa_remove_cpu(cpu); 1257 } 1258 1259 void cpu_disable_common(void) 1260 { 1261 int cpu = smp_processor_id(); 1262 1263 remove_siblinginfo(cpu); 1264 1265 /* It's now safe to remove this processor from the online map */ 1266 lock_vector_lock(); 1267 remove_cpu_from_maps(cpu); 1268 unlock_vector_lock(); 1269 fixup_irqs(); 1270 } 1271 1272 int native_cpu_disable(void) 1273 { 1274 int cpu = smp_processor_id(); 1275 1276 /* 1277 * Perhaps use cpufreq to drop frequency, but that could go 1278 * into generic code. 1279 * 1280 * We won't take down the boot processor on i386 due to some 1281 * interrupts only being able to be serviced by the BSP. 1282 * Especially so if we're not using an IOAPIC -zwane 1283 */ 1284 if (cpu == 0) 1285 return -EBUSY; 1286 1287 clear_local_APIC(); 1288 1289 cpu_disable_common(); 1290 return 0; 1291 } 1292 1293 void native_cpu_die(unsigned int cpu) 1294 { 1295 /* We don't do anything here: idle task is faking death itself. */ 1296 unsigned int i; 1297 1298 for (i = 0; i < 10; i++) { 1299 /* They ack this in play_dead by setting CPU_DEAD */ 1300 if (per_cpu(cpu_state, cpu) == CPU_DEAD) { 1301 if (system_state == SYSTEM_RUNNING) 1302 pr_info("CPU %u is now offline\n", cpu); 1303 1304 if (1 == num_online_cpus()) 1305 alternatives_smp_switch(0); 1306 return; 1307 } 1308 msleep(100); 1309 } 1310 pr_err("CPU %u didn't die...\n", cpu); 1311 } 1312 1313 void play_dead_common(void) 1314 { 1315 idle_task_exit(); 1316 reset_lazy_tlbstate(); 1317 amd_e400_remove_cpu(raw_smp_processor_id()); 1318 1319 mb(); 1320 /* Ack it */ 1321 __this_cpu_write(cpu_state, CPU_DEAD); 1322 1323 /* 1324 * With physical CPU hotplug, we should halt the cpu 1325 */ 1326 local_irq_disable(); 1327 } 1328 1329 /* 1330 * We need to flush the caches before going to sleep, lest we have 1331 * dirty data in our caches when we come back up. 1332 */ 1333 static inline void mwait_play_dead(void) 1334 { 1335 unsigned int eax, ebx, ecx, edx; 1336 unsigned int highest_cstate = 0; 1337 unsigned int highest_subcstate = 0; 1338 int i; 1339 void *mwait_ptr; 1340 struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info); 1341 1342 if (!(this_cpu_has(X86_FEATURE_MWAIT) && mwait_usable(c))) 1343 return; 1344 if (!this_cpu_has(X86_FEATURE_CLFLSH)) 1345 return; 1346 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1347 return; 1348 1349 eax = CPUID_MWAIT_LEAF; 1350 ecx = 0; 1351 native_cpuid(&eax, &ebx, &ecx, &edx); 1352 1353 /* 1354 * eax will be 0 if EDX enumeration is not valid. 1355 * Initialized below to cstate, sub_cstate value when EDX is valid. 1356 */ 1357 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1358 eax = 0; 1359 } else { 1360 edx >>= MWAIT_SUBSTATE_SIZE; 1361 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1362 if (edx & MWAIT_SUBSTATE_MASK) { 1363 highest_cstate = i; 1364 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1365 } 1366 } 1367 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1368 (highest_subcstate - 1); 1369 } 1370 1371 /* 1372 * This should be a memory location in a cache line which is 1373 * unlikely to be touched by other processors. The actual 1374 * content is immaterial as it is not actually modified in any way. 1375 */ 1376 mwait_ptr = ¤t_thread_info()->flags; 1377 1378 wbinvd(); 1379 1380 while (1) { 1381 /* 1382 * The CLFLUSH is a workaround for erratum AAI65 for 1383 * the Xeon 7400 series. It's not clear it is actually 1384 * needed, but it should be harmless in either case. 1385 * The WBINVD is insufficient due to the spurious-wakeup 1386 * case where we return around the loop. 1387 */ 1388 clflush(mwait_ptr); 1389 __monitor(mwait_ptr, 0, 0); 1390 mb(); 1391 __mwait(eax, 0); 1392 } 1393 } 1394 1395 static inline void hlt_play_dead(void) 1396 { 1397 if (__this_cpu_read(cpu_info.x86) >= 4) 1398 wbinvd(); 1399 1400 while (1) { 1401 native_halt(); 1402 } 1403 } 1404 1405 void native_play_dead(void) 1406 { 1407 play_dead_common(); 1408 tboot_shutdown(TB_SHUTDOWN_WFS); 1409 1410 mwait_play_dead(); /* Only returns on failure */ 1411 hlt_play_dead(); 1412 } 1413 1414 #else /* ... !CONFIG_HOTPLUG_CPU */ 1415 int native_cpu_disable(void) 1416 { 1417 return -ENOSYS; 1418 } 1419 1420 void native_cpu_die(unsigned int cpu) 1421 { 1422 /* We said "no" in __cpu_disable */ 1423 BUG(); 1424 } 1425 1426 void native_play_dead(void) 1427 { 1428 BUG(); 1429 } 1430 1431 #endif 1432