1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/module.h> 45 #include <linux/sched.h> 46 #include <linux/percpu.h> 47 #include <linux/bootmem.h> 48 #include <linux/err.h> 49 #include <linux/nmi.h> 50 #include <linux/tboot.h> 51 52 #include <asm/acpi.h> 53 #include <asm/desc.h> 54 #include <asm/nmi.h> 55 #include <asm/irq.h> 56 #include <asm/idle.h> 57 #include <asm/trampoline.h> 58 #include <asm/cpu.h> 59 #include <asm/numa.h> 60 #include <asm/pgtable.h> 61 #include <asm/tlbflush.h> 62 #include <asm/mtrr.h> 63 #include <asm/vmi.h> 64 #include <asm/apic.h> 65 #include <asm/setup.h> 66 #include <asm/uv/uv.h> 67 #include <linux/mc146818rtc.h> 68 69 #include <asm/smpboot_hooks.h> 70 71 #ifdef CONFIG_X86_32 72 u8 apicid_2_node[MAX_APICID]; 73 static int low_mappings; 74 #endif 75 76 /* State of each CPU */ 77 DEFINE_PER_CPU(int, cpu_state) = { 0 }; 78 79 /* Store all idle threads, this can be reused instead of creating 80 * a new thread. Also avoids complicated thread destroy functionality 81 * for idle threads. 82 */ 83 #ifdef CONFIG_HOTPLUG_CPU 84 /* 85 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is 86 * removed after init for !CONFIG_HOTPLUG_CPU. 87 */ 88 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); 89 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) 90 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) 91 #else 92 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; 93 #define get_idle_for_cpu(x) (idle_thread_array[(x)]) 94 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) 95 #endif 96 97 /* Number of siblings per CPU package */ 98 int smp_num_siblings = 1; 99 EXPORT_SYMBOL(smp_num_siblings); 100 101 /* Last level cache ID of each logical CPU */ 102 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; 103 104 /* representing HT siblings of each logical CPU */ 105 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); 106 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 107 108 /* representing HT and core siblings of each logical CPU */ 109 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); 110 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 111 112 /* Per CPU bogomips and other parameters */ 113 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 114 EXPORT_PER_CPU_SYMBOL(cpu_info); 115 116 atomic_t init_deasserted; 117 118 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) 119 /* which node each logical CPU is on */ 120 int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; 121 EXPORT_SYMBOL(cpu_to_node_map); 122 123 /* set up a mapping between cpu and node. */ 124 static void map_cpu_to_node(int cpu, int node) 125 { 126 printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); 127 cpumask_set_cpu(cpu, node_to_cpumask_map[node]); 128 cpu_to_node_map[cpu] = node; 129 } 130 131 /* undo a mapping between cpu and node. */ 132 static void unmap_cpu_to_node(int cpu) 133 { 134 int node; 135 136 printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); 137 for (node = 0; node < MAX_NUMNODES; node++) 138 cpumask_clear_cpu(cpu, node_to_cpumask_map[node]); 139 cpu_to_node_map[cpu] = 0; 140 } 141 #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ 142 #define map_cpu_to_node(cpu, node) ({}) 143 #define unmap_cpu_to_node(cpu) ({}) 144 #endif 145 146 #ifdef CONFIG_X86_32 147 static int boot_cpu_logical_apicid; 148 149 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = 150 { [0 ... NR_CPUS-1] = BAD_APICID }; 151 152 static void map_cpu_to_logical_apicid(void) 153 { 154 int cpu = smp_processor_id(); 155 int apicid = logical_smp_processor_id(); 156 int node = apic->apicid_to_node(apicid); 157 158 if (!node_online(node)) 159 node = first_online_node; 160 161 cpu_2_logical_apicid[cpu] = apicid; 162 map_cpu_to_node(cpu, node); 163 } 164 165 void numa_remove_cpu(int cpu) 166 { 167 cpu_2_logical_apicid[cpu] = BAD_APICID; 168 unmap_cpu_to_node(cpu); 169 } 170 #else 171 #define map_cpu_to_logical_apicid() do {} while (0) 172 #endif 173 174 /* 175 * Report back to the Boot Processor. 176 * Running on AP. 177 */ 178 static void __cpuinit smp_callin(void) 179 { 180 int cpuid, phys_id; 181 unsigned long timeout; 182 183 /* 184 * If waken up by an INIT in an 82489DX configuration 185 * we may get here before an INIT-deassert IPI reaches 186 * our local APIC. We have to wait for the IPI or we'll 187 * lock up on an APIC access. 188 */ 189 if (apic->wait_for_init_deassert) 190 apic->wait_for_init_deassert(&init_deasserted); 191 192 /* 193 * (This works even if the APIC is not enabled.) 194 */ 195 phys_id = read_apic_id(); 196 cpuid = smp_processor_id(); 197 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { 198 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, 199 phys_id, cpuid); 200 } 201 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); 202 203 /* 204 * STARTUP IPIs are fragile beasts as they might sometimes 205 * trigger some glue motherboard logic. Complete APIC bus 206 * silence for 1 second, this overestimates the time the 207 * boot CPU is spending to send the up to 2 STARTUP IPIs 208 * by a factor of two. This should be enough. 209 */ 210 211 /* 212 * Waiting 2s total for startup (udelay is not yet working) 213 */ 214 timeout = jiffies + 2*HZ; 215 while (time_before(jiffies, timeout)) { 216 /* 217 * Has the boot CPU finished it's STARTUP sequence? 218 */ 219 if (cpumask_test_cpu(cpuid, cpu_callout_mask)) 220 break; 221 cpu_relax(); 222 } 223 224 if (!time_before(jiffies, timeout)) { 225 panic("%s: CPU%d started up but did not get a callout!\n", 226 __func__, cpuid); 227 } 228 229 /* 230 * the boot CPU has finished the init stage and is spinning 231 * on callin_map until we finish. We are free to set up this 232 * CPU, first the APIC. (this is probably redundant on most 233 * boards) 234 */ 235 236 pr_debug("CALLIN, before setup_local_APIC().\n"); 237 if (apic->smp_callin_clear_local_apic) 238 apic->smp_callin_clear_local_apic(); 239 setup_local_APIC(); 240 end_local_APIC_setup(); 241 map_cpu_to_logical_apicid(); 242 243 notify_cpu_starting(cpuid); 244 /* 245 * Get our bogomips. 246 * 247 * Need to enable IRQs because it can take longer and then 248 * the NMI watchdog might kill us. 249 */ 250 local_irq_enable(); 251 calibrate_delay(); 252 local_irq_disable(); 253 pr_debug("Stack at about %p\n", &cpuid); 254 255 /* 256 * Save our processor parameters 257 */ 258 smp_store_cpu_info(cpuid); 259 260 /* 261 * Allow the master to continue. 262 */ 263 cpumask_set_cpu(cpuid, cpu_callin_mask); 264 } 265 266 /* 267 * Activate a secondary processor. 268 */ 269 notrace static void __cpuinit start_secondary(void *unused) 270 { 271 /* 272 * Don't put *anything* before cpu_init(), SMP booting is too 273 * fragile that we want to limit the things done here to the 274 * most necessary things. 275 */ 276 vmi_bringup(); 277 cpu_init(); 278 preempt_disable(); 279 smp_callin(); 280 281 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 282 barrier(); 283 /* 284 * Check TSC synchronization with the BP: 285 */ 286 check_tsc_sync_target(); 287 288 if (nmi_watchdog == NMI_IO_APIC) { 289 disable_8259A_irq(0); 290 enable_NMI_through_LVT0(); 291 enable_8259A_irq(0); 292 } 293 294 #ifdef CONFIG_X86_32 295 while (low_mappings) 296 cpu_relax(); 297 __flush_tlb_all(); 298 #endif 299 300 /* This must be done before setting cpu_online_mask */ 301 set_cpu_sibling_map(raw_smp_processor_id()); 302 wmb(); 303 304 /* 305 * We need to hold call_lock, so there is no inconsistency 306 * between the time smp_call_function() determines number of 307 * IPI recipients, and the time when the determination is made 308 * for which cpus receive the IPI. Holding this 309 * lock helps us to not include this cpu in a currently in progress 310 * smp_call_function(). 311 * 312 * We need to hold vector_lock so there the set of online cpus 313 * does not change while we are assigning vectors to cpus. Holding 314 * this lock ensures we don't half assign or remove an irq from a cpu. 315 */ 316 ipi_call_lock(); 317 lock_vector_lock(); 318 __setup_vector_irq(smp_processor_id()); 319 set_cpu_online(smp_processor_id(), true); 320 unlock_vector_lock(); 321 ipi_call_unlock(); 322 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; 323 324 /* enable local interrupts */ 325 local_irq_enable(); 326 327 x86_cpuinit.setup_percpu_clockev(); 328 329 wmb(); 330 cpu_idle(); 331 } 332 333 #ifdef CONFIG_CPUMASK_OFFSTACK 334 /* In this case, llc_shared_map is a pointer to a cpumask. */ 335 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, 336 const struct cpuinfo_x86 *src) 337 { 338 struct cpumask *llc = dst->llc_shared_map; 339 *dst = *src; 340 dst->llc_shared_map = llc; 341 } 342 #else 343 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, 344 const struct cpuinfo_x86 *src) 345 { 346 *dst = *src; 347 } 348 #endif /* CONFIG_CPUMASK_OFFSTACK */ 349 350 /* 351 * The bootstrap kernel entry code has set these up. Save them for 352 * a given CPU 353 */ 354 355 void __cpuinit smp_store_cpu_info(int id) 356 { 357 struct cpuinfo_x86 *c = &cpu_data(id); 358 359 copy_cpuinfo_x86(c, &boot_cpu_data); 360 c->cpu_index = id; 361 if (id != 0) 362 identify_secondary_cpu(c); 363 } 364 365 366 void __cpuinit set_cpu_sibling_map(int cpu) 367 { 368 int i; 369 struct cpuinfo_x86 *c = &cpu_data(cpu); 370 371 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 372 373 if (smp_num_siblings > 1) { 374 for_each_cpu(i, cpu_sibling_setup_mask) { 375 struct cpuinfo_x86 *o = &cpu_data(i); 376 377 if (c->phys_proc_id == o->phys_proc_id && 378 c->cpu_core_id == o->cpu_core_id) { 379 cpumask_set_cpu(i, cpu_sibling_mask(cpu)); 380 cpumask_set_cpu(cpu, cpu_sibling_mask(i)); 381 cpumask_set_cpu(i, cpu_core_mask(cpu)); 382 cpumask_set_cpu(cpu, cpu_core_mask(i)); 383 cpumask_set_cpu(i, c->llc_shared_map); 384 cpumask_set_cpu(cpu, o->llc_shared_map); 385 } 386 } 387 } else { 388 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); 389 } 390 391 cpumask_set_cpu(cpu, c->llc_shared_map); 392 393 if (current_cpu_data.x86_max_cores == 1) { 394 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); 395 c->booted_cores = 1; 396 return; 397 } 398 399 for_each_cpu(i, cpu_sibling_setup_mask) { 400 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && 401 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { 402 cpumask_set_cpu(i, c->llc_shared_map); 403 cpumask_set_cpu(cpu, cpu_data(i).llc_shared_map); 404 } 405 if (c->phys_proc_id == cpu_data(i).phys_proc_id) { 406 cpumask_set_cpu(i, cpu_core_mask(cpu)); 407 cpumask_set_cpu(cpu, cpu_core_mask(i)); 408 /* 409 * Does this new cpu bringup a new core? 410 */ 411 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { 412 /* 413 * for each core in package, increment 414 * the booted_cores for this new cpu 415 */ 416 if (cpumask_first(cpu_sibling_mask(i)) == i) 417 c->booted_cores++; 418 /* 419 * increment the core count for all 420 * the other cpus in this package 421 */ 422 if (i != cpu) 423 cpu_data(i).booted_cores++; 424 } else if (i != cpu && !c->booted_cores) 425 c->booted_cores = cpu_data(i).booted_cores; 426 } 427 } 428 } 429 430 /* maps the cpu to the sched domain representing multi-core */ 431 const struct cpumask *cpu_coregroup_mask(int cpu) 432 { 433 struct cpuinfo_x86 *c = &cpu_data(cpu); 434 /* 435 * For perf, we return last level cache shared map. 436 * And for power savings, we return cpu_core_map 437 */ 438 if ((sched_mc_power_savings || sched_smt_power_savings) && 439 !(cpu_has(c, X86_FEATURE_AMD_DCM))) 440 return cpu_core_mask(cpu); 441 else 442 return c->llc_shared_map; 443 } 444 445 static void impress_friends(void) 446 { 447 int cpu; 448 unsigned long bogosum = 0; 449 /* 450 * Allow the user to impress friends. 451 */ 452 pr_debug("Before bogomips.\n"); 453 for_each_possible_cpu(cpu) 454 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 455 bogosum += cpu_data(cpu).loops_per_jiffy; 456 printk(KERN_INFO 457 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", 458 num_online_cpus(), 459 bogosum/(500000/HZ), 460 (bogosum/(5000/HZ))%100); 461 462 pr_debug("Before bogocount - setting activated=1.\n"); 463 } 464 465 void __inquire_remote_apic(int apicid) 466 { 467 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 468 char *names[] = { "ID", "VERSION", "SPIV" }; 469 int timeout; 470 u32 status; 471 472 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); 473 474 for (i = 0; i < ARRAY_SIZE(regs); i++) { 475 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); 476 477 /* 478 * Wait for idle. 479 */ 480 status = safe_apic_wait_icr_idle(); 481 if (status) 482 printk(KERN_CONT 483 "a previous APIC delivery may have failed\n"); 484 485 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 486 487 timeout = 0; 488 do { 489 udelay(100); 490 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 491 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 492 493 switch (status) { 494 case APIC_ICR_RR_VALID: 495 status = apic_read(APIC_RRR); 496 printk(KERN_CONT "%08x\n", status); 497 break; 498 default: 499 printk(KERN_CONT "failed\n"); 500 } 501 } 502 } 503 504 /* 505 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 506 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 507 * won't ... remember to clear down the APIC, etc later. 508 */ 509 int __cpuinit 510 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) 511 { 512 unsigned long send_status, accept_status = 0; 513 int maxlvt; 514 515 /* Target chip */ 516 /* Boot on the stack */ 517 /* Kick the second */ 518 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); 519 520 pr_debug("Waiting for send to finish...\n"); 521 send_status = safe_apic_wait_icr_idle(); 522 523 /* 524 * Give the other CPU some time to accept the IPI. 525 */ 526 udelay(200); 527 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 528 maxlvt = lapic_get_maxlvt(); 529 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 530 apic_write(APIC_ESR, 0); 531 accept_status = (apic_read(APIC_ESR) & 0xEF); 532 } 533 pr_debug("NMI sent.\n"); 534 535 if (send_status) 536 printk(KERN_ERR "APIC never delivered???\n"); 537 if (accept_status) 538 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 539 540 return (send_status | accept_status); 541 } 542 543 static int __cpuinit 544 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 545 { 546 unsigned long send_status, accept_status = 0; 547 int maxlvt, num_starts, j; 548 549 maxlvt = lapic_get_maxlvt(); 550 551 /* 552 * Be paranoid about clearing APIC errors. 553 */ 554 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 555 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 556 apic_write(APIC_ESR, 0); 557 apic_read(APIC_ESR); 558 } 559 560 pr_debug("Asserting INIT.\n"); 561 562 /* 563 * Turn INIT on target chip 564 */ 565 /* 566 * Send IPI 567 */ 568 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 569 phys_apicid); 570 571 pr_debug("Waiting for send to finish...\n"); 572 send_status = safe_apic_wait_icr_idle(); 573 574 mdelay(10); 575 576 pr_debug("Deasserting INIT.\n"); 577 578 /* Target chip */ 579 /* Send IPI */ 580 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 581 582 pr_debug("Waiting for send to finish...\n"); 583 send_status = safe_apic_wait_icr_idle(); 584 585 mb(); 586 atomic_set(&init_deasserted, 1); 587 588 /* 589 * Should we send STARTUP IPIs ? 590 * 591 * Determine this based on the APIC version. 592 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 593 */ 594 if (APIC_INTEGRATED(apic_version[phys_apicid])) 595 num_starts = 2; 596 else 597 num_starts = 0; 598 599 /* 600 * Paravirt / VMI wants a startup IPI hook here to set up the 601 * target processor state. 602 */ 603 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, 604 (unsigned long)stack_start.sp); 605 606 /* 607 * Run STARTUP IPI loop. 608 */ 609 pr_debug("#startup loops: %d.\n", num_starts); 610 611 for (j = 1; j <= num_starts; j++) { 612 pr_debug("Sending STARTUP #%d.\n", j); 613 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 614 apic_write(APIC_ESR, 0); 615 apic_read(APIC_ESR); 616 pr_debug("After apic_write.\n"); 617 618 /* 619 * STARTUP IPI 620 */ 621 622 /* Target chip */ 623 /* Boot on the stack */ 624 /* Kick the second */ 625 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 626 phys_apicid); 627 628 /* 629 * Give the other CPU some time to accept the IPI. 630 */ 631 udelay(300); 632 633 pr_debug("Startup point 1.\n"); 634 635 pr_debug("Waiting for send to finish...\n"); 636 send_status = safe_apic_wait_icr_idle(); 637 638 /* 639 * Give the other CPU some time to accept the IPI. 640 */ 641 udelay(200); 642 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 643 apic_write(APIC_ESR, 0); 644 accept_status = (apic_read(APIC_ESR) & 0xEF); 645 if (send_status || accept_status) 646 break; 647 } 648 pr_debug("After Startup.\n"); 649 650 if (send_status) 651 printk(KERN_ERR "APIC never delivered???\n"); 652 if (accept_status) 653 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 654 655 return (send_status | accept_status); 656 } 657 658 struct create_idle { 659 struct work_struct work; 660 struct task_struct *idle; 661 struct completion done; 662 int cpu; 663 }; 664 665 static void __cpuinit do_fork_idle(struct work_struct *work) 666 { 667 struct create_idle *c_idle = 668 container_of(work, struct create_idle, work); 669 670 c_idle->idle = fork_idle(c_idle->cpu); 671 complete(&c_idle->done); 672 } 673 674 /* 675 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 676 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 677 * Returns zero if CPU booted OK, else error code from 678 * ->wakeup_secondary_cpu. 679 */ 680 static int __cpuinit do_boot_cpu(int apicid, int cpu) 681 { 682 unsigned long boot_error = 0; 683 unsigned long start_ip; 684 int timeout; 685 struct create_idle c_idle = { 686 .cpu = cpu, 687 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), 688 }; 689 690 INIT_WORK(&c_idle.work, do_fork_idle); 691 692 alternatives_smp_switch(1); 693 694 c_idle.idle = get_idle_for_cpu(cpu); 695 696 /* 697 * We can't use kernel_thread since we must avoid to 698 * reschedule the child. 699 */ 700 if (c_idle.idle) { 701 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) 702 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); 703 init_idle(c_idle.idle, cpu); 704 goto do_rest; 705 } 706 707 if (!keventd_up() || current_is_keventd()) 708 c_idle.work.func(&c_idle.work); 709 else { 710 schedule_work(&c_idle.work); 711 wait_for_completion(&c_idle.done); 712 } 713 714 if (IS_ERR(c_idle.idle)) { 715 printk("failed fork for CPU %d\n", cpu); 716 return PTR_ERR(c_idle.idle); 717 } 718 719 set_idle_for_cpu(cpu, c_idle.idle); 720 do_rest: 721 per_cpu(current_task, cpu) = c_idle.idle; 722 #ifdef CONFIG_X86_32 723 /* Stack for startup_32 can be just as for start_secondary onwards */ 724 irq_ctx_init(cpu); 725 #else 726 clear_tsk_thread_flag(c_idle.idle, TIF_FORK); 727 initial_gs = per_cpu_offset(cpu); 728 per_cpu(kernel_stack, cpu) = 729 (unsigned long)task_stack_page(c_idle.idle) - 730 KERNEL_STACK_OFFSET + THREAD_SIZE; 731 #endif 732 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 733 initial_code = (unsigned long)start_secondary; 734 stack_start.sp = (void *) c_idle.idle->thread.sp; 735 736 /* start_ip had better be page-aligned! */ 737 start_ip = setup_trampoline(); 738 739 /* So we see what's up */ 740 printk(KERN_INFO "Booting processor %d APIC 0x%x ip 0x%lx\n", 741 cpu, apicid, start_ip); 742 743 /* 744 * This grunge runs the startup process for 745 * the targeted processor. 746 */ 747 748 atomic_set(&init_deasserted, 0); 749 750 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 751 752 pr_debug("Setting warm reset code and vector.\n"); 753 754 smpboot_setup_warm_reset_vector(start_ip); 755 /* 756 * Be paranoid about clearing APIC errors. 757 */ 758 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 759 apic_write(APIC_ESR, 0); 760 apic_read(APIC_ESR); 761 } 762 } 763 764 /* 765 * Kick the secondary CPU. Use the method in the APIC driver 766 * if it's defined - or use an INIT boot APIC message otherwise: 767 */ 768 if (apic->wakeup_secondary_cpu) 769 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 770 else 771 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 772 773 if (!boot_error) { 774 /* 775 * allow APs to start initializing. 776 */ 777 pr_debug("Before Callout %d.\n", cpu); 778 cpumask_set_cpu(cpu, cpu_callout_mask); 779 pr_debug("After Callout %d.\n", cpu); 780 781 /* 782 * Wait 5s total for a response 783 */ 784 for (timeout = 0; timeout < 50000; timeout++) { 785 if (cpumask_test_cpu(cpu, cpu_callin_mask)) 786 break; /* It has booted */ 787 udelay(100); 788 } 789 790 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 791 /* number CPUs logically, starting from 1 (BSP is 0) */ 792 pr_debug("OK.\n"); 793 printk(KERN_INFO "CPU%d: ", cpu); 794 print_cpu_info(&cpu_data(cpu)); 795 pr_debug("CPU has booted.\n"); 796 } else { 797 boot_error = 1; 798 if (*((volatile unsigned char *)trampoline_base) 799 == 0xA5) 800 /* trampoline started but...? */ 801 printk(KERN_ERR "Stuck ??\n"); 802 else 803 /* trampoline code not run */ 804 printk(KERN_ERR "Not responding.\n"); 805 if (apic->inquire_remote_apic) 806 apic->inquire_remote_apic(apicid); 807 } 808 } 809 810 if (boot_error) { 811 /* Try to put things back the way they were before ... */ 812 numa_remove_cpu(cpu); /* was set by numa_add_cpu */ 813 814 /* was set by do_boot_cpu() */ 815 cpumask_clear_cpu(cpu, cpu_callout_mask); 816 817 /* was set by cpu_init() */ 818 cpumask_clear_cpu(cpu, cpu_initialized_mask); 819 820 set_cpu_present(cpu, false); 821 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; 822 } 823 824 /* mark "stuck" area as not stuck */ 825 *((volatile unsigned long *)trampoline_base) = 0; 826 827 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 828 /* 829 * Cleanup possible dangling ends... 830 */ 831 smpboot_restore_warm_reset_vector(); 832 } 833 834 return boot_error; 835 } 836 837 int __cpuinit native_cpu_up(unsigned int cpu) 838 { 839 int apicid = apic->cpu_present_to_apicid(cpu); 840 unsigned long flags; 841 int err; 842 843 WARN_ON(irqs_disabled()); 844 845 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 846 847 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || 848 !physid_isset(apicid, phys_cpu_present_map)) { 849 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); 850 return -EINVAL; 851 } 852 853 /* 854 * Already booted CPU? 855 */ 856 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 857 pr_debug("do_boot_cpu %d Already started\n", cpu); 858 return -ENOSYS; 859 } 860 861 /* 862 * Save current MTRR state in case it was changed since early boot 863 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 864 */ 865 mtrr_save_state(); 866 867 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; 868 869 #ifdef CONFIG_X86_32 870 /* init low mem mapping */ 871 clone_pgd_range(swapper_pg_dir, swapper_pg_dir + KERNEL_PGD_BOUNDARY, 872 min_t(unsigned long, KERNEL_PGD_PTRS, KERNEL_PGD_BOUNDARY)); 873 flush_tlb_all(); 874 low_mappings = 1; 875 876 err = do_boot_cpu(apicid, cpu); 877 878 zap_low_mappings(false); 879 low_mappings = 0; 880 #else 881 err = do_boot_cpu(apicid, cpu); 882 #endif 883 if (err) { 884 pr_debug("do_boot_cpu failed %d\n", err); 885 return -EIO; 886 } 887 888 /* 889 * Check TSC synchronization with the AP (keep irqs disabled 890 * while doing so): 891 */ 892 local_irq_save(flags); 893 check_tsc_sync_source(cpu); 894 local_irq_restore(flags); 895 896 while (!cpu_online(cpu)) { 897 cpu_relax(); 898 touch_nmi_watchdog(); 899 } 900 901 return 0; 902 } 903 904 /* 905 * Fall back to non SMP mode after errors. 906 * 907 * RED-PEN audit/test this more. I bet there is more state messed up here. 908 */ 909 static __init void disable_smp(void) 910 { 911 init_cpu_present(cpumask_of(0)); 912 init_cpu_possible(cpumask_of(0)); 913 smpboot_clear_io_apic_irqs(); 914 915 if (smp_found_config) 916 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 917 else 918 physid_set_mask_of_physid(0, &phys_cpu_present_map); 919 map_cpu_to_logical_apicid(); 920 cpumask_set_cpu(0, cpu_sibling_mask(0)); 921 cpumask_set_cpu(0, cpu_core_mask(0)); 922 } 923 924 /* 925 * Various sanity checks. 926 */ 927 static int __init smp_sanity_check(unsigned max_cpus) 928 { 929 preempt_disable(); 930 931 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 932 if (def_to_bigsmp && nr_cpu_ids > 8) { 933 unsigned int cpu; 934 unsigned nr; 935 936 printk(KERN_WARNING 937 "More than 8 CPUs detected - skipping them.\n" 938 "Use CONFIG_X86_BIGSMP.\n"); 939 940 nr = 0; 941 for_each_present_cpu(cpu) { 942 if (nr >= 8) 943 set_cpu_present(cpu, false); 944 nr++; 945 } 946 947 nr = 0; 948 for_each_possible_cpu(cpu) { 949 if (nr >= 8) 950 set_cpu_possible(cpu, false); 951 nr++; 952 } 953 954 nr_cpu_ids = 8; 955 } 956 #endif 957 958 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 959 printk(KERN_WARNING 960 "weird, boot CPU (#%d) not listed by the BIOS.\n", 961 hard_smp_processor_id()); 962 963 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 964 } 965 966 /* 967 * If we couldn't find an SMP configuration at boot time, 968 * get out of here now! 969 */ 970 if (!smp_found_config && !acpi_lapic) { 971 preempt_enable(); 972 printk(KERN_NOTICE "SMP motherboard not detected.\n"); 973 disable_smp(); 974 if (APIC_init_uniprocessor()) 975 printk(KERN_NOTICE "Local APIC not detected." 976 " Using dummy APIC emulation.\n"); 977 return -1; 978 } 979 980 /* 981 * Should not be necessary because the MP table should list the boot 982 * CPU too, but we do it for the sake of robustness anyway. 983 */ 984 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 985 printk(KERN_NOTICE 986 "weird, boot CPU (#%d) not listed by the BIOS.\n", 987 boot_cpu_physical_apicid); 988 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 989 } 990 preempt_enable(); 991 992 /* 993 * If we couldn't find a local APIC, then get out of here now! 994 */ 995 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 996 !cpu_has_apic) { 997 if (!disable_apic) { 998 pr_err("BIOS bug, local APIC #%d not detected!...\n", 999 boot_cpu_physical_apicid); 1000 pr_err("... forcing use of dummy APIC emulation." 1001 "(tell your hw vendor)\n"); 1002 } 1003 smpboot_clear_io_apic(); 1004 arch_disable_smp_support(); 1005 return -1; 1006 } 1007 1008 verify_local_APIC(); 1009 1010 /* 1011 * If SMP should be disabled, then really disable it! 1012 */ 1013 if (!max_cpus) { 1014 printk(KERN_INFO "SMP mode deactivated.\n"); 1015 smpboot_clear_io_apic(); 1016 1017 localise_nmi_watchdog(); 1018 1019 connect_bsp_APIC(); 1020 setup_local_APIC(); 1021 end_local_APIC_setup(); 1022 return -1; 1023 } 1024 1025 return 0; 1026 } 1027 1028 static void __init smp_cpu_index_default(void) 1029 { 1030 int i; 1031 struct cpuinfo_x86 *c; 1032 1033 for_each_possible_cpu(i) { 1034 c = &cpu_data(i); 1035 /* mark all to hotplug */ 1036 c->cpu_index = nr_cpu_ids; 1037 } 1038 } 1039 1040 /* 1041 * Prepare for SMP bootup. The MP table or ACPI has been read 1042 * earlier. Just do some sanity checking here and enable APIC mode. 1043 */ 1044 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1045 { 1046 unsigned int i; 1047 1048 preempt_disable(); 1049 smp_cpu_index_default(); 1050 current_cpu_data = boot_cpu_data; 1051 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1052 mb(); 1053 /* 1054 * Setup boot CPU information 1055 */ 1056 smp_store_cpu_info(0); /* Final full version of the data */ 1057 #ifdef CONFIG_X86_32 1058 boot_cpu_logical_apicid = logical_smp_processor_id(); 1059 #endif 1060 current_thread_info()->cpu = 0; /* needed? */ 1061 for_each_possible_cpu(i) { 1062 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1063 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1064 zalloc_cpumask_var(&cpu_data(i).llc_shared_map, GFP_KERNEL); 1065 } 1066 set_cpu_sibling_map(0); 1067 1068 enable_IR_x2apic(); 1069 #ifdef CONFIG_X86_64 1070 default_setup_apic_routing(); 1071 #endif 1072 1073 if (smp_sanity_check(max_cpus) < 0) { 1074 printk(KERN_INFO "SMP disabled\n"); 1075 disable_smp(); 1076 goto out; 1077 } 1078 1079 preempt_disable(); 1080 if (read_apic_id() != boot_cpu_physical_apicid) { 1081 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1082 read_apic_id(), boot_cpu_physical_apicid); 1083 /* Or can we switch back to PIC here? */ 1084 } 1085 preempt_enable(); 1086 1087 connect_bsp_APIC(); 1088 1089 /* 1090 * Switch from PIC to APIC mode. 1091 */ 1092 setup_local_APIC(); 1093 1094 /* 1095 * Enable IO APIC before setting up error vector 1096 */ 1097 if (!skip_ioapic_setup && nr_ioapics) 1098 enable_IO_APIC(); 1099 1100 end_local_APIC_setup(); 1101 1102 map_cpu_to_logical_apicid(); 1103 1104 if (apic->setup_portio_remap) 1105 apic->setup_portio_remap(); 1106 1107 smpboot_setup_io_apic(); 1108 /* 1109 * Set up local APIC timer on boot CPU. 1110 */ 1111 1112 printk(KERN_INFO "CPU%d: ", 0); 1113 print_cpu_info(&cpu_data(0)); 1114 x86_init.timers.setup_percpu_clockev(); 1115 1116 if (is_uv_system()) 1117 uv_system_init(); 1118 1119 set_mtrr_aps_delayed_init(); 1120 out: 1121 preempt_enable(); 1122 } 1123 1124 void arch_enable_nonboot_cpus_begin(void) 1125 { 1126 set_mtrr_aps_delayed_init(); 1127 } 1128 1129 void arch_enable_nonboot_cpus_end(void) 1130 { 1131 mtrr_aps_init(); 1132 } 1133 1134 /* 1135 * Early setup to make printk work. 1136 */ 1137 void __init native_smp_prepare_boot_cpu(void) 1138 { 1139 int me = smp_processor_id(); 1140 switch_to_new_gdt(me); 1141 /* already set me in cpu_online_mask in boot_cpu_init() */ 1142 cpumask_set_cpu(me, cpu_callout_mask); 1143 per_cpu(cpu_state, me) = CPU_ONLINE; 1144 } 1145 1146 void __init native_smp_cpus_done(unsigned int max_cpus) 1147 { 1148 pr_debug("Boot done.\n"); 1149 1150 impress_friends(); 1151 #ifdef CONFIG_X86_IO_APIC 1152 setup_ioapic_dest(); 1153 #endif 1154 check_nmi_watchdog(); 1155 mtrr_aps_init(); 1156 } 1157 1158 static int __initdata setup_possible_cpus = -1; 1159 static int __init _setup_possible_cpus(char *str) 1160 { 1161 get_option(&str, &setup_possible_cpus); 1162 return 0; 1163 } 1164 early_param("possible_cpus", _setup_possible_cpus); 1165 1166 1167 /* 1168 * cpu_possible_mask should be static, it cannot change as cpu's 1169 * are onlined, or offlined. The reason is per-cpu data-structures 1170 * are allocated by some modules at init time, and dont expect to 1171 * do this dynamically on cpu arrival/departure. 1172 * cpu_present_mask on the other hand can change dynamically. 1173 * In case when cpu_hotplug is not compiled, then we resort to current 1174 * behaviour, which is cpu_possible == cpu_present. 1175 * - Ashok Raj 1176 * 1177 * Three ways to find out the number of additional hotplug CPUs: 1178 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1179 * - The user can overwrite it with possible_cpus=NUM 1180 * - Otherwise don't reserve additional CPUs. 1181 * We do this because additional CPUs waste a lot of memory. 1182 * -AK 1183 */ 1184 __init void prefill_possible_map(void) 1185 { 1186 int i, possible; 1187 1188 /* no processor from mptable or madt */ 1189 if (!num_processors) 1190 num_processors = 1; 1191 1192 if (setup_possible_cpus == -1) 1193 possible = num_processors + disabled_cpus; 1194 else 1195 possible = setup_possible_cpus; 1196 1197 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1198 1199 if (possible > CONFIG_NR_CPUS) { 1200 printk(KERN_WARNING 1201 "%d Processors exceeds NR_CPUS limit of %d\n", 1202 possible, CONFIG_NR_CPUS); 1203 possible = CONFIG_NR_CPUS; 1204 } 1205 1206 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", 1207 possible, max_t(int, possible - num_processors, 0)); 1208 1209 for (i = 0; i < possible; i++) 1210 set_cpu_possible(i, true); 1211 1212 nr_cpu_ids = possible; 1213 } 1214 1215 #ifdef CONFIG_HOTPLUG_CPU 1216 1217 static void remove_siblinginfo(int cpu) 1218 { 1219 int sibling; 1220 struct cpuinfo_x86 *c = &cpu_data(cpu); 1221 1222 for_each_cpu(sibling, cpu_core_mask(cpu)) { 1223 cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); 1224 /*/ 1225 * last thread sibling in this cpu core going down 1226 */ 1227 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) 1228 cpu_data(sibling).booted_cores--; 1229 } 1230 1231 for_each_cpu(sibling, cpu_sibling_mask(cpu)) 1232 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); 1233 cpumask_clear(cpu_sibling_mask(cpu)); 1234 cpumask_clear(cpu_core_mask(cpu)); 1235 c->phys_proc_id = 0; 1236 c->cpu_core_id = 0; 1237 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1238 } 1239 1240 static void __ref remove_cpu_from_maps(int cpu) 1241 { 1242 set_cpu_online(cpu, false); 1243 cpumask_clear_cpu(cpu, cpu_callout_mask); 1244 cpumask_clear_cpu(cpu, cpu_callin_mask); 1245 /* was set by cpu_init() */ 1246 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1247 numa_remove_cpu(cpu); 1248 } 1249 1250 void cpu_disable_common(void) 1251 { 1252 int cpu = smp_processor_id(); 1253 /* 1254 * HACK: 1255 * Allow any queued timer interrupts to get serviced 1256 * This is only a temporary solution until we cleanup 1257 * fixup_irqs as we do for IA64. 1258 */ 1259 local_irq_enable(); 1260 mdelay(1); 1261 1262 local_irq_disable(); 1263 remove_siblinginfo(cpu); 1264 1265 /* It's now safe to remove this processor from the online map */ 1266 lock_vector_lock(); 1267 remove_cpu_from_maps(cpu); 1268 unlock_vector_lock(); 1269 fixup_irqs(); 1270 } 1271 1272 int native_cpu_disable(void) 1273 { 1274 int cpu = smp_processor_id(); 1275 1276 /* 1277 * Perhaps use cpufreq to drop frequency, but that could go 1278 * into generic code. 1279 * 1280 * We won't take down the boot processor on i386 due to some 1281 * interrupts only being able to be serviced by the BSP. 1282 * Especially so if we're not using an IOAPIC -zwane 1283 */ 1284 if (cpu == 0) 1285 return -EBUSY; 1286 1287 if (nmi_watchdog == NMI_LOCAL_APIC) 1288 stop_apic_nmi_watchdog(NULL); 1289 clear_local_APIC(); 1290 1291 cpu_disable_common(); 1292 return 0; 1293 } 1294 1295 void native_cpu_die(unsigned int cpu) 1296 { 1297 /* We don't do anything here: idle task is faking death itself. */ 1298 unsigned int i; 1299 1300 for (i = 0; i < 10; i++) { 1301 /* They ack this in play_dead by setting CPU_DEAD */ 1302 if (per_cpu(cpu_state, cpu) == CPU_DEAD) { 1303 printk(KERN_INFO "CPU %d is now offline\n", cpu); 1304 if (1 == num_online_cpus()) 1305 alternatives_smp_switch(0); 1306 return; 1307 } 1308 msleep(100); 1309 } 1310 printk(KERN_ERR "CPU %u didn't die...\n", cpu); 1311 } 1312 1313 void play_dead_common(void) 1314 { 1315 idle_task_exit(); 1316 reset_lazy_tlbstate(); 1317 irq_ctx_exit(raw_smp_processor_id()); 1318 c1e_remove_cpu(raw_smp_processor_id()); 1319 1320 mb(); 1321 /* Ack it */ 1322 __get_cpu_var(cpu_state) = CPU_DEAD; 1323 1324 /* 1325 * With physical CPU hotplug, we should halt the cpu 1326 */ 1327 local_irq_disable(); 1328 } 1329 1330 void native_play_dead(void) 1331 { 1332 play_dead_common(); 1333 tboot_shutdown(TB_SHUTDOWN_WFS); 1334 wbinvd_halt(); 1335 } 1336 1337 #else /* ... !CONFIG_HOTPLUG_CPU */ 1338 int native_cpu_disable(void) 1339 { 1340 return -ENOSYS; 1341 } 1342 1343 void native_cpu_die(unsigned int cpu) 1344 { 1345 /* We said "no" in __cpu_disable */ 1346 BUG(); 1347 } 1348 1349 void native_play_dead(void) 1350 { 1351 BUG(); 1352 } 1353 1354 #endif 1355