1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/module.h> 45 #include <linux/sched.h> 46 #include <linux/percpu.h> 47 #include <linux/bootmem.h> 48 #include <linux/err.h> 49 #include <linux/nmi.h> 50 #include <linux/tboot.h> 51 #include <linux/stackprotector.h> 52 #include <linux/gfp.h> 53 54 #include <asm/acpi.h> 55 #include <asm/desc.h> 56 #include <asm/nmi.h> 57 #include <asm/irq.h> 58 #include <asm/idle.h> 59 #include <asm/trampoline.h> 60 #include <asm/cpu.h> 61 #include <asm/numa.h> 62 #include <asm/pgtable.h> 63 #include <asm/tlbflush.h> 64 #include <asm/mtrr.h> 65 #include <asm/mwait.h> 66 #include <asm/apic.h> 67 #include <asm/setup.h> 68 #include <asm/uv/uv.h> 69 #include <linux/mc146818rtc.h> 70 71 #include <asm/smpboot_hooks.h> 72 #include <asm/i8259.h> 73 74 #ifdef CONFIG_X86_32 75 u8 apicid_2_node[MAX_APICID]; 76 #endif 77 78 /* State of each CPU */ 79 DEFINE_PER_CPU(int, cpu_state) = { 0 }; 80 81 /* Store all idle threads, this can be reused instead of creating 82 * a new thread. Also avoids complicated thread destroy functionality 83 * for idle threads. 84 */ 85 #ifdef CONFIG_HOTPLUG_CPU 86 /* 87 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is 88 * removed after init for !CONFIG_HOTPLUG_CPU. 89 */ 90 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); 91 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) 92 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) 93 94 /* 95 * We need this for trampoline_base protection from concurrent accesses when 96 * off- and onlining cores wildly. 97 */ 98 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex); 99 100 void cpu_hotplug_driver_lock(void) 101 { 102 mutex_lock(&x86_cpu_hotplug_driver_mutex); 103 } 104 105 void cpu_hotplug_driver_unlock(void) 106 { 107 mutex_unlock(&x86_cpu_hotplug_driver_mutex); 108 } 109 110 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; } 111 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; } 112 #else 113 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; 114 #define get_idle_for_cpu(x) (idle_thread_array[(x)]) 115 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) 116 #endif 117 118 /* Number of siblings per CPU package */ 119 int smp_num_siblings = 1; 120 EXPORT_SYMBOL(smp_num_siblings); 121 122 /* Last level cache ID of each logical CPU */ 123 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; 124 125 /* representing HT siblings of each logical CPU */ 126 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); 127 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 128 129 /* representing HT and core siblings of each logical CPU */ 130 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); 131 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 132 133 /* Per CPU bogomips and other parameters */ 134 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 135 EXPORT_PER_CPU_SYMBOL(cpu_info); 136 137 atomic_t init_deasserted; 138 139 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) 140 /* which node each logical CPU is on */ 141 int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; 142 EXPORT_SYMBOL(cpu_to_node_map); 143 144 /* set up a mapping between cpu and node. */ 145 static void map_cpu_to_node(int cpu, int node) 146 { 147 printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); 148 cpumask_set_cpu(cpu, node_to_cpumask_map[node]); 149 cpu_to_node_map[cpu] = node; 150 } 151 152 /* undo a mapping between cpu and node. */ 153 static void unmap_cpu_to_node(int cpu) 154 { 155 int node; 156 157 printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); 158 for (node = 0; node < MAX_NUMNODES; node++) 159 cpumask_clear_cpu(cpu, node_to_cpumask_map[node]); 160 cpu_to_node_map[cpu] = 0; 161 } 162 #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ 163 #define map_cpu_to_node(cpu, node) ({}) 164 #define unmap_cpu_to_node(cpu) ({}) 165 #endif 166 167 #ifdef CONFIG_X86_32 168 static int boot_cpu_logical_apicid; 169 170 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = 171 { [0 ... NR_CPUS-1] = BAD_APICID }; 172 173 static void map_cpu_to_logical_apicid(void) 174 { 175 int cpu = smp_processor_id(); 176 int apicid = logical_smp_processor_id(); 177 int node = apic->apicid_to_node(apicid); 178 179 if (!node_online(node)) 180 node = first_online_node; 181 182 cpu_2_logical_apicid[cpu] = apicid; 183 map_cpu_to_node(cpu, node); 184 } 185 186 void numa_remove_cpu(int cpu) 187 { 188 cpu_2_logical_apicid[cpu] = BAD_APICID; 189 unmap_cpu_to_node(cpu); 190 } 191 #else 192 #define map_cpu_to_logical_apicid() do {} while (0) 193 #endif 194 195 /* 196 * Report back to the Boot Processor. 197 * Running on AP. 198 */ 199 static void __cpuinit smp_callin(void) 200 { 201 int cpuid, phys_id; 202 unsigned long timeout; 203 204 /* 205 * If waken up by an INIT in an 82489DX configuration 206 * we may get here before an INIT-deassert IPI reaches 207 * our local APIC. We have to wait for the IPI or we'll 208 * lock up on an APIC access. 209 */ 210 if (apic->wait_for_init_deassert) 211 apic->wait_for_init_deassert(&init_deasserted); 212 213 /* 214 * (This works even if the APIC is not enabled.) 215 */ 216 phys_id = read_apic_id(); 217 cpuid = smp_processor_id(); 218 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { 219 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, 220 phys_id, cpuid); 221 } 222 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); 223 224 /* 225 * STARTUP IPIs are fragile beasts as they might sometimes 226 * trigger some glue motherboard logic. Complete APIC bus 227 * silence for 1 second, this overestimates the time the 228 * boot CPU is spending to send the up to 2 STARTUP IPIs 229 * by a factor of two. This should be enough. 230 */ 231 232 /* 233 * Waiting 2s total for startup (udelay is not yet working) 234 */ 235 timeout = jiffies + 2*HZ; 236 while (time_before(jiffies, timeout)) { 237 /* 238 * Has the boot CPU finished it's STARTUP sequence? 239 */ 240 if (cpumask_test_cpu(cpuid, cpu_callout_mask)) 241 break; 242 cpu_relax(); 243 } 244 245 if (!time_before(jiffies, timeout)) { 246 panic("%s: CPU%d started up but did not get a callout!\n", 247 __func__, cpuid); 248 } 249 250 /* 251 * the boot CPU has finished the init stage and is spinning 252 * on callin_map until we finish. We are free to set up this 253 * CPU, first the APIC. (this is probably redundant on most 254 * boards) 255 */ 256 257 pr_debug("CALLIN, before setup_local_APIC().\n"); 258 if (apic->smp_callin_clear_local_apic) 259 apic->smp_callin_clear_local_apic(); 260 setup_local_APIC(); 261 end_local_APIC_setup(); 262 map_cpu_to_logical_apicid(); 263 264 /* 265 * Need to setup vector mappings before we enable interrupts. 266 */ 267 setup_vector_irq(smp_processor_id()); 268 /* 269 * Get our bogomips. 270 * 271 * Need to enable IRQs because it can take longer and then 272 * the NMI watchdog might kill us. 273 */ 274 local_irq_enable(); 275 calibrate_delay(); 276 local_irq_disable(); 277 pr_debug("Stack at about %p\n", &cpuid); 278 279 /* 280 * Save our processor parameters 281 */ 282 smp_store_cpu_info(cpuid); 283 284 /* 285 * This must be done before setting cpu_online_mask 286 * or calling notify_cpu_starting. 287 */ 288 set_cpu_sibling_map(raw_smp_processor_id()); 289 wmb(); 290 291 notify_cpu_starting(cpuid); 292 293 /* 294 * Allow the master to continue. 295 */ 296 cpumask_set_cpu(cpuid, cpu_callin_mask); 297 } 298 299 /* 300 * Activate a secondary processor. 301 */ 302 notrace static void __cpuinit start_secondary(void *unused) 303 { 304 /* 305 * Don't put *anything* before cpu_init(), SMP booting is too 306 * fragile that we want to limit the things done here to the 307 * most necessary things. 308 */ 309 cpu_init(); 310 preempt_disable(); 311 smp_callin(); 312 313 #ifdef CONFIG_X86_32 314 /* switch away from the initial page table */ 315 load_cr3(swapper_pg_dir); 316 __flush_tlb_all(); 317 #endif 318 319 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 320 barrier(); 321 /* 322 * Check TSC synchronization with the BP: 323 */ 324 check_tsc_sync_target(); 325 326 /* 327 * We need to hold call_lock, so there is no inconsistency 328 * between the time smp_call_function() determines number of 329 * IPI recipients, and the time when the determination is made 330 * for which cpus receive the IPI. Holding this 331 * lock helps us to not include this cpu in a currently in progress 332 * smp_call_function(). 333 * 334 * We need to hold vector_lock so there the set of online cpus 335 * does not change while we are assigning vectors to cpus. Holding 336 * this lock ensures we don't half assign or remove an irq from a cpu. 337 */ 338 ipi_call_lock(); 339 lock_vector_lock(); 340 set_cpu_online(smp_processor_id(), true); 341 unlock_vector_lock(); 342 ipi_call_unlock(); 343 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; 344 x86_platform.nmi_init(); 345 346 /* enable local interrupts */ 347 local_irq_enable(); 348 349 /* to prevent fake stack check failure in clock setup */ 350 boot_init_stack_canary(); 351 352 x86_cpuinit.setup_percpu_clockev(); 353 354 wmb(); 355 cpu_idle(); 356 } 357 358 #ifdef CONFIG_CPUMASK_OFFSTACK 359 /* In this case, llc_shared_map is a pointer to a cpumask. */ 360 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, 361 const struct cpuinfo_x86 *src) 362 { 363 struct cpumask *llc = dst->llc_shared_map; 364 *dst = *src; 365 dst->llc_shared_map = llc; 366 } 367 #else 368 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, 369 const struct cpuinfo_x86 *src) 370 { 371 *dst = *src; 372 } 373 #endif /* CONFIG_CPUMASK_OFFSTACK */ 374 375 /* 376 * The bootstrap kernel entry code has set these up. Save them for 377 * a given CPU 378 */ 379 380 void __cpuinit smp_store_cpu_info(int id) 381 { 382 struct cpuinfo_x86 *c = &cpu_data(id); 383 384 copy_cpuinfo_x86(c, &boot_cpu_data); 385 c->cpu_index = id; 386 if (id != 0) 387 identify_secondary_cpu(c); 388 } 389 390 static void __cpuinit link_thread_siblings(int cpu1, int cpu2) 391 { 392 struct cpuinfo_x86 *c1 = &cpu_data(cpu1); 393 struct cpuinfo_x86 *c2 = &cpu_data(cpu2); 394 395 cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2)); 396 cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1)); 397 cpumask_set_cpu(cpu1, cpu_core_mask(cpu2)); 398 cpumask_set_cpu(cpu2, cpu_core_mask(cpu1)); 399 cpumask_set_cpu(cpu1, c2->llc_shared_map); 400 cpumask_set_cpu(cpu2, c1->llc_shared_map); 401 } 402 403 404 void __cpuinit set_cpu_sibling_map(int cpu) 405 { 406 int i; 407 struct cpuinfo_x86 *c = &cpu_data(cpu); 408 409 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 410 411 if (smp_num_siblings > 1) { 412 for_each_cpu(i, cpu_sibling_setup_mask) { 413 struct cpuinfo_x86 *o = &cpu_data(i); 414 415 if (cpu_has(c, X86_FEATURE_TOPOEXT)) { 416 if (c->phys_proc_id == o->phys_proc_id && 417 c->compute_unit_id == o->compute_unit_id) 418 link_thread_siblings(cpu, i); 419 } else if (c->phys_proc_id == o->phys_proc_id && 420 c->cpu_core_id == o->cpu_core_id) { 421 link_thread_siblings(cpu, i); 422 } 423 } 424 } else { 425 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); 426 } 427 428 cpumask_set_cpu(cpu, c->llc_shared_map); 429 430 if (__this_cpu_read(cpu_info.x86_max_cores) == 1) { 431 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); 432 c->booted_cores = 1; 433 return; 434 } 435 436 for_each_cpu(i, cpu_sibling_setup_mask) { 437 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && 438 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { 439 cpumask_set_cpu(i, c->llc_shared_map); 440 cpumask_set_cpu(cpu, cpu_data(i).llc_shared_map); 441 } 442 if (c->phys_proc_id == cpu_data(i).phys_proc_id) { 443 cpumask_set_cpu(i, cpu_core_mask(cpu)); 444 cpumask_set_cpu(cpu, cpu_core_mask(i)); 445 /* 446 * Does this new cpu bringup a new core? 447 */ 448 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { 449 /* 450 * for each core in package, increment 451 * the booted_cores for this new cpu 452 */ 453 if (cpumask_first(cpu_sibling_mask(i)) == i) 454 c->booted_cores++; 455 /* 456 * increment the core count for all 457 * the other cpus in this package 458 */ 459 if (i != cpu) 460 cpu_data(i).booted_cores++; 461 } else if (i != cpu && !c->booted_cores) 462 c->booted_cores = cpu_data(i).booted_cores; 463 } 464 } 465 } 466 467 /* maps the cpu to the sched domain representing multi-core */ 468 const struct cpumask *cpu_coregroup_mask(int cpu) 469 { 470 struct cpuinfo_x86 *c = &cpu_data(cpu); 471 /* 472 * For perf, we return last level cache shared map. 473 * And for power savings, we return cpu_core_map 474 */ 475 if ((sched_mc_power_savings || sched_smt_power_savings) && 476 !(cpu_has(c, X86_FEATURE_AMD_DCM))) 477 return cpu_core_mask(cpu); 478 else 479 return c->llc_shared_map; 480 } 481 482 static void impress_friends(void) 483 { 484 int cpu; 485 unsigned long bogosum = 0; 486 /* 487 * Allow the user to impress friends. 488 */ 489 pr_debug("Before bogomips.\n"); 490 for_each_possible_cpu(cpu) 491 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 492 bogosum += cpu_data(cpu).loops_per_jiffy; 493 printk(KERN_INFO 494 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", 495 num_online_cpus(), 496 bogosum/(500000/HZ), 497 (bogosum/(5000/HZ))%100); 498 499 pr_debug("Before bogocount - setting activated=1.\n"); 500 } 501 502 void __inquire_remote_apic(int apicid) 503 { 504 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 505 char *names[] = { "ID", "VERSION", "SPIV" }; 506 int timeout; 507 u32 status; 508 509 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); 510 511 for (i = 0; i < ARRAY_SIZE(regs); i++) { 512 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); 513 514 /* 515 * Wait for idle. 516 */ 517 status = safe_apic_wait_icr_idle(); 518 if (status) 519 printk(KERN_CONT 520 "a previous APIC delivery may have failed\n"); 521 522 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 523 524 timeout = 0; 525 do { 526 udelay(100); 527 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 528 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 529 530 switch (status) { 531 case APIC_ICR_RR_VALID: 532 status = apic_read(APIC_RRR); 533 printk(KERN_CONT "%08x\n", status); 534 break; 535 default: 536 printk(KERN_CONT "failed\n"); 537 } 538 } 539 } 540 541 /* 542 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 543 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 544 * won't ... remember to clear down the APIC, etc later. 545 */ 546 int __cpuinit 547 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) 548 { 549 unsigned long send_status, accept_status = 0; 550 int maxlvt; 551 552 /* Target chip */ 553 /* Boot on the stack */ 554 /* Kick the second */ 555 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); 556 557 pr_debug("Waiting for send to finish...\n"); 558 send_status = safe_apic_wait_icr_idle(); 559 560 /* 561 * Give the other CPU some time to accept the IPI. 562 */ 563 udelay(200); 564 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 565 maxlvt = lapic_get_maxlvt(); 566 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 567 apic_write(APIC_ESR, 0); 568 accept_status = (apic_read(APIC_ESR) & 0xEF); 569 } 570 pr_debug("NMI sent.\n"); 571 572 if (send_status) 573 printk(KERN_ERR "APIC never delivered???\n"); 574 if (accept_status) 575 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 576 577 return (send_status | accept_status); 578 } 579 580 static int __cpuinit 581 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 582 { 583 unsigned long send_status, accept_status = 0; 584 int maxlvt, num_starts, j; 585 586 maxlvt = lapic_get_maxlvt(); 587 588 /* 589 * Be paranoid about clearing APIC errors. 590 */ 591 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 592 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 593 apic_write(APIC_ESR, 0); 594 apic_read(APIC_ESR); 595 } 596 597 pr_debug("Asserting INIT.\n"); 598 599 /* 600 * Turn INIT on target chip 601 */ 602 /* 603 * Send IPI 604 */ 605 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 606 phys_apicid); 607 608 pr_debug("Waiting for send to finish...\n"); 609 send_status = safe_apic_wait_icr_idle(); 610 611 mdelay(10); 612 613 pr_debug("Deasserting INIT.\n"); 614 615 /* Target chip */ 616 /* Send IPI */ 617 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 618 619 pr_debug("Waiting for send to finish...\n"); 620 send_status = safe_apic_wait_icr_idle(); 621 622 mb(); 623 atomic_set(&init_deasserted, 1); 624 625 /* 626 * Should we send STARTUP IPIs ? 627 * 628 * Determine this based on the APIC version. 629 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 630 */ 631 if (APIC_INTEGRATED(apic_version[phys_apicid])) 632 num_starts = 2; 633 else 634 num_starts = 0; 635 636 /* 637 * Paravirt / VMI wants a startup IPI hook here to set up the 638 * target processor state. 639 */ 640 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, 641 stack_start); 642 643 /* 644 * Run STARTUP IPI loop. 645 */ 646 pr_debug("#startup loops: %d.\n", num_starts); 647 648 for (j = 1; j <= num_starts; j++) { 649 pr_debug("Sending STARTUP #%d.\n", j); 650 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 651 apic_write(APIC_ESR, 0); 652 apic_read(APIC_ESR); 653 pr_debug("After apic_write.\n"); 654 655 /* 656 * STARTUP IPI 657 */ 658 659 /* Target chip */ 660 /* Boot on the stack */ 661 /* Kick the second */ 662 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 663 phys_apicid); 664 665 /* 666 * Give the other CPU some time to accept the IPI. 667 */ 668 udelay(300); 669 670 pr_debug("Startup point 1.\n"); 671 672 pr_debug("Waiting for send to finish...\n"); 673 send_status = safe_apic_wait_icr_idle(); 674 675 /* 676 * Give the other CPU some time to accept the IPI. 677 */ 678 udelay(200); 679 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 680 apic_write(APIC_ESR, 0); 681 accept_status = (apic_read(APIC_ESR) & 0xEF); 682 if (send_status || accept_status) 683 break; 684 } 685 pr_debug("After Startup.\n"); 686 687 if (send_status) 688 printk(KERN_ERR "APIC never delivered???\n"); 689 if (accept_status) 690 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 691 692 return (send_status | accept_status); 693 } 694 695 struct create_idle { 696 struct work_struct work; 697 struct task_struct *idle; 698 struct completion done; 699 int cpu; 700 }; 701 702 static void __cpuinit do_fork_idle(struct work_struct *work) 703 { 704 struct create_idle *c_idle = 705 container_of(work, struct create_idle, work); 706 707 c_idle->idle = fork_idle(c_idle->cpu); 708 complete(&c_idle->done); 709 } 710 711 /* reduce the number of lines printed when booting a large cpu count system */ 712 static void __cpuinit announce_cpu(int cpu, int apicid) 713 { 714 static int current_node = -1; 715 int node = early_cpu_to_node(cpu); 716 717 if (system_state == SYSTEM_BOOTING) { 718 if (node != current_node) { 719 if (current_node > (-1)) 720 pr_cont(" Ok.\n"); 721 current_node = node; 722 pr_info("Booting Node %3d, Processors ", node); 723 } 724 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : ""); 725 return; 726 } else 727 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 728 node, cpu, apicid); 729 } 730 731 /* 732 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 733 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 734 * Returns zero if CPU booted OK, else error code from 735 * ->wakeup_secondary_cpu. 736 */ 737 static int __cpuinit do_boot_cpu(int apicid, int cpu) 738 { 739 unsigned long boot_error = 0; 740 unsigned long start_ip; 741 int timeout; 742 struct create_idle c_idle = { 743 .cpu = cpu, 744 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), 745 }; 746 747 INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle); 748 749 alternatives_smp_switch(1); 750 751 c_idle.idle = get_idle_for_cpu(cpu); 752 753 /* 754 * We can't use kernel_thread since we must avoid to 755 * reschedule the child. 756 */ 757 if (c_idle.idle) { 758 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) 759 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); 760 init_idle(c_idle.idle, cpu); 761 goto do_rest; 762 } 763 764 schedule_work(&c_idle.work); 765 wait_for_completion(&c_idle.done); 766 767 if (IS_ERR(c_idle.idle)) { 768 printk("failed fork for CPU %d\n", cpu); 769 destroy_work_on_stack(&c_idle.work); 770 return PTR_ERR(c_idle.idle); 771 } 772 773 set_idle_for_cpu(cpu, c_idle.idle); 774 do_rest: 775 per_cpu(current_task, cpu) = c_idle.idle; 776 #ifdef CONFIG_X86_32 777 /* Stack for startup_32 can be just as for start_secondary onwards */ 778 irq_ctx_init(cpu); 779 #else 780 clear_tsk_thread_flag(c_idle.idle, TIF_FORK); 781 initial_gs = per_cpu_offset(cpu); 782 per_cpu(kernel_stack, cpu) = 783 (unsigned long)task_stack_page(c_idle.idle) - 784 KERNEL_STACK_OFFSET + THREAD_SIZE; 785 #endif 786 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 787 initial_code = (unsigned long)start_secondary; 788 stack_start = c_idle.idle->thread.sp; 789 790 /* start_ip had better be page-aligned! */ 791 start_ip = setup_trampoline(); 792 793 /* So we see what's up */ 794 announce_cpu(cpu, apicid); 795 796 /* 797 * This grunge runs the startup process for 798 * the targeted processor. 799 */ 800 801 atomic_set(&init_deasserted, 0); 802 803 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 804 805 pr_debug("Setting warm reset code and vector.\n"); 806 807 smpboot_setup_warm_reset_vector(start_ip); 808 /* 809 * Be paranoid about clearing APIC errors. 810 */ 811 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 812 apic_write(APIC_ESR, 0); 813 apic_read(APIC_ESR); 814 } 815 } 816 817 /* 818 * Kick the secondary CPU. Use the method in the APIC driver 819 * if it's defined - or use an INIT boot APIC message otherwise: 820 */ 821 if (apic->wakeup_secondary_cpu) 822 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 823 else 824 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 825 826 if (!boot_error) { 827 /* 828 * allow APs to start initializing. 829 */ 830 pr_debug("Before Callout %d.\n", cpu); 831 cpumask_set_cpu(cpu, cpu_callout_mask); 832 pr_debug("After Callout %d.\n", cpu); 833 834 /* 835 * Wait 5s total for a response 836 */ 837 for (timeout = 0; timeout < 50000; timeout++) { 838 if (cpumask_test_cpu(cpu, cpu_callin_mask)) 839 break; /* It has booted */ 840 udelay(100); 841 /* 842 * Allow other tasks to run while we wait for the 843 * AP to come online. This also gives a chance 844 * for the MTRR work(triggered by the AP coming online) 845 * to be completed in the stop machine context. 846 */ 847 schedule(); 848 } 849 850 if (cpumask_test_cpu(cpu, cpu_callin_mask)) 851 pr_debug("CPU%d: has booted.\n", cpu); 852 else { 853 boot_error = 1; 854 if (*((volatile unsigned char *)trampoline_base) 855 == 0xA5) 856 /* trampoline started but...? */ 857 pr_err("CPU%d: Stuck ??\n", cpu); 858 else 859 /* trampoline code not run */ 860 pr_err("CPU%d: Not responding.\n", cpu); 861 if (apic->inquire_remote_apic) 862 apic->inquire_remote_apic(apicid); 863 } 864 } 865 866 if (boot_error) { 867 /* Try to put things back the way they were before ... */ 868 numa_remove_cpu(cpu); /* was set by numa_add_cpu */ 869 870 /* was set by do_boot_cpu() */ 871 cpumask_clear_cpu(cpu, cpu_callout_mask); 872 873 /* was set by cpu_init() */ 874 cpumask_clear_cpu(cpu, cpu_initialized_mask); 875 876 set_cpu_present(cpu, false); 877 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; 878 } 879 880 /* mark "stuck" area as not stuck */ 881 *((volatile unsigned long *)trampoline_base) = 0; 882 883 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 884 /* 885 * Cleanup possible dangling ends... 886 */ 887 smpboot_restore_warm_reset_vector(); 888 } 889 890 destroy_work_on_stack(&c_idle.work); 891 return boot_error; 892 } 893 894 int __cpuinit native_cpu_up(unsigned int cpu) 895 { 896 int apicid = apic->cpu_present_to_apicid(cpu); 897 unsigned long flags; 898 int err; 899 900 WARN_ON(irqs_disabled()); 901 902 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 903 904 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || 905 !physid_isset(apicid, phys_cpu_present_map)) { 906 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); 907 return -EINVAL; 908 } 909 910 /* 911 * Already booted CPU? 912 */ 913 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 914 pr_debug("do_boot_cpu %d Already started\n", cpu); 915 return -ENOSYS; 916 } 917 918 /* 919 * Save current MTRR state in case it was changed since early boot 920 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 921 */ 922 mtrr_save_state(); 923 924 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; 925 926 err = do_boot_cpu(apicid, cpu); 927 if (err) { 928 pr_debug("do_boot_cpu failed %d\n", err); 929 return -EIO; 930 } 931 932 /* 933 * Check TSC synchronization with the AP (keep irqs disabled 934 * while doing so): 935 */ 936 local_irq_save(flags); 937 check_tsc_sync_source(cpu); 938 local_irq_restore(flags); 939 940 while (!cpu_online(cpu)) { 941 cpu_relax(); 942 touch_nmi_watchdog(); 943 } 944 945 return 0; 946 } 947 948 /* 949 * Fall back to non SMP mode after errors. 950 * 951 * RED-PEN audit/test this more. I bet there is more state messed up here. 952 */ 953 static __init void disable_smp(void) 954 { 955 init_cpu_present(cpumask_of(0)); 956 init_cpu_possible(cpumask_of(0)); 957 smpboot_clear_io_apic_irqs(); 958 959 if (smp_found_config) 960 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 961 else 962 physid_set_mask_of_physid(0, &phys_cpu_present_map); 963 map_cpu_to_logical_apicid(); 964 cpumask_set_cpu(0, cpu_sibling_mask(0)); 965 cpumask_set_cpu(0, cpu_core_mask(0)); 966 } 967 968 /* 969 * Various sanity checks. 970 */ 971 static int __init smp_sanity_check(unsigned max_cpus) 972 { 973 preempt_disable(); 974 975 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 976 if (def_to_bigsmp && nr_cpu_ids > 8) { 977 unsigned int cpu; 978 unsigned nr; 979 980 printk(KERN_WARNING 981 "More than 8 CPUs detected - skipping them.\n" 982 "Use CONFIG_X86_BIGSMP.\n"); 983 984 nr = 0; 985 for_each_present_cpu(cpu) { 986 if (nr >= 8) 987 set_cpu_present(cpu, false); 988 nr++; 989 } 990 991 nr = 0; 992 for_each_possible_cpu(cpu) { 993 if (nr >= 8) 994 set_cpu_possible(cpu, false); 995 nr++; 996 } 997 998 nr_cpu_ids = 8; 999 } 1000 #endif 1001 1002 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1003 printk(KERN_WARNING 1004 "weird, boot CPU (#%d) not listed by the BIOS.\n", 1005 hard_smp_processor_id()); 1006 1007 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1008 } 1009 1010 /* 1011 * If we couldn't find an SMP configuration at boot time, 1012 * get out of here now! 1013 */ 1014 if (!smp_found_config && !acpi_lapic) { 1015 preempt_enable(); 1016 printk(KERN_NOTICE "SMP motherboard not detected.\n"); 1017 disable_smp(); 1018 if (APIC_init_uniprocessor()) 1019 printk(KERN_NOTICE "Local APIC not detected." 1020 " Using dummy APIC emulation.\n"); 1021 return -1; 1022 } 1023 1024 /* 1025 * Should not be necessary because the MP table should list the boot 1026 * CPU too, but we do it for the sake of robustness anyway. 1027 */ 1028 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1029 printk(KERN_NOTICE 1030 "weird, boot CPU (#%d) not listed by the BIOS.\n", 1031 boot_cpu_physical_apicid); 1032 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1033 } 1034 preempt_enable(); 1035 1036 /* 1037 * If we couldn't find a local APIC, then get out of here now! 1038 */ 1039 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 1040 !cpu_has_apic) { 1041 if (!disable_apic) { 1042 pr_err("BIOS bug, local APIC #%d not detected!...\n", 1043 boot_cpu_physical_apicid); 1044 pr_err("... forcing use of dummy APIC emulation." 1045 "(tell your hw vendor)\n"); 1046 } 1047 smpboot_clear_io_apic(); 1048 arch_disable_smp_support(); 1049 return -1; 1050 } 1051 1052 verify_local_APIC(); 1053 1054 /* 1055 * If SMP should be disabled, then really disable it! 1056 */ 1057 if (!max_cpus) { 1058 printk(KERN_INFO "SMP mode deactivated.\n"); 1059 smpboot_clear_io_apic(); 1060 1061 connect_bsp_APIC(); 1062 setup_local_APIC(); 1063 bsp_end_local_APIC_setup(); 1064 return -1; 1065 } 1066 1067 return 0; 1068 } 1069 1070 static void __init smp_cpu_index_default(void) 1071 { 1072 int i; 1073 struct cpuinfo_x86 *c; 1074 1075 for_each_possible_cpu(i) { 1076 c = &cpu_data(i); 1077 /* mark all to hotplug */ 1078 c->cpu_index = nr_cpu_ids; 1079 } 1080 } 1081 1082 /* 1083 * Prepare for SMP bootup. The MP table or ACPI has been read 1084 * earlier. Just do some sanity checking here and enable APIC mode. 1085 */ 1086 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1087 { 1088 unsigned int i; 1089 1090 preempt_disable(); 1091 smp_cpu_index_default(); 1092 memcpy(__this_cpu_ptr(&cpu_info), &boot_cpu_data, sizeof(cpu_info)); 1093 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1094 mb(); 1095 /* 1096 * Setup boot CPU information 1097 */ 1098 smp_store_cpu_info(0); /* Final full version of the data */ 1099 #ifdef CONFIG_X86_32 1100 boot_cpu_logical_apicid = logical_smp_processor_id(); 1101 #endif 1102 current_thread_info()->cpu = 0; /* needed? */ 1103 for_each_possible_cpu(i) { 1104 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1105 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1106 zalloc_cpumask_var(&cpu_data(i).llc_shared_map, GFP_KERNEL); 1107 } 1108 set_cpu_sibling_map(0); 1109 1110 1111 if (smp_sanity_check(max_cpus) < 0) { 1112 printk(KERN_INFO "SMP disabled\n"); 1113 disable_smp(); 1114 goto out; 1115 } 1116 1117 default_setup_apic_routing(); 1118 1119 preempt_disable(); 1120 if (read_apic_id() != boot_cpu_physical_apicid) { 1121 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1122 read_apic_id(), boot_cpu_physical_apicid); 1123 /* Or can we switch back to PIC here? */ 1124 } 1125 preempt_enable(); 1126 1127 connect_bsp_APIC(); 1128 1129 /* 1130 * Switch from PIC to APIC mode. 1131 */ 1132 setup_local_APIC(); 1133 1134 /* 1135 * Enable IO APIC before setting up error vector 1136 */ 1137 if (!skip_ioapic_setup && nr_ioapics) 1138 enable_IO_APIC(); 1139 1140 bsp_end_local_APIC_setup(); 1141 1142 map_cpu_to_logical_apicid(); 1143 1144 if (apic->setup_portio_remap) 1145 apic->setup_portio_remap(); 1146 1147 smpboot_setup_io_apic(); 1148 /* 1149 * Set up local APIC timer on boot CPU. 1150 */ 1151 1152 printk(KERN_INFO "CPU%d: ", 0); 1153 print_cpu_info(&cpu_data(0)); 1154 x86_init.timers.setup_percpu_clockev(); 1155 1156 if (is_uv_system()) 1157 uv_system_init(); 1158 1159 set_mtrr_aps_delayed_init(); 1160 out: 1161 preempt_enable(); 1162 } 1163 1164 void arch_disable_nonboot_cpus_begin(void) 1165 { 1166 /* 1167 * Avoid the smp alternatives switch during the disable_nonboot_cpus(). 1168 * In the suspend path, we will be back in the SMP mode shortly anyways. 1169 */ 1170 skip_smp_alternatives = true; 1171 } 1172 1173 void arch_disable_nonboot_cpus_end(void) 1174 { 1175 skip_smp_alternatives = false; 1176 } 1177 1178 void arch_enable_nonboot_cpus_begin(void) 1179 { 1180 set_mtrr_aps_delayed_init(); 1181 } 1182 1183 void arch_enable_nonboot_cpus_end(void) 1184 { 1185 mtrr_aps_init(); 1186 } 1187 1188 /* 1189 * Early setup to make printk work. 1190 */ 1191 void __init native_smp_prepare_boot_cpu(void) 1192 { 1193 int me = smp_processor_id(); 1194 switch_to_new_gdt(me); 1195 /* already set me in cpu_online_mask in boot_cpu_init() */ 1196 cpumask_set_cpu(me, cpu_callout_mask); 1197 per_cpu(cpu_state, me) = CPU_ONLINE; 1198 } 1199 1200 void __init native_smp_cpus_done(unsigned int max_cpus) 1201 { 1202 pr_debug("Boot done.\n"); 1203 1204 impress_friends(); 1205 #ifdef CONFIG_X86_IO_APIC 1206 setup_ioapic_dest(); 1207 #endif 1208 mtrr_aps_init(); 1209 } 1210 1211 static int __initdata setup_possible_cpus = -1; 1212 static int __init _setup_possible_cpus(char *str) 1213 { 1214 get_option(&str, &setup_possible_cpus); 1215 return 0; 1216 } 1217 early_param("possible_cpus", _setup_possible_cpus); 1218 1219 1220 /* 1221 * cpu_possible_mask should be static, it cannot change as cpu's 1222 * are onlined, or offlined. The reason is per-cpu data-structures 1223 * are allocated by some modules at init time, and dont expect to 1224 * do this dynamically on cpu arrival/departure. 1225 * cpu_present_mask on the other hand can change dynamically. 1226 * In case when cpu_hotplug is not compiled, then we resort to current 1227 * behaviour, which is cpu_possible == cpu_present. 1228 * - Ashok Raj 1229 * 1230 * Three ways to find out the number of additional hotplug CPUs: 1231 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1232 * - The user can overwrite it with possible_cpus=NUM 1233 * - Otherwise don't reserve additional CPUs. 1234 * We do this because additional CPUs waste a lot of memory. 1235 * -AK 1236 */ 1237 __init void prefill_possible_map(void) 1238 { 1239 int i, possible; 1240 1241 /* no processor from mptable or madt */ 1242 if (!num_processors) 1243 num_processors = 1; 1244 1245 i = setup_max_cpus ?: 1; 1246 if (setup_possible_cpus == -1) { 1247 possible = num_processors; 1248 #ifdef CONFIG_HOTPLUG_CPU 1249 if (setup_max_cpus) 1250 possible += disabled_cpus; 1251 #else 1252 if (possible > i) 1253 possible = i; 1254 #endif 1255 } else 1256 possible = setup_possible_cpus; 1257 1258 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1259 1260 /* nr_cpu_ids could be reduced via nr_cpus= */ 1261 if (possible > nr_cpu_ids) { 1262 printk(KERN_WARNING 1263 "%d Processors exceeds NR_CPUS limit of %d\n", 1264 possible, nr_cpu_ids); 1265 possible = nr_cpu_ids; 1266 } 1267 1268 #ifdef CONFIG_HOTPLUG_CPU 1269 if (!setup_max_cpus) 1270 #endif 1271 if (possible > i) { 1272 printk(KERN_WARNING 1273 "%d Processors exceeds max_cpus limit of %u\n", 1274 possible, setup_max_cpus); 1275 possible = i; 1276 } 1277 1278 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", 1279 possible, max_t(int, possible - num_processors, 0)); 1280 1281 for (i = 0; i < possible; i++) 1282 set_cpu_possible(i, true); 1283 for (; i < NR_CPUS; i++) 1284 set_cpu_possible(i, false); 1285 1286 nr_cpu_ids = possible; 1287 } 1288 1289 #ifdef CONFIG_HOTPLUG_CPU 1290 1291 static void remove_siblinginfo(int cpu) 1292 { 1293 int sibling; 1294 struct cpuinfo_x86 *c = &cpu_data(cpu); 1295 1296 for_each_cpu(sibling, cpu_core_mask(cpu)) { 1297 cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); 1298 /*/ 1299 * last thread sibling in this cpu core going down 1300 */ 1301 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) 1302 cpu_data(sibling).booted_cores--; 1303 } 1304 1305 for_each_cpu(sibling, cpu_sibling_mask(cpu)) 1306 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); 1307 cpumask_clear(cpu_sibling_mask(cpu)); 1308 cpumask_clear(cpu_core_mask(cpu)); 1309 c->phys_proc_id = 0; 1310 c->cpu_core_id = 0; 1311 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1312 } 1313 1314 static void __ref remove_cpu_from_maps(int cpu) 1315 { 1316 set_cpu_online(cpu, false); 1317 cpumask_clear_cpu(cpu, cpu_callout_mask); 1318 cpumask_clear_cpu(cpu, cpu_callin_mask); 1319 /* was set by cpu_init() */ 1320 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1321 numa_remove_cpu(cpu); 1322 } 1323 1324 void cpu_disable_common(void) 1325 { 1326 int cpu = smp_processor_id(); 1327 1328 remove_siblinginfo(cpu); 1329 1330 /* It's now safe to remove this processor from the online map */ 1331 lock_vector_lock(); 1332 remove_cpu_from_maps(cpu); 1333 unlock_vector_lock(); 1334 fixup_irqs(); 1335 } 1336 1337 int native_cpu_disable(void) 1338 { 1339 int cpu = smp_processor_id(); 1340 1341 /* 1342 * Perhaps use cpufreq to drop frequency, but that could go 1343 * into generic code. 1344 * 1345 * We won't take down the boot processor on i386 due to some 1346 * interrupts only being able to be serviced by the BSP. 1347 * Especially so if we're not using an IOAPIC -zwane 1348 */ 1349 if (cpu == 0) 1350 return -EBUSY; 1351 1352 clear_local_APIC(); 1353 1354 cpu_disable_common(); 1355 return 0; 1356 } 1357 1358 void native_cpu_die(unsigned int cpu) 1359 { 1360 /* We don't do anything here: idle task is faking death itself. */ 1361 unsigned int i; 1362 1363 for (i = 0; i < 10; i++) { 1364 /* They ack this in play_dead by setting CPU_DEAD */ 1365 if (per_cpu(cpu_state, cpu) == CPU_DEAD) { 1366 if (system_state == SYSTEM_RUNNING) 1367 pr_info("CPU %u is now offline\n", cpu); 1368 1369 if (1 == num_online_cpus()) 1370 alternatives_smp_switch(0); 1371 return; 1372 } 1373 msleep(100); 1374 } 1375 pr_err("CPU %u didn't die...\n", cpu); 1376 } 1377 1378 void play_dead_common(void) 1379 { 1380 idle_task_exit(); 1381 reset_lazy_tlbstate(); 1382 c1e_remove_cpu(raw_smp_processor_id()); 1383 1384 mb(); 1385 /* Ack it */ 1386 __this_cpu_write(cpu_state, CPU_DEAD); 1387 1388 /* 1389 * With physical CPU hotplug, we should halt the cpu 1390 */ 1391 local_irq_disable(); 1392 } 1393 1394 /* 1395 * We need to flush the caches before going to sleep, lest we have 1396 * dirty data in our caches when we come back up. 1397 */ 1398 static inline void mwait_play_dead(void) 1399 { 1400 unsigned int eax, ebx, ecx, edx; 1401 unsigned int highest_cstate = 0; 1402 unsigned int highest_subcstate = 0; 1403 int i; 1404 void *mwait_ptr; 1405 struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info); 1406 1407 if (!(cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c))) 1408 return; 1409 if (!cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_CLFLSH)) 1410 return; 1411 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1412 return; 1413 1414 eax = CPUID_MWAIT_LEAF; 1415 ecx = 0; 1416 native_cpuid(&eax, &ebx, &ecx, &edx); 1417 1418 /* 1419 * eax will be 0 if EDX enumeration is not valid. 1420 * Initialized below to cstate, sub_cstate value when EDX is valid. 1421 */ 1422 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1423 eax = 0; 1424 } else { 1425 edx >>= MWAIT_SUBSTATE_SIZE; 1426 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1427 if (edx & MWAIT_SUBSTATE_MASK) { 1428 highest_cstate = i; 1429 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1430 } 1431 } 1432 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1433 (highest_subcstate - 1); 1434 } 1435 1436 /* 1437 * This should be a memory location in a cache line which is 1438 * unlikely to be touched by other processors. The actual 1439 * content is immaterial as it is not actually modified in any way. 1440 */ 1441 mwait_ptr = ¤t_thread_info()->flags; 1442 1443 wbinvd(); 1444 1445 while (1) { 1446 /* 1447 * The CLFLUSH is a workaround for erratum AAI65 for 1448 * the Xeon 7400 series. It's not clear it is actually 1449 * needed, but it should be harmless in either case. 1450 * The WBINVD is insufficient due to the spurious-wakeup 1451 * case where we return around the loop. 1452 */ 1453 clflush(mwait_ptr); 1454 __monitor(mwait_ptr, 0, 0); 1455 mb(); 1456 __mwait(eax, 0); 1457 } 1458 } 1459 1460 static inline void hlt_play_dead(void) 1461 { 1462 if (__this_cpu_read(cpu_info.x86) >= 4) 1463 wbinvd(); 1464 1465 while (1) { 1466 native_halt(); 1467 } 1468 } 1469 1470 void native_play_dead(void) 1471 { 1472 play_dead_common(); 1473 tboot_shutdown(TB_SHUTDOWN_WFS); 1474 1475 mwait_play_dead(); /* Only returns on failure */ 1476 hlt_play_dead(); 1477 } 1478 1479 #else /* ... !CONFIG_HOTPLUG_CPU */ 1480 int native_cpu_disable(void) 1481 { 1482 return -ENOSYS; 1483 } 1484 1485 void native_cpu_die(unsigned int cpu) 1486 { 1487 /* We said "no" in __cpu_disable */ 1488 BUG(); 1489 } 1490 1491 void native_play_dead(void) 1492 { 1493 BUG(); 1494 } 1495 1496 #endif 1497