1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * x86 SMP booting functions 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 7 * Copyright 2001 Andi Kleen, SuSE Labs. 8 * 9 * Much of the core SMP work is based on previous work by Thomas Radke, to 10 * whom a great many thanks are extended. 11 * 12 * Thanks to Intel for making available several different Pentium, 13 * Pentium Pro and Pentium-II/Xeon MP machines. 14 * Original development of Linux SMP code supported by Caldera. 15 * 16 * Fixes 17 * Felix Koop : NR_CPUS used properly 18 * Jose Renau : Handle single CPU case. 19 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 20 * Greg Wright : Fix for kernel stacks panic. 21 * Erich Boleyn : MP v1.4 and additional changes. 22 * Matthias Sattler : Changes for 2.1 kernel map. 23 * Michel Lespinasse : Changes for 2.1 kernel map. 24 * Michael Chastain : Change trampoline.S to gnu as. 25 * Alan Cox : Dumb bug: 'B' step PPro's are fine 26 * Ingo Molnar : Added APIC timers, based on code 27 * from Jose Renau 28 * Ingo Molnar : various cleanups and rewrites 29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 31 * Andi Kleen : Changed for SMP boot into long mode. 32 * Martin J. Bligh : Added support for multi-quad systems 33 * Dave Jones : Report invalid combinations of Athlon CPUs. 34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 35 * Andi Kleen : Converted to new state machine. 36 * Ashok Raj : CPU hotplug support 37 * Glauber Costa : i386 and x86_64 integration 38 */ 39 40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/export.h> 45 #include <linux/sched.h> 46 #include <linux/sched/topology.h> 47 #include <linux/sched/hotplug.h> 48 #include <linux/sched/task_stack.h> 49 #include <linux/percpu.h> 50 #include <linux/memblock.h> 51 #include <linux/err.h> 52 #include <linux/nmi.h> 53 #include <linux/tboot.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 #include <linux/kexec.h> 57 #include <linux/numa.h> 58 #include <linux/pgtable.h> 59 #include <linux/overflow.h> 60 #include <linux/stackprotector.h> 61 #include <linux/cpuhotplug.h> 62 #include <linux/mc146818rtc.h> 63 #include <linux/acpi.h> 64 65 #include <asm/acpi.h> 66 #include <asm/cacheinfo.h> 67 #include <asm/cpuid.h> 68 #include <asm/desc.h> 69 #include <asm/nmi.h> 70 #include <asm/irq.h> 71 #include <asm/realmode.h> 72 #include <asm/cpu.h> 73 #include <asm/numa.h> 74 #include <asm/tlbflush.h> 75 #include <asm/mtrr.h> 76 #include <asm/mwait.h> 77 #include <asm/apic.h> 78 #include <asm/io_apic.h> 79 #include <asm/fpu/api.h> 80 #include <asm/setup.h> 81 #include <asm/uv/uv.h> 82 #include <asm/microcode.h> 83 #include <asm/i8259.h> 84 #include <asm/misc.h> 85 #include <asm/qspinlock.h> 86 #include <asm/intel-family.h> 87 #include <asm/cpu_device_id.h> 88 #include <asm/spec-ctrl.h> 89 #include <asm/hw_irq.h> 90 #include <asm/stackprotector.h> 91 #include <asm/sev.h> 92 #include <asm/spec-ctrl.h> 93 94 /* representing HT siblings of each logical CPU */ 95 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 96 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 97 98 /* representing HT and core siblings of each logical CPU */ 99 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 100 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 101 102 /* representing HT, core, and die siblings of each logical CPU */ 103 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); 104 EXPORT_PER_CPU_SYMBOL(cpu_die_map); 105 106 /* CPUs which are the primary SMT threads */ 107 struct cpumask __cpu_primary_thread_mask __read_mostly; 108 109 /* Representing CPUs for which sibling maps can be computed */ 110 static cpumask_var_t cpu_sibling_setup_mask; 111 112 struct mwait_cpu_dead { 113 unsigned int control; 114 unsigned int status; 115 }; 116 117 #define CPUDEAD_MWAIT_WAIT 0xDEADBEEF 118 #define CPUDEAD_MWAIT_KEXEC_HLT 0x4A17DEAD 119 120 /* 121 * Cache line aligned data for mwait_play_dead(). Separate on purpose so 122 * that it's unlikely to be touched by other CPUs. 123 */ 124 static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead); 125 126 /* Maximum number of SMT threads on any online core */ 127 int __read_mostly __max_smt_threads = 1; 128 129 /* Flag to indicate if a complete sched domain rebuild is required */ 130 bool x86_topology_update; 131 132 int arch_update_cpu_topology(void) 133 { 134 int retval = x86_topology_update; 135 136 x86_topology_update = false; 137 return retval; 138 } 139 140 static unsigned int smpboot_warm_reset_vector_count; 141 142 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 143 { 144 unsigned long flags; 145 146 spin_lock_irqsave(&rtc_lock, flags); 147 if (!smpboot_warm_reset_vector_count++) { 148 CMOS_WRITE(0xa, 0xf); 149 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = start_eip >> 4; 150 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = start_eip & 0xf; 151 } 152 spin_unlock_irqrestore(&rtc_lock, flags); 153 } 154 155 static inline void smpboot_restore_warm_reset_vector(void) 156 { 157 unsigned long flags; 158 159 /* 160 * Paranoid: Set warm reset code and vector here back 161 * to default values. 162 */ 163 spin_lock_irqsave(&rtc_lock, flags); 164 if (!--smpboot_warm_reset_vector_count) { 165 CMOS_WRITE(0, 0xf); 166 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 167 } 168 spin_unlock_irqrestore(&rtc_lock, flags); 169 170 } 171 172 /* Run the next set of setup steps for the upcoming CPU */ 173 static void ap_starting(void) 174 { 175 int cpuid = smp_processor_id(); 176 177 /* Mop up eventual mwait_play_dead() wreckage */ 178 this_cpu_write(mwait_cpu_dead.status, 0); 179 this_cpu_write(mwait_cpu_dead.control, 0); 180 181 /* 182 * If woken up by an INIT in an 82489DX configuration the alive 183 * synchronization guarantees that the CPU does not reach this 184 * point before an INIT_deassert IPI reaches the local APIC, so it 185 * is now safe to touch the local APIC. 186 * 187 * Set up this CPU, first the APIC, which is probably redundant on 188 * most boards. 189 */ 190 apic_ap_setup(); 191 192 /* Save the processor parameters. */ 193 identify_secondary_cpu(cpuid); 194 195 /* 196 * The topology information must be up to date before 197 * notify_cpu_starting(). 198 */ 199 set_cpu_sibling_map(cpuid); 200 201 ap_init_aperfmperf(); 202 203 pr_debug("Stack at about %p\n", &cpuid); 204 205 wmb(); 206 207 /* 208 * This runs the AP through all the cpuhp states to its target 209 * state CPUHP_ONLINE. 210 */ 211 notify_cpu_starting(cpuid); 212 } 213 214 static void ap_calibrate_delay(void) 215 { 216 /* 217 * Calibrate the delay loop and update loops_per_jiffy in cpu_data. 218 * identify_secondary_cpu() stored a value that is close but not as 219 * accurate as the value just calculated. 220 * 221 * As this is invoked after the TSC synchronization check, 222 * calibrate_delay_is_known() will skip the calibration routine 223 * when TSC is synchronized across sockets. 224 */ 225 calibrate_delay(); 226 cpu_data(smp_processor_id()).loops_per_jiffy = loops_per_jiffy; 227 } 228 229 /* 230 * Activate a secondary processor. 231 */ 232 static void notrace __noendbr start_secondary(void *unused) 233 { 234 /* 235 * Don't put *anything* except direct CPU state initialization 236 * before cpu_init(), SMP booting is too fragile that we want to 237 * limit the things done here to the most necessary things. 238 */ 239 cr4_init(); 240 241 /* 242 * 32-bit specific. 64-bit reaches this code with the correct page 243 * table established. Yet another historical divergence. 244 */ 245 if (IS_ENABLED(CONFIG_X86_32)) { 246 /* switch away from the initial page table */ 247 load_cr3(swapper_pg_dir); 248 __flush_tlb_all(); 249 } 250 251 cpu_init_exception_handling(false); 252 253 /* 254 * Load the microcode before reaching the AP alive synchronization 255 * point below so it is not part of the full per CPU serialized 256 * bringup part when "parallel" bringup is enabled. 257 * 258 * That's even safe when hyperthreading is enabled in the CPU as 259 * the core code starts the primary threads first and leaves the 260 * secondary threads waiting for SIPI. Loading microcode on 261 * physical cores concurrently is a safe operation. 262 * 263 * This covers both the Intel specific issue that concurrent 264 * microcode loading on SMT siblings must be prohibited and the 265 * vendor independent issue`that microcode loading which changes 266 * CPUID, MSRs etc. must be strictly serialized to maintain 267 * software state correctness. 268 */ 269 load_ucode_ap(); 270 271 /* 272 * Synchronization point with the hotplug core. Sets this CPUs 273 * synchronization state to ALIVE and spin-waits for the control CPU to 274 * release this CPU for further bringup. 275 */ 276 cpuhp_ap_sync_alive(); 277 278 cpu_init(); 279 fpu__init_cpu(); 280 rcutree_report_cpu_starting(raw_smp_processor_id()); 281 x86_cpuinit.early_percpu_clock_init(); 282 283 ap_starting(); 284 285 /* Check TSC synchronization with the control CPU. */ 286 check_tsc_sync_target(); 287 288 /* 289 * Calibrate the delay loop after the TSC synchronization check. 290 * This allows to skip the calibration when TSC is synchronized 291 * across sockets. 292 */ 293 ap_calibrate_delay(); 294 295 speculative_store_bypass_ht_init(); 296 297 /* 298 * Lock vector_lock, set CPU online and bring the vector 299 * allocator online. Online must be set with vector_lock held 300 * to prevent a concurrent irq setup/teardown from seeing a 301 * half valid vector space. 302 */ 303 lock_vector_lock(); 304 set_cpu_online(smp_processor_id(), true); 305 lapic_online(); 306 unlock_vector_lock(); 307 x86_platform.nmi_init(); 308 309 /* enable local interrupts */ 310 local_irq_enable(); 311 312 x86_cpuinit.setup_percpu_clockev(); 313 314 wmb(); 315 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 316 } 317 ANNOTATE_NOENDBR_SYM(start_secondary); 318 319 static bool 320 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 321 { 322 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 323 324 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 325 } 326 327 static bool 328 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 329 { 330 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 331 332 return !WARN_ONCE(!topology_same_node(c, o), 333 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 334 "[node: %d != %d]. Ignoring dependency.\n", 335 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 336 } 337 338 #define link_mask(mfunc, c1, c2) \ 339 do { \ 340 cpumask_set_cpu((c1), mfunc(c2)); \ 341 cpumask_set_cpu((c2), mfunc(c1)); \ 342 } while (0) 343 344 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 345 { 346 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 347 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 348 349 if (c->topo.pkg_id == o->topo.pkg_id && 350 c->topo.die_id == o->topo.die_id && 351 c->topo.amd_node_id == o->topo.amd_node_id && 352 per_cpu_llc_id(cpu1) == per_cpu_llc_id(cpu2)) { 353 if (c->topo.core_id == o->topo.core_id) 354 return topology_sane(c, o, "smt"); 355 356 if ((c->topo.cu_id != 0xff) && 357 (o->topo.cu_id != 0xff) && 358 (c->topo.cu_id == o->topo.cu_id)) 359 return topology_sane(c, o, "smt"); 360 } 361 362 } else if (c->topo.pkg_id == o->topo.pkg_id && 363 c->topo.die_id == o->topo.die_id && 364 c->topo.core_id == o->topo.core_id) { 365 return topology_sane(c, o, "smt"); 366 } 367 368 return false; 369 } 370 371 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 372 { 373 if (c->topo.pkg_id != o->topo.pkg_id || c->topo.die_id != o->topo.die_id) 374 return false; 375 376 if (cpu_feature_enabled(X86_FEATURE_TOPOEXT) && topology_amd_nodes_per_pkg() > 1) 377 return c->topo.amd_node_id == o->topo.amd_node_id; 378 379 return true; 380 } 381 382 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 383 { 384 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 385 386 /* If the arch didn't set up l2c_id, fall back to SMT */ 387 if (per_cpu_l2c_id(cpu1) == BAD_APICID) 388 return match_smt(c, o); 389 390 /* Do not match if L2 cache id does not match: */ 391 if (per_cpu_l2c_id(cpu1) != per_cpu_l2c_id(cpu2)) 392 return false; 393 394 return topology_sane(c, o, "l2c"); 395 } 396 397 /* 398 * Unlike the other levels, we do not enforce keeping a 399 * multicore group inside a NUMA node. If this happens, we will 400 * discard the MC level of the topology later. 401 */ 402 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 403 { 404 if (c->topo.pkg_id == o->topo.pkg_id) 405 return true; 406 return false; 407 } 408 409 /* 410 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs. 411 * 412 * Any Intel CPU that has multiple nodes per package and does not 413 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology. 414 * 415 * When in SNC mode, these CPUs enumerate an LLC that is shared 416 * by multiple NUMA nodes. The LLC is shared for off-package data 417 * access but private to the NUMA node (half of the package) for 418 * on-package access. CPUID (the source of the information about 419 * the LLC) can only enumerate the cache as shared or unshared, 420 * but not this particular configuration. 421 */ 422 423 static const struct x86_cpu_id intel_cod_cpu[] = { 424 X86_MATCH_VFM(INTEL_HASWELL_X, 0), /* COD */ 425 X86_MATCH_VFM(INTEL_BROADWELL_X, 0), /* COD */ 426 X86_MATCH_VFM(INTEL_ANY, 1), /* SNC */ 427 {} 428 }; 429 430 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 431 { 432 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu); 433 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 434 bool intel_snc = id && id->driver_data; 435 436 /* Do not match if we do not have a valid APICID for cpu: */ 437 if (per_cpu_llc_id(cpu1) == BAD_APICID) 438 return false; 439 440 /* Do not match if LLC id does not match: */ 441 if (per_cpu_llc_id(cpu1) != per_cpu_llc_id(cpu2)) 442 return false; 443 444 /* 445 * Allow the SNC topology without warning. Return of false 446 * means 'c' does not share the LLC of 'o'. This will be 447 * reflected to userspace. 448 */ 449 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc) 450 return false; 451 452 return topology_sane(c, o, "llc"); 453 } 454 455 456 static inline int x86_sched_itmt_flags(void) 457 { 458 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 459 } 460 461 #ifdef CONFIG_SCHED_MC 462 static int x86_core_flags(void) 463 { 464 return cpu_core_flags() | x86_sched_itmt_flags(); 465 } 466 #endif 467 #ifdef CONFIG_SCHED_CLUSTER 468 static int x86_cluster_flags(void) 469 { 470 return cpu_cluster_flags() | x86_sched_itmt_flags(); 471 } 472 #endif 473 474 /* 475 * Set if a package/die has multiple NUMA nodes inside. 476 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel 477 * Sub-NUMA Clustering have this. 478 */ 479 static bool x86_has_numa_in_package; 480 481 static struct sched_domain_topology_level x86_topology[6]; 482 483 static void __init build_sched_topology(void) 484 { 485 int i = 0; 486 487 #ifdef CONFIG_SCHED_SMT 488 x86_topology[i++] = (struct sched_domain_topology_level){ 489 cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) 490 }; 491 #endif 492 #ifdef CONFIG_SCHED_CLUSTER 493 x86_topology[i++] = (struct sched_domain_topology_level){ 494 cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) 495 }; 496 #endif 497 #ifdef CONFIG_SCHED_MC 498 x86_topology[i++] = (struct sched_domain_topology_level){ 499 cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) 500 }; 501 #endif 502 /* 503 * When there is NUMA topology inside the package skip the PKG domain 504 * since the NUMA domains will auto-magically create the right spanning 505 * domains based on the SLIT. 506 */ 507 if (!x86_has_numa_in_package) { 508 x86_topology[i++] = (struct sched_domain_topology_level){ 509 cpu_cpu_mask, x86_sched_itmt_flags, SD_INIT_NAME(PKG) 510 }; 511 } 512 513 /* 514 * There must be one trailing NULL entry left. 515 */ 516 BUG_ON(i >= ARRAY_SIZE(x86_topology)-1); 517 518 set_sched_topology(x86_topology); 519 } 520 521 void set_cpu_sibling_map(int cpu) 522 { 523 bool has_smt = __max_threads_per_core > 1; 524 bool has_mp = has_smt || topology_num_cores_per_package() > 1; 525 struct cpuinfo_x86 *c = &cpu_data(cpu); 526 struct cpuinfo_x86 *o; 527 int i, threads; 528 529 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 530 531 if (!has_mp) { 532 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 533 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 534 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu)); 535 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 536 cpumask_set_cpu(cpu, topology_die_cpumask(cpu)); 537 c->booted_cores = 1; 538 return; 539 } 540 541 for_each_cpu(i, cpu_sibling_setup_mask) { 542 o = &cpu_data(i); 543 544 if (match_pkg(c, o) && !topology_same_node(c, o)) 545 x86_has_numa_in_package = true; 546 547 if ((i == cpu) || (has_smt && match_smt(c, o))) 548 link_mask(topology_sibling_cpumask, cpu, i); 549 550 if ((i == cpu) || (has_mp && match_llc(c, o))) 551 link_mask(cpu_llc_shared_mask, cpu, i); 552 553 if ((i == cpu) || (has_mp && match_l2c(c, o))) 554 link_mask(cpu_l2c_shared_mask, cpu, i); 555 556 if ((i == cpu) || (has_mp && match_die(c, o))) 557 link_mask(topology_die_cpumask, cpu, i); 558 } 559 560 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 561 if (threads > __max_smt_threads) 562 __max_smt_threads = threads; 563 564 for_each_cpu(i, topology_sibling_cpumask(cpu)) 565 cpu_data(i).smt_active = threads > 1; 566 567 /* 568 * This needs a separate iteration over the cpus because we rely on all 569 * topology_sibling_cpumask links to be set-up. 570 */ 571 for_each_cpu(i, cpu_sibling_setup_mask) { 572 o = &cpu_data(i); 573 574 if ((i == cpu) || (has_mp && match_pkg(c, o))) { 575 link_mask(topology_core_cpumask, cpu, i); 576 577 /* 578 * Does this new cpu bringup a new core? 579 */ 580 if (threads == 1) { 581 /* 582 * for each core in package, increment 583 * the booted_cores for this new cpu 584 */ 585 if (cpumask_first( 586 topology_sibling_cpumask(i)) == i) 587 c->booted_cores++; 588 /* 589 * increment the core count for all 590 * the other cpus in this package 591 */ 592 if (i != cpu) 593 cpu_data(i).booted_cores++; 594 } else if (i != cpu && !c->booted_cores) 595 c->booted_cores = cpu_data(i).booted_cores; 596 } 597 } 598 } 599 600 /* maps the cpu to the sched domain representing multi-core */ 601 const struct cpumask *cpu_coregroup_mask(int cpu) 602 { 603 return cpu_llc_shared_mask(cpu); 604 } 605 606 const struct cpumask *cpu_clustergroup_mask(int cpu) 607 { 608 return cpu_l2c_shared_mask(cpu); 609 } 610 EXPORT_SYMBOL_GPL(cpu_clustergroup_mask); 611 612 static void impress_friends(void) 613 { 614 int cpu; 615 unsigned long bogosum = 0; 616 /* 617 * Allow the user to impress friends. 618 */ 619 pr_debug("Before bogomips\n"); 620 for_each_online_cpu(cpu) 621 bogosum += cpu_data(cpu).loops_per_jiffy; 622 623 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 624 num_online_cpus(), 625 bogosum/(500000/HZ), 626 (bogosum/(5000/HZ))%100); 627 628 pr_debug("Before bogocount - setting activated=1\n"); 629 } 630 631 /* 632 * The Multiprocessor Specification 1.4 (1997) example code suggests 633 * that there should be a 10ms delay between the BSP asserting INIT 634 * and de-asserting INIT, when starting a remote processor. 635 * But that slows boot and resume on modern processors, which include 636 * many cores and don't require that delay. 637 * 638 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 639 * Modern processor families are quirked to remove the delay entirely. 640 */ 641 #define UDELAY_10MS_DEFAULT 10000 642 643 static unsigned int init_udelay = UINT_MAX; 644 645 static int __init cpu_init_udelay(char *str) 646 { 647 get_option(&str, &init_udelay); 648 649 return 0; 650 } 651 early_param("cpu_init_udelay", cpu_init_udelay); 652 653 static void __init smp_quirk_init_udelay(void) 654 { 655 /* if cmdline changed it from default, leave it alone */ 656 if (init_udelay != UINT_MAX) 657 return; 658 659 /* if modern processor, use no delay */ 660 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 661 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || 662 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 663 init_udelay = 0; 664 return; 665 } 666 /* else, use legacy delay */ 667 init_udelay = UDELAY_10MS_DEFAULT; 668 } 669 670 /* 671 * Wake up AP by INIT, INIT, STARTUP sequence. 672 */ 673 static void send_init_sequence(u32 phys_apicid) 674 { 675 int maxlvt = lapic_get_maxlvt(); 676 677 /* Be paranoid about clearing APIC errors. */ 678 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 679 /* Due to the Pentium erratum 3AP. */ 680 if (maxlvt > 3) 681 apic_write(APIC_ESR, 0); 682 apic_read(APIC_ESR); 683 } 684 685 /* Assert INIT on the target CPU */ 686 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, phys_apicid); 687 safe_apic_wait_icr_idle(); 688 689 udelay(init_udelay); 690 691 /* Deassert INIT on the target CPU */ 692 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 693 safe_apic_wait_icr_idle(); 694 } 695 696 /* 697 * Wake up AP by INIT, INIT, STARTUP sequence. 698 */ 699 static int wakeup_secondary_cpu_via_init(u32 phys_apicid, unsigned long start_eip) 700 { 701 unsigned long send_status = 0, accept_status = 0; 702 int num_starts, j, maxlvt; 703 704 preempt_disable(); 705 maxlvt = lapic_get_maxlvt(); 706 send_init_sequence(phys_apicid); 707 708 mb(); 709 710 /* 711 * Should we send STARTUP IPIs ? 712 * 713 * Determine this based on the APIC version. 714 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 715 */ 716 if (APIC_INTEGRATED(boot_cpu_apic_version)) 717 num_starts = 2; 718 else 719 num_starts = 0; 720 721 /* 722 * Run STARTUP IPI loop. 723 */ 724 pr_debug("#startup loops: %d\n", num_starts); 725 726 for (j = 1; j <= num_starts; j++) { 727 pr_debug("Sending STARTUP #%d\n", j); 728 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 729 apic_write(APIC_ESR, 0); 730 apic_read(APIC_ESR); 731 pr_debug("After apic_write\n"); 732 733 /* 734 * STARTUP IPI 735 */ 736 737 /* Target chip */ 738 /* Boot on the stack */ 739 /* Kick the second */ 740 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 741 phys_apicid); 742 743 /* 744 * Give the other CPU some time to accept the IPI. 745 */ 746 if (init_udelay == 0) 747 udelay(10); 748 else 749 udelay(300); 750 751 pr_debug("Startup point 1\n"); 752 753 pr_debug("Waiting for send to finish...\n"); 754 send_status = safe_apic_wait_icr_idle(); 755 756 /* 757 * Give the other CPU some time to accept the IPI. 758 */ 759 if (init_udelay == 0) 760 udelay(10); 761 else 762 udelay(200); 763 764 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 765 apic_write(APIC_ESR, 0); 766 accept_status = (apic_read(APIC_ESR) & 0xEF); 767 if (send_status || accept_status) 768 break; 769 } 770 pr_debug("After Startup\n"); 771 772 if (send_status) 773 pr_err("APIC never delivered???\n"); 774 if (accept_status) 775 pr_err("APIC delivery error (%lx)\n", accept_status); 776 777 preempt_enable(); 778 return (send_status | accept_status); 779 } 780 781 /* reduce the number of lines printed when booting a large cpu count system */ 782 static void announce_cpu(int cpu, int apicid) 783 { 784 static int width, node_width, first = 1; 785 static int current_node = NUMA_NO_NODE; 786 int node = early_cpu_to_node(cpu); 787 788 if (!width) 789 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 790 791 if (!node_width) 792 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 793 794 if (system_state < SYSTEM_RUNNING) { 795 if (first) 796 pr_info("x86: Booting SMP configuration:\n"); 797 798 if (node != current_node) { 799 if (current_node > (-1)) 800 pr_cont("\n"); 801 current_node = node; 802 803 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 804 node_width - num_digits(node), " ", node); 805 } 806 807 /* Add padding for the BSP */ 808 if (first) 809 pr_cont("%*s", width + 1, " "); 810 first = 0; 811 812 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 813 } else 814 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 815 node, cpu, apicid); 816 } 817 818 int common_cpu_up(unsigned int cpu, struct task_struct *idle) 819 { 820 int ret; 821 822 /* Just in case we booted with a single CPU. */ 823 alternatives_enable_smp(); 824 825 per_cpu(current_task, cpu) = idle; 826 cpu_init_stack_canary(cpu, idle); 827 828 /* Initialize the interrupt stack(s) */ 829 ret = irq_init_percpu_irqstack(cpu); 830 if (ret) 831 return ret; 832 833 #ifdef CONFIG_X86_32 834 /* Stack for startup_32 can be just as for start_secondary onwards */ 835 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle); 836 #endif 837 return 0; 838 } 839 840 /* 841 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 842 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 843 * Returns zero if startup was successfully sent, else error code from 844 * ->wakeup_secondary_cpu. 845 */ 846 static int do_boot_cpu(u32 apicid, int cpu, struct task_struct *idle) 847 { 848 unsigned long start_ip = real_mode_header->trampoline_start; 849 int ret; 850 851 #ifdef CONFIG_X86_64 852 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */ 853 if (apic->wakeup_secondary_cpu_64) 854 start_ip = real_mode_header->trampoline_start64; 855 #endif 856 idle->thread.sp = (unsigned long)task_pt_regs(idle); 857 initial_code = (unsigned long)start_secondary; 858 859 if (IS_ENABLED(CONFIG_X86_32)) { 860 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 861 initial_stack = idle->thread.sp; 862 } else if (!(smpboot_control & STARTUP_PARALLEL_MASK)) { 863 smpboot_control = cpu; 864 } 865 866 /* Enable the espfix hack for this CPU */ 867 init_espfix_ap(cpu); 868 869 /* So we see what's up */ 870 announce_cpu(cpu, apicid); 871 872 /* 873 * This grunge runs the startup process for 874 * the targeted processor. 875 */ 876 if (x86_platform.legacy.warm_reset) { 877 878 pr_debug("Setting warm reset code and vector.\n"); 879 880 smpboot_setup_warm_reset_vector(start_ip); 881 /* 882 * Be paranoid about clearing APIC errors. 883 */ 884 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 885 apic_write(APIC_ESR, 0); 886 apic_read(APIC_ESR); 887 } 888 } 889 890 smp_mb(); 891 892 /* 893 * Wake up a CPU in difference cases: 894 * - Use a method from the APIC driver if one defined, with wakeup 895 * straight to 64-bit mode preferred over wakeup to RM. 896 * Otherwise, 897 * - Use an INIT boot APIC message 898 */ 899 if (apic->wakeup_secondary_cpu_64) 900 ret = apic->wakeup_secondary_cpu_64(apicid, start_ip); 901 else if (apic->wakeup_secondary_cpu) 902 ret = apic->wakeup_secondary_cpu(apicid, start_ip); 903 else 904 ret = wakeup_secondary_cpu_via_init(apicid, start_ip); 905 906 /* If the wakeup mechanism failed, cleanup the warm reset vector */ 907 if (ret) 908 arch_cpuhp_cleanup_kick_cpu(cpu); 909 return ret; 910 } 911 912 int native_kick_ap(unsigned int cpu, struct task_struct *tidle) 913 { 914 u32 apicid = apic->cpu_present_to_apicid(cpu); 915 int err; 916 917 lockdep_assert_irqs_enabled(); 918 919 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 920 921 if (apicid == BAD_APICID || !apic_id_valid(apicid)) { 922 pr_err("CPU %u has invalid APIC ID %x. Aborting bringup\n", cpu, apicid); 923 return -EINVAL; 924 } 925 926 if (!test_bit(apicid, phys_cpu_present_map)) { 927 pr_err("CPU %u APIC ID %x is not present. Aborting bringup\n", cpu, apicid); 928 return -EINVAL; 929 } 930 931 /* 932 * Save current MTRR state in case it was changed since early boot 933 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 934 */ 935 mtrr_save_state(); 936 937 /* the FPU context is blank, nobody can own it */ 938 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 939 940 err = common_cpu_up(cpu, tidle); 941 if (err) 942 return err; 943 944 err = do_boot_cpu(apicid, cpu, tidle); 945 if (err) 946 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 947 948 return err; 949 } 950 951 int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *tidle) 952 { 953 return smp_ops.kick_ap_alive(cpu, tidle); 954 } 955 956 void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu) 957 { 958 /* Cleanup possible dangling ends... */ 959 if (smp_ops.kick_ap_alive == native_kick_ap && x86_platform.legacy.warm_reset) 960 smpboot_restore_warm_reset_vector(); 961 } 962 963 void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu) 964 { 965 if (smp_ops.cleanup_dead_cpu) 966 smp_ops.cleanup_dead_cpu(cpu); 967 968 if (system_state == SYSTEM_RUNNING) 969 pr_info("CPU %u is now offline\n", cpu); 970 } 971 972 void arch_cpuhp_sync_state_poll(void) 973 { 974 if (smp_ops.poll_sync_state) 975 smp_ops.poll_sync_state(); 976 } 977 978 /** 979 * arch_disable_smp_support() - Disables SMP support for x86 at boottime 980 */ 981 void __init arch_disable_smp_support(void) 982 { 983 disable_ioapic_support(); 984 } 985 986 /* 987 * Fall back to non SMP mode after errors. 988 * 989 * RED-PEN audit/test this more. I bet there is more state messed up here. 990 */ 991 static __init void disable_smp(void) 992 { 993 pr_info("SMP disabled\n"); 994 995 disable_ioapic_support(); 996 topology_reset_possible_cpus_up(); 997 998 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 999 cpumask_set_cpu(0, topology_core_cpumask(0)); 1000 cpumask_set_cpu(0, topology_die_cpumask(0)); 1001 } 1002 1003 void __init smp_prepare_cpus_common(void) 1004 { 1005 unsigned int cpu, node; 1006 1007 /* Mark all except the boot CPU as hotpluggable */ 1008 for_each_possible_cpu(cpu) { 1009 if (cpu) 1010 per_cpu(cpu_info.cpu_index, cpu) = nr_cpu_ids; 1011 } 1012 1013 for_each_possible_cpu(cpu) { 1014 node = cpu_to_node(cpu); 1015 1016 zalloc_cpumask_var_node(&per_cpu(cpu_sibling_map, cpu), GFP_KERNEL, node); 1017 zalloc_cpumask_var_node(&per_cpu(cpu_core_map, cpu), GFP_KERNEL, node); 1018 zalloc_cpumask_var_node(&per_cpu(cpu_die_map, cpu), GFP_KERNEL, node); 1019 zalloc_cpumask_var_node(&per_cpu(cpu_llc_shared_map, cpu), GFP_KERNEL, node); 1020 zalloc_cpumask_var_node(&per_cpu(cpu_l2c_shared_map, cpu), GFP_KERNEL, node); 1021 } 1022 1023 set_cpu_sibling_map(0); 1024 } 1025 1026 void __init smp_prepare_boot_cpu(void) 1027 { 1028 smp_ops.smp_prepare_boot_cpu(); 1029 } 1030 1031 #ifdef CONFIG_X86_64 1032 /* Establish whether parallel bringup can be supported. */ 1033 bool __init arch_cpuhp_init_parallel_bringup(void) 1034 { 1035 if (!x86_cpuinit.parallel_bringup) { 1036 pr_info("Parallel CPU startup disabled by the platform\n"); 1037 return false; 1038 } 1039 1040 smpboot_control = STARTUP_READ_APICID; 1041 pr_debug("Parallel CPU startup enabled: 0x%08x\n", smpboot_control); 1042 return true; 1043 } 1044 #endif 1045 1046 /* 1047 * Prepare for SMP bootup. 1048 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1049 * for common interface support. 1050 */ 1051 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1052 { 1053 smp_prepare_cpus_common(); 1054 1055 switch (apic_intr_mode) { 1056 case APIC_PIC: 1057 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1058 disable_smp(); 1059 return; 1060 case APIC_SYMMETRIC_IO_NO_ROUTING: 1061 disable_smp(); 1062 /* Setup local timer */ 1063 x86_init.timers.setup_percpu_clockev(); 1064 return; 1065 case APIC_VIRTUAL_WIRE: 1066 case APIC_SYMMETRIC_IO: 1067 break; 1068 } 1069 1070 /* Setup local timer */ 1071 x86_init.timers.setup_percpu_clockev(); 1072 1073 pr_info("CPU0: "); 1074 print_cpu_info(&cpu_data(0)); 1075 1076 uv_system_init(); 1077 1078 smp_quirk_init_udelay(); 1079 1080 speculative_store_bypass_ht_init(); 1081 1082 snp_set_wakeup_secondary_cpu(); 1083 } 1084 1085 void arch_thaw_secondary_cpus_begin(void) 1086 { 1087 set_cache_aps_delayed_init(true); 1088 } 1089 1090 void arch_thaw_secondary_cpus_end(void) 1091 { 1092 cache_aps_init(); 1093 } 1094 1095 /* 1096 * Early setup to make printk work. 1097 */ 1098 void __init native_smp_prepare_boot_cpu(void) 1099 { 1100 int me = smp_processor_id(); 1101 1102 /* SMP handles this from setup_per_cpu_areas() */ 1103 if (!IS_ENABLED(CONFIG_SMP)) 1104 switch_gdt_and_percpu_base(me); 1105 1106 native_pv_lock_init(); 1107 } 1108 1109 void __init native_smp_cpus_done(unsigned int max_cpus) 1110 { 1111 pr_debug("Boot done\n"); 1112 1113 build_sched_topology(); 1114 nmi_selftest(); 1115 impress_friends(); 1116 cache_aps_init(); 1117 } 1118 1119 /* correctly size the local cpu masks */ 1120 void __init setup_cpu_local_masks(void) 1121 { 1122 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 1123 } 1124 1125 #ifdef CONFIG_HOTPLUG_CPU 1126 1127 /* Recompute SMT state for all CPUs on offline */ 1128 static void recompute_smt_state(void) 1129 { 1130 int max_threads, cpu; 1131 1132 max_threads = 0; 1133 for_each_online_cpu (cpu) { 1134 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1135 1136 if (threads > max_threads) 1137 max_threads = threads; 1138 } 1139 __max_smt_threads = max_threads; 1140 } 1141 1142 static void remove_siblinginfo(int cpu) 1143 { 1144 int sibling; 1145 struct cpuinfo_x86 *c = &cpu_data(cpu); 1146 1147 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1148 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1149 /*/ 1150 * last thread sibling in this cpu core going down 1151 */ 1152 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1153 cpu_data(sibling).booted_cores--; 1154 } 1155 1156 for_each_cpu(sibling, topology_die_cpumask(cpu)) 1157 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling)); 1158 1159 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) { 1160 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1161 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1) 1162 cpu_data(sibling).smt_active = false; 1163 } 1164 1165 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1166 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1167 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu)) 1168 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling)); 1169 cpumask_clear(cpu_llc_shared_mask(cpu)); 1170 cpumask_clear(cpu_l2c_shared_mask(cpu)); 1171 cpumask_clear(topology_sibling_cpumask(cpu)); 1172 cpumask_clear(topology_core_cpumask(cpu)); 1173 cpumask_clear(topology_die_cpumask(cpu)); 1174 c->topo.core_id = 0; 1175 c->booted_cores = 0; 1176 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1177 recompute_smt_state(); 1178 } 1179 1180 static void remove_cpu_from_maps(int cpu) 1181 { 1182 set_cpu_online(cpu, false); 1183 numa_remove_cpu(cpu); 1184 } 1185 1186 void cpu_disable_common(void) 1187 { 1188 int cpu = smp_processor_id(); 1189 1190 remove_siblinginfo(cpu); 1191 1192 /* It's now safe to remove this processor from the online map */ 1193 lock_vector_lock(); 1194 remove_cpu_from_maps(cpu); 1195 unlock_vector_lock(); 1196 fixup_irqs(); 1197 lapic_offline(); 1198 } 1199 1200 int native_cpu_disable(void) 1201 { 1202 int ret; 1203 1204 ret = lapic_can_unplug_cpu(); 1205 if (ret) 1206 return ret; 1207 1208 cpu_disable_common(); 1209 1210 /* 1211 * Disable the local APIC. Otherwise IPI broadcasts will reach 1212 * it. It still responds normally to INIT, NMI, SMI, and SIPI 1213 * messages. 1214 * 1215 * Disabling the APIC must happen after cpu_disable_common() 1216 * which invokes fixup_irqs(). 1217 * 1218 * Disabling the APIC preserves already set bits in IRR, but 1219 * an interrupt arriving after disabling the local APIC does not 1220 * set the corresponding IRR bit. 1221 * 1222 * fixup_irqs() scans IRR for set bits so it can raise a not 1223 * yet handled interrupt on the new destination CPU via an IPI 1224 * but obviously it can't do so for IRR bits which are not set. 1225 * IOW, interrupts arriving after disabling the local APIC will 1226 * be lost. 1227 */ 1228 apic_soft_disable(); 1229 1230 return 0; 1231 } 1232 1233 void play_dead_common(void) 1234 { 1235 idle_task_exit(); 1236 1237 cpuhp_ap_report_dead(); 1238 1239 local_irq_disable(); 1240 } 1241 1242 /* 1243 * We need to flush the caches before going to sleep, lest we have 1244 * dirty data in our caches when we come back up. 1245 */ 1246 void __noreturn mwait_play_dead(unsigned int eax_hint) 1247 { 1248 struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead); 1249 1250 /* Set up state for the kexec() hack below */ 1251 md->status = CPUDEAD_MWAIT_WAIT; 1252 md->control = CPUDEAD_MWAIT_WAIT; 1253 1254 wbinvd(); 1255 1256 while (1) { 1257 /* 1258 * The CLFLUSH is a workaround for erratum AAI65 for 1259 * the Xeon 7400 series. It's not clear it is actually 1260 * needed, but it should be harmless in either case. 1261 * The WBINVD is insufficient due to the spurious-wakeup 1262 * case where we return around the loop. 1263 */ 1264 mb(); 1265 clflush(md); 1266 mb(); 1267 __monitor(md, 0, 0); 1268 mb(); 1269 __mwait(eax_hint, 0); 1270 1271 if (READ_ONCE(md->control) == CPUDEAD_MWAIT_KEXEC_HLT) { 1272 /* 1273 * Kexec is about to happen. Don't go back into mwait() as 1274 * the kexec kernel might overwrite text and data including 1275 * page tables and stack. So mwait() would resume when the 1276 * monitor cache line is written to and then the CPU goes 1277 * south due to overwritten text, page tables and stack. 1278 * 1279 * Note: This does _NOT_ protect against a stray MCE, NMI, 1280 * SMI. They will resume execution at the instruction 1281 * following the HLT instruction and run into the problem 1282 * which this is trying to prevent. 1283 */ 1284 WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT); 1285 while(1) 1286 native_halt(); 1287 } 1288 } 1289 } 1290 1291 /* 1292 * Kick all "offline" CPUs out of mwait on kexec(). See comment in 1293 * mwait_play_dead(). 1294 */ 1295 void smp_kick_mwait_play_dead(void) 1296 { 1297 u32 newstate = CPUDEAD_MWAIT_KEXEC_HLT; 1298 struct mwait_cpu_dead *md; 1299 unsigned int cpu, i; 1300 1301 for_each_cpu_andnot(cpu, cpu_present_mask, cpu_online_mask) { 1302 md = per_cpu_ptr(&mwait_cpu_dead, cpu); 1303 1304 /* Does it sit in mwait_play_dead() ? */ 1305 if (READ_ONCE(md->status) != CPUDEAD_MWAIT_WAIT) 1306 continue; 1307 1308 /* Wait up to 5ms */ 1309 for (i = 0; READ_ONCE(md->status) != newstate && i < 1000; i++) { 1310 /* Bring it out of mwait */ 1311 WRITE_ONCE(md->control, newstate); 1312 udelay(5); 1313 } 1314 1315 if (READ_ONCE(md->status) != newstate) 1316 pr_err_once("CPU%u is stuck in mwait_play_dead()\n", cpu); 1317 } 1318 } 1319 1320 void __noreturn hlt_play_dead(void) 1321 { 1322 if (__this_cpu_read(cpu_info.x86) >= 4) 1323 wbinvd(); 1324 1325 while (1) 1326 native_halt(); 1327 } 1328 1329 /* 1330 * native_play_dead() is essentially a __noreturn function, but it can't 1331 * be marked as such as the compiler may complain about it. 1332 */ 1333 void native_play_dead(void) 1334 { 1335 if (cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS)) 1336 __update_spec_ctrl(0); 1337 1338 play_dead_common(); 1339 tboot_shutdown(TB_SHUTDOWN_WFS); 1340 1341 /* Below returns only on error. */ 1342 cpuidle_play_dead(); 1343 hlt_play_dead(); 1344 } 1345 1346 #else /* ... !CONFIG_HOTPLUG_CPU */ 1347 int native_cpu_disable(void) 1348 { 1349 return -ENOSYS; 1350 } 1351 1352 void native_play_dead(void) 1353 { 1354 BUG(); 1355 } 1356 1357 #endif 1358