1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/module.h> 45 #include <linux/sched.h> 46 #include <linux/percpu.h> 47 #include <linux/bootmem.h> 48 #include <linux/err.h> 49 #include <linux/nmi.h> 50 #include <linux/tboot.h> 51 #include <linux/stackprotector.h> 52 #include <linux/gfp.h> 53 54 #include <asm/acpi.h> 55 #include <asm/desc.h> 56 #include <asm/nmi.h> 57 #include <asm/irq.h> 58 #include <asm/idle.h> 59 #include <asm/trampoline.h> 60 #include <asm/cpu.h> 61 #include <asm/numa.h> 62 #include <asm/pgtable.h> 63 #include <asm/tlbflush.h> 64 #include <asm/mtrr.h> 65 #include <asm/mwait.h> 66 #include <asm/apic.h> 67 #include <asm/io_apic.h> 68 #include <asm/setup.h> 69 #include <asm/uv/uv.h> 70 #include <linux/mc146818rtc.h> 71 72 #include <asm/smpboot_hooks.h> 73 #include <asm/i8259.h> 74 75 /* State of each CPU */ 76 DEFINE_PER_CPU(int, cpu_state) = { 0 }; 77 78 /* Store all idle threads, this can be reused instead of creating 79 * a new thread. Also avoids complicated thread destroy functionality 80 * for idle threads. 81 */ 82 #ifdef CONFIG_HOTPLUG_CPU 83 /* 84 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is 85 * removed after init for !CONFIG_HOTPLUG_CPU. 86 */ 87 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); 88 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) 89 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) 90 91 /* 92 * We need this for trampoline_base protection from concurrent accesses when 93 * off- and onlining cores wildly. 94 */ 95 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex); 96 97 void cpu_hotplug_driver_lock(void) 98 { 99 mutex_lock(&x86_cpu_hotplug_driver_mutex); 100 } 101 102 void cpu_hotplug_driver_unlock(void) 103 { 104 mutex_unlock(&x86_cpu_hotplug_driver_mutex); 105 } 106 107 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; } 108 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; } 109 #else 110 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; 111 #define get_idle_for_cpu(x) (idle_thread_array[(x)]) 112 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) 113 #endif 114 115 /* Number of siblings per CPU package */ 116 int smp_num_siblings = 1; 117 EXPORT_SYMBOL(smp_num_siblings); 118 119 /* Last level cache ID of each logical CPU */ 120 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; 121 122 /* representing HT siblings of each logical CPU */ 123 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); 124 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 125 126 /* representing HT and core siblings of each logical CPU */ 127 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); 128 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 129 130 DEFINE_PER_CPU(cpumask_var_t, cpu_llc_shared_map); 131 132 /* Per CPU bogomips and other parameters */ 133 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 134 EXPORT_PER_CPU_SYMBOL(cpu_info); 135 136 atomic_t init_deasserted; 137 138 /* 139 * Report back to the Boot Processor. 140 * Running on AP. 141 */ 142 static void __cpuinit smp_callin(void) 143 { 144 int cpuid, phys_id; 145 unsigned long timeout; 146 147 /* 148 * If waken up by an INIT in an 82489DX configuration 149 * we may get here before an INIT-deassert IPI reaches 150 * our local APIC. We have to wait for the IPI or we'll 151 * lock up on an APIC access. 152 */ 153 if (apic->wait_for_init_deassert) 154 apic->wait_for_init_deassert(&init_deasserted); 155 156 /* 157 * (This works even if the APIC is not enabled.) 158 */ 159 phys_id = read_apic_id(); 160 cpuid = smp_processor_id(); 161 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { 162 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, 163 phys_id, cpuid); 164 } 165 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); 166 167 /* 168 * STARTUP IPIs are fragile beasts as they might sometimes 169 * trigger some glue motherboard logic. Complete APIC bus 170 * silence for 1 second, this overestimates the time the 171 * boot CPU is spending to send the up to 2 STARTUP IPIs 172 * by a factor of two. This should be enough. 173 */ 174 175 /* 176 * Waiting 2s total for startup (udelay is not yet working) 177 */ 178 timeout = jiffies + 2*HZ; 179 while (time_before(jiffies, timeout)) { 180 /* 181 * Has the boot CPU finished it's STARTUP sequence? 182 */ 183 if (cpumask_test_cpu(cpuid, cpu_callout_mask)) 184 break; 185 cpu_relax(); 186 } 187 188 if (!time_before(jiffies, timeout)) { 189 panic("%s: CPU%d started up but did not get a callout!\n", 190 __func__, cpuid); 191 } 192 193 /* 194 * the boot CPU has finished the init stage and is spinning 195 * on callin_map until we finish. We are free to set up this 196 * CPU, first the APIC. (this is probably redundant on most 197 * boards) 198 */ 199 200 pr_debug("CALLIN, before setup_local_APIC().\n"); 201 if (apic->smp_callin_clear_local_apic) 202 apic->smp_callin_clear_local_apic(); 203 setup_local_APIC(); 204 end_local_APIC_setup(); 205 206 /* 207 * Need to setup vector mappings before we enable interrupts. 208 */ 209 setup_vector_irq(smp_processor_id()); 210 211 /* 212 * Save our processor parameters. Note: this information 213 * is needed for clock calibration. 214 */ 215 smp_store_cpu_info(cpuid); 216 217 /* 218 * Get our bogomips. 219 * Update loops_per_jiffy in cpu_data. Previous call to 220 * smp_store_cpu_info() stored a value that is close but not as 221 * accurate as the value just calculated. 222 */ 223 calibrate_delay(); 224 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 225 pr_debug("Stack at about %p\n", &cpuid); 226 227 /* 228 * This must be done before setting cpu_online_mask 229 * or calling notify_cpu_starting. 230 */ 231 set_cpu_sibling_map(raw_smp_processor_id()); 232 wmb(); 233 234 notify_cpu_starting(cpuid); 235 236 /* 237 * Allow the master to continue. 238 */ 239 cpumask_set_cpu(cpuid, cpu_callin_mask); 240 } 241 242 /* 243 * Activate a secondary processor. 244 */ 245 notrace static void __cpuinit start_secondary(void *unused) 246 { 247 /* 248 * Don't put *anything* before cpu_init(), SMP booting is too 249 * fragile that we want to limit the things done here to the 250 * most necessary things. 251 */ 252 cpu_init(); 253 x86_cpuinit.early_percpu_clock_init(); 254 preempt_disable(); 255 smp_callin(); 256 257 #ifdef CONFIG_X86_32 258 /* switch away from the initial page table */ 259 load_cr3(swapper_pg_dir); 260 __flush_tlb_all(); 261 #endif 262 263 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 264 barrier(); 265 /* 266 * Check TSC synchronization with the BP: 267 */ 268 check_tsc_sync_target(); 269 270 /* 271 * We need to hold call_lock, so there is no inconsistency 272 * between the time smp_call_function() determines number of 273 * IPI recipients, and the time when the determination is made 274 * for which cpus receive the IPI. Holding this 275 * lock helps us to not include this cpu in a currently in progress 276 * smp_call_function(). 277 * 278 * We need to hold vector_lock so there the set of online cpus 279 * does not change while we are assigning vectors to cpus. Holding 280 * this lock ensures we don't half assign or remove an irq from a cpu. 281 */ 282 ipi_call_lock(); 283 lock_vector_lock(); 284 set_cpu_online(smp_processor_id(), true); 285 unlock_vector_lock(); 286 ipi_call_unlock(); 287 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; 288 x86_platform.nmi_init(); 289 290 /* enable local interrupts */ 291 local_irq_enable(); 292 293 /* to prevent fake stack check failure in clock setup */ 294 boot_init_stack_canary(); 295 296 x86_cpuinit.setup_percpu_clockev(); 297 298 wmb(); 299 cpu_idle(); 300 } 301 302 /* 303 * The bootstrap kernel entry code has set these up. Save them for 304 * a given CPU 305 */ 306 307 void __cpuinit smp_store_cpu_info(int id) 308 { 309 struct cpuinfo_x86 *c = &cpu_data(id); 310 311 *c = boot_cpu_data; 312 c->cpu_index = id; 313 if (id != 0) 314 identify_secondary_cpu(c); 315 } 316 317 static void __cpuinit link_thread_siblings(int cpu1, int cpu2) 318 { 319 cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2)); 320 cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1)); 321 cpumask_set_cpu(cpu1, cpu_core_mask(cpu2)); 322 cpumask_set_cpu(cpu2, cpu_core_mask(cpu1)); 323 cpumask_set_cpu(cpu1, cpu_llc_shared_mask(cpu2)); 324 cpumask_set_cpu(cpu2, cpu_llc_shared_mask(cpu1)); 325 } 326 327 328 void __cpuinit set_cpu_sibling_map(int cpu) 329 { 330 int i; 331 struct cpuinfo_x86 *c = &cpu_data(cpu); 332 333 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 334 335 if (smp_num_siblings > 1) { 336 for_each_cpu(i, cpu_sibling_setup_mask) { 337 struct cpuinfo_x86 *o = &cpu_data(i); 338 339 if (cpu_has(c, X86_FEATURE_TOPOEXT)) { 340 if (c->phys_proc_id == o->phys_proc_id && 341 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i) && 342 c->compute_unit_id == o->compute_unit_id) 343 link_thread_siblings(cpu, i); 344 } else if (c->phys_proc_id == o->phys_proc_id && 345 c->cpu_core_id == o->cpu_core_id) { 346 link_thread_siblings(cpu, i); 347 } 348 } 349 } else { 350 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); 351 } 352 353 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 354 355 if (__this_cpu_read(cpu_info.x86_max_cores) == 1) { 356 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); 357 c->booted_cores = 1; 358 return; 359 } 360 361 for_each_cpu(i, cpu_sibling_setup_mask) { 362 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && 363 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { 364 cpumask_set_cpu(i, cpu_llc_shared_mask(cpu)); 365 cpumask_set_cpu(cpu, cpu_llc_shared_mask(i)); 366 } 367 if (c->phys_proc_id == cpu_data(i).phys_proc_id) { 368 cpumask_set_cpu(i, cpu_core_mask(cpu)); 369 cpumask_set_cpu(cpu, cpu_core_mask(i)); 370 /* 371 * Does this new cpu bringup a new core? 372 */ 373 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { 374 /* 375 * for each core in package, increment 376 * the booted_cores for this new cpu 377 */ 378 if (cpumask_first(cpu_sibling_mask(i)) == i) 379 c->booted_cores++; 380 /* 381 * increment the core count for all 382 * the other cpus in this package 383 */ 384 if (i != cpu) 385 cpu_data(i).booted_cores++; 386 } else if (i != cpu && !c->booted_cores) 387 c->booted_cores = cpu_data(i).booted_cores; 388 } 389 } 390 } 391 392 /* maps the cpu to the sched domain representing multi-core */ 393 const struct cpumask *cpu_coregroup_mask(int cpu) 394 { 395 struct cpuinfo_x86 *c = &cpu_data(cpu); 396 /* 397 * For perf, we return last level cache shared map. 398 * And for power savings, we return cpu_core_map 399 */ 400 if ((sched_mc_power_savings || sched_smt_power_savings) && 401 !(cpu_has(c, X86_FEATURE_AMD_DCM))) 402 return cpu_core_mask(cpu); 403 else 404 return cpu_llc_shared_mask(cpu); 405 } 406 407 static void impress_friends(void) 408 { 409 int cpu; 410 unsigned long bogosum = 0; 411 /* 412 * Allow the user to impress friends. 413 */ 414 pr_debug("Before bogomips.\n"); 415 for_each_possible_cpu(cpu) 416 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 417 bogosum += cpu_data(cpu).loops_per_jiffy; 418 printk(KERN_INFO 419 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", 420 num_online_cpus(), 421 bogosum/(500000/HZ), 422 (bogosum/(5000/HZ))%100); 423 424 pr_debug("Before bogocount - setting activated=1.\n"); 425 } 426 427 void __inquire_remote_apic(int apicid) 428 { 429 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 430 const char * const names[] = { "ID", "VERSION", "SPIV" }; 431 int timeout; 432 u32 status; 433 434 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); 435 436 for (i = 0; i < ARRAY_SIZE(regs); i++) { 437 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); 438 439 /* 440 * Wait for idle. 441 */ 442 status = safe_apic_wait_icr_idle(); 443 if (status) 444 printk(KERN_CONT 445 "a previous APIC delivery may have failed\n"); 446 447 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 448 449 timeout = 0; 450 do { 451 udelay(100); 452 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 453 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 454 455 switch (status) { 456 case APIC_ICR_RR_VALID: 457 status = apic_read(APIC_RRR); 458 printk(KERN_CONT "%08x\n", status); 459 break; 460 default: 461 printk(KERN_CONT "failed\n"); 462 } 463 } 464 } 465 466 /* 467 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 468 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 469 * won't ... remember to clear down the APIC, etc later. 470 */ 471 int __cpuinit 472 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) 473 { 474 unsigned long send_status, accept_status = 0; 475 int maxlvt; 476 477 /* Target chip */ 478 /* Boot on the stack */ 479 /* Kick the second */ 480 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); 481 482 pr_debug("Waiting for send to finish...\n"); 483 send_status = safe_apic_wait_icr_idle(); 484 485 /* 486 * Give the other CPU some time to accept the IPI. 487 */ 488 udelay(200); 489 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 490 maxlvt = lapic_get_maxlvt(); 491 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 492 apic_write(APIC_ESR, 0); 493 accept_status = (apic_read(APIC_ESR) & 0xEF); 494 } 495 pr_debug("NMI sent.\n"); 496 497 if (send_status) 498 printk(KERN_ERR "APIC never delivered???\n"); 499 if (accept_status) 500 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 501 502 return (send_status | accept_status); 503 } 504 505 static int __cpuinit 506 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 507 { 508 unsigned long send_status, accept_status = 0; 509 int maxlvt, num_starts, j; 510 511 maxlvt = lapic_get_maxlvt(); 512 513 /* 514 * Be paranoid about clearing APIC errors. 515 */ 516 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 517 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 518 apic_write(APIC_ESR, 0); 519 apic_read(APIC_ESR); 520 } 521 522 pr_debug("Asserting INIT.\n"); 523 524 /* 525 * Turn INIT on target chip 526 */ 527 /* 528 * Send IPI 529 */ 530 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 531 phys_apicid); 532 533 pr_debug("Waiting for send to finish...\n"); 534 send_status = safe_apic_wait_icr_idle(); 535 536 mdelay(10); 537 538 pr_debug("Deasserting INIT.\n"); 539 540 /* Target chip */ 541 /* Send IPI */ 542 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 543 544 pr_debug("Waiting for send to finish...\n"); 545 send_status = safe_apic_wait_icr_idle(); 546 547 mb(); 548 atomic_set(&init_deasserted, 1); 549 550 /* 551 * Should we send STARTUP IPIs ? 552 * 553 * Determine this based on the APIC version. 554 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 555 */ 556 if (APIC_INTEGRATED(apic_version[phys_apicid])) 557 num_starts = 2; 558 else 559 num_starts = 0; 560 561 /* 562 * Paravirt / VMI wants a startup IPI hook here to set up the 563 * target processor state. 564 */ 565 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, 566 stack_start); 567 568 /* 569 * Run STARTUP IPI loop. 570 */ 571 pr_debug("#startup loops: %d.\n", num_starts); 572 573 for (j = 1; j <= num_starts; j++) { 574 pr_debug("Sending STARTUP #%d.\n", j); 575 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 576 apic_write(APIC_ESR, 0); 577 apic_read(APIC_ESR); 578 pr_debug("After apic_write.\n"); 579 580 /* 581 * STARTUP IPI 582 */ 583 584 /* Target chip */ 585 /* Boot on the stack */ 586 /* Kick the second */ 587 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 588 phys_apicid); 589 590 /* 591 * Give the other CPU some time to accept the IPI. 592 */ 593 udelay(300); 594 595 pr_debug("Startup point 1.\n"); 596 597 pr_debug("Waiting for send to finish...\n"); 598 send_status = safe_apic_wait_icr_idle(); 599 600 /* 601 * Give the other CPU some time to accept the IPI. 602 */ 603 udelay(200); 604 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 605 apic_write(APIC_ESR, 0); 606 accept_status = (apic_read(APIC_ESR) & 0xEF); 607 if (send_status || accept_status) 608 break; 609 } 610 pr_debug("After Startup.\n"); 611 612 if (send_status) 613 printk(KERN_ERR "APIC never delivered???\n"); 614 if (accept_status) 615 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 616 617 return (send_status | accept_status); 618 } 619 620 struct create_idle { 621 struct work_struct work; 622 struct task_struct *idle; 623 struct completion done; 624 int cpu; 625 }; 626 627 static void __cpuinit do_fork_idle(struct work_struct *work) 628 { 629 struct create_idle *c_idle = 630 container_of(work, struct create_idle, work); 631 632 c_idle->idle = fork_idle(c_idle->cpu); 633 complete(&c_idle->done); 634 } 635 636 /* reduce the number of lines printed when booting a large cpu count system */ 637 static void __cpuinit announce_cpu(int cpu, int apicid) 638 { 639 static int current_node = -1; 640 int node = early_cpu_to_node(cpu); 641 642 if (system_state == SYSTEM_BOOTING) { 643 if (node != current_node) { 644 if (current_node > (-1)) 645 pr_cont(" Ok.\n"); 646 current_node = node; 647 pr_info("Booting Node %3d, Processors ", node); 648 } 649 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : ""); 650 return; 651 } else 652 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 653 node, cpu, apicid); 654 } 655 656 /* 657 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 658 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 659 * Returns zero if CPU booted OK, else error code from 660 * ->wakeup_secondary_cpu. 661 */ 662 static int __cpuinit do_boot_cpu(int apicid, int cpu) 663 { 664 unsigned long boot_error = 0; 665 unsigned long start_ip; 666 int timeout; 667 struct create_idle c_idle = { 668 .cpu = cpu, 669 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), 670 }; 671 672 INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle); 673 674 alternatives_smp_switch(1); 675 676 c_idle.idle = get_idle_for_cpu(cpu); 677 678 /* 679 * We can't use kernel_thread since we must avoid to 680 * reschedule the child. 681 */ 682 if (c_idle.idle) { 683 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) 684 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); 685 init_idle(c_idle.idle, cpu); 686 goto do_rest; 687 } 688 689 schedule_work(&c_idle.work); 690 wait_for_completion(&c_idle.done); 691 692 if (IS_ERR(c_idle.idle)) { 693 printk("failed fork for CPU %d\n", cpu); 694 destroy_work_on_stack(&c_idle.work); 695 return PTR_ERR(c_idle.idle); 696 } 697 698 set_idle_for_cpu(cpu, c_idle.idle); 699 do_rest: 700 per_cpu(current_task, cpu) = c_idle.idle; 701 #ifdef CONFIG_X86_32 702 /* Stack for startup_32 can be just as for start_secondary onwards */ 703 irq_ctx_init(cpu); 704 #else 705 clear_tsk_thread_flag(c_idle.idle, TIF_FORK); 706 initial_gs = per_cpu_offset(cpu); 707 per_cpu(kernel_stack, cpu) = 708 (unsigned long)task_stack_page(c_idle.idle) - 709 KERNEL_STACK_OFFSET + THREAD_SIZE; 710 #endif 711 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 712 initial_code = (unsigned long)start_secondary; 713 stack_start = c_idle.idle->thread.sp; 714 715 /* start_ip had better be page-aligned! */ 716 start_ip = trampoline_address(); 717 718 /* So we see what's up */ 719 announce_cpu(cpu, apicid); 720 721 /* 722 * This grunge runs the startup process for 723 * the targeted processor. 724 */ 725 726 atomic_set(&init_deasserted, 0); 727 728 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 729 730 pr_debug("Setting warm reset code and vector.\n"); 731 732 smpboot_setup_warm_reset_vector(start_ip); 733 /* 734 * Be paranoid about clearing APIC errors. 735 */ 736 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 737 apic_write(APIC_ESR, 0); 738 apic_read(APIC_ESR); 739 } 740 } 741 742 /* 743 * Kick the secondary CPU. Use the method in the APIC driver 744 * if it's defined - or use an INIT boot APIC message otherwise: 745 */ 746 if (apic->wakeup_secondary_cpu) 747 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 748 else 749 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 750 751 if (!boot_error) { 752 /* 753 * allow APs to start initializing. 754 */ 755 pr_debug("Before Callout %d.\n", cpu); 756 cpumask_set_cpu(cpu, cpu_callout_mask); 757 pr_debug("After Callout %d.\n", cpu); 758 759 /* 760 * Wait 5s total for a response 761 */ 762 for (timeout = 0; timeout < 50000; timeout++) { 763 if (cpumask_test_cpu(cpu, cpu_callin_mask)) 764 break; /* It has booted */ 765 udelay(100); 766 /* 767 * Allow other tasks to run while we wait for the 768 * AP to come online. This also gives a chance 769 * for the MTRR work(triggered by the AP coming online) 770 * to be completed in the stop machine context. 771 */ 772 schedule(); 773 } 774 775 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 776 print_cpu_msr(&cpu_data(cpu)); 777 pr_debug("CPU%d: has booted.\n", cpu); 778 } else { 779 boot_error = 1; 780 if (*(volatile u32 *)TRAMPOLINE_SYM(trampoline_status) 781 == 0xA5A5A5A5) 782 /* trampoline started but...? */ 783 pr_err("CPU%d: Stuck ??\n", cpu); 784 else 785 /* trampoline code not run */ 786 pr_err("CPU%d: Not responding.\n", cpu); 787 if (apic->inquire_remote_apic) 788 apic->inquire_remote_apic(apicid); 789 } 790 } 791 792 if (boot_error) { 793 /* Try to put things back the way they were before ... */ 794 numa_remove_cpu(cpu); /* was set by numa_add_cpu */ 795 796 /* was set by do_boot_cpu() */ 797 cpumask_clear_cpu(cpu, cpu_callout_mask); 798 799 /* was set by cpu_init() */ 800 cpumask_clear_cpu(cpu, cpu_initialized_mask); 801 802 set_cpu_present(cpu, false); 803 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; 804 } 805 806 /* mark "stuck" area as not stuck */ 807 *(volatile u32 *)TRAMPOLINE_SYM(trampoline_status) = 0; 808 809 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 810 /* 811 * Cleanup possible dangling ends... 812 */ 813 smpboot_restore_warm_reset_vector(); 814 } 815 816 destroy_work_on_stack(&c_idle.work); 817 return boot_error; 818 } 819 820 int __cpuinit native_cpu_up(unsigned int cpu) 821 { 822 int apicid = apic->cpu_present_to_apicid(cpu); 823 unsigned long flags; 824 int err; 825 826 WARN_ON(irqs_disabled()); 827 828 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 829 830 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || 831 !physid_isset(apicid, phys_cpu_present_map) || 832 !apic->apic_id_valid(apicid)) { 833 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); 834 return -EINVAL; 835 } 836 837 /* 838 * Already booted CPU? 839 */ 840 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 841 pr_debug("do_boot_cpu %d Already started\n", cpu); 842 return -ENOSYS; 843 } 844 845 /* 846 * Save current MTRR state in case it was changed since early boot 847 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 848 */ 849 mtrr_save_state(); 850 851 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; 852 853 err = do_boot_cpu(apicid, cpu); 854 if (err) { 855 pr_debug("do_boot_cpu failed %d\n", err); 856 return -EIO; 857 } 858 859 /* 860 * Check TSC synchronization with the AP (keep irqs disabled 861 * while doing so): 862 */ 863 local_irq_save(flags); 864 check_tsc_sync_source(cpu); 865 local_irq_restore(flags); 866 867 while (!cpu_online(cpu)) { 868 cpu_relax(); 869 touch_nmi_watchdog(); 870 } 871 872 return 0; 873 } 874 875 /** 876 * arch_disable_smp_support() - disables SMP support for x86 at runtime 877 */ 878 void arch_disable_smp_support(void) 879 { 880 disable_ioapic_support(); 881 } 882 883 /* 884 * Fall back to non SMP mode after errors. 885 * 886 * RED-PEN audit/test this more. I bet there is more state messed up here. 887 */ 888 static __init void disable_smp(void) 889 { 890 init_cpu_present(cpumask_of(0)); 891 init_cpu_possible(cpumask_of(0)); 892 smpboot_clear_io_apic_irqs(); 893 894 if (smp_found_config) 895 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 896 else 897 physid_set_mask_of_physid(0, &phys_cpu_present_map); 898 cpumask_set_cpu(0, cpu_sibling_mask(0)); 899 cpumask_set_cpu(0, cpu_core_mask(0)); 900 } 901 902 /* 903 * Various sanity checks. 904 */ 905 static int __init smp_sanity_check(unsigned max_cpus) 906 { 907 preempt_disable(); 908 909 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 910 if (def_to_bigsmp && nr_cpu_ids > 8) { 911 unsigned int cpu; 912 unsigned nr; 913 914 printk(KERN_WARNING 915 "More than 8 CPUs detected - skipping them.\n" 916 "Use CONFIG_X86_BIGSMP.\n"); 917 918 nr = 0; 919 for_each_present_cpu(cpu) { 920 if (nr >= 8) 921 set_cpu_present(cpu, false); 922 nr++; 923 } 924 925 nr = 0; 926 for_each_possible_cpu(cpu) { 927 if (nr >= 8) 928 set_cpu_possible(cpu, false); 929 nr++; 930 } 931 932 nr_cpu_ids = 8; 933 } 934 #endif 935 936 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 937 printk(KERN_WARNING 938 "weird, boot CPU (#%d) not listed by the BIOS.\n", 939 hard_smp_processor_id()); 940 941 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 942 } 943 944 /* 945 * If we couldn't find an SMP configuration at boot time, 946 * get out of here now! 947 */ 948 if (!smp_found_config && !acpi_lapic) { 949 preempt_enable(); 950 printk(KERN_NOTICE "SMP motherboard not detected.\n"); 951 disable_smp(); 952 if (APIC_init_uniprocessor()) 953 printk(KERN_NOTICE "Local APIC not detected." 954 " Using dummy APIC emulation.\n"); 955 return -1; 956 } 957 958 /* 959 * Should not be necessary because the MP table should list the boot 960 * CPU too, but we do it for the sake of robustness anyway. 961 */ 962 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 963 printk(KERN_NOTICE 964 "weird, boot CPU (#%d) not listed by the BIOS.\n", 965 boot_cpu_physical_apicid); 966 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 967 } 968 preempt_enable(); 969 970 /* 971 * If we couldn't find a local APIC, then get out of here now! 972 */ 973 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 974 !cpu_has_apic) { 975 if (!disable_apic) { 976 pr_err("BIOS bug, local APIC #%d not detected!...\n", 977 boot_cpu_physical_apicid); 978 pr_err("... forcing use of dummy APIC emulation." 979 "(tell your hw vendor)\n"); 980 } 981 smpboot_clear_io_apic(); 982 disable_ioapic_support(); 983 return -1; 984 } 985 986 verify_local_APIC(); 987 988 /* 989 * If SMP should be disabled, then really disable it! 990 */ 991 if (!max_cpus) { 992 printk(KERN_INFO "SMP mode deactivated.\n"); 993 smpboot_clear_io_apic(); 994 995 connect_bsp_APIC(); 996 setup_local_APIC(); 997 bsp_end_local_APIC_setup(); 998 return -1; 999 } 1000 1001 return 0; 1002 } 1003 1004 static void __init smp_cpu_index_default(void) 1005 { 1006 int i; 1007 struct cpuinfo_x86 *c; 1008 1009 for_each_possible_cpu(i) { 1010 c = &cpu_data(i); 1011 /* mark all to hotplug */ 1012 c->cpu_index = nr_cpu_ids; 1013 } 1014 } 1015 1016 /* 1017 * Prepare for SMP bootup. The MP table or ACPI has been read 1018 * earlier. Just do some sanity checking here and enable APIC mode. 1019 */ 1020 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1021 { 1022 unsigned int i; 1023 1024 preempt_disable(); 1025 smp_cpu_index_default(); 1026 1027 /* 1028 * Setup boot CPU information 1029 */ 1030 smp_store_cpu_info(0); /* Final full version of the data */ 1031 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1032 mb(); 1033 1034 current_thread_info()->cpu = 0; /* needed? */ 1035 for_each_possible_cpu(i) { 1036 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1037 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1038 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1039 } 1040 set_cpu_sibling_map(0); 1041 1042 1043 if (smp_sanity_check(max_cpus) < 0) { 1044 printk(KERN_INFO "SMP disabled\n"); 1045 disable_smp(); 1046 goto out; 1047 } 1048 1049 default_setup_apic_routing(); 1050 1051 preempt_disable(); 1052 if (read_apic_id() != boot_cpu_physical_apicid) { 1053 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1054 read_apic_id(), boot_cpu_physical_apicid); 1055 /* Or can we switch back to PIC here? */ 1056 } 1057 preempt_enable(); 1058 1059 connect_bsp_APIC(); 1060 1061 /* 1062 * Switch from PIC to APIC mode. 1063 */ 1064 setup_local_APIC(); 1065 1066 /* 1067 * Enable IO APIC before setting up error vector 1068 */ 1069 if (!skip_ioapic_setup && nr_ioapics) 1070 enable_IO_APIC(); 1071 1072 bsp_end_local_APIC_setup(); 1073 1074 if (apic->setup_portio_remap) 1075 apic->setup_portio_remap(); 1076 1077 smpboot_setup_io_apic(); 1078 /* 1079 * Set up local APIC timer on boot CPU. 1080 */ 1081 1082 printk(KERN_INFO "CPU%d: ", 0); 1083 print_cpu_info(&cpu_data(0)); 1084 x86_init.timers.setup_percpu_clockev(); 1085 1086 if (is_uv_system()) 1087 uv_system_init(); 1088 1089 set_mtrr_aps_delayed_init(); 1090 out: 1091 preempt_enable(); 1092 } 1093 1094 void arch_disable_nonboot_cpus_begin(void) 1095 { 1096 /* 1097 * Avoid the smp alternatives switch during the disable_nonboot_cpus(). 1098 * In the suspend path, we will be back in the SMP mode shortly anyways. 1099 */ 1100 skip_smp_alternatives = true; 1101 } 1102 1103 void arch_disable_nonboot_cpus_end(void) 1104 { 1105 skip_smp_alternatives = false; 1106 } 1107 1108 void arch_enable_nonboot_cpus_begin(void) 1109 { 1110 set_mtrr_aps_delayed_init(); 1111 } 1112 1113 void arch_enable_nonboot_cpus_end(void) 1114 { 1115 mtrr_aps_init(); 1116 } 1117 1118 /* 1119 * Early setup to make printk work. 1120 */ 1121 void __init native_smp_prepare_boot_cpu(void) 1122 { 1123 int me = smp_processor_id(); 1124 switch_to_new_gdt(me); 1125 /* already set me in cpu_online_mask in boot_cpu_init() */ 1126 cpumask_set_cpu(me, cpu_callout_mask); 1127 per_cpu(cpu_state, me) = CPU_ONLINE; 1128 } 1129 1130 void __init native_smp_cpus_done(unsigned int max_cpus) 1131 { 1132 pr_debug("Boot done.\n"); 1133 1134 nmi_selftest(); 1135 impress_friends(); 1136 #ifdef CONFIG_X86_IO_APIC 1137 setup_ioapic_dest(); 1138 #endif 1139 mtrr_aps_init(); 1140 } 1141 1142 static int __initdata setup_possible_cpus = -1; 1143 static int __init _setup_possible_cpus(char *str) 1144 { 1145 get_option(&str, &setup_possible_cpus); 1146 return 0; 1147 } 1148 early_param("possible_cpus", _setup_possible_cpus); 1149 1150 1151 /* 1152 * cpu_possible_mask should be static, it cannot change as cpu's 1153 * are onlined, or offlined. The reason is per-cpu data-structures 1154 * are allocated by some modules at init time, and dont expect to 1155 * do this dynamically on cpu arrival/departure. 1156 * cpu_present_mask on the other hand can change dynamically. 1157 * In case when cpu_hotplug is not compiled, then we resort to current 1158 * behaviour, which is cpu_possible == cpu_present. 1159 * - Ashok Raj 1160 * 1161 * Three ways to find out the number of additional hotplug CPUs: 1162 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1163 * - The user can overwrite it with possible_cpus=NUM 1164 * - Otherwise don't reserve additional CPUs. 1165 * We do this because additional CPUs waste a lot of memory. 1166 * -AK 1167 */ 1168 __init void prefill_possible_map(void) 1169 { 1170 int i, possible; 1171 1172 /* no processor from mptable or madt */ 1173 if (!num_processors) 1174 num_processors = 1; 1175 1176 i = setup_max_cpus ?: 1; 1177 if (setup_possible_cpus == -1) { 1178 possible = num_processors; 1179 #ifdef CONFIG_HOTPLUG_CPU 1180 if (setup_max_cpus) 1181 possible += disabled_cpus; 1182 #else 1183 if (possible > i) 1184 possible = i; 1185 #endif 1186 } else 1187 possible = setup_possible_cpus; 1188 1189 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1190 1191 /* nr_cpu_ids could be reduced via nr_cpus= */ 1192 if (possible > nr_cpu_ids) { 1193 printk(KERN_WARNING 1194 "%d Processors exceeds NR_CPUS limit of %d\n", 1195 possible, nr_cpu_ids); 1196 possible = nr_cpu_ids; 1197 } 1198 1199 #ifdef CONFIG_HOTPLUG_CPU 1200 if (!setup_max_cpus) 1201 #endif 1202 if (possible > i) { 1203 printk(KERN_WARNING 1204 "%d Processors exceeds max_cpus limit of %u\n", 1205 possible, setup_max_cpus); 1206 possible = i; 1207 } 1208 1209 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", 1210 possible, max_t(int, possible - num_processors, 0)); 1211 1212 for (i = 0; i < possible; i++) 1213 set_cpu_possible(i, true); 1214 for (; i < NR_CPUS; i++) 1215 set_cpu_possible(i, false); 1216 1217 nr_cpu_ids = possible; 1218 } 1219 1220 #ifdef CONFIG_HOTPLUG_CPU 1221 1222 static void remove_siblinginfo(int cpu) 1223 { 1224 int sibling; 1225 struct cpuinfo_x86 *c = &cpu_data(cpu); 1226 1227 for_each_cpu(sibling, cpu_core_mask(cpu)) { 1228 cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); 1229 /*/ 1230 * last thread sibling in this cpu core going down 1231 */ 1232 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) 1233 cpu_data(sibling).booted_cores--; 1234 } 1235 1236 for_each_cpu(sibling, cpu_sibling_mask(cpu)) 1237 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); 1238 cpumask_clear(cpu_sibling_mask(cpu)); 1239 cpumask_clear(cpu_core_mask(cpu)); 1240 c->phys_proc_id = 0; 1241 c->cpu_core_id = 0; 1242 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1243 } 1244 1245 static void __ref remove_cpu_from_maps(int cpu) 1246 { 1247 set_cpu_online(cpu, false); 1248 cpumask_clear_cpu(cpu, cpu_callout_mask); 1249 cpumask_clear_cpu(cpu, cpu_callin_mask); 1250 /* was set by cpu_init() */ 1251 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1252 numa_remove_cpu(cpu); 1253 } 1254 1255 void cpu_disable_common(void) 1256 { 1257 int cpu = smp_processor_id(); 1258 1259 remove_siblinginfo(cpu); 1260 1261 /* It's now safe to remove this processor from the online map */ 1262 lock_vector_lock(); 1263 remove_cpu_from_maps(cpu); 1264 unlock_vector_lock(); 1265 fixup_irqs(); 1266 } 1267 1268 int native_cpu_disable(void) 1269 { 1270 int cpu = smp_processor_id(); 1271 1272 /* 1273 * Perhaps use cpufreq to drop frequency, but that could go 1274 * into generic code. 1275 * 1276 * We won't take down the boot processor on i386 due to some 1277 * interrupts only being able to be serviced by the BSP. 1278 * Especially so if we're not using an IOAPIC -zwane 1279 */ 1280 if (cpu == 0) 1281 return -EBUSY; 1282 1283 clear_local_APIC(); 1284 1285 cpu_disable_common(); 1286 return 0; 1287 } 1288 1289 void native_cpu_die(unsigned int cpu) 1290 { 1291 /* We don't do anything here: idle task is faking death itself. */ 1292 unsigned int i; 1293 1294 for (i = 0; i < 10; i++) { 1295 /* They ack this in play_dead by setting CPU_DEAD */ 1296 if (per_cpu(cpu_state, cpu) == CPU_DEAD) { 1297 if (system_state == SYSTEM_RUNNING) 1298 pr_info("CPU %u is now offline\n", cpu); 1299 1300 if (1 == num_online_cpus()) 1301 alternatives_smp_switch(0); 1302 return; 1303 } 1304 msleep(100); 1305 } 1306 pr_err("CPU %u didn't die...\n", cpu); 1307 } 1308 1309 void play_dead_common(void) 1310 { 1311 idle_task_exit(); 1312 reset_lazy_tlbstate(); 1313 amd_e400_remove_cpu(raw_smp_processor_id()); 1314 1315 mb(); 1316 /* Ack it */ 1317 __this_cpu_write(cpu_state, CPU_DEAD); 1318 1319 /* 1320 * With physical CPU hotplug, we should halt the cpu 1321 */ 1322 local_irq_disable(); 1323 } 1324 1325 /* 1326 * We need to flush the caches before going to sleep, lest we have 1327 * dirty data in our caches when we come back up. 1328 */ 1329 static inline void mwait_play_dead(void) 1330 { 1331 unsigned int eax, ebx, ecx, edx; 1332 unsigned int highest_cstate = 0; 1333 unsigned int highest_subcstate = 0; 1334 int i; 1335 void *mwait_ptr; 1336 struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info); 1337 1338 if (!(this_cpu_has(X86_FEATURE_MWAIT) && mwait_usable(c))) 1339 return; 1340 if (!this_cpu_has(X86_FEATURE_CLFLSH)) 1341 return; 1342 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1343 return; 1344 1345 eax = CPUID_MWAIT_LEAF; 1346 ecx = 0; 1347 native_cpuid(&eax, &ebx, &ecx, &edx); 1348 1349 /* 1350 * eax will be 0 if EDX enumeration is not valid. 1351 * Initialized below to cstate, sub_cstate value when EDX is valid. 1352 */ 1353 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1354 eax = 0; 1355 } else { 1356 edx >>= MWAIT_SUBSTATE_SIZE; 1357 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1358 if (edx & MWAIT_SUBSTATE_MASK) { 1359 highest_cstate = i; 1360 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1361 } 1362 } 1363 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1364 (highest_subcstate - 1); 1365 } 1366 1367 /* 1368 * This should be a memory location in a cache line which is 1369 * unlikely to be touched by other processors. The actual 1370 * content is immaterial as it is not actually modified in any way. 1371 */ 1372 mwait_ptr = ¤t_thread_info()->flags; 1373 1374 wbinvd(); 1375 1376 while (1) { 1377 /* 1378 * The CLFLUSH is a workaround for erratum AAI65 for 1379 * the Xeon 7400 series. It's not clear it is actually 1380 * needed, but it should be harmless in either case. 1381 * The WBINVD is insufficient due to the spurious-wakeup 1382 * case where we return around the loop. 1383 */ 1384 clflush(mwait_ptr); 1385 __monitor(mwait_ptr, 0, 0); 1386 mb(); 1387 __mwait(eax, 0); 1388 } 1389 } 1390 1391 static inline void hlt_play_dead(void) 1392 { 1393 if (__this_cpu_read(cpu_info.x86) >= 4) 1394 wbinvd(); 1395 1396 while (1) { 1397 native_halt(); 1398 } 1399 } 1400 1401 void native_play_dead(void) 1402 { 1403 play_dead_common(); 1404 tboot_shutdown(TB_SHUTDOWN_WFS); 1405 1406 mwait_play_dead(); /* Only returns on failure */ 1407 hlt_play_dead(); 1408 } 1409 1410 #else /* ... !CONFIG_HOTPLUG_CPU */ 1411 int native_cpu_disable(void) 1412 { 1413 return -ENOSYS; 1414 } 1415 1416 void native_cpu_die(unsigned int cpu) 1417 { 1418 /* We said "no" in __cpu_disable */ 1419 BUG(); 1420 } 1421 1422 void native_play_dead(void) 1423 { 1424 BUG(); 1425 } 1426 1427 #endif 1428