1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 43 44 #include <linux/init.h> 45 #include <linux/smp.h> 46 #include <linux/export.h> 47 #include <linux/sched.h> 48 #include <linux/sched/topology.h> 49 #include <linux/sched/hotplug.h> 50 #include <linux/sched/task_stack.h> 51 #include <linux/percpu.h> 52 #include <linux/bootmem.h> 53 #include <linux/err.h> 54 #include <linux/nmi.h> 55 #include <linux/tboot.h> 56 #include <linux/stackprotector.h> 57 #include <linux/gfp.h> 58 #include <linux/cpuidle.h> 59 60 #include <asm/acpi.h> 61 #include <asm/desc.h> 62 #include <asm/nmi.h> 63 #include <asm/irq.h> 64 #include <asm/realmode.h> 65 #include <asm/cpu.h> 66 #include <asm/numa.h> 67 #include <asm/pgtable.h> 68 #include <asm/tlbflush.h> 69 #include <asm/mtrr.h> 70 #include <asm/mwait.h> 71 #include <asm/apic.h> 72 #include <asm/io_apic.h> 73 #include <asm/fpu/internal.h> 74 #include <asm/setup.h> 75 #include <asm/uv/uv.h> 76 #include <linux/mc146818rtc.h> 77 #include <asm/i8259.h> 78 #include <asm/realmode.h> 79 #include <asm/misc.h> 80 81 /* Number of siblings per CPU package */ 82 int smp_num_siblings = 1; 83 EXPORT_SYMBOL(smp_num_siblings); 84 85 /* Last level cache ID of each logical CPU */ 86 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 87 88 /* representing HT siblings of each logical CPU */ 89 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 90 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 91 92 /* representing HT and core siblings of each logical CPU */ 93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 94 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 95 96 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); 97 98 /* Per CPU bogomips and other parameters */ 99 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 100 EXPORT_PER_CPU_SYMBOL(cpu_info); 101 102 /* Logical package management. We might want to allocate that dynamically */ 103 static int *physical_to_logical_pkg __read_mostly; 104 static unsigned long *physical_package_map __read_mostly;; 105 static unsigned int max_physical_pkg_id __read_mostly; 106 unsigned int __max_logical_packages __read_mostly; 107 EXPORT_SYMBOL(__max_logical_packages); 108 static unsigned int logical_packages __read_mostly; 109 110 /* Maximum number of SMT threads on any online core */ 111 int __max_smt_threads __read_mostly; 112 113 /* Flag to indicate if a complete sched domain rebuild is required */ 114 bool x86_topology_update; 115 116 int arch_update_cpu_topology(void) 117 { 118 int retval = x86_topology_update; 119 120 x86_topology_update = false; 121 return retval; 122 } 123 124 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 125 { 126 unsigned long flags; 127 128 spin_lock_irqsave(&rtc_lock, flags); 129 CMOS_WRITE(0xa, 0xf); 130 spin_unlock_irqrestore(&rtc_lock, flags); 131 local_flush_tlb(); 132 pr_debug("1.\n"); 133 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = 134 start_eip >> 4; 135 pr_debug("2.\n"); 136 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 137 start_eip & 0xf; 138 pr_debug("3.\n"); 139 } 140 141 static inline void smpboot_restore_warm_reset_vector(void) 142 { 143 unsigned long flags; 144 145 /* 146 * Install writable page 0 entry to set BIOS data area. 147 */ 148 local_flush_tlb(); 149 150 /* 151 * Paranoid: Set warm reset code and vector here back 152 * to default values. 153 */ 154 spin_lock_irqsave(&rtc_lock, flags); 155 CMOS_WRITE(0, 0xf); 156 spin_unlock_irqrestore(&rtc_lock, flags); 157 158 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 159 } 160 161 /* 162 * Report back to the Boot Processor during boot time or to the caller processor 163 * during CPU online. 164 */ 165 static void smp_callin(void) 166 { 167 int cpuid, phys_id; 168 169 /* 170 * If waken up by an INIT in an 82489DX configuration 171 * cpu_callout_mask guarantees we don't get here before 172 * an INIT_deassert IPI reaches our local APIC, so it is 173 * now safe to touch our local APIC. 174 */ 175 cpuid = smp_processor_id(); 176 177 /* 178 * (This works even if the APIC is not enabled.) 179 */ 180 phys_id = read_apic_id(); 181 182 /* 183 * the boot CPU has finished the init stage and is spinning 184 * on callin_map until we finish. We are free to set up this 185 * CPU, first the APIC. (this is probably redundant on most 186 * boards) 187 */ 188 apic_ap_setup(); 189 190 /* 191 * Save our processor parameters. Note: this information 192 * is needed for clock calibration. 193 */ 194 smp_store_cpu_info(cpuid); 195 196 /* 197 * Get our bogomips. 198 * Update loops_per_jiffy in cpu_data. Previous call to 199 * smp_store_cpu_info() stored a value that is close but not as 200 * accurate as the value just calculated. 201 */ 202 calibrate_delay(); 203 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 204 pr_debug("Stack at about %p\n", &cpuid); 205 206 /* 207 * This must be done before setting cpu_online_mask 208 * or calling notify_cpu_starting. 209 */ 210 set_cpu_sibling_map(raw_smp_processor_id()); 211 wmb(); 212 213 notify_cpu_starting(cpuid); 214 215 /* 216 * Allow the master to continue. 217 */ 218 cpumask_set_cpu(cpuid, cpu_callin_mask); 219 } 220 221 static int cpu0_logical_apicid; 222 static int enable_start_cpu0; 223 /* 224 * Activate a secondary processor. 225 */ 226 static void notrace start_secondary(void *unused) 227 { 228 /* 229 * Don't put *anything* except direct CPU state initialization 230 * before cpu_init(), SMP booting is too fragile that we want to 231 * limit the things done here to the most necessary things. 232 */ 233 if (boot_cpu_has(X86_FEATURE_PCID)) 234 __write_cr4(__read_cr4() | X86_CR4_PCIDE); 235 cpu_init(); 236 x86_cpuinit.early_percpu_clock_init(); 237 preempt_disable(); 238 smp_callin(); 239 240 enable_start_cpu0 = 0; 241 242 #ifdef CONFIG_X86_32 243 /* switch away from the initial page table */ 244 load_cr3(swapper_pg_dir); 245 __flush_tlb_all(); 246 #endif 247 248 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 249 barrier(); 250 /* 251 * Check TSC synchronization with the BP: 252 */ 253 check_tsc_sync_target(); 254 255 /* 256 * Lock vector_lock and initialize the vectors on this cpu 257 * before setting the cpu online. We must set it online with 258 * vector_lock held to prevent a concurrent setup/teardown 259 * from seeing a half valid vector space. 260 */ 261 lock_vector_lock(); 262 setup_vector_irq(smp_processor_id()); 263 set_cpu_online(smp_processor_id(), true); 264 unlock_vector_lock(); 265 cpu_set_state_online(smp_processor_id()); 266 x86_platform.nmi_init(); 267 268 /* enable local interrupts */ 269 local_irq_enable(); 270 271 /* to prevent fake stack check failure in clock setup */ 272 boot_init_stack_canary(); 273 274 x86_cpuinit.setup_percpu_clockev(); 275 276 wmb(); 277 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 278 } 279 280 /** 281 * topology_update_package_map - Update the physical to logical package map 282 * @pkg: The physical package id as retrieved via CPUID 283 * @cpu: The cpu for which this is updated 284 */ 285 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 286 { 287 unsigned int new; 288 289 /* Called from early boot ? */ 290 if (!physical_package_map) 291 return 0; 292 293 if (pkg >= max_physical_pkg_id) 294 return -EINVAL; 295 296 /* Set the logical package id */ 297 if (test_and_set_bit(pkg, physical_package_map)) 298 goto found; 299 300 if (logical_packages >= __max_logical_packages) { 301 pr_warn("Package %u of CPU %u exceeds BIOS package data %u.\n", 302 logical_packages, cpu, __max_logical_packages); 303 return -ENOSPC; 304 } 305 306 new = logical_packages++; 307 if (new != pkg) { 308 pr_info("CPU %u Converting physical %u to logical package %u\n", 309 cpu, pkg, new); 310 } 311 physical_to_logical_pkg[pkg] = new; 312 313 found: 314 cpu_data(cpu).logical_proc_id = physical_to_logical_pkg[pkg]; 315 return 0; 316 } 317 318 /** 319 * topology_phys_to_logical_pkg - Map a physical package id to a logical 320 * 321 * Returns logical package id or -1 if not found 322 */ 323 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 324 { 325 if (phys_pkg >= max_physical_pkg_id) 326 return -1; 327 return physical_to_logical_pkg[phys_pkg]; 328 } 329 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 330 331 static void __init smp_init_package_map(struct cpuinfo_x86 *c, unsigned int cpu) 332 { 333 unsigned int ncpus; 334 size_t size; 335 336 /* 337 * Today neither Intel nor AMD support heterogenous systems. That 338 * might change in the future.... 339 * 340 * While ideally we'd want '* smp_num_siblings' in the below @ncpus 341 * computation, this won't actually work since some Intel BIOSes 342 * report inconsistent HT data when they disable HT. 343 * 344 * In particular, they reduce the APIC-IDs to only include the cores, 345 * but leave the CPUID topology to say there are (2) siblings. 346 * This means we don't know how many threads there will be until 347 * after the APIC enumeration. 348 * 349 * By not including this we'll sometimes over-estimate the number of 350 * logical packages by the amount of !present siblings, but this is 351 * still better than MAX_LOCAL_APIC. 352 * 353 * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited 354 * on the command line leading to a similar issue as the HT disable 355 * problem because the hyperthreads are usually enumerated after the 356 * primary cores. 357 */ 358 ncpus = boot_cpu_data.x86_max_cores; 359 if (!ncpus) { 360 pr_warn("x86_max_cores == zero !?!?"); 361 ncpus = 1; 362 } 363 364 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); 365 logical_packages = 0; 366 367 /* 368 * Possibly larger than what we need as the number of apic ids per 369 * package can be smaller than the actual used apic ids. 370 */ 371 max_physical_pkg_id = DIV_ROUND_UP(MAX_LOCAL_APIC, ncpus); 372 size = max_physical_pkg_id * sizeof(unsigned int); 373 physical_to_logical_pkg = kmalloc(size, GFP_KERNEL); 374 memset(physical_to_logical_pkg, 0xff, size); 375 size = BITS_TO_LONGS(max_physical_pkg_id) * sizeof(unsigned long); 376 physical_package_map = kzalloc(size, GFP_KERNEL); 377 378 pr_info("Max logical packages: %u\n", __max_logical_packages); 379 380 topology_update_package_map(c->phys_proc_id, cpu); 381 } 382 383 void __init smp_store_boot_cpu_info(void) 384 { 385 int id = 0; /* CPU 0 */ 386 struct cpuinfo_x86 *c = &cpu_data(id); 387 388 *c = boot_cpu_data; 389 c->cpu_index = id; 390 smp_init_package_map(c, id); 391 } 392 393 /* 394 * The bootstrap kernel entry code has set these up. Save them for 395 * a given CPU 396 */ 397 void smp_store_cpu_info(int id) 398 { 399 struct cpuinfo_x86 *c = &cpu_data(id); 400 401 *c = boot_cpu_data; 402 c->cpu_index = id; 403 /* 404 * During boot time, CPU0 has this setup already. Save the info when 405 * bringing up AP or offlined CPU0. 406 */ 407 identify_secondary_cpu(c); 408 } 409 410 static bool 411 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 412 { 413 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 414 415 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 416 } 417 418 static bool 419 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 420 { 421 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 422 423 return !WARN_ONCE(!topology_same_node(c, o), 424 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 425 "[node: %d != %d]. Ignoring dependency.\n", 426 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 427 } 428 429 #define link_mask(mfunc, c1, c2) \ 430 do { \ 431 cpumask_set_cpu((c1), mfunc(c2)); \ 432 cpumask_set_cpu((c2), mfunc(c1)); \ 433 } while (0) 434 435 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 436 { 437 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 438 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 439 440 if (c->phys_proc_id == o->phys_proc_id && 441 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { 442 if (c->cpu_core_id == o->cpu_core_id) 443 return topology_sane(c, o, "smt"); 444 445 if ((c->cu_id != 0xff) && 446 (o->cu_id != 0xff) && 447 (c->cu_id == o->cu_id)) 448 return topology_sane(c, o, "smt"); 449 } 450 451 } else if (c->phys_proc_id == o->phys_proc_id && 452 c->cpu_core_id == o->cpu_core_id) { 453 return topology_sane(c, o, "smt"); 454 } 455 456 return false; 457 } 458 459 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 460 { 461 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 462 463 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && 464 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) 465 return topology_sane(c, o, "llc"); 466 467 return false; 468 } 469 470 /* 471 * Unlike the other levels, we do not enforce keeping a 472 * multicore group inside a NUMA node. If this happens, we will 473 * discard the MC level of the topology later. 474 */ 475 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 476 { 477 if (c->phys_proc_id == o->phys_proc_id) 478 return true; 479 return false; 480 } 481 482 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC) 483 static inline int x86_sched_itmt_flags(void) 484 { 485 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 486 } 487 488 #ifdef CONFIG_SCHED_MC 489 static int x86_core_flags(void) 490 { 491 return cpu_core_flags() | x86_sched_itmt_flags(); 492 } 493 #endif 494 #ifdef CONFIG_SCHED_SMT 495 static int x86_smt_flags(void) 496 { 497 return cpu_smt_flags() | x86_sched_itmt_flags(); 498 } 499 #endif 500 #endif 501 502 static struct sched_domain_topology_level x86_numa_in_package_topology[] = { 503 #ifdef CONFIG_SCHED_SMT 504 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 505 #endif 506 #ifdef CONFIG_SCHED_MC 507 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 508 #endif 509 { NULL, }, 510 }; 511 512 static struct sched_domain_topology_level x86_topology[] = { 513 #ifdef CONFIG_SCHED_SMT 514 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 515 #endif 516 #ifdef CONFIG_SCHED_MC 517 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 518 #endif 519 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 520 { NULL, }, 521 }; 522 523 /* 524 * Set if a package/die has multiple NUMA nodes inside. 525 * AMD Magny-Cours and Intel Cluster-on-Die have this. 526 */ 527 static bool x86_has_numa_in_package; 528 529 void set_cpu_sibling_map(int cpu) 530 { 531 bool has_smt = smp_num_siblings > 1; 532 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 533 struct cpuinfo_x86 *c = &cpu_data(cpu); 534 struct cpuinfo_x86 *o; 535 int i, threads; 536 537 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 538 539 if (!has_mp) { 540 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 541 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 542 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 543 c->booted_cores = 1; 544 return; 545 } 546 547 for_each_cpu(i, cpu_sibling_setup_mask) { 548 o = &cpu_data(i); 549 550 if ((i == cpu) || (has_smt && match_smt(c, o))) 551 link_mask(topology_sibling_cpumask, cpu, i); 552 553 if ((i == cpu) || (has_mp && match_llc(c, o))) 554 link_mask(cpu_llc_shared_mask, cpu, i); 555 556 } 557 558 /* 559 * This needs a separate iteration over the cpus because we rely on all 560 * topology_sibling_cpumask links to be set-up. 561 */ 562 for_each_cpu(i, cpu_sibling_setup_mask) { 563 o = &cpu_data(i); 564 565 if ((i == cpu) || (has_mp && match_die(c, o))) { 566 link_mask(topology_core_cpumask, cpu, i); 567 568 /* 569 * Does this new cpu bringup a new core? 570 */ 571 if (cpumask_weight( 572 topology_sibling_cpumask(cpu)) == 1) { 573 /* 574 * for each core in package, increment 575 * the booted_cores for this new cpu 576 */ 577 if (cpumask_first( 578 topology_sibling_cpumask(i)) == i) 579 c->booted_cores++; 580 /* 581 * increment the core count for all 582 * the other cpus in this package 583 */ 584 if (i != cpu) 585 cpu_data(i).booted_cores++; 586 } else if (i != cpu && !c->booted_cores) 587 c->booted_cores = cpu_data(i).booted_cores; 588 } 589 if (match_die(c, o) && !topology_same_node(c, o)) 590 x86_has_numa_in_package = true; 591 } 592 593 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 594 if (threads > __max_smt_threads) 595 __max_smt_threads = threads; 596 } 597 598 /* maps the cpu to the sched domain representing multi-core */ 599 const struct cpumask *cpu_coregroup_mask(int cpu) 600 { 601 return cpu_llc_shared_mask(cpu); 602 } 603 604 static void impress_friends(void) 605 { 606 int cpu; 607 unsigned long bogosum = 0; 608 /* 609 * Allow the user to impress friends. 610 */ 611 pr_debug("Before bogomips\n"); 612 for_each_possible_cpu(cpu) 613 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 614 bogosum += cpu_data(cpu).loops_per_jiffy; 615 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 616 num_online_cpus(), 617 bogosum/(500000/HZ), 618 (bogosum/(5000/HZ))%100); 619 620 pr_debug("Before bogocount - setting activated=1\n"); 621 } 622 623 void __inquire_remote_apic(int apicid) 624 { 625 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 626 const char * const names[] = { "ID", "VERSION", "SPIV" }; 627 int timeout; 628 u32 status; 629 630 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 631 632 for (i = 0; i < ARRAY_SIZE(regs); i++) { 633 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 634 635 /* 636 * Wait for idle. 637 */ 638 status = safe_apic_wait_icr_idle(); 639 if (status) 640 pr_cont("a previous APIC delivery may have failed\n"); 641 642 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 643 644 timeout = 0; 645 do { 646 udelay(100); 647 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 648 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 649 650 switch (status) { 651 case APIC_ICR_RR_VALID: 652 status = apic_read(APIC_RRR); 653 pr_cont("%08x\n", status); 654 break; 655 default: 656 pr_cont("failed\n"); 657 } 658 } 659 } 660 661 /* 662 * The Multiprocessor Specification 1.4 (1997) example code suggests 663 * that there should be a 10ms delay between the BSP asserting INIT 664 * and de-asserting INIT, when starting a remote processor. 665 * But that slows boot and resume on modern processors, which include 666 * many cores and don't require that delay. 667 * 668 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 669 * Modern processor families are quirked to remove the delay entirely. 670 */ 671 #define UDELAY_10MS_DEFAULT 10000 672 673 static unsigned int init_udelay = UINT_MAX; 674 675 static int __init cpu_init_udelay(char *str) 676 { 677 get_option(&str, &init_udelay); 678 679 return 0; 680 } 681 early_param("cpu_init_udelay", cpu_init_udelay); 682 683 static void __init smp_quirk_init_udelay(void) 684 { 685 /* if cmdline changed it from default, leave it alone */ 686 if (init_udelay != UINT_MAX) 687 return; 688 689 /* if modern processor, use no delay */ 690 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 691 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 692 init_udelay = 0; 693 return; 694 } 695 /* else, use legacy delay */ 696 init_udelay = UDELAY_10MS_DEFAULT; 697 } 698 699 /* 700 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 701 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 702 * won't ... remember to clear down the APIC, etc later. 703 */ 704 int 705 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 706 { 707 unsigned long send_status, accept_status = 0; 708 int maxlvt; 709 710 /* Target chip */ 711 /* Boot on the stack */ 712 /* Kick the second */ 713 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); 714 715 pr_debug("Waiting for send to finish...\n"); 716 send_status = safe_apic_wait_icr_idle(); 717 718 /* 719 * Give the other CPU some time to accept the IPI. 720 */ 721 udelay(200); 722 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 723 maxlvt = lapic_get_maxlvt(); 724 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 725 apic_write(APIC_ESR, 0); 726 accept_status = (apic_read(APIC_ESR) & 0xEF); 727 } 728 pr_debug("NMI sent\n"); 729 730 if (send_status) 731 pr_err("APIC never delivered???\n"); 732 if (accept_status) 733 pr_err("APIC delivery error (%lx)\n", accept_status); 734 735 return (send_status | accept_status); 736 } 737 738 static int 739 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 740 { 741 unsigned long send_status = 0, accept_status = 0; 742 int maxlvt, num_starts, j; 743 744 maxlvt = lapic_get_maxlvt(); 745 746 /* 747 * Be paranoid about clearing APIC errors. 748 */ 749 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 750 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 751 apic_write(APIC_ESR, 0); 752 apic_read(APIC_ESR); 753 } 754 755 pr_debug("Asserting INIT\n"); 756 757 /* 758 * Turn INIT on target chip 759 */ 760 /* 761 * Send IPI 762 */ 763 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 764 phys_apicid); 765 766 pr_debug("Waiting for send to finish...\n"); 767 send_status = safe_apic_wait_icr_idle(); 768 769 udelay(init_udelay); 770 771 pr_debug("Deasserting INIT\n"); 772 773 /* Target chip */ 774 /* Send IPI */ 775 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 776 777 pr_debug("Waiting for send to finish...\n"); 778 send_status = safe_apic_wait_icr_idle(); 779 780 mb(); 781 782 /* 783 * Should we send STARTUP IPIs ? 784 * 785 * Determine this based on the APIC version. 786 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 787 */ 788 if (APIC_INTEGRATED(boot_cpu_apic_version)) 789 num_starts = 2; 790 else 791 num_starts = 0; 792 793 /* 794 * Run STARTUP IPI loop. 795 */ 796 pr_debug("#startup loops: %d\n", num_starts); 797 798 for (j = 1; j <= num_starts; j++) { 799 pr_debug("Sending STARTUP #%d\n", j); 800 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 801 apic_write(APIC_ESR, 0); 802 apic_read(APIC_ESR); 803 pr_debug("After apic_write\n"); 804 805 /* 806 * STARTUP IPI 807 */ 808 809 /* Target chip */ 810 /* Boot on the stack */ 811 /* Kick the second */ 812 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 813 phys_apicid); 814 815 /* 816 * Give the other CPU some time to accept the IPI. 817 */ 818 if (init_udelay == 0) 819 udelay(10); 820 else 821 udelay(300); 822 823 pr_debug("Startup point 1\n"); 824 825 pr_debug("Waiting for send to finish...\n"); 826 send_status = safe_apic_wait_icr_idle(); 827 828 /* 829 * Give the other CPU some time to accept the IPI. 830 */ 831 if (init_udelay == 0) 832 udelay(10); 833 else 834 udelay(200); 835 836 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 837 apic_write(APIC_ESR, 0); 838 accept_status = (apic_read(APIC_ESR) & 0xEF); 839 if (send_status || accept_status) 840 break; 841 } 842 pr_debug("After Startup\n"); 843 844 if (send_status) 845 pr_err("APIC never delivered???\n"); 846 if (accept_status) 847 pr_err("APIC delivery error (%lx)\n", accept_status); 848 849 return (send_status | accept_status); 850 } 851 852 /* reduce the number of lines printed when booting a large cpu count system */ 853 static void announce_cpu(int cpu, int apicid) 854 { 855 static int current_node = -1; 856 int node = early_cpu_to_node(cpu); 857 static int width, node_width; 858 859 if (!width) 860 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 861 862 if (!node_width) 863 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 864 865 if (cpu == 1) 866 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 867 868 if (system_state < SYSTEM_RUNNING) { 869 if (node != current_node) { 870 if (current_node > (-1)) 871 pr_cont("\n"); 872 current_node = node; 873 874 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 875 node_width - num_digits(node), " ", node); 876 } 877 878 /* Add padding for the BSP */ 879 if (cpu == 1) 880 pr_cont("%*s", width + 1, " "); 881 882 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 883 884 } else 885 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 886 node, cpu, apicid); 887 } 888 889 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 890 { 891 int cpu; 892 893 cpu = smp_processor_id(); 894 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 895 return NMI_HANDLED; 896 897 return NMI_DONE; 898 } 899 900 /* 901 * Wake up AP by INIT, INIT, STARTUP sequence. 902 * 903 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 904 * boot-strap code which is not a desired behavior for waking up BSP. To 905 * void the boot-strap code, wake up CPU0 by NMI instead. 906 * 907 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 908 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 909 * We'll change this code in the future to wake up hard offlined CPU0 if 910 * real platform and request are available. 911 */ 912 static int 913 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 914 int *cpu0_nmi_registered) 915 { 916 int id; 917 int boot_error; 918 919 preempt_disable(); 920 921 /* 922 * Wake up AP by INIT, INIT, STARTUP sequence. 923 */ 924 if (cpu) { 925 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 926 goto out; 927 } 928 929 /* 930 * Wake up BSP by nmi. 931 * 932 * Register a NMI handler to help wake up CPU0. 933 */ 934 boot_error = register_nmi_handler(NMI_LOCAL, 935 wakeup_cpu0_nmi, 0, "wake_cpu0"); 936 937 if (!boot_error) { 938 enable_start_cpu0 = 1; 939 *cpu0_nmi_registered = 1; 940 if (apic->dest_logical == APIC_DEST_LOGICAL) 941 id = cpu0_logical_apicid; 942 else 943 id = apicid; 944 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 945 } 946 947 out: 948 preempt_enable(); 949 950 return boot_error; 951 } 952 953 void common_cpu_up(unsigned int cpu, struct task_struct *idle) 954 { 955 /* Just in case we booted with a single CPU. */ 956 alternatives_enable_smp(); 957 958 per_cpu(current_task, cpu) = idle; 959 960 #ifdef CONFIG_X86_32 961 /* Stack for startup_32 can be just as for start_secondary onwards */ 962 irq_ctx_init(cpu); 963 per_cpu(cpu_current_top_of_stack, cpu) = 964 (unsigned long)task_stack_page(idle) + THREAD_SIZE; 965 #else 966 initial_gs = per_cpu_offset(cpu); 967 #endif 968 } 969 970 /* 971 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 972 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 973 * Returns zero if CPU booted OK, else error code from 974 * ->wakeup_secondary_cpu. 975 */ 976 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle, 977 int *cpu0_nmi_registered) 978 { 979 volatile u32 *trampoline_status = 980 (volatile u32 *) __va(real_mode_header->trampoline_status); 981 /* start_ip had better be page-aligned! */ 982 unsigned long start_ip = real_mode_header->trampoline_start; 983 984 unsigned long boot_error = 0; 985 unsigned long timeout; 986 987 idle->thread.sp = (unsigned long)task_pt_regs(idle); 988 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 989 initial_code = (unsigned long)start_secondary; 990 initial_stack = idle->thread.sp; 991 992 /* 993 * Enable the espfix hack for this CPU 994 */ 995 #ifdef CONFIG_X86_ESPFIX64 996 init_espfix_ap(cpu); 997 #endif 998 999 /* So we see what's up */ 1000 announce_cpu(cpu, apicid); 1001 1002 /* 1003 * This grunge runs the startup process for 1004 * the targeted processor. 1005 */ 1006 1007 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 1008 1009 pr_debug("Setting warm reset code and vector.\n"); 1010 1011 smpboot_setup_warm_reset_vector(start_ip); 1012 /* 1013 * Be paranoid about clearing APIC errors. 1014 */ 1015 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 1016 apic_write(APIC_ESR, 0); 1017 apic_read(APIC_ESR); 1018 } 1019 } 1020 1021 /* 1022 * AP might wait on cpu_callout_mask in cpu_init() with 1023 * cpu_initialized_mask set if previous attempt to online 1024 * it timed-out. Clear cpu_initialized_mask so that after 1025 * INIT/SIPI it could start with a clean state. 1026 */ 1027 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1028 smp_mb(); 1029 1030 /* 1031 * Wake up a CPU in difference cases: 1032 * - Use the method in the APIC driver if it's defined 1033 * Otherwise, 1034 * - Use an INIT boot APIC message for APs or NMI for BSP. 1035 */ 1036 if (apic->wakeup_secondary_cpu) 1037 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 1038 else 1039 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 1040 cpu0_nmi_registered); 1041 1042 if (!boot_error) { 1043 /* 1044 * Wait 10s total for first sign of life from AP 1045 */ 1046 boot_error = -1; 1047 timeout = jiffies + 10*HZ; 1048 while (time_before(jiffies, timeout)) { 1049 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 1050 /* 1051 * Tell AP to proceed with initialization 1052 */ 1053 cpumask_set_cpu(cpu, cpu_callout_mask); 1054 boot_error = 0; 1055 break; 1056 } 1057 schedule(); 1058 } 1059 } 1060 1061 if (!boot_error) { 1062 /* 1063 * Wait till AP completes initial initialization 1064 */ 1065 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 1066 /* 1067 * Allow other tasks to run while we wait for the 1068 * AP to come online. This also gives a chance 1069 * for the MTRR work(triggered by the AP coming online) 1070 * to be completed in the stop machine context. 1071 */ 1072 schedule(); 1073 } 1074 } 1075 1076 /* mark "stuck" area as not stuck */ 1077 *trampoline_status = 0; 1078 1079 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 1080 /* 1081 * Cleanup possible dangling ends... 1082 */ 1083 smpboot_restore_warm_reset_vector(); 1084 } 1085 1086 return boot_error; 1087 } 1088 1089 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 1090 { 1091 int apicid = apic->cpu_present_to_apicid(cpu); 1092 int cpu0_nmi_registered = 0; 1093 unsigned long flags; 1094 int err, ret = 0; 1095 1096 WARN_ON(irqs_disabled()); 1097 1098 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1099 1100 if (apicid == BAD_APICID || 1101 !physid_isset(apicid, phys_cpu_present_map) || 1102 !apic->apic_id_valid(apicid)) { 1103 pr_err("%s: bad cpu %d\n", __func__, cpu); 1104 return -EINVAL; 1105 } 1106 1107 /* 1108 * Already booted CPU? 1109 */ 1110 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 1111 pr_debug("do_boot_cpu %d Already started\n", cpu); 1112 return -ENOSYS; 1113 } 1114 1115 /* 1116 * Save current MTRR state in case it was changed since early boot 1117 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1118 */ 1119 mtrr_save_state(); 1120 1121 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 1122 err = cpu_check_up_prepare(cpu); 1123 if (err && err != -EBUSY) 1124 return err; 1125 1126 /* the FPU context is blank, nobody can own it */ 1127 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1128 1129 common_cpu_up(cpu, tidle); 1130 1131 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered); 1132 if (err) { 1133 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1134 ret = -EIO; 1135 goto unreg_nmi; 1136 } 1137 1138 /* 1139 * Check TSC synchronization with the AP (keep irqs disabled 1140 * while doing so): 1141 */ 1142 local_irq_save(flags); 1143 check_tsc_sync_source(cpu); 1144 local_irq_restore(flags); 1145 1146 while (!cpu_online(cpu)) { 1147 cpu_relax(); 1148 touch_nmi_watchdog(); 1149 } 1150 1151 unreg_nmi: 1152 /* 1153 * Clean up the nmi handler. Do this after the callin and callout sync 1154 * to avoid impact of possible long unregister time. 1155 */ 1156 if (cpu0_nmi_registered) 1157 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 1158 1159 return ret; 1160 } 1161 1162 /** 1163 * arch_disable_smp_support() - disables SMP support for x86 at runtime 1164 */ 1165 void arch_disable_smp_support(void) 1166 { 1167 disable_ioapic_support(); 1168 } 1169 1170 /* 1171 * Fall back to non SMP mode after errors. 1172 * 1173 * RED-PEN audit/test this more. I bet there is more state messed up here. 1174 */ 1175 static __init void disable_smp(void) 1176 { 1177 pr_info("SMP disabled\n"); 1178 1179 disable_ioapic_support(); 1180 1181 init_cpu_present(cpumask_of(0)); 1182 init_cpu_possible(cpumask_of(0)); 1183 1184 if (smp_found_config) 1185 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1186 else 1187 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1188 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1189 cpumask_set_cpu(0, topology_core_cpumask(0)); 1190 } 1191 1192 enum { 1193 SMP_OK, 1194 SMP_NO_CONFIG, 1195 SMP_NO_APIC, 1196 SMP_FORCE_UP, 1197 }; 1198 1199 /* 1200 * Various sanity checks. 1201 */ 1202 static int __init smp_sanity_check(unsigned max_cpus) 1203 { 1204 preempt_disable(); 1205 1206 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1207 if (def_to_bigsmp && nr_cpu_ids > 8) { 1208 unsigned int cpu; 1209 unsigned nr; 1210 1211 pr_warn("More than 8 CPUs detected - skipping them\n" 1212 "Use CONFIG_X86_BIGSMP\n"); 1213 1214 nr = 0; 1215 for_each_present_cpu(cpu) { 1216 if (nr >= 8) 1217 set_cpu_present(cpu, false); 1218 nr++; 1219 } 1220 1221 nr = 0; 1222 for_each_possible_cpu(cpu) { 1223 if (nr >= 8) 1224 set_cpu_possible(cpu, false); 1225 nr++; 1226 } 1227 1228 nr_cpu_ids = 8; 1229 } 1230 #endif 1231 1232 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1233 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1234 hard_smp_processor_id()); 1235 1236 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1237 } 1238 1239 /* 1240 * If we couldn't find an SMP configuration at boot time, 1241 * get out of here now! 1242 */ 1243 if (!smp_found_config && !acpi_lapic) { 1244 preempt_enable(); 1245 pr_notice("SMP motherboard not detected\n"); 1246 return SMP_NO_CONFIG; 1247 } 1248 1249 /* 1250 * Should not be necessary because the MP table should list the boot 1251 * CPU too, but we do it for the sake of robustness anyway. 1252 */ 1253 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1254 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1255 boot_cpu_physical_apicid); 1256 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1257 } 1258 preempt_enable(); 1259 1260 /* 1261 * If we couldn't find a local APIC, then get out of here now! 1262 */ 1263 if (APIC_INTEGRATED(boot_cpu_apic_version) && 1264 !boot_cpu_has(X86_FEATURE_APIC)) { 1265 if (!disable_apic) { 1266 pr_err("BIOS bug, local APIC #%d not detected!...\n", 1267 boot_cpu_physical_apicid); 1268 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); 1269 } 1270 return SMP_NO_APIC; 1271 } 1272 1273 /* 1274 * If SMP should be disabled, then really disable it! 1275 */ 1276 if (!max_cpus) { 1277 pr_info("SMP mode deactivated\n"); 1278 return SMP_FORCE_UP; 1279 } 1280 1281 return SMP_OK; 1282 } 1283 1284 static void __init smp_cpu_index_default(void) 1285 { 1286 int i; 1287 struct cpuinfo_x86 *c; 1288 1289 for_each_possible_cpu(i) { 1290 c = &cpu_data(i); 1291 /* mark all to hotplug */ 1292 c->cpu_index = nr_cpu_ids; 1293 } 1294 } 1295 1296 /* 1297 * Prepare for SMP bootup. The MP table or ACPI has been read 1298 * earlier. Just do some sanity checking here and enable APIC mode. 1299 */ 1300 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1301 { 1302 unsigned int i; 1303 1304 smp_cpu_index_default(); 1305 1306 /* 1307 * Setup boot CPU information 1308 */ 1309 smp_store_boot_cpu_info(); /* Final full version of the data */ 1310 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1311 mb(); 1312 1313 for_each_possible_cpu(i) { 1314 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1315 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1316 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1317 } 1318 1319 /* 1320 * Set 'default' x86 topology, this matches default_topology() in that 1321 * it has NUMA nodes as a topology level. See also 1322 * native_smp_cpus_done(). 1323 * 1324 * Must be done before set_cpus_sibling_map() is ran. 1325 */ 1326 set_sched_topology(x86_topology); 1327 1328 set_cpu_sibling_map(0); 1329 1330 switch (smp_sanity_check(max_cpus)) { 1331 case SMP_NO_CONFIG: 1332 disable_smp(); 1333 if (APIC_init_uniprocessor()) 1334 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); 1335 return; 1336 case SMP_NO_APIC: 1337 disable_smp(); 1338 return; 1339 case SMP_FORCE_UP: 1340 disable_smp(); 1341 apic_bsp_setup(false); 1342 return; 1343 case SMP_OK: 1344 break; 1345 } 1346 1347 if (read_apic_id() != boot_cpu_physical_apicid) { 1348 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1349 read_apic_id(), boot_cpu_physical_apicid); 1350 /* Or can we switch back to PIC here? */ 1351 } 1352 1353 default_setup_apic_routing(); 1354 cpu0_logical_apicid = apic_bsp_setup(false); 1355 1356 pr_info("CPU0: "); 1357 print_cpu_info(&cpu_data(0)); 1358 1359 uv_system_init(); 1360 1361 set_mtrr_aps_delayed_init(); 1362 1363 smp_quirk_init_udelay(); 1364 } 1365 1366 void arch_enable_nonboot_cpus_begin(void) 1367 { 1368 set_mtrr_aps_delayed_init(); 1369 } 1370 1371 void arch_enable_nonboot_cpus_end(void) 1372 { 1373 mtrr_aps_init(); 1374 } 1375 1376 /* 1377 * Early setup to make printk work. 1378 */ 1379 void __init native_smp_prepare_boot_cpu(void) 1380 { 1381 int me = smp_processor_id(); 1382 switch_to_new_gdt(me); 1383 /* already set me in cpu_online_mask in boot_cpu_init() */ 1384 cpumask_set_cpu(me, cpu_callout_mask); 1385 cpu_set_state_online(me); 1386 } 1387 1388 void __init native_smp_cpus_done(unsigned int max_cpus) 1389 { 1390 pr_debug("Boot done\n"); 1391 1392 if (x86_has_numa_in_package) 1393 set_sched_topology(x86_numa_in_package_topology); 1394 1395 nmi_selftest(); 1396 impress_friends(); 1397 setup_ioapic_dest(); 1398 mtrr_aps_init(); 1399 } 1400 1401 static int __initdata setup_possible_cpus = -1; 1402 static int __init _setup_possible_cpus(char *str) 1403 { 1404 get_option(&str, &setup_possible_cpus); 1405 return 0; 1406 } 1407 early_param("possible_cpus", _setup_possible_cpus); 1408 1409 1410 /* 1411 * cpu_possible_mask should be static, it cannot change as cpu's 1412 * are onlined, or offlined. The reason is per-cpu data-structures 1413 * are allocated by some modules at init time, and dont expect to 1414 * do this dynamically on cpu arrival/departure. 1415 * cpu_present_mask on the other hand can change dynamically. 1416 * In case when cpu_hotplug is not compiled, then we resort to current 1417 * behaviour, which is cpu_possible == cpu_present. 1418 * - Ashok Raj 1419 * 1420 * Three ways to find out the number of additional hotplug CPUs: 1421 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1422 * - The user can overwrite it with possible_cpus=NUM 1423 * - Otherwise don't reserve additional CPUs. 1424 * We do this because additional CPUs waste a lot of memory. 1425 * -AK 1426 */ 1427 __init void prefill_possible_map(void) 1428 { 1429 int i, possible; 1430 1431 /* No boot processor was found in mptable or ACPI MADT */ 1432 if (!num_processors) { 1433 if (boot_cpu_has(X86_FEATURE_APIC)) { 1434 int apicid = boot_cpu_physical_apicid; 1435 int cpu = hard_smp_processor_id(); 1436 1437 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); 1438 1439 /* Make sure boot cpu is enumerated */ 1440 if (apic->cpu_present_to_apicid(0) == BAD_APICID && 1441 apic->apic_id_valid(apicid)) 1442 generic_processor_info(apicid, boot_cpu_apic_version); 1443 } 1444 1445 if (!num_processors) 1446 num_processors = 1; 1447 } 1448 1449 i = setup_max_cpus ?: 1; 1450 if (setup_possible_cpus == -1) { 1451 possible = num_processors; 1452 #ifdef CONFIG_HOTPLUG_CPU 1453 if (setup_max_cpus) 1454 possible += disabled_cpus; 1455 #else 1456 if (possible > i) 1457 possible = i; 1458 #endif 1459 } else 1460 possible = setup_possible_cpus; 1461 1462 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1463 1464 /* nr_cpu_ids could be reduced via nr_cpus= */ 1465 if (possible > nr_cpu_ids) { 1466 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", 1467 possible, nr_cpu_ids); 1468 possible = nr_cpu_ids; 1469 } 1470 1471 #ifdef CONFIG_HOTPLUG_CPU 1472 if (!setup_max_cpus) 1473 #endif 1474 if (possible > i) { 1475 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1476 possible, setup_max_cpus); 1477 possible = i; 1478 } 1479 1480 nr_cpu_ids = possible; 1481 1482 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1483 possible, max_t(int, possible - num_processors, 0)); 1484 1485 reset_cpu_possible_mask(); 1486 1487 for (i = 0; i < possible; i++) 1488 set_cpu_possible(i, true); 1489 } 1490 1491 #ifdef CONFIG_HOTPLUG_CPU 1492 1493 /* Recompute SMT state for all CPUs on offline */ 1494 static void recompute_smt_state(void) 1495 { 1496 int max_threads, cpu; 1497 1498 max_threads = 0; 1499 for_each_online_cpu (cpu) { 1500 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1501 1502 if (threads > max_threads) 1503 max_threads = threads; 1504 } 1505 __max_smt_threads = max_threads; 1506 } 1507 1508 static void remove_siblinginfo(int cpu) 1509 { 1510 int sibling; 1511 struct cpuinfo_x86 *c = &cpu_data(cpu); 1512 1513 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1514 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1515 /*/ 1516 * last thread sibling in this cpu core going down 1517 */ 1518 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1519 cpu_data(sibling).booted_cores--; 1520 } 1521 1522 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) 1523 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1524 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1525 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1526 cpumask_clear(cpu_llc_shared_mask(cpu)); 1527 cpumask_clear(topology_sibling_cpumask(cpu)); 1528 cpumask_clear(topology_core_cpumask(cpu)); 1529 c->phys_proc_id = 0; 1530 c->cpu_core_id = 0; 1531 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1532 recompute_smt_state(); 1533 } 1534 1535 static void remove_cpu_from_maps(int cpu) 1536 { 1537 set_cpu_online(cpu, false); 1538 cpumask_clear_cpu(cpu, cpu_callout_mask); 1539 cpumask_clear_cpu(cpu, cpu_callin_mask); 1540 /* was set by cpu_init() */ 1541 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1542 numa_remove_cpu(cpu); 1543 } 1544 1545 void cpu_disable_common(void) 1546 { 1547 int cpu = smp_processor_id(); 1548 1549 remove_siblinginfo(cpu); 1550 1551 /* It's now safe to remove this processor from the online map */ 1552 lock_vector_lock(); 1553 remove_cpu_from_maps(cpu); 1554 unlock_vector_lock(); 1555 fixup_irqs(); 1556 } 1557 1558 int native_cpu_disable(void) 1559 { 1560 int ret; 1561 1562 ret = check_irq_vectors_for_cpu_disable(); 1563 if (ret) 1564 return ret; 1565 1566 clear_local_APIC(); 1567 cpu_disable_common(); 1568 1569 return 0; 1570 } 1571 1572 int common_cpu_die(unsigned int cpu) 1573 { 1574 int ret = 0; 1575 1576 /* We don't do anything here: idle task is faking death itself. */ 1577 1578 /* They ack this in play_dead() by setting CPU_DEAD */ 1579 if (cpu_wait_death(cpu, 5)) { 1580 if (system_state == SYSTEM_RUNNING) 1581 pr_info("CPU %u is now offline\n", cpu); 1582 } else { 1583 pr_err("CPU %u didn't die...\n", cpu); 1584 ret = -1; 1585 } 1586 1587 return ret; 1588 } 1589 1590 void native_cpu_die(unsigned int cpu) 1591 { 1592 common_cpu_die(cpu); 1593 } 1594 1595 void play_dead_common(void) 1596 { 1597 idle_task_exit(); 1598 1599 /* Ack it */ 1600 (void)cpu_report_death(); 1601 1602 /* 1603 * With physical CPU hotplug, we should halt the cpu 1604 */ 1605 local_irq_disable(); 1606 } 1607 1608 static bool wakeup_cpu0(void) 1609 { 1610 if (smp_processor_id() == 0 && enable_start_cpu0) 1611 return true; 1612 1613 return false; 1614 } 1615 1616 /* 1617 * We need to flush the caches before going to sleep, lest we have 1618 * dirty data in our caches when we come back up. 1619 */ 1620 static inline void mwait_play_dead(void) 1621 { 1622 unsigned int eax, ebx, ecx, edx; 1623 unsigned int highest_cstate = 0; 1624 unsigned int highest_subcstate = 0; 1625 void *mwait_ptr; 1626 int i; 1627 1628 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1629 return; 1630 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1631 return; 1632 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1633 return; 1634 1635 eax = CPUID_MWAIT_LEAF; 1636 ecx = 0; 1637 native_cpuid(&eax, &ebx, &ecx, &edx); 1638 1639 /* 1640 * eax will be 0 if EDX enumeration is not valid. 1641 * Initialized below to cstate, sub_cstate value when EDX is valid. 1642 */ 1643 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1644 eax = 0; 1645 } else { 1646 edx >>= MWAIT_SUBSTATE_SIZE; 1647 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1648 if (edx & MWAIT_SUBSTATE_MASK) { 1649 highest_cstate = i; 1650 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1651 } 1652 } 1653 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1654 (highest_subcstate - 1); 1655 } 1656 1657 /* 1658 * This should be a memory location in a cache line which is 1659 * unlikely to be touched by other processors. The actual 1660 * content is immaterial as it is not actually modified in any way. 1661 */ 1662 mwait_ptr = ¤t_thread_info()->flags; 1663 1664 wbinvd(); 1665 1666 while (1) { 1667 /* 1668 * The CLFLUSH is a workaround for erratum AAI65 for 1669 * the Xeon 7400 series. It's not clear it is actually 1670 * needed, but it should be harmless in either case. 1671 * The WBINVD is insufficient due to the spurious-wakeup 1672 * case where we return around the loop. 1673 */ 1674 mb(); 1675 clflush(mwait_ptr); 1676 mb(); 1677 __monitor(mwait_ptr, 0, 0); 1678 mb(); 1679 __mwait(eax, 0); 1680 /* 1681 * If NMI wants to wake up CPU0, start CPU0. 1682 */ 1683 if (wakeup_cpu0()) 1684 start_cpu0(); 1685 } 1686 } 1687 1688 void hlt_play_dead(void) 1689 { 1690 if (__this_cpu_read(cpu_info.x86) >= 4) 1691 wbinvd(); 1692 1693 while (1) { 1694 native_halt(); 1695 /* 1696 * If NMI wants to wake up CPU0, start CPU0. 1697 */ 1698 if (wakeup_cpu0()) 1699 start_cpu0(); 1700 } 1701 } 1702 1703 void native_play_dead(void) 1704 { 1705 play_dead_common(); 1706 tboot_shutdown(TB_SHUTDOWN_WFS); 1707 1708 mwait_play_dead(); /* Only returns on failure */ 1709 if (cpuidle_play_dead()) 1710 hlt_play_dead(); 1711 } 1712 1713 #else /* ... !CONFIG_HOTPLUG_CPU */ 1714 int native_cpu_disable(void) 1715 { 1716 return -ENOSYS; 1717 } 1718 1719 void native_cpu_die(unsigned int cpu) 1720 { 1721 /* We said "no" in __cpu_disable */ 1722 BUG(); 1723 } 1724 1725 void native_play_dead(void) 1726 { 1727 BUG(); 1728 } 1729 1730 #endif 1731