1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * x86 SMP booting functions 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 7 * Copyright 2001 Andi Kleen, SuSE Labs. 8 * 9 * Much of the core SMP work is based on previous work by Thomas Radke, to 10 * whom a great many thanks are extended. 11 * 12 * Thanks to Intel for making available several different Pentium, 13 * Pentium Pro and Pentium-II/Xeon MP machines. 14 * Original development of Linux SMP code supported by Caldera. 15 * 16 * Fixes 17 * Felix Koop : NR_CPUS used properly 18 * Jose Renau : Handle single CPU case. 19 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 20 * Greg Wright : Fix for kernel stacks panic. 21 * Erich Boleyn : MP v1.4 and additional changes. 22 * Matthias Sattler : Changes for 2.1 kernel map. 23 * Michel Lespinasse : Changes for 2.1 kernel map. 24 * Michael Chastain : Change trampoline.S to gnu as. 25 * Alan Cox : Dumb bug: 'B' step PPro's are fine 26 * Ingo Molnar : Added APIC timers, based on code 27 * from Jose Renau 28 * Ingo Molnar : various cleanups and rewrites 29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 31 * Andi Kleen : Changed for SMP boot into long mode. 32 * Martin J. Bligh : Added support for multi-quad systems 33 * Dave Jones : Report invalid combinations of Athlon CPUs. 34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 35 * Andi Kleen : Converted to new state machine. 36 * Ashok Raj : CPU hotplug support 37 * Glauber Costa : i386 and x86_64 integration 38 */ 39 40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/export.h> 45 #include <linux/sched.h> 46 #include <linux/sched/topology.h> 47 #include <linux/sched/hotplug.h> 48 #include <linux/sched/task_stack.h> 49 #include <linux/percpu.h> 50 #include <linux/memblock.h> 51 #include <linux/err.h> 52 #include <linux/nmi.h> 53 #include <linux/tboot.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 #include <linux/kexec.h> 57 #include <linux/numa.h> 58 #include <linux/pgtable.h> 59 #include <linux/overflow.h> 60 #include <linux/stackprotector.h> 61 #include <linux/cpuhotplug.h> 62 #include <linux/mc146818rtc.h> 63 64 #include <asm/acpi.h> 65 #include <asm/cacheinfo.h> 66 #include <asm/desc.h> 67 #include <asm/nmi.h> 68 #include <asm/irq.h> 69 #include <asm/realmode.h> 70 #include <asm/cpu.h> 71 #include <asm/numa.h> 72 #include <asm/tlbflush.h> 73 #include <asm/mtrr.h> 74 #include <asm/mwait.h> 75 #include <asm/apic.h> 76 #include <asm/io_apic.h> 77 #include <asm/fpu/api.h> 78 #include <asm/setup.h> 79 #include <asm/uv/uv.h> 80 #include <asm/microcode.h> 81 #include <asm/i8259.h> 82 #include <asm/misc.h> 83 #include <asm/qspinlock.h> 84 #include <asm/intel-family.h> 85 #include <asm/cpu_device_id.h> 86 #include <asm/spec-ctrl.h> 87 #include <asm/hw_irq.h> 88 #include <asm/stackprotector.h> 89 #include <asm/sev.h> 90 #include <asm/spec-ctrl.h> 91 92 /* representing HT siblings of each logical CPU */ 93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 94 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 95 96 /* representing HT and core siblings of each logical CPU */ 97 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 98 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 99 100 /* representing HT, core, and die siblings of each logical CPU */ 101 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); 102 EXPORT_PER_CPU_SYMBOL(cpu_die_map); 103 104 /* CPUs which are the primary SMT threads */ 105 struct cpumask __cpu_primary_thread_mask __read_mostly; 106 107 /* Representing CPUs for which sibling maps can be computed */ 108 static cpumask_var_t cpu_sibling_setup_mask; 109 110 struct mwait_cpu_dead { 111 unsigned int control; 112 unsigned int status; 113 }; 114 115 #define CPUDEAD_MWAIT_WAIT 0xDEADBEEF 116 #define CPUDEAD_MWAIT_KEXEC_HLT 0x4A17DEAD 117 118 /* 119 * Cache line aligned data for mwait_play_dead(). Separate on purpose so 120 * that it's unlikely to be touched by other CPUs. 121 */ 122 static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead); 123 124 /* Maximum number of SMT threads on any online core */ 125 int __read_mostly __max_smt_threads = 1; 126 127 /* Flag to indicate if a complete sched domain rebuild is required */ 128 bool x86_topology_update; 129 130 int arch_update_cpu_topology(void) 131 { 132 int retval = x86_topology_update; 133 134 x86_topology_update = false; 135 return retval; 136 } 137 138 static unsigned int smpboot_warm_reset_vector_count; 139 140 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 141 { 142 unsigned long flags; 143 144 spin_lock_irqsave(&rtc_lock, flags); 145 if (!smpboot_warm_reset_vector_count++) { 146 CMOS_WRITE(0xa, 0xf); 147 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = start_eip >> 4; 148 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = start_eip & 0xf; 149 } 150 spin_unlock_irqrestore(&rtc_lock, flags); 151 } 152 153 static inline void smpboot_restore_warm_reset_vector(void) 154 { 155 unsigned long flags; 156 157 /* 158 * Paranoid: Set warm reset code and vector here back 159 * to default values. 160 */ 161 spin_lock_irqsave(&rtc_lock, flags); 162 if (!--smpboot_warm_reset_vector_count) { 163 CMOS_WRITE(0, 0xf); 164 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 165 } 166 spin_unlock_irqrestore(&rtc_lock, flags); 167 168 } 169 170 /* Run the next set of setup steps for the upcoming CPU */ 171 static void ap_starting(void) 172 { 173 int cpuid = smp_processor_id(); 174 175 /* Mop up eventual mwait_play_dead() wreckage */ 176 this_cpu_write(mwait_cpu_dead.status, 0); 177 this_cpu_write(mwait_cpu_dead.control, 0); 178 179 /* 180 * If woken up by an INIT in an 82489DX configuration the alive 181 * synchronization guarantees that the CPU does not reach this 182 * point before an INIT_deassert IPI reaches the local APIC, so it 183 * is now safe to touch the local APIC. 184 * 185 * Set up this CPU, first the APIC, which is probably redundant on 186 * most boards. 187 */ 188 apic_ap_setup(); 189 190 /* Save the processor parameters. */ 191 smp_store_cpu_info(cpuid); 192 193 /* 194 * The topology information must be up to date before 195 * notify_cpu_starting(). 196 */ 197 set_cpu_sibling_map(cpuid); 198 199 ap_init_aperfmperf(); 200 201 pr_debug("Stack at about %p\n", &cpuid); 202 203 wmb(); 204 205 /* 206 * This runs the AP through all the cpuhp states to its target 207 * state CPUHP_ONLINE. 208 */ 209 notify_cpu_starting(cpuid); 210 } 211 212 static void ap_calibrate_delay(void) 213 { 214 /* 215 * Calibrate the delay loop and update loops_per_jiffy in cpu_data. 216 * smp_store_cpu_info() stored a value that is close but not as 217 * accurate as the value just calculated. 218 * 219 * As this is invoked after the TSC synchronization check, 220 * calibrate_delay_is_known() will skip the calibration routine 221 * when TSC is synchronized across sockets. 222 */ 223 calibrate_delay(); 224 cpu_data(smp_processor_id()).loops_per_jiffy = loops_per_jiffy; 225 } 226 227 /* 228 * Activate a secondary processor. 229 */ 230 static void notrace start_secondary(void *unused) 231 { 232 /* 233 * Don't put *anything* except direct CPU state initialization 234 * before cpu_init(), SMP booting is too fragile that we want to 235 * limit the things done here to the most necessary things. 236 */ 237 cr4_init(); 238 239 /* 240 * 32-bit specific. 64-bit reaches this code with the correct page 241 * table established. Yet another historical divergence. 242 */ 243 if (IS_ENABLED(CONFIG_X86_32)) { 244 /* switch away from the initial page table */ 245 load_cr3(swapper_pg_dir); 246 __flush_tlb_all(); 247 } 248 249 cpu_init_exception_handling(); 250 251 /* 252 * Load the microcode before reaching the AP alive synchronization 253 * point below so it is not part of the full per CPU serialized 254 * bringup part when "parallel" bringup is enabled. 255 * 256 * That's even safe when hyperthreading is enabled in the CPU as 257 * the core code starts the primary threads first and leaves the 258 * secondary threads waiting for SIPI. Loading microcode on 259 * physical cores concurrently is a safe operation. 260 * 261 * This covers both the Intel specific issue that concurrent 262 * microcode loading on SMT siblings must be prohibited and the 263 * vendor independent issue`that microcode loading which changes 264 * CPUID, MSRs etc. must be strictly serialized to maintain 265 * software state correctness. 266 */ 267 load_ucode_ap(); 268 269 /* 270 * Synchronization point with the hotplug core. Sets this CPUs 271 * synchronization state to ALIVE and spin-waits for the control CPU to 272 * release this CPU for further bringup. 273 */ 274 cpuhp_ap_sync_alive(); 275 276 cpu_init(); 277 fpu__init_cpu(); 278 rcutree_report_cpu_starting(raw_smp_processor_id()); 279 x86_cpuinit.early_percpu_clock_init(); 280 281 ap_starting(); 282 283 /* Check TSC synchronization with the control CPU. */ 284 check_tsc_sync_target(); 285 286 /* 287 * Calibrate the delay loop after the TSC synchronization check. 288 * This allows to skip the calibration when TSC is synchronized 289 * across sockets. 290 */ 291 ap_calibrate_delay(); 292 293 speculative_store_bypass_ht_init(); 294 295 /* 296 * Lock vector_lock, set CPU online and bring the vector 297 * allocator online. Online must be set with vector_lock held 298 * to prevent a concurrent irq setup/teardown from seeing a 299 * half valid vector space. 300 */ 301 lock_vector_lock(); 302 set_cpu_online(smp_processor_id(), true); 303 lapic_online(); 304 unlock_vector_lock(); 305 x86_platform.nmi_init(); 306 307 /* enable local interrupts */ 308 local_irq_enable(); 309 310 x86_cpuinit.setup_percpu_clockev(); 311 312 wmb(); 313 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 314 } 315 316 static void __init smp_store_boot_cpu_info(void) 317 { 318 struct cpuinfo_x86 *c = &cpu_data(0); 319 320 *c = boot_cpu_data; 321 c->initialized = true; 322 } 323 324 /* 325 * The bootstrap kernel entry code has set these up. Save them for 326 * a given CPU 327 */ 328 void smp_store_cpu_info(int id) 329 { 330 struct cpuinfo_x86 *c = &cpu_data(id); 331 332 /* Copy boot_cpu_data only on the first bringup */ 333 if (!c->initialized) 334 *c = boot_cpu_data; 335 c->cpu_index = id; 336 /* 337 * During boot time, CPU0 has this setup already. Save the info when 338 * bringing up an AP. 339 */ 340 identify_secondary_cpu(c); 341 c->initialized = true; 342 } 343 344 static bool 345 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 346 { 347 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 348 349 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 350 } 351 352 static bool 353 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 354 { 355 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 356 357 return !WARN_ONCE(!topology_same_node(c, o), 358 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 359 "[node: %d != %d]. Ignoring dependency.\n", 360 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 361 } 362 363 #define link_mask(mfunc, c1, c2) \ 364 do { \ 365 cpumask_set_cpu((c1), mfunc(c2)); \ 366 cpumask_set_cpu((c2), mfunc(c1)); \ 367 } while (0) 368 369 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 370 { 371 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 372 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 373 374 if (c->topo.pkg_id == o->topo.pkg_id && 375 c->topo.die_id == o->topo.die_id && 376 c->topo.amd_node_id == o->topo.amd_node_id && 377 per_cpu_llc_id(cpu1) == per_cpu_llc_id(cpu2)) { 378 if (c->topo.core_id == o->topo.core_id) 379 return topology_sane(c, o, "smt"); 380 381 if ((c->topo.cu_id != 0xff) && 382 (o->topo.cu_id != 0xff) && 383 (c->topo.cu_id == o->topo.cu_id)) 384 return topology_sane(c, o, "smt"); 385 } 386 387 } else if (c->topo.pkg_id == o->topo.pkg_id && 388 c->topo.die_id == o->topo.die_id && 389 c->topo.core_id == o->topo.core_id) { 390 return topology_sane(c, o, "smt"); 391 } 392 393 return false; 394 } 395 396 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 397 { 398 if (c->topo.pkg_id != o->topo.pkg_id || c->topo.die_id != o->topo.die_id) 399 return false; 400 401 if (cpu_feature_enabled(X86_FEATURE_TOPOEXT) && topology_amd_nodes_per_pkg() > 1) 402 return c->topo.amd_node_id == o->topo.amd_node_id; 403 404 return true; 405 } 406 407 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 408 { 409 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 410 411 /* If the arch didn't set up l2c_id, fall back to SMT */ 412 if (per_cpu_l2c_id(cpu1) == BAD_APICID) 413 return match_smt(c, o); 414 415 /* Do not match if L2 cache id does not match: */ 416 if (per_cpu_l2c_id(cpu1) != per_cpu_l2c_id(cpu2)) 417 return false; 418 419 return topology_sane(c, o, "l2c"); 420 } 421 422 /* 423 * Unlike the other levels, we do not enforce keeping a 424 * multicore group inside a NUMA node. If this happens, we will 425 * discard the MC level of the topology later. 426 */ 427 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 428 { 429 if (c->topo.pkg_id == o->topo.pkg_id) 430 return true; 431 return false; 432 } 433 434 /* 435 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs. 436 * 437 * Any Intel CPU that has multiple nodes per package and does not 438 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology. 439 * 440 * When in SNC mode, these CPUs enumerate an LLC that is shared 441 * by multiple NUMA nodes. The LLC is shared for off-package data 442 * access but private to the NUMA node (half of the package) for 443 * on-package access. CPUID (the source of the information about 444 * the LLC) can only enumerate the cache as shared or unshared, 445 * but not this particular configuration. 446 */ 447 448 static const struct x86_cpu_id intel_cod_cpu[] = { 449 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */ 450 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */ 451 X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */ 452 {} 453 }; 454 455 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 456 { 457 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu); 458 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 459 bool intel_snc = id && id->driver_data; 460 461 /* Do not match if we do not have a valid APICID for cpu: */ 462 if (per_cpu_llc_id(cpu1) == BAD_APICID) 463 return false; 464 465 /* Do not match if LLC id does not match: */ 466 if (per_cpu_llc_id(cpu1) != per_cpu_llc_id(cpu2)) 467 return false; 468 469 /* 470 * Allow the SNC topology without warning. Return of false 471 * means 'c' does not share the LLC of 'o'. This will be 472 * reflected to userspace. 473 */ 474 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc) 475 return false; 476 477 return topology_sane(c, o, "llc"); 478 } 479 480 481 static inline int x86_sched_itmt_flags(void) 482 { 483 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 484 } 485 486 #ifdef CONFIG_SCHED_MC 487 static int x86_core_flags(void) 488 { 489 return cpu_core_flags() | x86_sched_itmt_flags(); 490 } 491 #endif 492 #ifdef CONFIG_SCHED_SMT 493 static int x86_smt_flags(void) 494 { 495 return cpu_smt_flags(); 496 } 497 #endif 498 #ifdef CONFIG_SCHED_CLUSTER 499 static int x86_cluster_flags(void) 500 { 501 return cpu_cluster_flags() | x86_sched_itmt_flags(); 502 } 503 #endif 504 505 static int x86_die_flags(void) 506 { 507 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) 508 return x86_sched_itmt_flags(); 509 510 return 0; 511 } 512 513 /* 514 * Set if a package/die has multiple NUMA nodes inside. 515 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel 516 * Sub-NUMA Clustering have this. 517 */ 518 static bool x86_has_numa_in_package; 519 520 static struct sched_domain_topology_level x86_topology[6]; 521 522 static void __init build_sched_topology(void) 523 { 524 int i = 0; 525 526 #ifdef CONFIG_SCHED_SMT 527 x86_topology[i++] = (struct sched_domain_topology_level){ 528 cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) 529 }; 530 #endif 531 #ifdef CONFIG_SCHED_CLUSTER 532 x86_topology[i++] = (struct sched_domain_topology_level){ 533 cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) 534 }; 535 #endif 536 #ifdef CONFIG_SCHED_MC 537 x86_topology[i++] = (struct sched_domain_topology_level){ 538 cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) 539 }; 540 #endif 541 /* 542 * When there is NUMA topology inside the package skip the PKG domain 543 * since the NUMA domains will auto-magically create the right spanning 544 * domains based on the SLIT. 545 */ 546 if (!x86_has_numa_in_package) { 547 x86_topology[i++] = (struct sched_domain_topology_level){ 548 cpu_cpu_mask, x86_die_flags, SD_INIT_NAME(PKG) 549 }; 550 } 551 552 /* 553 * There must be one trailing NULL entry left. 554 */ 555 BUG_ON(i >= ARRAY_SIZE(x86_topology)-1); 556 557 set_sched_topology(x86_topology); 558 } 559 560 void set_cpu_sibling_map(int cpu) 561 { 562 bool has_smt = __max_threads_per_core > 1; 563 bool has_mp = has_smt || topology_num_cores_per_package() > 1; 564 struct cpuinfo_x86 *c = &cpu_data(cpu); 565 struct cpuinfo_x86 *o; 566 int i, threads; 567 568 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 569 570 if (!has_mp) { 571 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 572 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 573 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu)); 574 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 575 cpumask_set_cpu(cpu, topology_die_cpumask(cpu)); 576 c->booted_cores = 1; 577 return; 578 } 579 580 for_each_cpu(i, cpu_sibling_setup_mask) { 581 o = &cpu_data(i); 582 583 if (match_pkg(c, o) && !topology_same_node(c, o)) 584 x86_has_numa_in_package = true; 585 586 if ((i == cpu) || (has_smt && match_smt(c, o))) 587 link_mask(topology_sibling_cpumask, cpu, i); 588 589 if ((i == cpu) || (has_mp && match_llc(c, o))) 590 link_mask(cpu_llc_shared_mask, cpu, i); 591 592 if ((i == cpu) || (has_mp && match_l2c(c, o))) 593 link_mask(cpu_l2c_shared_mask, cpu, i); 594 595 if ((i == cpu) || (has_mp && match_die(c, o))) 596 link_mask(topology_die_cpumask, cpu, i); 597 } 598 599 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 600 if (threads > __max_smt_threads) 601 __max_smt_threads = threads; 602 603 for_each_cpu(i, topology_sibling_cpumask(cpu)) 604 cpu_data(i).smt_active = threads > 1; 605 606 /* 607 * This needs a separate iteration over the cpus because we rely on all 608 * topology_sibling_cpumask links to be set-up. 609 */ 610 for_each_cpu(i, cpu_sibling_setup_mask) { 611 o = &cpu_data(i); 612 613 if ((i == cpu) || (has_mp && match_pkg(c, o))) { 614 link_mask(topology_core_cpumask, cpu, i); 615 616 /* 617 * Does this new cpu bringup a new core? 618 */ 619 if (threads == 1) { 620 /* 621 * for each core in package, increment 622 * the booted_cores for this new cpu 623 */ 624 if (cpumask_first( 625 topology_sibling_cpumask(i)) == i) 626 c->booted_cores++; 627 /* 628 * increment the core count for all 629 * the other cpus in this package 630 */ 631 if (i != cpu) 632 cpu_data(i).booted_cores++; 633 } else if (i != cpu && !c->booted_cores) 634 c->booted_cores = cpu_data(i).booted_cores; 635 } 636 } 637 } 638 639 /* maps the cpu to the sched domain representing multi-core */ 640 const struct cpumask *cpu_coregroup_mask(int cpu) 641 { 642 return cpu_llc_shared_mask(cpu); 643 } 644 645 const struct cpumask *cpu_clustergroup_mask(int cpu) 646 { 647 return cpu_l2c_shared_mask(cpu); 648 } 649 EXPORT_SYMBOL_GPL(cpu_clustergroup_mask); 650 651 static void impress_friends(void) 652 { 653 int cpu; 654 unsigned long bogosum = 0; 655 /* 656 * Allow the user to impress friends. 657 */ 658 pr_debug("Before bogomips\n"); 659 for_each_online_cpu(cpu) 660 bogosum += cpu_data(cpu).loops_per_jiffy; 661 662 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 663 num_online_cpus(), 664 bogosum/(500000/HZ), 665 (bogosum/(5000/HZ))%100); 666 667 pr_debug("Before bogocount - setting activated=1\n"); 668 } 669 670 /* 671 * The Multiprocessor Specification 1.4 (1997) example code suggests 672 * that there should be a 10ms delay between the BSP asserting INIT 673 * and de-asserting INIT, when starting a remote processor. 674 * But that slows boot and resume on modern processors, which include 675 * many cores and don't require that delay. 676 * 677 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 678 * Modern processor families are quirked to remove the delay entirely. 679 */ 680 #define UDELAY_10MS_DEFAULT 10000 681 682 static unsigned int init_udelay = UINT_MAX; 683 684 static int __init cpu_init_udelay(char *str) 685 { 686 get_option(&str, &init_udelay); 687 688 return 0; 689 } 690 early_param("cpu_init_udelay", cpu_init_udelay); 691 692 static void __init smp_quirk_init_udelay(void) 693 { 694 /* if cmdline changed it from default, leave it alone */ 695 if (init_udelay != UINT_MAX) 696 return; 697 698 /* if modern processor, use no delay */ 699 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 700 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || 701 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 702 init_udelay = 0; 703 return; 704 } 705 /* else, use legacy delay */ 706 init_udelay = UDELAY_10MS_DEFAULT; 707 } 708 709 /* 710 * Wake up AP by INIT, INIT, STARTUP sequence. 711 */ 712 static void send_init_sequence(u32 phys_apicid) 713 { 714 int maxlvt = lapic_get_maxlvt(); 715 716 /* Be paranoid about clearing APIC errors. */ 717 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 718 /* Due to the Pentium erratum 3AP. */ 719 if (maxlvt > 3) 720 apic_write(APIC_ESR, 0); 721 apic_read(APIC_ESR); 722 } 723 724 /* Assert INIT on the target CPU */ 725 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, phys_apicid); 726 safe_apic_wait_icr_idle(); 727 728 udelay(init_udelay); 729 730 /* Deassert INIT on the target CPU */ 731 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 732 safe_apic_wait_icr_idle(); 733 } 734 735 /* 736 * Wake up AP by INIT, INIT, STARTUP sequence. 737 */ 738 static int wakeup_secondary_cpu_via_init(u32 phys_apicid, unsigned long start_eip) 739 { 740 unsigned long send_status = 0, accept_status = 0; 741 int num_starts, j, maxlvt; 742 743 preempt_disable(); 744 maxlvt = lapic_get_maxlvt(); 745 send_init_sequence(phys_apicid); 746 747 mb(); 748 749 /* 750 * Should we send STARTUP IPIs ? 751 * 752 * Determine this based on the APIC version. 753 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 754 */ 755 if (APIC_INTEGRATED(boot_cpu_apic_version)) 756 num_starts = 2; 757 else 758 num_starts = 0; 759 760 /* 761 * Run STARTUP IPI loop. 762 */ 763 pr_debug("#startup loops: %d\n", num_starts); 764 765 for (j = 1; j <= num_starts; j++) { 766 pr_debug("Sending STARTUP #%d\n", j); 767 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 768 apic_write(APIC_ESR, 0); 769 apic_read(APIC_ESR); 770 pr_debug("After apic_write\n"); 771 772 /* 773 * STARTUP IPI 774 */ 775 776 /* Target chip */ 777 /* Boot on the stack */ 778 /* Kick the second */ 779 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 780 phys_apicid); 781 782 /* 783 * Give the other CPU some time to accept the IPI. 784 */ 785 if (init_udelay == 0) 786 udelay(10); 787 else 788 udelay(300); 789 790 pr_debug("Startup point 1\n"); 791 792 pr_debug("Waiting for send to finish...\n"); 793 send_status = safe_apic_wait_icr_idle(); 794 795 /* 796 * Give the other CPU some time to accept the IPI. 797 */ 798 if (init_udelay == 0) 799 udelay(10); 800 else 801 udelay(200); 802 803 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 804 apic_write(APIC_ESR, 0); 805 accept_status = (apic_read(APIC_ESR) & 0xEF); 806 if (send_status || accept_status) 807 break; 808 } 809 pr_debug("After Startup\n"); 810 811 if (send_status) 812 pr_err("APIC never delivered???\n"); 813 if (accept_status) 814 pr_err("APIC delivery error (%lx)\n", accept_status); 815 816 preempt_enable(); 817 return (send_status | accept_status); 818 } 819 820 /* reduce the number of lines printed when booting a large cpu count system */ 821 static void announce_cpu(int cpu, int apicid) 822 { 823 static int width, node_width, first = 1; 824 static int current_node = NUMA_NO_NODE; 825 int node = early_cpu_to_node(cpu); 826 827 if (!width) 828 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 829 830 if (!node_width) 831 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 832 833 if (system_state < SYSTEM_RUNNING) { 834 if (first) 835 pr_info("x86: Booting SMP configuration:\n"); 836 837 if (node != current_node) { 838 if (current_node > (-1)) 839 pr_cont("\n"); 840 current_node = node; 841 842 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 843 node_width - num_digits(node), " ", node); 844 } 845 846 /* Add padding for the BSP */ 847 if (first) 848 pr_cont("%*s", width + 1, " "); 849 first = 0; 850 851 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 852 } else 853 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 854 node, cpu, apicid); 855 } 856 857 int common_cpu_up(unsigned int cpu, struct task_struct *idle) 858 { 859 int ret; 860 861 /* Just in case we booted with a single CPU. */ 862 alternatives_enable_smp(); 863 864 per_cpu(pcpu_hot.current_task, cpu) = idle; 865 cpu_init_stack_canary(cpu, idle); 866 867 /* Initialize the interrupt stack(s) */ 868 ret = irq_init_percpu_irqstack(cpu); 869 if (ret) 870 return ret; 871 872 #ifdef CONFIG_X86_32 873 /* Stack for startup_32 can be just as for start_secondary onwards */ 874 per_cpu(pcpu_hot.top_of_stack, cpu) = task_top_of_stack(idle); 875 #endif 876 return 0; 877 } 878 879 /* 880 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 881 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 882 * Returns zero if startup was successfully sent, else error code from 883 * ->wakeup_secondary_cpu. 884 */ 885 static int do_boot_cpu(u32 apicid, int cpu, struct task_struct *idle) 886 { 887 unsigned long start_ip = real_mode_header->trampoline_start; 888 int ret; 889 890 #ifdef CONFIG_X86_64 891 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */ 892 if (apic->wakeup_secondary_cpu_64) 893 start_ip = real_mode_header->trampoline_start64; 894 #endif 895 idle->thread.sp = (unsigned long)task_pt_regs(idle); 896 initial_code = (unsigned long)start_secondary; 897 898 if (IS_ENABLED(CONFIG_X86_32)) { 899 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 900 initial_stack = idle->thread.sp; 901 } else if (!(smpboot_control & STARTUP_PARALLEL_MASK)) { 902 smpboot_control = cpu; 903 } 904 905 /* Enable the espfix hack for this CPU */ 906 init_espfix_ap(cpu); 907 908 /* So we see what's up */ 909 announce_cpu(cpu, apicid); 910 911 /* 912 * This grunge runs the startup process for 913 * the targeted processor. 914 */ 915 if (x86_platform.legacy.warm_reset) { 916 917 pr_debug("Setting warm reset code and vector.\n"); 918 919 smpboot_setup_warm_reset_vector(start_ip); 920 /* 921 * Be paranoid about clearing APIC errors. 922 */ 923 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 924 apic_write(APIC_ESR, 0); 925 apic_read(APIC_ESR); 926 } 927 } 928 929 smp_mb(); 930 931 /* 932 * Wake up a CPU in difference cases: 933 * - Use a method from the APIC driver if one defined, with wakeup 934 * straight to 64-bit mode preferred over wakeup to RM. 935 * Otherwise, 936 * - Use an INIT boot APIC message 937 */ 938 if (apic->wakeup_secondary_cpu_64) 939 ret = apic->wakeup_secondary_cpu_64(apicid, start_ip); 940 else if (apic->wakeup_secondary_cpu) 941 ret = apic->wakeup_secondary_cpu(apicid, start_ip); 942 else 943 ret = wakeup_secondary_cpu_via_init(apicid, start_ip); 944 945 /* If the wakeup mechanism failed, cleanup the warm reset vector */ 946 if (ret) 947 arch_cpuhp_cleanup_kick_cpu(cpu); 948 return ret; 949 } 950 951 int native_kick_ap(unsigned int cpu, struct task_struct *tidle) 952 { 953 u32 apicid = apic->cpu_present_to_apicid(cpu); 954 int err; 955 956 lockdep_assert_irqs_enabled(); 957 958 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 959 960 if (apicid == BAD_APICID || !apic_id_valid(apicid)) { 961 pr_err("CPU %u has invalid APIC ID %x. Aborting bringup\n", cpu, apicid); 962 return -EINVAL; 963 } 964 965 if (!test_bit(apicid, phys_cpu_present_map)) { 966 pr_err("CPU %u APIC ID %x is not present. Aborting bringup\n", cpu, apicid); 967 return -EINVAL; 968 } 969 970 /* 971 * Save current MTRR state in case it was changed since early boot 972 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 973 */ 974 mtrr_save_state(); 975 976 /* the FPU context is blank, nobody can own it */ 977 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 978 979 err = common_cpu_up(cpu, tidle); 980 if (err) 981 return err; 982 983 err = do_boot_cpu(apicid, cpu, tidle); 984 if (err) 985 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 986 987 return err; 988 } 989 990 int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *tidle) 991 { 992 return smp_ops.kick_ap_alive(cpu, tidle); 993 } 994 995 void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu) 996 { 997 /* Cleanup possible dangling ends... */ 998 if (smp_ops.kick_ap_alive == native_kick_ap && x86_platform.legacy.warm_reset) 999 smpboot_restore_warm_reset_vector(); 1000 } 1001 1002 void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu) 1003 { 1004 if (smp_ops.cleanup_dead_cpu) 1005 smp_ops.cleanup_dead_cpu(cpu); 1006 1007 if (system_state == SYSTEM_RUNNING) 1008 pr_info("CPU %u is now offline\n", cpu); 1009 } 1010 1011 void arch_cpuhp_sync_state_poll(void) 1012 { 1013 if (smp_ops.poll_sync_state) 1014 smp_ops.poll_sync_state(); 1015 } 1016 1017 /** 1018 * arch_disable_smp_support() - Disables SMP support for x86 at boottime 1019 */ 1020 void __init arch_disable_smp_support(void) 1021 { 1022 disable_ioapic_support(); 1023 } 1024 1025 /* 1026 * Fall back to non SMP mode after errors. 1027 * 1028 * RED-PEN audit/test this more. I bet there is more state messed up here. 1029 */ 1030 static __init void disable_smp(void) 1031 { 1032 pr_info("SMP disabled\n"); 1033 1034 disable_ioapic_support(); 1035 topology_reset_possible_cpus_up(); 1036 1037 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1038 cpumask_set_cpu(0, topology_core_cpumask(0)); 1039 cpumask_set_cpu(0, topology_die_cpumask(0)); 1040 } 1041 1042 static void __init smp_cpu_index_default(void) 1043 { 1044 int i; 1045 struct cpuinfo_x86 *c; 1046 1047 for_each_possible_cpu(i) { 1048 c = &cpu_data(i); 1049 /* mark all to hotplug */ 1050 c->cpu_index = nr_cpu_ids; 1051 } 1052 } 1053 1054 void __init smp_prepare_cpus_common(void) 1055 { 1056 unsigned int i; 1057 1058 smp_cpu_index_default(); 1059 1060 /* 1061 * Setup boot CPU information 1062 */ 1063 smp_store_boot_cpu_info(); /* Final full version of the data */ 1064 mb(); 1065 1066 for_each_possible_cpu(i) { 1067 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1068 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1069 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL); 1070 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1071 zalloc_cpumask_var(&per_cpu(cpu_l2c_shared_map, i), GFP_KERNEL); 1072 } 1073 1074 set_cpu_sibling_map(0); 1075 } 1076 1077 void __init smp_prepare_boot_cpu(void) 1078 { 1079 smp_ops.smp_prepare_boot_cpu(); 1080 } 1081 1082 #ifdef CONFIG_X86_64 1083 /* Establish whether parallel bringup can be supported. */ 1084 bool __init arch_cpuhp_init_parallel_bringup(void) 1085 { 1086 if (!x86_cpuinit.parallel_bringup) { 1087 pr_info("Parallel CPU startup disabled by the platform\n"); 1088 return false; 1089 } 1090 1091 smpboot_control = STARTUP_READ_APICID; 1092 pr_debug("Parallel CPU startup enabled: 0x%08x\n", smpboot_control); 1093 return true; 1094 } 1095 #endif 1096 1097 /* 1098 * Prepare for SMP bootup. 1099 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1100 * for common interface support. 1101 */ 1102 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1103 { 1104 smp_prepare_cpus_common(); 1105 1106 switch (apic_intr_mode) { 1107 case APIC_PIC: 1108 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1109 disable_smp(); 1110 return; 1111 case APIC_SYMMETRIC_IO_NO_ROUTING: 1112 disable_smp(); 1113 /* Setup local timer */ 1114 x86_init.timers.setup_percpu_clockev(); 1115 return; 1116 case APIC_VIRTUAL_WIRE: 1117 case APIC_SYMMETRIC_IO: 1118 break; 1119 } 1120 1121 /* Setup local timer */ 1122 x86_init.timers.setup_percpu_clockev(); 1123 1124 pr_info("CPU0: "); 1125 print_cpu_info(&cpu_data(0)); 1126 1127 uv_system_init(); 1128 1129 smp_quirk_init_udelay(); 1130 1131 speculative_store_bypass_ht_init(); 1132 1133 snp_set_wakeup_secondary_cpu(); 1134 } 1135 1136 void arch_thaw_secondary_cpus_begin(void) 1137 { 1138 set_cache_aps_delayed_init(true); 1139 } 1140 1141 void arch_thaw_secondary_cpus_end(void) 1142 { 1143 cache_aps_init(); 1144 } 1145 1146 /* 1147 * Early setup to make printk work. 1148 */ 1149 void __init native_smp_prepare_boot_cpu(void) 1150 { 1151 int me = smp_processor_id(); 1152 1153 /* SMP handles this from setup_per_cpu_areas() */ 1154 if (!IS_ENABLED(CONFIG_SMP)) 1155 switch_gdt_and_percpu_base(me); 1156 1157 native_pv_lock_init(); 1158 } 1159 1160 void __init native_smp_cpus_done(unsigned int max_cpus) 1161 { 1162 pr_debug("Boot done\n"); 1163 1164 build_sched_topology(); 1165 nmi_selftest(); 1166 impress_friends(); 1167 cache_aps_init(); 1168 } 1169 1170 /* correctly size the local cpu masks */ 1171 void __init setup_cpu_local_masks(void) 1172 { 1173 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 1174 } 1175 1176 #ifdef CONFIG_HOTPLUG_CPU 1177 1178 /* Recompute SMT state for all CPUs on offline */ 1179 static void recompute_smt_state(void) 1180 { 1181 int max_threads, cpu; 1182 1183 max_threads = 0; 1184 for_each_online_cpu (cpu) { 1185 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1186 1187 if (threads > max_threads) 1188 max_threads = threads; 1189 } 1190 __max_smt_threads = max_threads; 1191 } 1192 1193 static void remove_siblinginfo(int cpu) 1194 { 1195 int sibling; 1196 struct cpuinfo_x86 *c = &cpu_data(cpu); 1197 1198 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1199 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1200 /*/ 1201 * last thread sibling in this cpu core going down 1202 */ 1203 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1204 cpu_data(sibling).booted_cores--; 1205 } 1206 1207 for_each_cpu(sibling, topology_die_cpumask(cpu)) 1208 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling)); 1209 1210 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) { 1211 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1212 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1) 1213 cpu_data(sibling).smt_active = false; 1214 } 1215 1216 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1217 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1218 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu)) 1219 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling)); 1220 cpumask_clear(cpu_llc_shared_mask(cpu)); 1221 cpumask_clear(cpu_l2c_shared_mask(cpu)); 1222 cpumask_clear(topology_sibling_cpumask(cpu)); 1223 cpumask_clear(topology_core_cpumask(cpu)); 1224 cpumask_clear(topology_die_cpumask(cpu)); 1225 c->topo.core_id = 0; 1226 c->booted_cores = 0; 1227 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1228 recompute_smt_state(); 1229 } 1230 1231 static void remove_cpu_from_maps(int cpu) 1232 { 1233 set_cpu_online(cpu, false); 1234 numa_remove_cpu(cpu); 1235 } 1236 1237 void cpu_disable_common(void) 1238 { 1239 int cpu = smp_processor_id(); 1240 1241 remove_siblinginfo(cpu); 1242 1243 /* It's now safe to remove this processor from the online map */ 1244 lock_vector_lock(); 1245 remove_cpu_from_maps(cpu); 1246 unlock_vector_lock(); 1247 fixup_irqs(); 1248 lapic_offline(); 1249 } 1250 1251 int native_cpu_disable(void) 1252 { 1253 int ret; 1254 1255 ret = lapic_can_unplug_cpu(); 1256 if (ret) 1257 return ret; 1258 1259 cpu_disable_common(); 1260 1261 /* 1262 * Disable the local APIC. Otherwise IPI broadcasts will reach 1263 * it. It still responds normally to INIT, NMI, SMI, and SIPI 1264 * messages. 1265 * 1266 * Disabling the APIC must happen after cpu_disable_common() 1267 * which invokes fixup_irqs(). 1268 * 1269 * Disabling the APIC preserves already set bits in IRR, but 1270 * an interrupt arriving after disabling the local APIC does not 1271 * set the corresponding IRR bit. 1272 * 1273 * fixup_irqs() scans IRR for set bits so it can raise a not 1274 * yet handled interrupt on the new destination CPU via an IPI 1275 * but obviously it can't do so for IRR bits which are not set. 1276 * IOW, interrupts arriving after disabling the local APIC will 1277 * be lost. 1278 */ 1279 apic_soft_disable(); 1280 1281 return 0; 1282 } 1283 1284 void play_dead_common(void) 1285 { 1286 idle_task_exit(); 1287 1288 cpuhp_ap_report_dead(); 1289 1290 local_irq_disable(); 1291 } 1292 1293 /* 1294 * We need to flush the caches before going to sleep, lest we have 1295 * dirty data in our caches when we come back up. 1296 */ 1297 static inline void mwait_play_dead(void) 1298 { 1299 struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead); 1300 unsigned int eax, ebx, ecx, edx; 1301 unsigned int highest_cstate = 0; 1302 unsigned int highest_subcstate = 0; 1303 int i; 1304 1305 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1306 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 1307 return; 1308 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1309 return; 1310 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1311 return; 1312 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1313 return; 1314 1315 eax = CPUID_MWAIT_LEAF; 1316 ecx = 0; 1317 native_cpuid(&eax, &ebx, &ecx, &edx); 1318 1319 /* 1320 * eax will be 0 if EDX enumeration is not valid. 1321 * Initialized below to cstate, sub_cstate value when EDX is valid. 1322 */ 1323 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1324 eax = 0; 1325 } else { 1326 edx >>= MWAIT_SUBSTATE_SIZE; 1327 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1328 if (edx & MWAIT_SUBSTATE_MASK) { 1329 highest_cstate = i; 1330 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1331 } 1332 } 1333 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1334 (highest_subcstate - 1); 1335 } 1336 1337 /* Set up state for the kexec() hack below */ 1338 md->status = CPUDEAD_MWAIT_WAIT; 1339 md->control = CPUDEAD_MWAIT_WAIT; 1340 1341 wbinvd(); 1342 1343 while (1) { 1344 /* 1345 * The CLFLUSH is a workaround for erratum AAI65 for 1346 * the Xeon 7400 series. It's not clear it is actually 1347 * needed, but it should be harmless in either case. 1348 * The WBINVD is insufficient due to the spurious-wakeup 1349 * case where we return around the loop. 1350 */ 1351 mb(); 1352 clflush(md); 1353 mb(); 1354 __monitor(md, 0, 0); 1355 mb(); 1356 __mwait(eax, 0); 1357 1358 if (READ_ONCE(md->control) == CPUDEAD_MWAIT_KEXEC_HLT) { 1359 /* 1360 * Kexec is about to happen. Don't go back into mwait() as 1361 * the kexec kernel might overwrite text and data including 1362 * page tables and stack. So mwait() would resume when the 1363 * monitor cache line is written to and then the CPU goes 1364 * south due to overwritten text, page tables and stack. 1365 * 1366 * Note: This does _NOT_ protect against a stray MCE, NMI, 1367 * SMI. They will resume execution at the instruction 1368 * following the HLT instruction and run into the problem 1369 * which this is trying to prevent. 1370 */ 1371 WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT); 1372 while(1) 1373 native_halt(); 1374 } 1375 } 1376 } 1377 1378 /* 1379 * Kick all "offline" CPUs out of mwait on kexec(). See comment in 1380 * mwait_play_dead(). 1381 */ 1382 void smp_kick_mwait_play_dead(void) 1383 { 1384 u32 newstate = CPUDEAD_MWAIT_KEXEC_HLT; 1385 struct mwait_cpu_dead *md; 1386 unsigned int cpu, i; 1387 1388 for_each_cpu_andnot(cpu, cpu_present_mask, cpu_online_mask) { 1389 md = per_cpu_ptr(&mwait_cpu_dead, cpu); 1390 1391 /* Does it sit in mwait_play_dead() ? */ 1392 if (READ_ONCE(md->status) != CPUDEAD_MWAIT_WAIT) 1393 continue; 1394 1395 /* Wait up to 5ms */ 1396 for (i = 0; READ_ONCE(md->status) != newstate && i < 1000; i++) { 1397 /* Bring it out of mwait */ 1398 WRITE_ONCE(md->control, newstate); 1399 udelay(5); 1400 } 1401 1402 if (READ_ONCE(md->status) != newstate) 1403 pr_err_once("CPU%u is stuck in mwait_play_dead()\n", cpu); 1404 } 1405 } 1406 1407 void __noreturn hlt_play_dead(void) 1408 { 1409 if (__this_cpu_read(cpu_info.x86) >= 4) 1410 wbinvd(); 1411 1412 while (1) 1413 native_halt(); 1414 } 1415 1416 /* 1417 * native_play_dead() is essentially a __noreturn function, but it can't 1418 * be marked as such as the compiler may complain about it. 1419 */ 1420 void native_play_dead(void) 1421 { 1422 if (cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS)) 1423 __update_spec_ctrl(0); 1424 1425 play_dead_common(); 1426 tboot_shutdown(TB_SHUTDOWN_WFS); 1427 1428 mwait_play_dead(); 1429 if (cpuidle_play_dead()) 1430 hlt_play_dead(); 1431 } 1432 1433 #else /* ... !CONFIG_HOTPLUG_CPU */ 1434 int native_cpu_disable(void) 1435 { 1436 return -ENOSYS; 1437 } 1438 1439 void native_play_dead(void) 1440 { 1441 BUG(); 1442 } 1443 1444 #endif 1445