1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/module.h> 45 #include <linux/sched.h> 46 #include <linux/percpu.h> 47 #include <linux/bootmem.h> 48 #include <linux/err.h> 49 #include <linux/nmi.h> 50 #include <linux/tboot.h> 51 #include <linux/stackprotector.h> 52 #include <linux/gfp.h> 53 54 #include <asm/acpi.h> 55 #include <asm/desc.h> 56 #include <asm/nmi.h> 57 #include <asm/irq.h> 58 #include <asm/idle.h> 59 #include <asm/trampoline.h> 60 #include <asm/cpu.h> 61 #include <asm/numa.h> 62 #include <asm/pgtable.h> 63 #include <asm/tlbflush.h> 64 #include <asm/mtrr.h> 65 #include <asm/vmi.h> 66 #include <asm/apic.h> 67 #include <asm/setup.h> 68 #include <asm/uv/uv.h> 69 #include <linux/mc146818rtc.h> 70 71 #include <asm/smpboot_hooks.h> 72 #include <asm/i8259.h> 73 74 #ifdef CONFIG_X86_32 75 u8 apicid_2_node[MAX_APICID]; 76 #endif 77 78 /* State of each CPU */ 79 DEFINE_PER_CPU(int, cpu_state) = { 0 }; 80 81 /* Store all idle threads, this can be reused instead of creating 82 * a new thread. Also avoids complicated thread destroy functionality 83 * for idle threads. 84 */ 85 #ifdef CONFIG_HOTPLUG_CPU 86 /* 87 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is 88 * removed after init for !CONFIG_HOTPLUG_CPU. 89 */ 90 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); 91 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) 92 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) 93 94 /* 95 * We need this for trampoline_base protection from concurrent accesses when 96 * off- and onlining cores wildly. 97 */ 98 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex); 99 100 void cpu_hotplug_driver_lock() 101 { 102 mutex_lock(&x86_cpu_hotplug_driver_mutex); 103 } 104 105 void cpu_hotplug_driver_unlock() 106 { 107 mutex_unlock(&x86_cpu_hotplug_driver_mutex); 108 } 109 110 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; } 111 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; } 112 #else 113 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; 114 #define get_idle_for_cpu(x) (idle_thread_array[(x)]) 115 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) 116 #endif 117 118 /* Number of siblings per CPU package */ 119 int smp_num_siblings = 1; 120 EXPORT_SYMBOL(smp_num_siblings); 121 122 /* Last level cache ID of each logical CPU */ 123 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; 124 125 /* representing HT siblings of each logical CPU */ 126 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); 127 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 128 129 /* representing HT and core siblings of each logical CPU */ 130 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); 131 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 132 133 /* Per CPU bogomips and other parameters */ 134 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 135 EXPORT_PER_CPU_SYMBOL(cpu_info); 136 137 atomic_t init_deasserted; 138 139 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) 140 /* which node each logical CPU is on */ 141 int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; 142 EXPORT_SYMBOL(cpu_to_node_map); 143 144 /* set up a mapping between cpu and node. */ 145 static void map_cpu_to_node(int cpu, int node) 146 { 147 printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); 148 cpumask_set_cpu(cpu, node_to_cpumask_map[node]); 149 cpu_to_node_map[cpu] = node; 150 } 151 152 /* undo a mapping between cpu and node. */ 153 static void unmap_cpu_to_node(int cpu) 154 { 155 int node; 156 157 printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); 158 for (node = 0; node < MAX_NUMNODES; node++) 159 cpumask_clear_cpu(cpu, node_to_cpumask_map[node]); 160 cpu_to_node_map[cpu] = 0; 161 } 162 #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ 163 #define map_cpu_to_node(cpu, node) ({}) 164 #define unmap_cpu_to_node(cpu) ({}) 165 #endif 166 167 #ifdef CONFIG_X86_32 168 static int boot_cpu_logical_apicid; 169 170 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = 171 { [0 ... NR_CPUS-1] = BAD_APICID }; 172 173 static void map_cpu_to_logical_apicid(void) 174 { 175 int cpu = smp_processor_id(); 176 int apicid = logical_smp_processor_id(); 177 int node = apic->apicid_to_node(apicid); 178 179 if (!node_online(node)) 180 node = first_online_node; 181 182 cpu_2_logical_apicid[cpu] = apicid; 183 map_cpu_to_node(cpu, node); 184 } 185 186 void numa_remove_cpu(int cpu) 187 { 188 cpu_2_logical_apicid[cpu] = BAD_APICID; 189 unmap_cpu_to_node(cpu); 190 } 191 #else 192 #define map_cpu_to_logical_apicid() do {} while (0) 193 #endif 194 195 /* 196 * Report back to the Boot Processor. 197 * Running on AP. 198 */ 199 static void __cpuinit smp_callin(void) 200 { 201 int cpuid, phys_id; 202 unsigned long timeout; 203 204 /* 205 * If waken up by an INIT in an 82489DX configuration 206 * we may get here before an INIT-deassert IPI reaches 207 * our local APIC. We have to wait for the IPI or we'll 208 * lock up on an APIC access. 209 */ 210 if (apic->wait_for_init_deassert) 211 apic->wait_for_init_deassert(&init_deasserted); 212 213 /* 214 * (This works even if the APIC is not enabled.) 215 */ 216 phys_id = read_apic_id(); 217 cpuid = smp_processor_id(); 218 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { 219 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, 220 phys_id, cpuid); 221 } 222 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); 223 224 /* 225 * STARTUP IPIs are fragile beasts as they might sometimes 226 * trigger some glue motherboard logic. Complete APIC bus 227 * silence for 1 second, this overestimates the time the 228 * boot CPU is spending to send the up to 2 STARTUP IPIs 229 * by a factor of two. This should be enough. 230 */ 231 232 /* 233 * Waiting 2s total for startup (udelay is not yet working) 234 */ 235 timeout = jiffies + 2*HZ; 236 while (time_before(jiffies, timeout)) { 237 /* 238 * Has the boot CPU finished it's STARTUP sequence? 239 */ 240 if (cpumask_test_cpu(cpuid, cpu_callout_mask)) 241 break; 242 cpu_relax(); 243 } 244 245 if (!time_before(jiffies, timeout)) { 246 panic("%s: CPU%d started up but did not get a callout!\n", 247 __func__, cpuid); 248 } 249 250 /* 251 * the boot CPU has finished the init stage and is spinning 252 * on callin_map until we finish. We are free to set up this 253 * CPU, first the APIC. (this is probably redundant on most 254 * boards) 255 */ 256 257 pr_debug("CALLIN, before setup_local_APIC().\n"); 258 if (apic->smp_callin_clear_local_apic) 259 apic->smp_callin_clear_local_apic(); 260 setup_local_APIC(); 261 end_local_APIC_setup(); 262 map_cpu_to_logical_apicid(); 263 264 /* 265 * Need to setup vector mappings before we enable interrupts. 266 */ 267 setup_vector_irq(smp_processor_id()); 268 /* 269 * Get our bogomips. 270 * 271 * Need to enable IRQs because it can take longer and then 272 * the NMI watchdog might kill us. 273 */ 274 local_irq_enable(); 275 calibrate_delay(); 276 local_irq_disable(); 277 pr_debug("Stack at about %p\n", &cpuid); 278 279 /* 280 * Save our processor parameters 281 */ 282 smp_store_cpu_info(cpuid); 283 284 notify_cpu_starting(cpuid); 285 286 /* 287 * Allow the master to continue. 288 */ 289 cpumask_set_cpu(cpuid, cpu_callin_mask); 290 } 291 292 /* 293 * Activate a secondary processor. 294 */ 295 notrace static void __cpuinit start_secondary(void *unused) 296 { 297 /* 298 * Don't put *anything* before cpu_init(), SMP booting is too 299 * fragile that we want to limit the things done here to the 300 * most necessary things. 301 */ 302 303 #ifdef CONFIG_X86_32 304 /* 305 * Switch away from the trampoline page-table 306 * 307 * Do this before cpu_init() because it needs to access per-cpu 308 * data which may not be mapped in the trampoline page-table. 309 */ 310 load_cr3(swapper_pg_dir); 311 __flush_tlb_all(); 312 #endif 313 314 vmi_bringup(); 315 cpu_init(); 316 preempt_disable(); 317 smp_callin(); 318 319 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 320 barrier(); 321 /* 322 * Check TSC synchronization with the BP: 323 */ 324 check_tsc_sync_target(); 325 326 if (nmi_watchdog == NMI_IO_APIC) { 327 legacy_pic->chip->mask(0); 328 enable_NMI_through_LVT0(); 329 legacy_pic->chip->unmask(0); 330 } 331 332 /* This must be done before setting cpu_online_mask */ 333 set_cpu_sibling_map(raw_smp_processor_id()); 334 wmb(); 335 336 /* 337 * We need to hold call_lock, so there is no inconsistency 338 * between the time smp_call_function() determines number of 339 * IPI recipients, and the time when the determination is made 340 * for which cpus receive the IPI. Holding this 341 * lock helps us to not include this cpu in a currently in progress 342 * smp_call_function(). 343 * 344 * We need to hold vector_lock so there the set of online cpus 345 * does not change while we are assigning vectors to cpus. Holding 346 * this lock ensures we don't half assign or remove an irq from a cpu. 347 */ 348 ipi_call_lock(); 349 lock_vector_lock(); 350 set_cpu_online(smp_processor_id(), true); 351 unlock_vector_lock(); 352 ipi_call_unlock(); 353 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; 354 x86_platform.nmi_init(); 355 356 /* enable local interrupts */ 357 local_irq_enable(); 358 359 /* to prevent fake stack check failure in clock setup */ 360 boot_init_stack_canary(); 361 362 x86_cpuinit.setup_percpu_clockev(); 363 364 wmb(); 365 cpu_idle(); 366 } 367 368 #ifdef CONFIG_CPUMASK_OFFSTACK 369 /* In this case, llc_shared_map is a pointer to a cpumask. */ 370 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, 371 const struct cpuinfo_x86 *src) 372 { 373 struct cpumask *llc = dst->llc_shared_map; 374 *dst = *src; 375 dst->llc_shared_map = llc; 376 } 377 #else 378 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, 379 const struct cpuinfo_x86 *src) 380 { 381 *dst = *src; 382 } 383 #endif /* CONFIG_CPUMASK_OFFSTACK */ 384 385 /* 386 * The bootstrap kernel entry code has set these up. Save them for 387 * a given CPU 388 */ 389 390 void __cpuinit smp_store_cpu_info(int id) 391 { 392 struct cpuinfo_x86 *c = &cpu_data(id); 393 394 copy_cpuinfo_x86(c, &boot_cpu_data); 395 c->cpu_index = id; 396 if (id != 0) 397 identify_secondary_cpu(c); 398 } 399 400 401 void __cpuinit set_cpu_sibling_map(int cpu) 402 { 403 int i; 404 struct cpuinfo_x86 *c = &cpu_data(cpu); 405 406 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 407 408 if (smp_num_siblings > 1) { 409 for_each_cpu(i, cpu_sibling_setup_mask) { 410 struct cpuinfo_x86 *o = &cpu_data(i); 411 412 if (c->phys_proc_id == o->phys_proc_id && 413 c->cpu_core_id == o->cpu_core_id) { 414 cpumask_set_cpu(i, cpu_sibling_mask(cpu)); 415 cpumask_set_cpu(cpu, cpu_sibling_mask(i)); 416 cpumask_set_cpu(i, cpu_core_mask(cpu)); 417 cpumask_set_cpu(cpu, cpu_core_mask(i)); 418 cpumask_set_cpu(i, c->llc_shared_map); 419 cpumask_set_cpu(cpu, o->llc_shared_map); 420 } 421 } 422 } else { 423 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); 424 } 425 426 cpumask_set_cpu(cpu, c->llc_shared_map); 427 428 if (current_cpu_data.x86_max_cores == 1) { 429 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); 430 c->booted_cores = 1; 431 return; 432 } 433 434 for_each_cpu(i, cpu_sibling_setup_mask) { 435 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && 436 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { 437 cpumask_set_cpu(i, c->llc_shared_map); 438 cpumask_set_cpu(cpu, cpu_data(i).llc_shared_map); 439 } 440 if (c->phys_proc_id == cpu_data(i).phys_proc_id) { 441 cpumask_set_cpu(i, cpu_core_mask(cpu)); 442 cpumask_set_cpu(cpu, cpu_core_mask(i)); 443 /* 444 * Does this new cpu bringup a new core? 445 */ 446 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { 447 /* 448 * for each core in package, increment 449 * the booted_cores for this new cpu 450 */ 451 if (cpumask_first(cpu_sibling_mask(i)) == i) 452 c->booted_cores++; 453 /* 454 * increment the core count for all 455 * the other cpus in this package 456 */ 457 if (i != cpu) 458 cpu_data(i).booted_cores++; 459 } else if (i != cpu && !c->booted_cores) 460 c->booted_cores = cpu_data(i).booted_cores; 461 } 462 } 463 } 464 465 /* maps the cpu to the sched domain representing multi-core */ 466 const struct cpumask *cpu_coregroup_mask(int cpu) 467 { 468 struct cpuinfo_x86 *c = &cpu_data(cpu); 469 /* 470 * For perf, we return last level cache shared map. 471 * And for power savings, we return cpu_core_map 472 */ 473 if ((sched_mc_power_savings || sched_smt_power_savings) && 474 !(cpu_has(c, X86_FEATURE_AMD_DCM))) 475 return cpu_core_mask(cpu); 476 else 477 return c->llc_shared_map; 478 } 479 480 static void impress_friends(void) 481 { 482 int cpu; 483 unsigned long bogosum = 0; 484 /* 485 * Allow the user to impress friends. 486 */ 487 pr_debug("Before bogomips.\n"); 488 for_each_possible_cpu(cpu) 489 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 490 bogosum += cpu_data(cpu).loops_per_jiffy; 491 printk(KERN_INFO 492 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", 493 num_online_cpus(), 494 bogosum/(500000/HZ), 495 (bogosum/(5000/HZ))%100); 496 497 pr_debug("Before bogocount - setting activated=1.\n"); 498 } 499 500 void __inquire_remote_apic(int apicid) 501 { 502 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 503 char *names[] = { "ID", "VERSION", "SPIV" }; 504 int timeout; 505 u32 status; 506 507 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); 508 509 for (i = 0; i < ARRAY_SIZE(regs); i++) { 510 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); 511 512 /* 513 * Wait for idle. 514 */ 515 status = safe_apic_wait_icr_idle(); 516 if (status) 517 printk(KERN_CONT 518 "a previous APIC delivery may have failed\n"); 519 520 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 521 522 timeout = 0; 523 do { 524 udelay(100); 525 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 526 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 527 528 switch (status) { 529 case APIC_ICR_RR_VALID: 530 status = apic_read(APIC_RRR); 531 printk(KERN_CONT "%08x\n", status); 532 break; 533 default: 534 printk(KERN_CONT "failed\n"); 535 } 536 } 537 } 538 539 /* 540 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 541 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 542 * won't ... remember to clear down the APIC, etc later. 543 */ 544 int __cpuinit 545 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) 546 { 547 unsigned long send_status, accept_status = 0; 548 int maxlvt; 549 550 /* Target chip */ 551 /* Boot on the stack */ 552 /* Kick the second */ 553 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); 554 555 pr_debug("Waiting for send to finish...\n"); 556 send_status = safe_apic_wait_icr_idle(); 557 558 /* 559 * Give the other CPU some time to accept the IPI. 560 */ 561 udelay(200); 562 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 563 maxlvt = lapic_get_maxlvt(); 564 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 565 apic_write(APIC_ESR, 0); 566 accept_status = (apic_read(APIC_ESR) & 0xEF); 567 } 568 pr_debug("NMI sent.\n"); 569 570 if (send_status) 571 printk(KERN_ERR "APIC never delivered???\n"); 572 if (accept_status) 573 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 574 575 return (send_status | accept_status); 576 } 577 578 static int __cpuinit 579 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 580 { 581 unsigned long send_status, accept_status = 0; 582 int maxlvt, num_starts, j; 583 584 maxlvt = lapic_get_maxlvt(); 585 586 /* 587 * Be paranoid about clearing APIC errors. 588 */ 589 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 590 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 591 apic_write(APIC_ESR, 0); 592 apic_read(APIC_ESR); 593 } 594 595 pr_debug("Asserting INIT.\n"); 596 597 /* 598 * Turn INIT on target chip 599 */ 600 /* 601 * Send IPI 602 */ 603 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 604 phys_apicid); 605 606 pr_debug("Waiting for send to finish...\n"); 607 send_status = safe_apic_wait_icr_idle(); 608 609 mdelay(10); 610 611 pr_debug("Deasserting INIT.\n"); 612 613 /* Target chip */ 614 /* Send IPI */ 615 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 616 617 pr_debug("Waiting for send to finish...\n"); 618 send_status = safe_apic_wait_icr_idle(); 619 620 mb(); 621 atomic_set(&init_deasserted, 1); 622 623 /* 624 * Should we send STARTUP IPIs ? 625 * 626 * Determine this based on the APIC version. 627 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 628 */ 629 if (APIC_INTEGRATED(apic_version[phys_apicid])) 630 num_starts = 2; 631 else 632 num_starts = 0; 633 634 /* 635 * Paravirt / VMI wants a startup IPI hook here to set up the 636 * target processor state. 637 */ 638 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, 639 (unsigned long)stack_start.sp); 640 641 /* 642 * Run STARTUP IPI loop. 643 */ 644 pr_debug("#startup loops: %d.\n", num_starts); 645 646 for (j = 1; j <= num_starts; j++) { 647 pr_debug("Sending STARTUP #%d.\n", j); 648 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 649 apic_write(APIC_ESR, 0); 650 apic_read(APIC_ESR); 651 pr_debug("After apic_write.\n"); 652 653 /* 654 * STARTUP IPI 655 */ 656 657 /* Target chip */ 658 /* Boot on the stack */ 659 /* Kick the second */ 660 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 661 phys_apicid); 662 663 /* 664 * Give the other CPU some time to accept the IPI. 665 */ 666 udelay(300); 667 668 pr_debug("Startup point 1.\n"); 669 670 pr_debug("Waiting for send to finish...\n"); 671 send_status = safe_apic_wait_icr_idle(); 672 673 /* 674 * Give the other CPU some time to accept the IPI. 675 */ 676 udelay(200); 677 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 678 apic_write(APIC_ESR, 0); 679 accept_status = (apic_read(APIC_ESR) & 0xEF); 680 if (send_status || accept_status) 681 break; 682 } 683 pr_debug("After Startup.\n"); 684 685 if (send_status) 686 printk(KERN_ERR "APIC never delivered???\n"); 687 if (accept_status) 688 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 689 690 return (send_status | accept_status); 691 } 692 693 struct create_idle { 694 struct work_struct work; 695 struct task_struct *idle; 696 struct completion done; 697 int cpu; 698 }; 699 700 static void __cpuinit do_fork_idle(struct work_struct *work) 701 { 702 struct create_idle *c_idle = 703 container_of(work, struct create_idle, work); 704 705 c_idle->idle = fork_idle(c_idle->cpu); 706 complete(&c_idle->done); 707 } 708 709 /* reduce the number of lines printed when booting a large cpu count system */ 710 static void __cpuinit announce_cpu(int cpu, int apicid) 711 { 712 static int current_node = -1; 713 int node = early_cpu_to_node(cpu); 714 715 if (system_state == SYSTEM_BOOTING) { 716 if (node != current_node) { 717 if (current_node > (-1)) 718 pr_cont(" Ok.\n"); 719 current_node = node; 720 pr_info("Booting Node %3d, Processors ", node); 721 } 722 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : ""); 723 return; 724 } else 725 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 726 node, cpu, apicid); 727 } 728 729 /* 730 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 731 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 732 * Returns zero if CPU booted OK, else error code from 733 * ->wakeup_secondary_cpu. 734 */ 735 static int __cpuinit do_boot_cpu(int apicid, int cpu) 736 { 737 unsigned long boot_error = 0; 738 unsigned long start_ip; 739 int timeout; 740 struct create_idle c_idle = { 741 .cpu = cpu, 742 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), 743 }; 744 745 INIT_WORK_ON_STACK(&c_idle.work, do_fork_idle); 746 747 alternatives_smp_switch(1); 748 749 c_idle.idle = get_idle_for_cpu(cpu); 750 751 /* 752 * We can't use kernel_thread since we must avoid to 753 * reschedule the child. 754 */ 755 if (c_idle.idle) { 756 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) 757 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); 758 init_idle(c_idle.idle, cpu); 759 goto do_rest; 760 } 761 762 schedule_work(&c_idle.work); 763 wait_for_completion(&c_idle.done); 764 765 if (IS_ERR(c_idle.idle)) { 766 printk("failed fork for CPU %d\n", cpu); 767 destroy_work_on_stack(&c_idle.work); 768 return PTR_ERR(c_idle.idle); 769 } 770 771 set_idle_for_cpu(cpu, c_idle.idle); 772 do_rest: 773 per_cpu(current_task, cpu) = c_idle.idle; 774 #ifdef CONFIG_X86_32 775 /* Stack for startup_32 can be just as for start_secondary onwards */ 776 irq_ctx_init(cpu); 777 initial_page_table = __pa(&trampoline_pg_dir); 778 #else 779 clear_tsk_thread_flag(c_idle.idle, TIF_FORK); 780 initial_gs = per_cpu_offset(cpu); 781 per_cpu(kernel_stack, cpu) = 782 (unsigned long)task_stack_page(c_idle.idle) - 783 KERNEL_STACK_OFFSET + THREAD_SIZE; 784 #endif 785 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 786 initial_code = (unsigned long)start_secondary; 787 stack_start.sp = (void *) c_idle.idle->thread.sp; 788 789 /* start_ip had better be page-aligned! */ 790 start_ip = setup_trampoline(); 791 792 /* So we see what's up */ 793 announce_cpu(cpu, apicid); 794 795 /* 796 * This grunge runs the startup process for 797 * the targeted processor. 798 */ 799 800 atomic_set(&init_deasserted, 0); 801 802 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 803 804 pr_debug("Setting warm reset code and vector.\n"); 805 806 smpboot_setup_warm_reset_vector(start_ip); 807 /* 808 * Be paranoid about clearing APIC errors. 809 */ 810 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 811 apic_write(APIC_ESR, 0); 812 apic_read(APIC_ESR); 813 } 814 } 815 816 /* 817 * Kick the secondary CPU. Use the method in the APIC driver 818 * if it's defined - or use an INIT boot APIC message otherwise: 819 */ 820 if (apic->wakeup_secondary_cpu) 821 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 822 else 823 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 824 825 if (!boot_error) { 826 /* 827 * allow APs to start initializing. 828 */ 829 pr_debug("Before Callout %d.\n", cpu); 830 cpumask_set_cpu(cpu, cpu_callout_mask); 831 pr_debug("After Callout %d.\n", cpu); 832 833 /* 834 * Wait 5s total for a response 835 */ 836 for (timeout = 0; timeout < 50000; timeout++) { 837 if (cpumask_test_cpu(cpu, cpu_callin_mask)) 838 break; /* It has booted */ 839 udelay(100); 840 /* 841 * Allow other tasks to run while we wait for the 842 * AP to come online. This also gives a chance 843 * for the MTRR work(triggered by the AP coming online) 844 * to be completed in the stop machine context. 845 */ 846 schedule(); 847 } 848 849 if (cpumask_test_cpu(cpu, cpu_callin_mask)) 850 pr_debug("CPU%d: has booted.\n", cpu); 851 else { 852 boot_error = 1; 853 if (*((volatile unsigned char *)trampoline_base) 854 == 0xA5) 855 /* trampoline started but...? */ 856 pr_err("CPU%d: Stuck ??\n", cpu); 857 else 858 /* trampoline code not run */ 859 pr_err("CPU%d: Not responding.\n", cpu); 860 if (apic->inquire_remote_apic) 861 apic->inquire_remote_apic(apicid); 862 } 863 } 864 865 if (boot_error) { 866 /* Try to put things back the way they were before ... */ 867 numa_remove_cpu(cpu); /* was set by numa_add_cpu */ 868 869 /* was set by do_boot_cpu() */ 870 cpumask_clear_cpu(cpu, cpu_callout_mask); 871 872 /* was set by cpu_init() */ 873 cpumask_clear_cpu(cpu, cpu_initialized_mask); 874 875 set_cpu_present(cpu, false); 876 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; 877 } 878 879 /* mark "stuck" area as not stuck */ 880 *((volatile unsigned long *)trampoline_base) = 0; 881 882 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 883 /* 884 * Cleanup possible dangling ends... 885 */ 886 smpboot_restore_warm_reset_vector(); 887 } 888 889 destroy_work_on_stack(&c_idle.work); 890 return boot_error; 891 } 892 893 int __cpuinit native_cpu_up(unsigned int cpu) 894 { 895 int apicid = apic->cpu_present_to_apicid(cpu); 896 unsigned long flags; 897 int err; 898 899 WARN_ON(irqs_disabled()); 900 901 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 902 903 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || 904 !physid_isset(apicid, phys_cpu_present_map)) { 905 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); 906 return -EINVAL; 907 } 908 909 /* 910 * Already booted CPU? 911 */ 912 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 913 pr_debug("do_boot_cpu %d Already started\n", cpu); 914 return -ENOSYS; 915 } 916 917 /* 918 * Save current MTRR state in case it was changed since early boot 919 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 920 */ 921 mtrr_save_state(); 922 923 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; 924 925 err = do_boot_cpu(apicid, cpu); 926 927 if (err) { 928 pr_debug("do_boot_cpu failed %d\n", err); 929 return -EIO; 930 } 931 932 /* 933 * Check TSC synchronization with the AP (keep irqs disabled 934 * while doing so): 935 */ 936 local_irq_save(flags); 937 check_tsc_sync_source(cpu); 938 local_irq_restore(flags); 939 940 while (!cpu_online(cpu)) { 941 cpu_relax(); 942 touch_nmi_watchdog(); 943 } 944 945 return 0; 946 } 947 948 /* 949 * Fall back to non SMP mode after errors. 950 * 951 * RED-PEN audit/test this more. I bet there is more state messed up here. 952 */ 953 static __init void disable_smp(void) 954 { 955 init_cpu_present(cpumask_of(0)); 956 init_cpu_possible(cpumask_of(0)); 957 smpboot_clear_io_apic_irqs(); 958 959 if (smp_found_config) 960 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 961 else 962 physid_set_mask_of_physid(0, &phys_cpu_present_map); 963 map_cpu_to_logical_apicid(); 964 cpumask_set_cpu(0, cpu_sibling_mask(0)); 965 cpumask_set_cpu(0, cpu_core_mask(0)); 966 } 967 968 /* 969 * Various sanity checks. 970 */ 971 static int __init smp_sanity_check(unsigned max_cpus) 972 { 973 preempt_disable(); 974 975 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 976 if (def_to_bigsmp && nr_cpu_ids > 8) { 977 unsigned int cpu; 978 unsigned nr; 979 980 printk(KERN_WARNING 981 "More than 8 CPUs detected - skipping them.\n" 982 "Use CONFIG_X86_BIGSMP.\n"); 983 984 nr = 0; 985 for_each_present_cpu(cpu) { 986 if (nr >= 8) 987 set_cpu_present(cpu, false); 988 nr++; 989 } 990 991 nr = 0; 992 for_each_possible_cpu(cpu) { 993 if (nr >= 8) 994 set_cpu_possible(cpu, false); 995 nr++; 996 } 997 998 nr_cpu_ids = 8; 999 } 1000 #endif 1001 1002 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1003 printk(KERN_WARNING 1004 "weird, boot CPU (#%d) not listed by the BIOS.\n", 1005 hard_smp_processor_id()); 1006 1007 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1008 } 1009 1010 /* 1011 * If we couldn't find an SMP configuration at boot time, 1012 * get out of here now! 1013 */ 1014 if (!smp_found_config && !acpi_lapic) { 1015 preempt_enable(); 1016 printk(KERN_NOTICE "SMP motherboard not detected.\n"); 1017 disable_smp(); 1018 if (APIC_init_uniprocessor()) 1019 printk(KERN_NOTICE "Local APIC not detected." 1020 " Using dummy APIC emulation.\n"); 1021 return -1; 1022 } 1023 1024 /* 1025 * Should not be necessary because the MP table should list the boot 1026 * CPU too, but we do it for the sake of robustness anyway. 1027 */ 1028 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1029 printk(KERN_NOTICE 1030 "weird, boot CPU (#%d) not listed by the BIOS.\n", 1031 boot_cpu_physical_apicid); 1032 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1033 } 1034 preempt_enable(); 1035 1036 /* 1037 * If we couldn't find a local APIC, then get out of here now! 1038 */ 1039 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 1040 !cpu_has_apic) { 1041 if (!disable_apic) { 1042 pr_err("BIOS bug, local APIC #%d not detected!...\n", 1043 boot_cpu_physical_apicid); 1044 pr_err("... forcing use of dummy APIC emulation." 1045 "(tell your hw vendor)\n"); 1046 } 1047 smpboot_clear_io_apic(); 1048 arch_disable_smp_support(); 1049 return -1; 1050 } 1051 1052 verify_local_APIC(); 1053 1054 /* 1055 * If SMP should be disabled, then really disable it! 1056 */ 1057 if (!max_cpus) { 1058 printk(KERN_INFO "SMP mode deactivated.\n"); 1059 smpboot_clear_io_apic(); 1060 1061 localise_nmi_watchdog(); 1062 1063 connect_bsp_APIC(); 1064 setup_local_APIC(); 1065 end_local_APIC_setup(); 1066 return -1; 1067 } 1068 1069 return 0; 1070 } 1071 1072 static void __init smp_cpu_index_default(void) 1073 { 1074 int i; 1075 struct cpuinfo_x86 *c; 1076 1077 for_each_possible_cpu(i) { 1078 c = &cpu_data(i); 1079 /* mark all to hotplug */ 1080 c->cpu_index = nr_cpu_ids; 1081 } 1082 } 1083 1084 /* 1085 * Prepare for SMP bootup. The MP table or ACPI has been read 1086 * earlier. Just do some sanity checking here and enable APIC mode. 1087 */ 1088 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1089 { 1090 unsigned int i; 1091 1092 preempt_disable(); 1093 smp_cpu_index_default(); 1094 current_cpu_data = boot_cpu_data; 1095 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1096 mb(); 1097 /* 1098 * Setup boot CPU information 1099 */ 1100 smp_store_cpu_info(0); /* Final full version of the data */ 1101 #ifdef CONFIG_X86_32 1102 boot_cpu_logical_apicid = logical_smp_processor_id(); 1103 #endif 1104 current_thread_info()->cpu = 0; /* needed? */ 1105 for_each_possible_cpu(i) { 1106 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1107 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1108 zalloc_cpumask_var(&cpu_data(i).llc_shared_map, GFP_KERNEL); 1109 } 1110 set_cpu_sibling_map(0); 1111 1112 enable_IR_x2apic(); 1113 default_setup_apic_routing(); 1114 1115 if (smp_sanity_check(max_cpus) < 0) { 1116 printk(KERN_INFO "SMP disabled\n"); 1117 disable_smp(); 1118 goto out; 1119 } 1120 1121 preempt_disable(); 1122 if (read_apic_id() != boot_cpu_physical_apicid) { 1123 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1124 read_apic_id(), boot_cpu_physical_apicid); 1125 /* Or can we switch back to PIC here? */ 1126 } 1127 preempt_enable(); 1128 1129 connect_bsp_APIC(); 1130 1131 /* 1132 * Switch from PIC to APIC mode. 1133 */ 1134 setup_local_APIC(); 1135 1136 /* 1137 * Enable IO APIC before setting up error vector 1138 */ 1139 if (!skip_ioapic_setup && nr_ioapics) 1140 enable_IO_APIC(); 1141 1142 end_local_APIC_setup(); 1143 1144 map_cpu_to_logical_apicid(); 1145 1146 if (apic->setup_portio_remap) 1147 apic->setup_portio_remap(); 1148 1149 smpboot_setup_io_apic(); 1150 /* 1151 * Set up local APIC timer on boot CPU. 1152 */ 1153 1154 printk(KERN_INFO "CPU%d: ", 0); 1155 print_cpu_info(&cpu_data(0)); 1156 x86_init.timers.setup_percpu_clockev(); 1157 1158 if (is_uv_system()) 1159 uv_system_init(); 1160 1161 set_mtrr_aps_delayed_init(); 1162 out: 1163 preempt_enable(); 1164 } 1165 1166 void arch_enable_nonboot_cpus_begin(void) 1167 { 1168 set_mtrr_aps_delayed_init(); 1169 } 1170 1171 void arch_enable_nonboot_cpus_end(void) 1172 { 1173 mtrr_aps_init(); 1174 } 1175 1176 /* 1177 * Early setup to make printk work. 1178 */ 1179 void __init native_smp_prepare_boot_cpu(void) 1180 { 1181 int me = smp_processor_id(); 1182 switch_to_new_gdt(me); 1183 /* already set me in cpu_online_mask in boot_cpu_init() */ 1184 cpumask_set_cpu(me, cpu_callout_mask); 1185 per_cpu(cpu_state, me) = CPU_ONLINE; 1186 } 1187 1188 void __init native_smp_cpus_done(unsigned int max_cpus) 1189 { 1190 pr_debug("Boot done.\n"); 1191 1192 impress_friends(); 1193 #ifdef CONFIG_X86_IO_APIC 1194 setup_ioapic_dest(); 1195 #endif 1196 check_nmi_watchdog(); 1197 mtrr_aps_init(); 1198 } 1199 1200 static int __initdata setup_possible_cpus = -1; 1201 static int __init _setup_possible_cpus(char *str) 1202 { 1203 get_option(&str, &setup_possible_cpus); 1204 return 0; 1205 } 1206 early_param("possible_cpus", _setup_possible_cpus); 1207 1208 1209 /* 1210 * cpu_possible_mask should be static, it cannot change as cpu's 1211 * are onlined, or offlined. The reason is per-cpu data-structures 1212 * are allocated by some modules at init time, and dont expect to 1213 * do this dynamically on cpu arrival/departure. 1214 * cpu_present_mask on the other hand can change dynamically. 1215 * In case when cpu_hotplug is not compiled, then we resort to current 1216 * behaviour, which is cpu_possible == cpu_present. 1217 * - Ashok Raj 1218 * 1219 * Three ways to find out the number of additional hotplug CPUs: 1220 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1221 * - The user can overwrite it with possible_cpus=NUM 1222 * - Otherwise don't reserve additional CPUs. 1223 * We do this because additional CPUs waste a lot of memory. 1224 * -AK 1225 */ 1226 __init void prefill_possible_map(void) 1227 { 1228 int i, possible; 1229 1230 /* no processor from mptable or madt */ 1231 if (!num_processors) 1232 num_processors = 1; 1233 1234 i = setup_max_cpus ?: 1; 1235 if (setup_possible_cpus == -1) { 1236 possible = num_processors; 1237 #ifdef CONFIG_HOTPLUG_CPU 1238 if (setup_max_cpus) 1239 possible += disabled_cpus; 1240 #else 1241 if (possible > i) 1242 possible = i; 1243 #endif 1244 } else 1245 possible = setup_possible_cpus; 1246 1247 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1248 1249 /* nr_cpu_ids could be reduced via nr_cpus= */ 1250 if (possible > nr_cpu_ids) { 1251 printk(KERN_WARNING 1252 "%d Processors exceeds NR_CPUS limit of %d\n", 1253 possible, nr_cpu_ids); 1254 possible = nr_cpu_ids; 1255 } 1256 1257 #ifdef CONFIG_HOTPLUG_CPU 1258 if (!setup_max_cpus) 1259 #endif 1260 if (possible > i) { 1261 printk(KERN_WARNING 1262 "%d Processors exceeds max_cpus limit of %u\n", 1263 possible, setup_max_cpus); 1264 possible = i; 1265 } 1266 1267 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", 1268 possible, max_t(int, possible - num_processors, 0)); 1269 1270 for (i = 0; i < possible; i++) 1271 set_cpu_possible(i, true); 1272 for (; i < NR_CPUS; i++) 1273 set_cpu_possible(i, false); 1274 1275 nr_cpu_ids = possible; 1276 } 1277 1278 #ifdef CONFIG_HOTPLUG_CPU 1279 1280 static void remove_siblinginfo(int cpu) 1281 { 1282 int sibling; 1283 struct cpuinfo_x86 *c = &cpu_data(cpu); 1284 1285 for_each_cpu(sibling, cpu_core_mask(cpu)) { 1286 cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); 1287 /*/ 1288 * last thread sibling in this cpu core going down 1289 */ 1290 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) 1291 cpu_data(sibling).booted_cores--; 1292 } 1293 1294 for_each_cpu(sibling, cpu_sibling_mask(cpu)) 1295 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); 1296 cpumask_clear(cpu_sibling_mask(cpu)); 1297 cpumask_clear(cpu_core_mask(cpu)); 1298 c->phys_proc_id = 0; 1299 c->cpu_core_id = 0; 1300 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1301 } 1302 1303 static void __ref remove_cpu_from_maps(int cpu) 1304 { 1305 set_cpu_online(cpu, false); 1306 cpumask_clear_cpu(cpu, cpu_callout_mask); 1307 cpumask_clear_cpu(cpu, cpu_callin_mask); 1308 /* was set by cpu_init() */ 1309 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1310 numa_remove_cpu(cpu); 1311 } 1312 1313 void cpu_disable_common(void) 1314 { 1315 int cpu = smp_processor_id(); 1316 1317 remove_siblinginfo(cpu); 1318 1319 /* It's now safe to remove this processor from the online map */ 1320 lock_vector_lock(); 1321 remove_cpu_from_maps(cpu); 1322 unlock_vector_lock(); 1323 fixup_irqs(); 1324 } 1325 1326 int native_cpu_disable(void) 1327 { 1328 int cpu = smp_processor_id(); 1329 1330 /* 1331 * Perhaps use cpufreq to drop frequency, but that could go 1332 * into generic code. 1333 * 1334 * We won't take down the boot processor on i386 due to some 1335 * interrupts only being able to be serviced by the BSP. 1336 * Especially so if we're not using an IOAPIC -zwane 1337 */ 1338 if (cpu == 0) 1339 return -EBUSY; 1340 1341 if (nmi_watchdog == NMI_LOCAL_APIC) 1342 stop_apic_nmi_watchdog(NULL); 1343 clear_local_APIC(); 1344 1345 cpu_disable_common(); 1346 return 0; 1347 } 1348 1349 void native_cpu_die(unsigned int cpu) 1350 { 1351 /* We don't do anything here: idle task is faking death itself. */ 1352 unsigned int i; 1353 1354 for (i = 0; i < 10; i++) { 1355 /* They ack this in play_dead by setting CPU_DEAD */ 1356 if (per_cpu(cpu_state, cpu) == CPU_DEAD) { 1357 if (system_state == SYSTEM_RUNNING) 1358 pr_info("CPU %u is now offline\n", cpu); 1359 1360 if (1 == num_online_cpus()) 1361 alternatives_smp_switch(0); 1362 return; 1363 } 1364 msleep(100); 1365 } 1366 pr_err("CPU %u didn't die...\n", cpu); 1367 } 1368 1369 void play_dead_common(void) 1370 { 1371 idle_task_exit(); 1372 reset_lazy_tlbstate(); 1373 irq_ctx_exit(raw_smp_processor_id()); 1374 c1e_remove_cpu(raw_smp_processor_id()); 1375 1376 mb(); 1377 /* Ack it */ 1378 __get_cpu_var(cpu_state) = CPU_DEAD; 1379 1380 /* 1381 * With physical CPU hotplug, we should halt the cpu 1382 */ 1383 local_irq_disable(); 1384 } 1385 1386 void native_play_dead(void) 1387 { 1388 play_dead_common(); 1389 tboot_shutdown(TB_SHUTDOWN_WFS); 1390 wbinvd_halt(); 1391 } 1392 1393 #else /* ... !CONFIG_HOTPLUG_CPU */ 1394 int native_cpu_disable(void) 1395 { 1396 return -ENOSYS; 1397 } 1398 1399 void native_cpu_die(unsigned int cpu) 1400 { 1401 /* We said "no" in __cpu_disable */ 1402 BUG(); 1403 } 1404 1405 void native_play_dead(void) 1406 { 1407 BUG(); 1408 } 1409 1410 #endif 1411