1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/module.h> 45 #include <linux/sched.h> 46 #include <linux/percpu.h> 47 #include <linux/bootmem.h> 48 #include <linux/err.h> 49 #include <linux/nmi.h> 50 #include <linux/tboot.h> 51 52 #include <asm/acpi.h> 53 #include <asm/desc.h> 54 #include <asm/nmi.h> 55 #include <asm/irq.h> 56 #include <asm/idle.h> 57 #include <asm/trampoline.h> 58 #include <asm/cpu.h> 59 #include <asm/numa.h> 60 #include <asm/pgtable.h> 61 #include <asm/tlbflush.h> 62 #include <asm/mtrr.h> 63 #include <asm/vmi.h> 64 #include <asm/apic.h> 65 #include <asm/setup.h> 66 #include <asm/uv/uv.h> 67 #include <linux/mc146818rtc.h> 68 69 #include <asm/smpboot_hooks.h> 70 71 #ifdef CONFIG_X86_32 72 u8 apicid_2_node[MAX_APICID]; 73 static int low_mappings; 74 #endif 75 76 /* State of each CPU */ 77 DEFINE_PER_CPU(int, cpu_state) = { 0 }; 78 79 /* Store all idle threads, this can be reused instead of creating 80 * a new thread. Also avoids complicated thread destroy functionality 81 * for idle threads. 82 */ 83 #ifdef CONFIG_HOTPLUG_CPU 84 /* 85 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is 86 * removed after init for !CONFIG_HOTPLUG_CPU. 87 */ 88 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); 89 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) 90 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) 91 #else 92 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; 93 #define get_idle_for_cpu(x) (idle_thread_array[(x)]) 94 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) 95 #endif 96 97 /* Number of siblings per CPU package */ 98 int smp_num_siblings = 1; 99 EXPORT_SYMBOL(smp_num_siblings); 100 101 /* Last level cache ID of each logical CPU */ 102 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; 103 104 /* representing HT siblings of each logical CPU */ 105 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); 106 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 107 108 /* representing HT and core siblings of each logical CPU */ 109 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); 110 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 111 112 /* Per CPU bogomips and other parameters */ 113 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 114 EXPORT_PER_CPU_SYMBOL(cpu_info); 115 116 atomic_t init_deasserted; 117 118 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) 119 /* which node each logical CPU is on */ 120 int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; 121 EXPORT_SYMBOL(cpu_to_node_map); 122 123 /* set up a mapping between cpu and node. */ 124 static void map_cpu_to_node(int cpu, int node) 125 { 126 printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); 127 cpumask_set_cpu(cpu, node_to_cpumask_map[node]); 128 cpu_to_node_map[cpu] = node; 129 } 130 131 /* undo a mapping between cpu and node. */ 132 static void unmap_cpu_to_node(int cpu) 133 { 134 int node; 135 136 printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); 137 for (node = 0; node < MAX_NUMNODES; node++) 138 cpumask_clear_cpu(cpu, node_to_cpumask_map[node]); 139 cpu_to_node_map[cpu] = 0; 140 } 141 #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ 142 #define map_cpu_to_node(cpu, node) ({}) 143 #define unmap_cpu_to_node(cpu) ({}) 144 #endif 145 146 #ifdef CONFIG_X86_32 147 static int boot_cpu_logical_apicid; 148 149 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = 150 { [0 ... NR_CPUS-1] = BAD_APICID }; 151 152 static void map_cpu_to_logical_apicid(void) 153 { 154 int cpu = smp_processor_id(); 155 int apicid = logical_smp_processor_id(); 156 int node = apic->apicid_to_node(apicid); 157 158 if (!node_online(node)) 159 node = first_online_node; 160 161 cpu_2_logical_apicid[cpu] = apicid; 162 map_cpu_to_node(cpu, node); 163 } 164 165 void numa_remove_cpu(int cpu) 166 { 167 cpu_2_logical_apicid[cpu] = BAD_APICID; 168 unmap_cpu_to_node(cpu); 169 } 170 #else 171 #define map_cpu_to_logical_apicid() do {} while (0) 172 #endif 173 174 /* 175 * Report back to the Boot Processor. 176 * Running on AP. 177 */ 178 static void __cpuinit smp_callin(void) 179 { 180 int cpuid, phys_id; 181 unsigned long timeout; 182 183 /* 184 * If waken up by an INIT in an 82489DX configuration 185 * we may get here before an INIT-deassert IPI reaches 186 * our local APIC. We have to wait for the IPI or we'll 187 * lock up on an APIC access. 188 */ 189 if (apic->wait_for_init_deassert) 190 apic->wait_for_init_deassert(&init_deasserted); 191 192 /* 193 * (This works even if the APIC is not enabled.) 194 */ 195 phys_id = read_apic_id(); 196 cpuid = smp_processor_id(); 197 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { 198 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, 199 phys_id, cpuid); 200 } 201 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); 202 203 /* 204 * STARTUP IPIs are fragile beasts as they might sometimes 205 * trigger some glue motherboard logic. Complete APIC bus 206 * silence for 1 second, this overestimates the time the 207 * boot CPU is spending to send the up to 2 STARTUP IPIs 208 * by a factor of two. This should be enough. 209 */ 210 211 /* 212 * Waiting 2s total for startup (udelay is not yet working) 213 */ 214 timeout = jiffies + 2*HZ; 215 while (time_before(jiffies, timeout)) { 216 /* 217 * Has the boot CPU finished it's STARTUP sequence? 218 */ 219 if (cpumask_test_cpu(cpuid, cpu_callout_mask)) 220 break; 221 cpu_relax(); 222 } 223 224 if (!time_before(jiffies, timeout)) { 225 panic("%s: CPU%d started up but did not get a callout!\n", 226 __func__, cpuid); 227 } 228 229 /* 230 * the boot CPU has finished the init stage and is spinning 231 * on callin_map until we finish. We are free to set up this 232 * CPU, first the APIC. (this is probably redundant on most 233 * boards) 234 */ 235 236 pr_debug("CALLIN, before setup_local_APIC().\n"); 237 if (apic->smp_callin_clear_local_apic) 238 apic->smp_callin_clear_local_apic(); 239 setup_local_APIC(); 240 end_local_APIC_setup(); 241 map_cpu_to_logical_apicid(); 242 243 notify_cpu_starting(cpuid); 244 /* 245 * Get our bogomips. 246 * 247 * Need to enable IRQs because it can take longer and then 248 * the NMI watchdog might kill us. 249 */ 250 local_irq_enable(); 251 calibrate_delay(); 252 local_irq_disable(); 253 pr_debug("Stack at about %p\n", &cpuid); 254 255 /* 256 * Save our processor parameters 257 */ 258 smp_store_cpu_info(cpuid); 259 260 /* 261 * Allow the master to continue. 262 */ 263 cpumask_set_cpu(cpuid, cpu_callin_mask); 264 } 265 266 /* 267 * Activate a secondary processor. 268 */ 269 notrace static void __cpuinit start_secondary(void *unused) 270 { 271 /* 272 * Don't put *anything* before cpu_init(), SMP booting is too 273 * fragile that we want to limit the things done here to the 274 * most necessary things. 275 */ 276 vmi_bringup(); 277 cpu_init(); 278 preempt_disable(); 279 smp_callin(); 280 281 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 282 barrier(); 283 /* 284 * Check TSC synchronization with the BP: 285 */ 286 check_tsc_sync_target(); 287 288 if (nmi_watchdog == NMI_IO_APIC) { 289 disable_8259A_irq(0); 290 enable_NMI_through_LVT0(); 291 enable_8259A_irq(0); 292 } 293 294 #ifdef CONFIG_X86_32 295 while (low_mappings) 296 cpu_relax(); 297 __flush_tlb_all(); 298 #endif 299 300 /* This must be done before setting cpu_online_mask */ 301 set_cpu_sibling_map(raw_smp_processor_id()); 302 wmb(); 303 304 /* 305 * We need to hold call_lock, so there is no inconsistency 306 * between the time smp_call_function() determines number of 307 * IPI recipients, and the time when the determination is made 308 * for which cpus receive the IPI. Holding this 309 * lock helps us to not include this cpu in a currently in progress 310 * smp_call_function(). 311 * 312 * We need to hold vector_lock so there the set of online cpus 313 * does not change while we are assigning vectors to cpus. Holding 314 * this lock ensures we don't half assign or remove an irq from a cpu. 315 */ 316 ipi_call_lock(); 317 lock_vector_lock(); 318 __setup_vector_irq(smp_processor_id()); 319 set_cpu_online(smp_processor_id(), true); 320 unlock_vector_lock(); 321 ipi_call_unlock(); 322 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; 323 x86_platform.nmi_init(); 324 325 /* enable local interrupts */ 326 local_irq_enable(); 327 328 x86_cpuinit.setup_percpu_clockev(); 329 330 wmb(); 331 cpu_idle(); 332 } 333 334 #ifdef CONFIG_CPUMASK_OFFSTACK 335 /* In this case, llc_shared_map is a pointer to a cpumask. */ 336 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, 337 const struct cpuinfo_x86 *src) 338 { 339 struct cpumask *llc = dst->llc_shared_map; 340 *dst = *src; 341 dst->llc_shared_map = llc; 342 } 343 #else 344 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, 345 const struct cpuinfo_x86 *src) 346 { 347 *dst = *src; 348 } 349 #endif /* CONFIG_CPUMASK_OFFSTACK */ 350 351 /* 352 * The bootstrap kernel entry code has set these up. Save them for 353 * a given CPU 354 */ 355 356 void __cpuinit smp_store_cpu_info(int id) 357 { 358 struct cpuinfo_x86 *c = &cpu_data(id); 359 360 copy_cpuinfo_x86(c, &boot_cpu_data); 361 c->cpu_index = id; 362 if (id != 0) 363 identify_secondary_cpu(c); 364 } 365 366 367 void __cpuinit set_cpu_sibling_map(int cpu) 368 { 369 int i; 370 struct cpuinfo_x86 *c = &cpu_data(cpu); 371 372 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 373 374 if (smp_num_siblings > 1) { 375 for_each_cpu(i, cpu_sibling_setup_mask) { 376 struct cpuinfo_x86 *o = &cpu_data(i); 377 378 if (c->phys_proc_id == o->phys_proc_id && 379 c->cpu_core_id == o->cpu_core_id) { 380 cpumask_set_cpu(i, cpu_sibling_mask(cpu)); 381 cpumask_set_cpu(cpu, cpu_sibling_mask(i)); 382 cpumask_set_cpu(i, cpu_core_mask(cpu)); 383 cpumask_set_cpu(cpu, cpu_core_mask(i)); 384 cpumask_set_cpu(i, c->llc_shared_map); 385 cpumask_set_cpu(cpu, o->llc_shared_map); 386 } 387 } 388 } else { 389 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); 390 } 391 392 cpumask_set_cpu(cpu, c->llc_shared_map); 393 394 if (current_cpu_data.x86_max_cores == 1) { 395 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); 396 c->booted_cores = 1; 397 return; 398 } 399 400 for_each_cpu(i, cpu_sibling_setup_mask) { 401 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && 402 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { 403 cpumask_set_cpu(i, c->llc_shared_map); 404 cpumask_set_cpu(cpu, cpu_data(i).llc_shared_map); 405 } 406 if (c->phys_proc_id == cpu_data(i).phys_proc_id) { 407 cpumask_set_cpu(i, cpu_core_mask(cpu)); 408 cpumask_set_cpu(cpu, cpu_core_mask(i)); 409 /* 410 * Does this new cpu bringup a new core? 411 */ 412 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { 413 /* 414 * for each core in package, increment 415 * the booted_cores for this new cpu 416 */ 417 if (cpumask_first(cpu_sibling_mask(i)) == i) 418 c->booted_cores++; 419 /* 420 * increment the core count for all 421 * the other cpus in this package 422 */ 423 if (i != cpu) 424 cpu_data(i).booted_cores++; 425 } else if (i != cpu && !c->booted_cores) 426 c->booted_cores = cpu_data(i).booted_cores; 427 } 428 } 429 } 430 431 /* maps the cpu to the sched domain representing multi-core */ 432 const struct cpumask *cpu_coregroup_mask(int cpu) 433 { 434 struct cpuinfo_x86 *c = &cpu_data(cpu); 435 /* 436 * For perf, we return last level cache shared map. 437 * And for power savings, we return cpu_core_map 438 */ 439 if ((sched_mc_power_savings || sched_smt_power_savings) && 440 !(cpu_has(c, X86_FEATURE_AMD_DCM))) 441 return cpu_core_mask(cpu); 442 else 443 return c->llc_shared_map; 444 } 445 446 static void impress_friends(void) 447 { 448 int cpu; 449 unsigned long bogosum = 0; 450 /* 451 * Allow the user to impress friends. 452 */ 453 pr_debug("Before bogomips.\n"); 454 for_each_possible_cpu(cpu) 455 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 456 bogosum += cpu_data(cpu).loops_per_jiffy; 457 printk(KERN_INFO 458 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", 459 num_online_cpus(), 460 bogosum/(500000/HZ), 461 (bogosum/(5000/HZ))%100); 462 463 pr_debug("Before bogocount - setting activated=1.\n"); 464 } 465 466 void __inquire_remote_apic(int apicid) 467 { 468 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 469 char *names[] = { "ID", "VERSION", "SPIV" }; 470 int timeout; 471 u32 status; 472 473 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); 474 475 for (i = 0; i < ARRAY_SIZE(regs); i++) { 476 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); 477 478 /* 479 * Wait for idle. 480 */ 481 status = safe_apic_wait_icr_idle(); 482 if (status) 483 printk(KERN_CONT 484 "a previous APIC delivery may have failed\n"); 485 486 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 487 488 timeout = 0; 489 do { 490 udelay(100); 491 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 492 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 493 494 switch (status) { 495 case APIC_ICR_RR_VALID: 496 status = apic_read(APIC_RRR); 497 printk(KERN_CONT "%08x\n", status); 498 break; 499 default: 500 printk(KERN_CONT "failed\n"); 501 } 502 } 503 } 504 505 /* 506 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 507 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 508 * won't ... remember to clear down the APIC, etc later. 509 */ 510 int __cpuinit 511 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) 512 { 513 unsigned long send_status, accept_status = 0; 514 int maxlvt; 515 516 /* Target chip */ 517 /* Boot on the stack */ 518 /* Kick the second */ 519 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); 520 521 pr_debug("Waiting for send to finish...\n"); 522 send_status = safe_apic_wait_icr_idle(); 523 524 /* 525 * Give the other CPU some time to accept the IPI. 526 */ 527 udelay(200); 528 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 529 maxlvt = lapic_get_maxlvt(); 530 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 531 apic_write(APIC_ESR, 0); 532 accept_status = (apic_read(APIC_ESR) & 0xEF); 533 } 534 pr_debug("NMI sent.\n"); 535 536 if (send_status) 537 printk(KERN_ERR "APIC never delivered???\n"); 538 if (accept_status) 539 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 540 541 return (send_status | accept_status); 542 } 543 544 static int __cpuinit 545 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 546 { 547 unsigned long send_status, accept_status = 0; 548 int maxlvt, num_starts, j; 549 550 maxlvt = lapic_get_maxlvt(); 551 552 /* 553 * Be paranoid about clearing APIC errors. 554 */ 555 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 556 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 557 apic_write(APIC_ESR, 0); 558 apic_read(APIC_ESR); 559 } 560 561 pr_debug("Asserting INIT.\n"); 562 563 /* 564 * Turn INIT on target chip 565 */ 566 /* 567 * Send IPI 568 */ 569 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 570 phys_apicid); 571 572 pr_debug("Waiting for send to finish...\n"); 573 send_status = safe_apic_wait_icr_idle(); 574 575 mdelay(10); 576 577 pr_debug("Deasserting INIT.\n"); 578 579 /* Target chip */ 580 /* Send IPI */ 581 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 582 583 pr_debug("Waiting for send to finish...\n"); 584 send_status = safe_apic_wait_icr_idle(); 585 586 mb(); 587 atomic_set(&init_deasserted, 1); 588 589 /* 590 * Should we send STARTUP IPIs ? 591 * 592 * Determine this based on the APIC version. 593 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 594 */ 595 if (APIC_INTEGRATED(apic_version[phys_apicid])) 596 num_starts = 2; 597 else 598 num_starts = 0; 599 600 /* 601 * Paravirt / VMI wants a startup IPI hook here to set up the 602 * target processor state. 603 */ 604 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, 605 (unsigned long)stack_start.sp); 606 607 /* 608 * Run STARTUP IPI loop. 609 */ 610 pr_debug("#startup loops: %d.\n", num_starts); 611 612 for (j = 1; j <= num_starts; j++) { 613 pr_debug("Sending STARTUP #%d.\n", j); 614 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 615 apic_write(APIC_ESR, 0); 616 apic_read(APIC_ESR); 617 pr_debug("After apic_write.\n"); 618 619 /* 620 * STARTUP IPI 621 */ 622 623 /* Target chip */ 624 /* Boot on the stack */ 625 /* Kick the second */ 626 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 627 phys_apicid); 628 629 /* 630 * Give the other CPU some time to accept the IPI. 631 */ 632 udelay(300); 633 634 pr_debug("Startup point 1.\n"); 635 636 pr_debug("Waiting for send to finish...\n"); 637 send_status = safe_apic_wait_icr_idle(); 638 639 /* 640 * Give the other CPU some time to accept the IPI. 641 */ 642 udelay(200); 643 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 644 apic_write(APIC_ESR, 0); 645 accept_status = (apic_read(APIC_ESR) & 0xEF); 646 if (send_status || accept_status) 647 break; 648 } 649 pr_debug("After Startup.\n"); 650 651 if (send_status) 652 printk(KERN_ERR "APIC never delivered???\n"); 653 if (accept_status) 654 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 655 656 return (send_status | accept_status); 657 } 658 659 struct create_idle { 660 struct work_struct work; 661 struct task_struct *idle; 662 struct completion done; 663 int cpu; 664 }; 665 666 static void __cpuinit do_fork_idle(struct work_struct *work) 667 { 668 struct create_idle *c_idle = 669 container_of(work, struct create_idle, work); 670 671 c_idle->idle = fork_idle(c_idle->cpu); 672 complete(&c_idle->done); 673 } 674 675 /* reduce the number of lines printed when booting a large cpu count system */ 676 static void __cpuinit announce_cpu(int cpu, int apicid) 677 { 678 static int current_node = -1; 679 int node = cpu_to_node(cpu); 680 681 if (system_state == SYSTEM_BOOTING) { 682 if (node != current_node) { 683 if (current_node > (-1)) 684 pr_cont(" Ok.\n"); 685 current_node = node; 686 pr_info("Booting Node %3d, Processors ", node); 687 } 688 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : ""); 689 return; 690 } else 691 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 692 node, cpu, apicid); 693 } 694 695 /* 696 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 697 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 698 * Returns zero if CPU booted OK, else error code from 699 * ->wakeup_secondary_cpu. 700 */ 701 static int __cpuinit do_boot_cpu(int apicid, int cpu) 702 { 703 unsigned long boot_error = 0; 704 unsigned long start_ip; 705 int timeout; 706 struct create_idle c_idle = { 707 .cpu = cpu, 708 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), 709 }; 710 711 INIT_WORK_ON_STACK(&c_idle.work, do_fork_idle); 712 713 alternatives_smp_switch(1); 714 715 c_idle.idle = get_idle_for_cpu(cpu); 716 717 /* 718 * We can't use kernel_thread since we must avoid to 719 * reschedule the child. 720 */ 721 if (c_idle.idle) { 722 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) 723 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); 724 init_idle(c_idle.idle, cpu); 725 goto do_rest; 726 } 727 728 if (!keventd_up() || current_is_keventd()) 729 c_idle.work.func(&c_idle.work); 730 else { 731 schedule_work(&c_idle.work); 732 wait_for_completion(&c_idle.done); 733 } 734 735 if (IS_ERR(c_idle.idle)) { 736 printk("failed fork for CPU %d\n", cpu); 737 destroy_work_on_stack(&c_idle.work); 738 return PTR_ERR(c_idle.idle); 739 } 740 741 set_idle_for_cpu(cpu, c_idle.idle); 742 do_rest: 743 per_cpu(current_task, cpu) = c_idle.idle; 744 #ifdef CONFIG_X86_32 745 /* Stack for startup_32 can be just as for start_secondary onwards */ 746 irq_ctx_init(cpu); 747 #else 748 clear_tsk_thread_flag(c_idle.idle, TIF_FORK); 749 initial_gs = per_cpu_offset(cpu); 750 per_cpu(kernel_stack, cpu) = 751 (unsigned long)task_stack_page(c_idle.idle) - 752 KERNEL_STACK_OFFSET + THREAD_SIZE; 753 #endif 754 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 755 initial_code = (unsigned long)start_secondary; 756 stack_start.sp = (void *) c_idle.idle->thread.sp; 757 758 /* start_ip had better be page-aligned! */ 759 start_ip = setup_trampoline(); 760 761 /* So we see what's up */ 762 announce_cpu(cpu, apicid); 763 764 /* 765 * This grunge runs the startup process for 766 * the targeted processor. 767 */ 768 769 atomic_set(&init_deasserted, 0); 770 771 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 772 773 pr_debug("Setting warm reset code and vector.\n"); 774 775 smpboot_setup_warm_reset_vector(start_ip); 776 /* 777 * Be paranoid about clearing APIC errors. 778 */ 779 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 780 apic_write(APIC_ESR, 0); 781 apic_read(APIC_ESR); 782 } 783 } 784 785 /* 786 * Kick the secondary CPU. Use the method in the APIC driver 787 * if it's defined - or use an INIT boot APIC message otherwise: 788 */ 789 if (apic->wakeup_secondary_cpu) 790 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 791 else 792 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 793 794 if (!boot_error) { 795 /* 796 * allow APs to start initializing. 797 */ 798 pr_debug("Before Callout %d.\n", cpu); 799 cpumask_set_cpu(cpu, cpu_callout_mask); 800 pr_debug("After Callout %d.\n", cpu); 801 802 /* 803 * Wait 5s total for a response 804 */ 805 for (timeout = 0; timeout < 50000; timeout++) { 806 if (cpumask_test_cpu(cpu, cpu_callin_mask)) 807 break; /* It has booted */ 808 udelay(100); 809 } 810 811 if (cpumask_test_cpu(cpu, cpu_callin_mask)) 812 pr_debug("CPU%d: has booted.\n", cpu); 813 else { 814 boot_error = 1; 815 if (*((volatile unsigned char *)trampoline_base) 816 == 0xA5) 817 /* trampoline started but...? */ 818 pr_err("CPU%d: Stuck ??\n", cpu); 819 else 820 /* trampoline code not run */ 821 pr_err("CPU%d: Not responding.\n", cpu); 822 if (apic->inquire_remote_apic) 823 apic->inquire_remote_apic(apicid); 824 } 825 } 826 827 if (boot_error) { 828 /* Try to put things back the way they were before ... */ 829 numa_remove_cpu(cpu); /* was set by numa_add_cpu */ 830 831 /* was set by do_boot_cpu() */ 832 cpumask_clear_cpu(cpu, cpu_callout_mask); 833 834 /* was set by cpu_init() */ 835 cpumask_clear_cpu(cpu, cpu_initialized_mask); 836 837 set_cpu_present(cpu, false); 838 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; 839 } 840 841 /* mark "stuck" area as not stuck */ 842 *((volatile unsigned long *)trampoline_base) = 0; 843 844 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 845 /* 846 * Cleanup possible dangling ends... 847 */ 848 smpboot_restore_warm_reset_vector(); 849 } 850 851 destroy_work_on_stack(&c_idle.work); 852 return boot_error; 853 } 854 855 int __cpuinit native_cpu_up(unsigned int cpu) 856 { 857 int apicid = apic->cpu_present_to_apicid(cpu); 858 unsigned long flags; 859 int err; 860 861 WARN_ON(irqs_disabled()); 862 863 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 864 865 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || 866 !physid_isset(apicid, phys_cpu_present_map)) { 867 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); 868 return -EINVAL; 869 } 870 871 /* 872 * Already booted CPU? 873 */ 874 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 875 pr_debug("do_boot_cpu %d Already started\n", cpu); 876 return -ENOSYS; 877 } 878 879 /* 880 * Save current MTRR state in case it was changed since early boot 881 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 882 */ 883 mtrr_save_state(); 884 885 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; 886 887 #ifdef CONFIG_X86_32 888 /* init low mem mapping */ 889 clone_pgd_range(swapper_pg_dir, swapper_pg_dir + KERNEL_PGD_BOUNDARY, 890 min_t(unsigned long, KERNEL_PGD_PTRS, KERNEL_PGD_BOUNDARY)); 891 flush_tlb_all(); 892 low_mappings = 1; 893 894 err = do_boot_cpu(apicid, cpu); 895 896 zap_low_mappings(false); 897 low_mappings = 0; 898 #else 899 err = do_boot_cpu(apicid, cpu); 900 #endif 901 if (err) { 902 pr_debug("do_boot_cpu failed %d\n", err); 903 return -EIO; 904 } 905 906 /* 907 * Check TSC synchronization with the AP (keep irqs disabled 908 * while doing so): 909 */ 910 local_irq_save(flags); 911 check_tsc_sync_source(cpu); 912 local_irq_restore(flags); 913 914 while (!cpu_online(cpu)) { 915 cpu_relax(); 916 touch_nmi_watchdog(); 917 } 918 919 return 0; 920 } 921 922 /* 923 * Fall back to non SMP mode after errors. 924 * 925 * RED-PEN audit/test this more. I bet there is more state messed up here. 926 */ 927 static __init void disable_smp(void) 928 { 929 init_cpu_present(cpumask_of(0)); 930 init_cpu_possible(cpumask_of(0)); 931 smpboot_clear_io_apic_irqs(); 932 933 if (smp_found_config) 934 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 935 else 936 physid_set_mask_of_physid(0, &phys_cpu_present_map); 937 map_cpu_to_logical_apicid(); 938 cpumask_set_cpu(0, cpu_sibling_mask(0)); 939 cpumask_set_cpu(0, cpu_core_mask(0)); 940 } 941 942 /* 943 * Various sanity checks. 944 */ 945 static int __init smp_sanity_check(unsigned max_cpus) 946 { 947 preempt_disable(); 948 949 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 950 if (def_to_bigsmp && nr_cpu_ids > 8) { 951 unsigned int cpu; 952 unsigned nr; 953 954 printk(KERN_WARNING 955 "More than 8 CPUs detected - skipping them.\n" 956 "Use CONFIG_X86_BIGSMP.\n"); 957 958 nr = 0; 959 for_each_present_cpu(cpu) { 960 if (nr >= 8) 961 set_cpu_present(cpu, false); 962 nr++; 963 } 964 965 nr = 0; 966 for_each_possible_cpu(cpu) { 967 if (nr >= 8) 968 set_cpu_possible(cpu, false); 969 nr++; 970 } 971 972 nr_cpu_ids = 8; 973 } 974 #endif 975 976 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 977 printk(KERN_WARNING 978 "weird, boot CPU (#%d) not listed by the BIOS.\n", 979 hard_smp_processor_id()); 980 981 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 982 } 983 984 /* 985 * If we couldn't find an SMP configuration at boot time, 986 * get out of here now! 987 */ 988 if (!smp_found_config && !acpi_lapic) { 989 preempt_enable(); 990 printk(KERN_NOTICE "SMP motherboard not detected.\n"); 991 disable_smp(); 992 if (APIC_init_uniprocessor()) 993 printk(KERN_NOTICE "Local APIC not detected." 994 " Using dummy APIC emulation.\n"); 995 return -1; 996 } 997 998 /* 999 * Should not be necessary because the MP table should list the boot 1000 * CPU too, but we do it for the sake of robustness anyway. 1001 */ 1002 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1003 printk(KERN_NOTICE 1004 "weird, boot CPU (#%d) not listed by the BIOS.\n", 1005 boot_cpu_physical_apicid); 1006 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1007 } 1008 preempt_enable(); 1009 1010 /* 1011 * If we couldn't find a local APIC, then get out of here now! 1012 */ 1013 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 1014 !cpu_has_apic) { 1015 if (!disable_apic) { 1016 pr_err("BIOS bug, local APIC #%d not detected!...\n", 1017 boot_cpu_physical_apicid); 1018 pr_err("... forcing use of dummy APIC emulation." 1019 "(tell your hw vendor)\n"); 1020 } 1021 smpboot_clear_io_apic(); 1022 arch_disable_smp_support(); 1023 return -1; 1024 } 1025 1026 verify_local_APIC(); 1027 1028 /* 1029 * If SMP should be disabled, then really disable it! 1030 */ 1031 if (!max_cpus) { 1032 printk(KERN_INFO "SMP mode deactivated.\n"); 1033 smpboot_clear_io_apic(); 1034 1035 localise_nmi_watchdog(); 1036 1037 connect_bsp_APIC(); 1038 setup_local_APIC(); 1039 end_local_APIC_setup(); 1040 return -1; 1041 } 1042 1043 return 0; 1044 } 1045 1046 static void __init smp_cpu_index_default(void) 1047 { 1048 int i; 1049 struct cpuinfo_x86 *c; 1050 1051 for_each_possible_cpu(i) { 1052 c = &cpu_data(i); 1053 /* mark all to hotplug */ 1054 c->cpu_index = nr_cpu_ids; 1055 } 1056 } 1057 1058 /* 1059 * Prepare for SMP bootup. The MP table or ACPI has been read 1060 * earlier. Just do some sanity checking here and enable APIC mode. 1061 */ 1062 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1063 { 1064 unsigned int i; 1065 1066 preempt_disable(); 1067 smp_cpu_index_default(); 1068 current_cpu_data = boot_cpu_data; 1069 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1070 mb(); 1071 /* 1072 * Setup boot CPU information 1073 */ 1074 smp_store_cpu_info(0); /* Final full version of the data */ 1075 #ifdef CONFIG_X86_32 1076 boot_cpu_logical_apicid = logical_smp_processor_id(); 1077 #endif 1078 current_thread_info()->cpu = 0; /* needed? */ 1079 for_each_possible_cpu(i) { 1080 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1081 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1082 zalloc_cpumask_var(&cpu_data(i).llc_shared_map, GFP_KERNEL); 1083 } 1084 set_cpu_sibling_map(0); 1085 1086 enable_IR_x2apic(); 1087 default_setup_apic_routing(); 1088 1089 if (smp_sanity_check(max_cpus) < 0) { 1090 printk(KERN_INFO "SMP disabled\n"); 1091 disable_smp(); 1092 goto out; 1093 } 1094 1095 preempt_disable(); 1096 if (read_apic_id() != boot_cpu_physical_apicid) { 1097 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1098 read_apic_id(), boot_cpu_physical_apicid); 1099 /* Or can we switch back to PIC here? */ 1100 } 1101 preempt_enable(); 1102 1103 connect_bsp_APIC(); 1104 1105 /* 1106 * Switch from PIC to APIC mode. 1107 */ 1108 setup_local_APIC(); 1109 1110 /* 1111 * Enable IO APIC before setting up error vector 1112 */ 1113 if (!skip_ioapic_setup && nr_ioapics) 1114 enable_IO_APIC(); 1115 1116 end_local_APIC_setup(); 1117 1118 map_cpu_to_logical_apicid(); 1119 1120 if (apic->setup_portio_remap) 1121 apic->setup_portio_remap(); 1122 1123 smpboot_setup_io_apic(); 1124 /* 1125 * Set up local APIC timer on boot CPU. 1126 */ 1127 1128 printk(KERN_INFO "CPU%d: ", 0); 1129 print_cpu_info(&cpu_data(0)); 1130 x86_init.timers.setup_percpu_clockev(); 1131 1132 if (is_uv_system()) 1133 uv_system_init(); 1134 1135 set_mtrr_aps_delayed_init(); 1136 out: 1137 preempt_enable(); 1138 } 1139 1140 void arch_enable_nonboot_cpus_begin(void) 1141 { 1142 set_mtrr_aps_delayed_init(); 1143 } 1144 1145 void arch_enable_nonboot_cpus_end(void) 1146 { 1147 mtrr_aps_init(); 1148 } 1149 1150 /* 1151 * Early setup to make printk work. 1152 */ 1153 void __init native_smp_prepare_boot_cpu(void) 1154 { 1155 int me = smp_processor_id(); 1156 switch_to_new_gdt(me); 1157 /* already set me in cpu_online_mask in boot_cpu_init() */ 1158 cpumask_set_cpu(me, cpu_callout_mask); 1159 per_cpu(cpu_state, me) = CPU_ONLINE; 1160 } 1161 1162 void __init native_smp_cpus_done(unsigned int max_cpus) 1163 { 1164 pr_debug("Boot done.\n"); 1165 1166 impress_friends(); 1167 #ifdef CONFIG_X86_IO_APIC 1168 setup_ioapic_dest(); 1169 #endif 1170 check_nmi_watchdog(); 1171 mtrr_aps_init(); 1172 } 1173 1174 static int __initdata setup_possible_cpus = -1; 1175 static int __init _setup_possible_cpus(char *str) 1176 { 1177 get_option(&str, &setup_possible_cpus); 1178 return 0; 1179 } 1180 early_param("possible_cpus", _setup_possible_cpus); 1181 1182 1183 /* 1184 * cpu_possible_mask should be static, it cannot change as cpu's 1185 * are onlined, or offlined. The reason is per-cpu data-structures 1186 * are allocated by some modules at init time, and dont expect to 1187 * do this dynamically on cpu arrival/departure. 1188 * cpu_present_mask on the other hand can change dynamically. 1189 * In case when cpu_hotplug is not compiled, then we resort to current 1190 * behaviour, which is cpu_possible == cpu_present. 1191 * - Ashok Raj 1192 * 1193 * Three ways to find out the number of additional hotplug CPUs: 1194 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1195 * - The user can overwrite it with possible_cpus=NUM 1196 * - Otherwise don't reserve additional CPUs. 1197 * We do this because additional CPUs waste a lot of memory. 1198 * -AK 1199 */ 1200 __init void prefill_possible_map(void) 1201 { 1202 int i, possible; 1203 1204 /* no processor from mptable or madt */ 1205 if (!num_processors) 1206 num_processors = 1; 1207 1208 if (setup_possible_cpus == -1) 1209 possible = num_processors + disabled_cpus; 1210 else 1211 possible = setup_possible_cpus; 1212 1213 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1214 1215 if (possible > CONFIG_NR_CPUS) { 1216 printk(KERN_WARNING 1217 "%d Processors exceeds NR_CPUS limit of %d\n", 1218 possible, CONFIG_NR_CPUS); 1219 possible = CONFIG_NR_CPUS; 1220 } 1221 1222 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", 1223 possible, max_t(int, possible - num_processors, 0)); 1224 1225 for (i = 0; i < possible; i++) 1226 set_cpu_possible(i, true); 1227 1228 nr_cpu_ids = possible; 1229 } 1230 1231 #ifdef CONFIG_HOTPLUG_CPU 1232 1233 static void remove_siblinginfo(int cpu) 1234 { 1235 int sibling; 1236 struct cpuinfo_x86 *c = &cpu_data(cpu); 1237 1238 for_each_cpu(sibling, cpu_core_mask(cpu)) { 1239 cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); 1240 /*/ 1241 * last thread sibling in this cpu core going down 1242 */ 1243 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) 1244 cpu_data(sibling).booted_cores--; 1245 } 1246 1247 for_each_cpu(sibling, cpu_sibling_mask(cpu)) 1248 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); 1249 cpumask_clear(cpu_sibling_mask(cpu)); 1250 cpumask_clear(cpu_core_mask(cpu)); 1251 c->phys_proc_id = 0; 1252 c->cpu_core_id = 0; 1253 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1254 } 1255 1256 static void __ref remove_cpu_from_maps(int cpu) 1257 { 1258 set_cpu_online(cpu, false); 1259 cpumask_clear_cpu(cpu, cpu_callout_mask); 1260 cpumask_clear_cpu(cpu, cpu_callin_mask); 1261 /* was set by cpu_init() */ 1262 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1263 numa_remove_cpu(cpu); 1264 } 1265 1266 void cpu_disable_common(void) 1267 { 1268 int cpu = smp_processor_id(); 1269 1270 remove_siblinginfo(cpu); 1271 1272 /* It's now safe to remove this processor from the online map */ 1273 lock_vector_lock(); 1274 remove_cpu_from_maps(cpu); 1275 unlock_vector_lock(); 1276 fixup_irqs(); 1277 } 1278 1279 int native_cpu_disable(void) 1280 { 1281 int cpu = smp_processor_id(); 1282 1283 /* 1284 * Perhaps use cpufreq to drop frequency, but that could go 1285 * into generic code. 1286 * 1287 * We won't take down the boot processor on i386 due to some 1288 * interrupts only being able to be serviced by the BSP. 1289 * Especially so if we're not using an IOAPIC -zwane 1290 */ 1291 if (cpu == 0) 1292 return -EBUSY; 1293 1294 if (nmi_watchdog == NMI_LOCAL_APIC) 1295 stop_apic_nmi_watchdog(NULL); 1296 clear_local_APIC(); 1297 1298 cpu_disable_common(); 1299 return 0; 1300 } 1301 1302 void native_cpu_die(unsigned int cpu) 1303 { 1304 /* We don't do anything here: idle task is faking death itself. */ 1305 unsigned int i; 1306 1307 for (i = 0; i < 10; i++) { 1308 /* They ack this in play_dead by setting CPU_DEAD */ 1309 if (per_cpu(cpu_state, cpu) == CPU_DEAD) { 1310 if (system_state == SYSTEM_RUNNING) 1311 pr_info("CPU %u is now offline\n", cpu); 1312 1313 if (1 == num_online_cpus()) 1314 alternatives_smp_switch(0); 1315 return; 1316 } 1317 msleep(100); 1318 } 1319 pr_err("CPU %u didn't die...\n", cpu); 1320 } 1321 1322 void play_dead_common(void) 1323 { 1324 idle_task_exit(); 1325 reset_lazy_tlbstate(); 1326 irq_ctx_exit(raw_smp_processor_id()); 1327 c1e_remove_cpu(raw_smp_processor_id()); 1328 1329 mb(); 1330 /* Ack it */ 1331 __get_cpu_var(cpu_state) = CPU_DEAD; 1332 1333 /* 1334 * With physical CPU hotplug, we should halt the cpu 1335 */ 1336 local_irq_disable(); 1337 } 1338 1339 void native_play_dead(void) 1340 { 1341 play_dead_common(); 1342 tboot_shutdown(TB_SHUTDOWN_WFS); 1343 wbinvd_halt(); 1344 } 1345 1346 #else /* ... !CONFIG_HOTPLUG_CPU */ 1347 int native_cpu_disable(void) 1348 { 1349 return -ENOSYS; 1350 } 1351 1352 void native_cpu_die(unsigned int cpu) 1353 { 1354 /* We said "no" in __cpu_disable */ 1355 BUG(); 1356 } 1357 1358 void native_play_dead(void) 1359 { 1360 BUG(); 1361 } 1362 1363 #endif 1364