1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * x86 SMP booting functions 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 7 * Copyright 2001 Andi Kleen, SuSE Labs. 8 * 9 * Much of the core SMP work is based on previous work by Thomas Radke, to 10 * whom a great many thanks are extended. 11 * 12 * Thanks to Intel for making available several different Pentium, 13 * Pentium Pro and Pentium-II/Xeon MP machines. 14 * Original development of Linux SMP code supported by Caldera. 15 * 16 * Fixes 17 * Felix Koop : NR_CPUS used properly 18 * Jose Renau : Handle single CPU case. 19 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 20 * Greg Wright : Fix for kernel stacks panic. 21 * Erich Boleyn : MP v1.4 and additional changes. 22 * Matthias Sattler : Changes for 2.1 kernel map. 23 * Michel Lespinasse : Changes for 2.1 kernel map. 24 * Michael Chastain : Change trampoline.S to gnu as. 25 * Alan Cox : Dumb bug: 'B' step PPro's are fine 26 * Ingo Molnar : Added APIC timers, based on code 27 * from Jose Renau 28 * Ingo Molnar : various cleanups and rewrites 29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 31 * Andi Kleen : Changed for SMP boot into long mode. 32 * Martin J. Bligh : Added support for multi-quad systems 33 * Dave Jones : Report invalid combinations of Athlon CPUs. 34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 35 * Andi Kleen : Converted to new state machine. 36 * Ashok Raj : CPU hotplug support 37 * Glauber Costa : i386 and x86_64 integration 38 */ 39 40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/export.h> 45 #include <linux/sched.h> 46 #include <linux/sched/topology.h> 47 #include <linux/sched/hotplug.h> 48 #include <linux/sched/task_stack.h> 49 #include <linux/percpu.h> 50 #include <linux/memblock.h> 51 #include <linux/err.h> 52 #include <linux/nmi.h> 53 #include <linux/tboot.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 #include <linux/kexec.h> 57 #include <linux/numa.h> 58 #include <linux/pgtable.h> 59 #include <linux/overflow.h> 60 #include <linux/stackprotector.h> 61 #include <linux/cpuhotplug.h> 62 #include <linux/mc146818rtc.h> 63 64 #include <asm/acpi.h> 65 #include <asm/cacheinfo.h> 66 #include <asm/desc.h> 67 #include <asm/nmi.h> 68 #include <asm/irq.h> 69 #include <asm/realmode.h> 70 #include <asm/cpu.h> 71 #include <asm/numa.h> 72 #include <asm/tlbflush.h> 73 #include <asm/mtrr.h> 74 #include <asm/mwait.h> 75 #include <asm/apic.h> 76 #include <asm/io_apic.h> 77 #include <asm/fpu/api.h> 78 #include <asm/setup.h> 79 #include <asm/uv/uv.h> 80 #include <asm/microcode.h> 81 #include <asm/i8259.h> 82 #include <asm/misc.h> 83 #include <asm/qspinlock.h> 84 #include <asm/intel-family.h> 85 #include <asm/cpu_device_id.h> 86 #include <asm/spec-ctrl.h> 87 #include <asm/hw_irq.h> 88 #include <asm/stackprotector.h> 89 #include <asm/sev.h> 90 #include <asm/spec-ctrl.h> 91 92 /* representing HT siblings of each logical CPU */ 93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 94 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 95 96 /* representing HT and core siblings of each logical CPU */ 97 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 98 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 99 100 /* representing HT, core, and die siblings of each logical CPU */ 101 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); 102 EXPORT_PER_CPU_SYMBOL(cpu_die_map); 103 104 /* Per CPU bogomips and other parameters */ 105 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 106 EXPORT_PER_CPU_SYMBOL(cpu_info); 107 108 /* CPUs which are the primary SMT threads */ 109 struct cpumask __cpu_primary_thread_mask __read_mostly; 110 111 /* Representing CPUs for which sibling maps can be computed */ 112 static cpumask_var_t cpu_sibling_setup_mask; 113 114 struct mwait_cpu_dead { 115 unsigned int control; 116 unsigned int status; 117 }; 118 119 #define CPUDEAD_MWAIT_WAIT 0xDEADBEEF 120 #define CPUDEAD_MWAIT_KEXEC_HLT 0x4A17DEAD 121 122 /* 123 * Cache line aligned data for mwait_play_dead(). Separate on purpose so 124 * that it's unlikely to be touched by other CPUs. 125 */ 126 static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead); 127 128 /* Logical package management. */ 129 struct logical_maps { 130 u32 phys_pkg_id; 131 u32 phys_die_id; 132 u32 logical_pkg_id; 133 u32 logical_die_id; 134 }; 135 136 /* Temporary workaround until the full topology mechanics is in place */ 137 static DEFINE_PER_CPU_READ_MOSTLY(struct logical_maps, logical_maps) = { 138 .phys_pkg_id = U32_MAX, 139 .phys_die_id = U32_MAX, 140 }; 141 142 unsigned int __max_logical_packages __read_mostly; 143 EXPORT_SYMBOL(__max_logical_packages); 144 static unsigned int logical_packages __read_mostly; 145 static unsigned int logical_die __read_mostly; 146 147 /* Maximum number of SMT threads on any online core */ 148 int __read_mostly __max_smt_threads = 1; 149 150 /* Flag to indicate if a complete sched domain rebuild is required */ 151 bool x86_topology_update; 152 153 int arch_update_cpu_topology(void) 154 { 155 int retval = x86_topology_update; 156 157 x86_topology_update = false; 158 return retval; 159 } 160 161 static unsigned int smpboot_warm_reset_vector_count; 162 163 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 164 { 165 unsigned long flags; 166 167 spin_lock_irqsave(&rtc_lock, flags); 168 if (!smpboot_warm_reset_vector_count++) { 169 CMOS_WRITE(0xa, 0xf); 170 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = start_eip >> 4; 171 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = start_eip & 0xf; 172 } 173 spin_unlock_irqrestore(&rtc_lock, flags); 174 } 175 176 static inline void smpboot_restore_warm_reset_vector(void) 177 { 178 unsigned long flags; 179 180 /* 181 * Paranoid: Set warm reset code and vector here back 182 * to default values. 183 */ 184 spin_lock_irqsave(&rtc_lock, flags); 185 if (!--smpboot_warm_reset_vector_count) { 186 CMOS_WRITE(0, 0xf); 187 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 188 } 189 spin_unlock_irqrestore(&rtc_lock, flags); 190 191 } 192 193 /* Run the next set of setup steps for the upcoming CPU */ 194 static void ap_starting(void) 195 { 196 int cpuid = smp_processor_id(); 197 198 /* Mop up eventual mwait_play_dead() wreckage */ 199 this_cpu_write(mwait_cpu_dead.status, 0); 200 this_cpu_write(mwait_cpu_dead.control, 0); 201 202 /* 203 * If woken up by an INIT in an 82489DX configuration the alive 204 * synchronization guarantees that the CPU does not reach this 205 * point before an INIT_deassert IPI reaches the local APIC, so it 206 * is now safe to touch the local APIC. 207 * 208 * Set up this CPU, first the APIC, which is probably redundant on 209 * most boards. 210 */ 211 apic_ap_setup(); 212 213 /* Save the processor parameters. */ 214 smp_store_cpu_info(cpuid); 215 216 /* 217 * The topology information must be up to date before 218 * notify_cpu_starting(). 219 */ 220 set_cpu_sibling_map(cpuid); 221 222 ap_init_aperfmperf(); 223 224 pr_debug("Stack at about %p\n", &cpuid); 225 226 wmb(); 227 228 /* 229 * This runs the AP through all the cpuhp states to its target 230 * state CPUHP_ONLINE. 231 */ 232 notify_cpu_starting(cpuid); 233 } 234 235 static void ap_calibrate_delay(void) 236 { 237 /* 238 * Calibrate the delay loop and update loops_per_jiffy in cpu_data. 239 * smp_store_cpu_info() stored a value that is close but not as 240 * accurate as the value just calculated. 241 * 242 * As this is invoked after the TSC synchronization check, 243 * calibrate_delay_is_known() will skip the calibration routine 244 * when TSC is synchronized across sockets. 245 */ 246 calibrate_delay(); 247 cpu_data(smp_processor_id()).loops_per_jiffy = loops_per_jiffy; 248 } 249 250 /* 251 * Activate a secondary processor. 252 */ 253 static void notrace start_secondary(void *unused) 254 { 255 /* 256 * Don't put *anything* except direct CPU state initialization 257 * before cpu_init(), SMP booting is too fragile that we want to 258 * limit the things done here to the most necessary things. 259 */ 260 cr4_init(); 261 262 /* 263 * 32-bit specific. 64-bit reaches this code with the correct page 264 * table established. Yet another historical divergence. 265 */ 266 if (IS_ENABLED(CONFIG_X86_32)) { 267 /* switch away from the initial page table */ 268 load_cr3(swapper_pg_dir); 269 __flush_tlb_all(); 270 } 271 272 cpu_init_exception_handling(); 273 274 /* 275 * Load the microcode before reaching the AP alive synchronization 276 * point below so it is not part of the full per CPU serialized 277 * bringup part when "parallel" bringup is enabled. 278 * 279 * That's even safe when hyperthreading is enabled in the CPU as 280 * the core code starts the primary threads first and leaves the 281 * secondary threads waiting for SIPI. Loading microcode on 282 * physical cores concurrently is a safe operation. 283 * 284 * This covers both the Intel specific issue that concurrent 285 * microcode loading on SMT siblings must be prohibited and the 286 * vendor independent issue`that microcode loading which changes 287 * CPUID, MSRs etc. must be strictly serialized to maintain 288 * software state correctness. 289 */ 290 load_ucode_ap(); 291 292 /* 293 * Synchronization point with the hotplug core. Sets this CPUs 294 * synchronization state to ALIVE and spin-waits for the control CPU to 295 * release this CPU for further bringup. 296 */ 297 cpuhp_ap_sync_alive(); 298 299 cpu_init(); 300 fpu__init_cpu(); 301 rcutree_report_cpu_starting(raw_smp_processor_id()); 302 x86_cpuinit.early_percpu_clock_init(); 303 304 ap_starting(); 305 306 /* Check TSC synchronization with the control CPU. */ 307 check_tsc_sync_target(); 308 309 /* 310 * Calibrate the delay loop after the TSC synchronization check. 311 * This allows to skip the calibration when TSC is synchronized 312 * across sockets. 313 */ 314 ap_calibrate_delay(); 315 316 speculative_store_bypass_ht_init(); 317 318 /* 319 * Lock vector_lock, set CPU online and bring the vector 320 * allocator online. Online must be set with vector_lock held 321 * to prevent a concurrent irq setup/teardown from seeing a 322 * half valid vector space. 323 */ 324 lock_vector_lock(); 325 set_cpu_online(smp_processor_id(), true); 326 lapic_online(); 327 unlock_vector_lock(); 328 x86_platform.nmi_init(); 329 330 /* enable local interrupts */ 331 local_irq_enable(); 332 333 x86_cpuinit.setup_percpu_clockev(); 334 335 wmb(); 336 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 337 } 338 339 /** 340 * topology_phys_to_logical_pkg - Map a physical package id to a logical 341 * @phys_pkg: The physical package id to map 342 * 343 * Returns logical package id or -1 if not found 344 */ 345 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 346 { 347 int cpu; 348 349 for_each_possible_cpu(cpu) { 350 if (per_cpu(logical_maps.phys_pkg_id, cpu) == phys_pkg) 351 return per_cpu(logical_maps.logical_pkg_id, cpu); 352 } 353 return -1; 354 } 355 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 356 357 /** 358 * topology_phys_to_logical_die - Map a physical die id to logical 359 * @die_id: The physical die id to map 360 * @cur_cpu: The CPU for which the mapping is done 361 * 362 * Returns logical die id or -1 if not found 363 */ 364 static int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu) 365 { 366 int cpu, proc_id = cpu_data(cur_cpu).topo.pkg_id; 367 368 for_each_possible_cpu(cpu) { 369 if (per_cpu(logical_maps.phys_pkg_id, cpu) == proc_id && 370 per_cpu(logical_maps.phys_die_id, cpu) == die_id) 371 return per_cpu(logical_maps.logical_die_id, cpu); 372 } 373 return -1; 374 } 375 376 /** 377 * topology_update_package_map - Update the physical to logical package map 378 * @pkg: The physical package id as retrieved via CPUID 379 * @cpu: The cpu for which this is updated 380 */ 381 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 382 { 383 int new; 384 385 /* Already available somewhere? */ 386 new = topology_phys_to_logical_pkg(pkg); 387 if (new >= 0) 388 goto found; 389 390 new = logical_packages++; 391 if (new != pkg) { 392 pr_info("CPU %u Converting physical %u to logical package %u\n", 393 cpu, pkg, new); 394 } 395 found: 396 per_cpu(logical_maps.phys_pkg_id, cpu) = pkg; 397 per_cpu(logical_maps.logical_pkg_id, cpu) = new; 398 cpu_data(cpu).topo.logical_pkg_id = new; 399 return 0; 400 } 401 /** 402 * topology_update_die_map - Update the physical to logical die map 403 * @die: The die id as retrieved via CPUID 404 * @cpu: The cpu for which this is updated 405 */ 406 int topology_update_die_map(unsigned int die, unsigned int cpu) 407 { 408 int new; 409 410 /* Already available somewhere? */ 411 new = topology_phys_to_logical_die(die, cpu); 412 if (new >= 0) 413 goto found; 414 415 new = logical_die++; 416 if (new != die) { 417 pr_info("CPU %u Converting physical %u to logical die %u\n", 418 cpu, die, new); 419 } 420 found: 421 per_cpu(logical_maps.phys_die_id, cpu) = die; 422 per_cpu(logical_maps.logical_die_id, cpu) = new; 423 cpu_data(cpu).topo.logical_die_id = new; 424 return 0; 425 } 426 427 static void __init smp_store_boot_cpu_info(void) 428 { 429 int id = 0; /* CPU 0 */ 430 struct cpuinfo_x86 *c = &cpu_data(id); 431 432 *c = boot_cpu_data; 433 c->cpu_index = id; 434 topology_update_package_map(c->topo.pkg_id, id); 435 topology_update_die_map(c->topo.die_id, id); 436 c->initialized = true; 437 } 438 439 /* 440 * The bootstrap kernel entry code has set these up. Save them for 441 * a given CPU 442 */ 443 void smp_store_cpu_info(int id) 444 { 445 struct cpuinfo_x86 *c = &cpu_data(id); 446 447 /* Copy boot_cpu_data only on the first bringup */ 448 if (!c->initialized) 449 *c = boot_cpu_data; 450 c->cpu_index = id; 451 /* 452 * During boot time, CPU0 has this setup already. Save the info when 453 * bringing up an AP. 454 */ 455 identify_secondary_cpu(c); 456 c->initialized = true; 457 } 458 459 static bool 460 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 461 { 462 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 463 464 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 465 } 466 467 static bool 468 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 469 { 470 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 471 472 return !WARN_ONCE(!topology_same_node(c, o), 473 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 474 "[node: %d != %d]. Ignoring dependency.\n", 475 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 476 } 477 478 #define link_mask(mfunc, c1, c2) \ 479 do { \ 480 cpumask_set_cpu((c1), mfunc(c2)); \ 481 cpumask_set_cpu((c2), mfunc(c1)); \ 482 } while (0) 483 484 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 485 { 486 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 487 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 488 489 if (c->topo.pkg_id == o->topo.pkg_id && 490 c->topo.die_id == o->topo.die_id && 491 per_cpu_llc_id(cpu1) == per_cpu_llc_id(cpu2)) { 492 if (c->topo.core_id == o->topo.core_id) 493 return topology_sane(c, o, "smt"); 494 495 if ((c->topo.cu_id != 0xff) && 496 (o->topo.cu_id != 0xff) && 497 (c->topo.cu_id == o->topo.cu_id)) 498 return topology_sane(c, o, "smt"); 499 } 500 501 } else if (c->topo.pkg_id == o->topo.pkg_id && 502 c->topo.die_id == o->topo.die_id && 503 c->topo.core_id == o->topo.core_id) { 504 return topology_sane(c, o, "smt"); 505 } 506 507 return false; 508 } 509 510 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 511 { 512 if (c->topo.pkg_id == o->topo.pkg_id && 513 c->topo.die_id == o->topo.die_id) 514 return true; 515 return false; 516 } 517 518 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 519 { 520 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 521 522 /* If the arch didn't set up l2c_id, fall back to SMT */ 523 if (per_cpu_l2c_id(cpu1) == BAD_APICID) 524 return match_smt(c, o); 525 526 /* Do not match if L2 cache id does not match: */ 527 if (per_cpu_l2c_id(cpu1) != per_cpu_l2c_id(cpu2)) 528 return false; 529 530 return topology_sane(c, o, "l2c"); 531 } 532 533 /* 534 * Unlike the other levels, we do not enforce keeping a 535 * multicore group inside a NUMA node. If this happens, we will 536 * discard the MC level of the topology later. 537 */ 538 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 539 { 540 if (c->topo.pkg_id == o->topo.pkg_id) 541 return true; 542 return false; 543 } 544 545 /* 546 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs. 547 * 548 * Any Intel CPU that has multiple nodes per package and does not 549 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology. 550 * 551 * When in SNC mode, these CPUs enumerate an LLC that is shared 552 * by multiple NUMA nodes. The LLC is shared for off-package data 553 * access but private to the NUMA node (half of the package) for 554 * on-package access. CPUID (the source of the information about 555 * the LLC) can only enumerate the cache as shared or unshared, 556 * but not this particular configuration. 557 */ 558 559 static const struct x86_cpu_id intel_cod_cpu[] = { 560 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */ 561 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */ 562 X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */ 563 {} 564 }; 565 566 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 567 { 568 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu); 569 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 570 bool intel_snc = id && id->driver_data; 571 572 /* Do not match if we do not have a valid APICID for cpu: */ 573 if (per_cpu_llc_id(cpu1) == BAD_APICID) 574 return false; 575 576 /* Do not match if LLC id does not match: */ 577 if (per_cpu_llc_id(cpu1) != per_cpu_llc_id(cpu2)) 578 return false; 579 580 /* 581 * Allow the SNC topology without warning. Return of false 582 * means 'c' does not share the LLC of 'o'. This will be 583 * reflected to userspace. 584 */ 585 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc) 586 return false; 587 588 return topology_sane(c, o, "llc"); 589 } 590 591 592 static inline int x86_sched_itmt_flags(void) 593 { 594 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 595 } 596 597 #ifdef CONFIG_SCHED_MC 598 static int x86_core_flags(void) 599 { 600 return cpu_core_flags() | x86_sched_itmt_flags(); 601 } 602 #endif 603 #ifdef CONFIG_SCHED_SMT 604 static int x86_smt_flags(void) 605 { 606 return cpu_smt_flags(); 607 } 608 #endif 609 #ifdef CONFIG_SCHED_CLUSTER 610 static int x86_cluster_flags(void) 611 { 612 return cpu_cluster_flags() | x86_sched_itmt_flags(); 613 } 614 #endif 615 616 static int x86_die_flags(void) 617 { 618 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) 619 return x86_sched_itmt_flags(); 620 621 return 0; 622 } 623 624 /* 625 * Set if a package/die has multiple NUMA nodes inside. 626 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel 627 * Sub-NUMA Clustering have this. 628 */ 629 static bool x86_has_numa_in_package; 630 631 static struct sched_domain_topology_level x86_topology[6]; 632 633 static void __init build_sched_topology(void) 634 { 635 int i = 0; 636 637 #ifdef CONFIG_SCHED_SMT 638 x86_topology[i++] = (struct sched_domain_topology_level){ 639 cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) 640 }; 641 #endif 642 #ifdef CONFIG_SCHED_CLUSTER 643 x86_topology[i++] = (struct sched_domain_topology_level){ 644 cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) 645 }; 646 #endif 647 #ifdef CONFIG_SCHED_MC 648 x86_topology[i++] = (struct sched_domain_topology_level){ 649 cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) 650 }; 651 #endif 652 /* 653 * When there is NUMA topology inside the package skip the PKG domain 654 * since the NUMA domains will auto-magically create the right spanning 655 * domains based on the SLIT. 656 */ 657 if (!x86_has_numa_in_package) { 658 x86_topology[i++] = (struct sched_domain_topology_level){ 659 cpu_cpu_mask, x86_die_flags, SD_INIT_NAME(PKG) 660 }; 661 } 662 663 /* 664 * There must be one trailing NULL entry left. 665 */ 666 BUG_ON(i >= ARRAY_SIZE(x86_topology)-1); 667 668 set_sched_topology(x86_topology); 669 } 670 671 void set_cpu_sibling_map(int cpu) 672 { 673 bool has_smt = smp_num_siblings > 1; 674 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 675 struct cpuinfo_x86 *c = &cpu_data(cpu); 676 struct cpuinfo_x86 *o; 677 int i, threads; 678 679 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 680 681 if (!has_mp) { 682 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 683 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 684 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu)); 685 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 686 cpumask_set_cpu(cpu, topology_die_cpumask(cpu)); 687 c->booted_cores = 1; 688 return; 689 } 690 691 for_each_cpu(i, cpu_sibling_setup_mask) { 692 o = &cpu_data(i); 693 694 if (match_pkg(c, o) && !topology_same_node(c, o)) 695 x86_has_numa_in_package = true; 696 697 if ((i == cpu) || (has_smt && match_smt(c, o))) 698 link_mask(topology_sibling_cpumask, cpu, i); 699 700 if ((i == cpu) || (has_mp && match_llc(c, o))) 701 link_mask(cpu_llc_shared_mask, cpu, i); 702 703 if ((i == cpu) || (has_mp && match_l2c(c, o))) 704 link_mask(cpu_l2c_shared_mask, cpu, i); 705 706 if ((i == cpu) || (has_mp && match_die(c, o))) 707 link_mask(topology_die_cpumask, cpu, i); 708 } 709 710 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 711 if (threads > __max_smt_threads) 712 __max_smt_threads = threads; 713 714 for_each_cpu(i, topology_sibling_cpumask(cpu)) 715 cpu_data(i).smt_active = threads > 1; 716 717 /* 718 * This needs a separate iteration over the cpus because we rely on all 719 * topology_sibling_cpumask links to be set-up. 720 */ 721 for_each_cpu(i, cpu_sibling_setup_mask) { 722 o = &cpu_data(i); 723 724 if ((i == cpu) || (has_mp && match_pkg(c, o))) { 725 link_mask(topology_core_cpumask, cpu, i); 726 727 /* 728 * Does this new cpu bringup a new core? 729 */ 730 if (threads == 1) { 731 /* 732 * for each core in package, increment 733 * the booted_cores for this new cpu 734 */ 735 if (cpumask_first( 736 topology_sibling_cpumask(i)) == i) 737 c->booted_cores++; 738 /* 739 * increment the core count for all 740 * the other cpus in this package 741 */ 742 if (i != cpu) 743 cpu_data(i).booted_cores++; 744 } else if (i != cpu && !c->booted_cores) 745 c->booted_cores = cpu_data(i).booted_cores; 746 } 747 } 748 } 749 750 /* maps the cpu to the sched domain representing multi-core */ 751 const struct cpumask *cpu_coregroup_mask(int cpu) 752 { 753 return cpu_llc_shared_mask(cpu); 754 } 755 756 const struct cpumask *cpu_clustergroup_mask(int cpu) 757 { 758 return cpu_l2c_shared_mask(cpu); 759 } 760 EXPORT_SYMBOL_GPL(cpu_clustergroup_mask); 761 762 static void impress_friends(void) 763 { 764 int cpu; 765 unsigned long bogosum = 0; 766 /* 767 * Allow the user to impress friends. 768 */ 769 pr_debug("Before bogomips\n"); 770 for_each_online_cpu(cpu) 771 bogosum += cpu_data(cpu).loops_per_jiffy; 772 773 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 774 num_online_cpus(), 775 bogosum/(500000/HZ), 776 (bogosum/(5000/HZ))%100); 777 778 pr_debug("Before bogocount - setting activated=1\n"); 779 } 780 781 /* 782 * The Multiprocessor Specification 1.4 (1997) example code suggests 783 * that there should be a 10ms delay between the BSP asserting INIT 784 * and de-asserting INIT, when starting a remote processor. 785 * But that slows boot and resume on modern processors, which include 786 * many cores and don't require that delay. 787 * 788 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 789 * Modern processor families are quirked to remove the delay entirely. 790 */ 791 #define UDELAY_10MS_DEFAULT 10000 792 793 static unsigned int init_udelay = UINT_MAX; 794 795 static int __init cpu_init_udelay(char *str) 796 { 797 get_option(&str, &init_udelay); 798 799 return 0; 800 } 801 early_param("cpu_init_udelay", cpu_init_udelay); 802 803 static void __init smp_quirk_init_udelay(void) 804 { 805 /* if cmdline changed it from default, leave it alone */ 806 if (init_udelay != UINT_MAX) 807 return; 808 809 /* if modern processor, use no delay */ 810 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 811 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || 812 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 813 init_udelay = 0; 814 return; 815 } 816 /* else, use legacy delay */ 817 init_udelay = UDELAY_10MS_DEFAULT; 818 } 819 820 /* 821 * Wake up AP by INIT, INIT, STARTUP sequence. 822 */ 823 static void send_init_sequence(u32 phys_apicid) 824 { 825 int maxlvt = lapic_get_maxlvt(); 826 827 /* Be paranoid about clearing APIC errors. */ 828 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 829 /* Due to the Pentium erratum 3AP. */ 830 if (maxlvt > 3) 831 apic_write(APIC_ESR, 0); 832 apic_read(APIC_ESR); 833 } 834 835 /* Assert INIT on the target CPU */ 836 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, phys_apicid); 837 safe_apic_wait_icr_idle(); 838 839 udelay(init_udelay); 840 841 /* Deassert INIT on the target CPU */ 842 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 843 safe_apic_wait_icr_idle(); 844 } 845 846 /* 847 * Wake up AP by INIT, INIT, STARTUP sequence. 848 */ 849 static int wakeup_secondary_cpu_via_init(u32 phys_apicid, unsigned long start_eip) 850 { 851 unsigned long send_status = 0, accept_status = 0; 852 int num_starts, j, maxlvt; 853 854 preempt_disable(); 855 maxlvt = lapic_get_maxlvt(); 856 send_init_sequence(phys_apicid); 857 858 mb(); 859 860 /* 861 * Should we send STARTUP IPIs ? 862 * 863 * Determine this based on the APIC version. 864 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 865 */ 866 if (APIC_INTEGRATED(boot_cpu_apic_version)) 867 num_starts = 2; 868 else 869 num_starts = 0; 870 871 /* 872 * Run STARTUP IPI loop. 873 */ 874 pr_debug("#startup loops: %d\n", num_starts); 875 876 for (j = 1; j <= num_starts; j++) { 877 pr_debug("Sending STARTUP #%d\n", j); 878 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 879 apic_write(APIC_ESR, 0); 880 apic_read(APIC_ESR); 881 pr_debug("After apic_write\n"); 882 883 /* 884 * STARTUP IPI 885 */ 886 887 /* Target chip */ 888 /* Boot on the stack */ 889 /* Kick the second */ 890 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 891 phys_apicid); 892 893 /* 894 * Give the other CPU some time to accept the IPI. 895 */ 896 if (init_udelay == 0) 897 udelay(10); 898 else 899 udelay(300); 900 901 pr_debug("Startup point 1\n"); 902 903 pr_debug("Waiting for send to finish...\n"); 904 send_status = safe_apic_wait_icr_idle(); 905 906 /* 907 * Give the other CPU some time to accept the IPI. 908 */ 909 if (init_udelay == 0) 910 udelay(10); 911 else 912 udelay(200); 913 914 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 915 apic_write(APIC_ESR, 0); 916 accept_status = (apic_read(APIC_ESR) & 0xEF); 917 if (send_status || accept_status) 918 break; 919 } 920 pr_debug("After Startup\n"); 921 922 if (send_status) 923 pr_err("APIC never delivered???\n"); 924 if (accept_status) 925 pr_err("APIC delivery error (%lx)\n", accept_status); 926 927 preempt_enable(); 928 return (send_status | accept_status); 929 } 930 931 /* reduce the number of lines printed when booting a large cpu count system */ 932 static void announce_cpu(int cpu, int apicid) 933 { 934 static int width, node_width, first = 1; 935 static int current_node = NUMA_NO_NODE; 936 int node = early_cpu_to_node(cpu); 937 938 if (!width) 939 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 940 941 if (!node_width) 942 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 943 944 if (system_state < SYSTEM_RUNNING) { 945 if (first) 946 pr_info("x86: Booting SMP configuration:\n"); 947 948 if (node != current_node) { 949 if (current_node > (-1)) 950 pr_cont("\n"); 951 current_node = node; 952 953 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 954 node_width - num_digits(node), " ", node); 955 } 956 957 /* Add padding for the BSP */ 958 if (first) 959 pr_cont("%*s", width + 1, " "); 960 first = 0; 961 962 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 963 } else 964 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 965 node, cpu, apicid); 966 } 967 968 int common_cpu_up(unsigned int cpu, struct task_struct *idle) 969 { 970 int ret; 971 972 /* Just in case we booted with a single CPU. */ 973 alternatives_enable_smp(); 974 975 per_cpu(pcpu_hot.current_task, cpu) = idle; 976 cpu_init_stack_canary(cpu, idle); 977 978 /* Initialize the interrupt stack(s) */ 979 ret = irq_init_percpu_irqstack(cpu); 980 if (ret) 981 return ret; 982 983 #ifdef CONFIG_X86_32 984 /* Stack for startup_32 can be just as for start_secondary onwards */ 985 per_cpu(pcpu_hot.top_of_stack, cpu) = task_top_of_stack(idle); 986 #endif 987 return 0; 988 } 989 990 /* 991 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 992 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 993 * Returns zero if startup was successfully sent, else error code from 994 * ->wakeup_secondary_cpu. 995 */ 996 static int do_boot_cpu(u32 apicid, int cpu, struct task_struct *idle) 997 { 998 unsigned long start_ip = real_mode_header->trampoline_start; 999 int ret; 1000 1001 #ifdef CONFIG_X86_64 1002 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */ 1003 if (apic->wakeup_secondary_cpu_64) 1004 start_ip = real_mode_header->trampoline_start64; 1005 #endif 1006 idle->thread.sp = (unsigned long)task_pt_regs(idle); 1007 initial_code = (unsigned long)start_secondary; 1008 1009 if (IS_ENABLED(CONFIG_X86_32)) { 1010 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 1011 initial_stack = idle->thread.sp; 1012 } else if (!(smpboot_control & STARTUP_PARALLEL_MASK)) { 1013 smpboot_control = cpu; 1014 } 1015 1016 /* Enable the espfix hack for this CPU */ 1017 init_espfix_ap(cpu); 1018 1019 /* So we see what's up */ 1020 announce_cpu(cpu, apicid); 1021 1022 /* 1023 * This grunge runs the startup process for 1024 * the targeted processor. 1025 */ 1026 if (x86_platform.legacy.warm_reset) { 1027 1028 pr_debug("Setting warm reset code and vector.\n"); 1029 1030 smpboot_setup_warm_reset_vector(start_ip); 1031 /* 1032 * Be paranoid about clearing APIC errors. 1033 */ 1034 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 1035 apic_write(APIC_ESR, 0); 1036 apic_read(APIC_ESR); 1037 } 1038 } 1039 1040 smp_mb(); 1041 1042 /* 1043 * Wake up a CPU in difference cases: 1044 * - Use a method from the APIC driver if one defined, with wakeup 1045 * straight to 64-bit mode preferred over wakeup to RM. 1046 * Otherwise, 1047 * - Use an INIT boot APIC message 1048 */ 1049 if (apic->wakeup_secondary_cpu_64) 1050 ret = apic->wakeup_secondary_cpu_64(apicid, start_ip); 1051 else if (apic->wakeup_secondary_cpu) 1052 ret = apic->wakeup_secondary_cpu(apicid, start_ip); 1053 else 1054 ret = wakeup_secondary_cpu_via_init(apicid, start_ip); 1055 1056 /* If the wakeup mechanism failed, cleanup the warm reset vector */ 1057 if (ret) 1058 arch_cpuhp_cleanup_kick_cpu(cpu); 1059 return ret; 1060 } 1061 1062 int native_kick_ap(unsigned int cpu, struct task_struct *tidle) 1063 { 1064 u32 apicid = apic->cpu_present_to_apicid(cpu); 1065 int err; 1066 1067 lockdep_assert_irqs_enabled(); 1068 1069 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1070 1071 if (apicid == BAD_APICID || !physid_isset(apicid, phys_cpu_present_map) || 1072 !apic_id_valid(apicid)) { 1073 pr_err("%s: bad cpu %d\n", __func__, cpu); 1074 return -EINVAL; 1075 } 1076 1077 /* 1078 * Save current MTRR state in case it was changed since early boot 1079 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1080 */ 1081 mtrr_save_state(); 1082 1083 /* the FPU context is blank, nobody can own it */ 1084 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1085 1086 err = common_cpu_up(cpu, tidle); 1087 if (err) 1088 return err; 1089 1090 err = do_boot_cpu(apicid, cpu, tidle); 1091 if (err) 1092 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1093 1094 return err; 1095 } 1096 1097 int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *tidle) 1098 { 1099 return smp_ops.kick_ap_alive(cpu, tidle); 1100 } 1101 1102 void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu) 1103 { 1104 /* Cleanup possible dangling ends... */ 1105 if (smp_ops.kick_ap_alive == native_kick_ap && x86_platform.legacy.warm_reset) 1106 smpboot_restore_warm_reset_vector(); 1107 } 1108 1109 void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu) 1110 { 1111 if (smp_ops.cleanup_dead_cpu) 1112 smp_ops.cleanup_dead_cpu(cpu); 1113 1114 if (system_state == SYSTEM_RUNNING) 1115 pr_info("CPU %u is now offline\n", cpu); 1116 } 1117 1118 void arch_cpuhp_sync_state_poll(void) 1119 { 1120 if (smp_ops.poll_sync_state) 1121 smp_ops.poll_sync_state(); 1122 } 1123 1124 /** 1125 * arch_disable_smp_support() - Disables SMP support for x86 at boottime 1126 */ 1127 void __init arch_disable_smp_support(void) 1128 { 1129 disable_ioapic_support(); 1130 } 1131 1132 /* 1133 * Fall back to non SMP mode after errors. 1134 * 1135 * RED-PEN audit/test this more. I bet there is more state messed up here. 1136 */ 1137 static __init void disable_smp(void) 1138 { 1139 pr_info("SMP disabled\n"); 1140 1141 disable_ioapic_support(); 1142 1143 init_cpu_present(cpumask_of(0)); 1144 init_cpu_possible(cpumask_of(0)); 1145 1146 if (smp_found_config) 1147 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1148 else 1149 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1150 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1151 cpumask_set_cpu(0, topology_core_cpumask(0)); 1152 cpumask_set_cpu(0, topology_die_cpumask(0)); 1153 } 1154 1155 static void __init smp_cpu_index_default(void) 1156 { 1157 int i; 1158 struct cpuinfo_x86 *c; 1159 1160 for_each_possible_cpu(i) { 1161 c = &cpu_data(i); 1162 /* mark all to hotplug */ 1163 c->cpu_index = nr_cpu_ids; 1164 } 1165 } 1166 1167 void __init smp_prepare_cpus_common(void) 1168 { 1169 unsigned int i; 1170 1171 smp_cpu_index_default(); 1172 1173 /* 1174 * Setup boot CPU information 1175 */ 1176 smp_store_boot_cpu_info(); /* Final full version of the data */ 1177 mb(); 1178 1179 for_each_possible_cpu(i) { 1180 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1181 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1182 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL); 1183 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1184 zalloc_cpumask_var(&per_cpu(cpu_l2c_shared_map, i), GFP_KERNEL); 1185 } 1186 1187 set_cpu_sibling_map(0); 1188 } 1189 1190 #ifdef CONFIG_X86_64 1191 /* Establish whether parallel bringup can be supported. */ 1192 bool __init arch_cpuhp_init_parallel_bringup(void) 1193 { 1194 if (!x86_cpuinit.parallel_bringup) { 1195 pr_info("Parallel CPU startup disabled by the platform\n"); 1196 return false; 1197 } 1198 1199 smpboot_control = STARTUP_READ_APICID; 1200 pr_debug("Parallel CPU startup enabled: 0x%08x\n", smpboot_control); 1201 return true; 1202 } 1203 #endif 1204 1205 /* 1206 * Prepare for SMP bootup. 1207 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1208 * for common interface support. 1209 */ 1210 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1211 { 1212 smp_prepare_cpus_common(); 1213 1214 switch (apic_intr_mode) { 1215 case APIC_PIC: 1216 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1217 disable_smp(); 1218 return; 1219 case APIC_SYMMETRIC_IO_NO_ROUTING: 1220 disable_smp(); 1221 /* Setup local timer */ 1222 x86_init.timers.setup_percpu_clockev(); 1223 return; 1224 case APIC_VIRTUAL_WIRE: 1225 case APIC_SYMMETRIC_IO: 1226 break; 1227 } 1228 1229 /* Setup local timer */ 1230 x86_init.timers.setup_percpu_clockev(); 1231 1232 pr_info("CPU0: "); 1233 print_cpu_info(&cpu_data(0)); 1234 1235 uv_system_init(); 1236 1237 smp_quirk_init_udelay(); 1238 1239 speculative_store_bypass_ht_init(); 1240 1241 snp_set_wakeup_secondary_cpu(); 1242 } 1243 1244 void arch_thaw_secondary_cpus_begin(void) 1245 { 1246 set_cache_aps_delayed_init(true); 1247 } 1248 1249 void arch_thaw_secondary_cpus_end(void) 1250 { 1251 cache_aps_init(); 1252 } 1253 1254 /* 1255 * Early setup to make printk work. 1256 */ 1257 void __init native_smp_prepare_boot_cpu(void) 1258 { 1259 int me = smp_processor_id(); 1260 1261 /* SMP handles this from setup_per_cpu_areas() */ 1262 if (!IS_ENABLED(CONFIG_SMP)) 1263 switch_gdt_and_percpu_base(me); 1264 1265 native_pv_lock_init(); 1266 } 1267 1268 void __init calculate_max_logical_packages(void) 1269 { 1270 int ncpus; 1271 1272 /* 1273 * Today neither Intel nor AMD support heterogeneous systems so 1274 * extrapolate the boot cpu's data to all packages. 1275 */ 1276 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); 1277 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); 1278 pr_info("Max logical packages: %u\n", __max_logical_packages); 1279 } 1280 1281 void __init native_smp_cpus_done(unsigned int max_cpus) 1282 { 1283 pr_debug("Boot done\n"); 1284 1285 calculate_max_logical_packages(); 1286 build_sched_topology(); 1287 nmi_selftest(); 1288 impress_friends(); 1289 cache_aps_init(); 1290 } 1291 1292 static int __initdata setup_possible_cpus = -1; 1293 static int __init _setup_possible_cpus(char *str) 1294 { 1295 get_option(&str, &setup_possible_cpus); 1296 return 0; 1297 } 1298 early_param("possible_cpus", _setup_possible_cpus); 1299 1300 1301 /* 1302 * cpu_possible_mask should be static, it cannot change as cpu's 1303 * are onlined, or offlined. The reason is per-cpu data-structures 1304 * are allocated by some modules at init time, and don't expect to 1305 * do this dynamically on cpu arrival/departure. 1306 * cpu_present_mask on the other hand can change dynamically. 1307 * In case when cpu_hotplug is not compiled, then we resort to current 1308 * behaviour, which is cpu_possible == cpu_present. 1309 * - Ashok Raj 1310 * 1311 * Three ways to find out the number of additional hotplug CPUs: 1312 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1313 * - The user can overwrite it with possible_cpus=NUM 1314 * - Otherwise don't reserve additional CPUs. 1315 * We do this because additional CPUs waste a lot of memory. 1316 * -AK 1317 */ 1318 __init void prefill_possible_map(void) 1319 { 1320 int i, possible; 1321 1322 i = setup_max_cpus ?: 1; 1323 if (setup_possible_cpus == -1) { 1324 possible = num_processors; 1325 #ifdef CONFIG_HOTPLUG_CPU 1326 if (setup_max_cpus) 1327 possible += disabled_cpus; 1328 #else 1329 if (possible > i) 1330 possible = i; 1331 #endif 1332 } else 1333 possible = setup_possible_cpus; 1334 1335 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1336 1337 /* nr_cpu_ids could be reduced via nr_cpus= */ 1338 if (possible > nr_cpu_ids) { 1339 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", 1340 possible, nr_cpu_ids); 1341 possible = nr_cpu_ids; 1342 } 1343 1344 #ifdef CONFIG_HOTPLUG_CPU 1345 if (!setup_max_cpus) 1346 #endif 1347 if (possible > i) { 1348 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1349 possible, setup_max_cpus); 1350 possible = i; 1351 } 1352 1353 set_nr_cpu_ids(possible); 1354 1355 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1356 possible, max_t(int, possible - num_processors, 0)); 1357 1358 reset_cpu_possible_mask(); 1359 1360 for (i = 0; i < possible; i++) 1361 set_cpu_possible(i, true); 1362 } 1363 1364 /* correctly size the local cpu masks */ 1365 void __init setup_cpu_local_masks(void) 1366 { 1367 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 1368 } 1369 1370 #ifdef CONFIG_HOTPLUG_CPU 1371 1372 /* Recompute SMT state for all CPUs on offline */ 1373 static void recompute_smt_state(void) 1374 { 1375 int max_threads, cpu; 1376 1377 max_threads = 0; 1378 for_each_online_cpu (cpu) { 1379 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1380 1381 if (threads > max_threads) 1382 max_threads = threads; 1383 } 1384 __max_smt_threads = max_threads; 1385 } 1386 1387 static void remove_siblinginfo(int cpu) 1388 { 1389 int sibling; 1390 struct cpuinfo_x86 *c = &cpu_data(cpu); 1391 1392 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1393 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1394 /*/ 1395 * last thread sibling in this cpu core going down 1396 */ 1397 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1398 cpu_data(sibling).booted_cores--; 1399 } 1400 1401 for_each_cpu(sibling, topology_die_cpumask(cpu)) 1402 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling)); 1403 1404 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) { 1405 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1406 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1) 1407 cpu_data(sibling).smt_active = false; 1408 } 1409 1410 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1411 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1412 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu)) 1413 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling)); 1414 cpumask_clear(cpu_llc_shared_mask(cpu)); 1415 cpumask_clear(cpu_l2c_shared_mask(cpu)); 1416 cpumask_clear(topology_sibling_cpumask(cpu)); 1417 cpumask_clear(topology_core_cpumask(cpu)); 1418 cpumask_clear(topology_die_cpumask(cpu)); 1419 c->topo.core_id = 0; 1420 c->booted_cores = 0; 1421 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1422 recompute_smt_state(); 1423 } 1424 1425 static void remove_cpu_from_maps(int cpu) 1426 { 1427 set_cpu_online(cpu, false); 1428 numa_remove_cpu(cpu); 1429 } 1430 1431 void cpu_disable_common(void) 1432 { 1433 int cpu = smp_processor_id(); 1434 1435 remove_siblinginfo(cpu); 1436 1437 /* It's now safe to remove this processor from the online map */ 1438 lock_vector_lock(); 1439 remove_cpu_from_maps(cpu); 1440 unlock_vector_lock(); 1441 fixup_irqs(); 1442 lapic_offline(); 1443 } 1444 1445 int native_cpu_disable(void) 1446 { 1447 int ret; 1448 1449 ret = lapic_can_unplug_cpu(); 1450 if (ret) 1451 return ret; 1452 1453 cpu_disable_common(); 1454 1455 /* 1456 * Disable the local APIC. Otherwise IPI broadcasts will reach 1457 * it. It still responds normally to INIT, NMI, SMI, and SIPI 1458 * messages. 1459 * 1460 * Disabling the APIC must happen after cpu_disable_common() 1461 * which invokes fixup_irqs(). 1462 * 1463 * Disabling the APIC preserves already set bits in IRR, but 1464 * an interrupt arriving after disabling the local APIC does not 1465 * set the corresponding IRR bit. 1466 * 1467 * fixup_irqs() scans IRR for set bits so it can raise a not 1468 * yet handled interrupt on the new destination CPU via an IPI 1469 * but obviously it can't do so for IRR bits which are not set. 1470 * IOW, interrupts arriving after disabling the local APIC will 1471 * be lost. 1472 */ 1473 apic_soft_disable(); 1474 1475 return 0; 1476 } 1477 1478 void play_dead_common(void) 1479 { 1480 idle_task_exit(); 1481 1482 cpuhp_ap_report_dead(); 1483 1484 local_irq_disable(); 1485 } 1486 1487 /* 1488 * We need to flush the caches before going to sleep, lest we have 1489 * dirty data in our caches when we come back up. 1490 */ 1491 static inline void mwait_play_dead(void) 1492 { 1493 struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead); 1494 unsigned int eax, ebx, ecx, edx; 1495 unsigned int highest_cstate = 0; 1496 unsigned int highest_subcstate = 0; 1497 int i; 1498 1499 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1500 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 1501 return; 1502 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1503 return; 1504 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1505 return; 1506 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1507 return; 1508 1509 eax = CPUID_MWAIT_LEAF; 1510 ecx = 0; 1511 native_cpuid(&eax, &ebx, &ecx, &edx); 1512 1513 /* 1514 * eax will be 0 if EDX enumeration is not valid. 1515 * Initialized below to cstate, sub_cstate value when EDX is valid. 1516 */ 1517 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1518 eax = 0; 1519 } else { 1520 edx >>= MWAIT_SUBSTATE_SIZE; 1521 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1522 if (edx & MWAIT_SUBSTATE_MASK) { 1523 highest_cstate = i; 1524 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1525 } 1526 } 1527 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1528 (highest_subcstate - 1); 1529 } 1530 1531 /* Set up state for the kexec() hack below */ 1532 md->status = CPUDEAD_MWAIT_WAIT; 1533 md->control = CPUDEAD_MWAIT_WAIT; 1534 1535 wbinvd(); 1536 1537 while (1) { 1538 /* 1539 * The CLFLUSH is a workaround for erratum AAI65 for 1540 * the Xeon 7400 series. It's not clear it is actually 1541 * needed, but it should be harmless in either case. 1542 * The WBINVD is insufficient due to the spurious-wakeup 1543 * case where we return around the loop. 1544 */ 1545 mb(); 1546 clflush(md); 1547 mb(); 1548 __monitor(md, 0, 0); 1549 mb(); 1550 __mwait(eax, 0); 1551 1552 if (READ_ONCE(md->control) == CPUDEAD_MWAIT_KEXEC_HLT) { 1553 /* 1554 * Kexec is about to happen. Don't go back into mwait() as 1555 * the kexec kernel might overwrite text and data including 1556 * page tables and stack. So mwait() would resume when the 1557 * monitor cache line is written to and then the CPU goes 1558 * south due to overwritten text, page tables and stack. 1559 * 1560 * Note: This does _NOT_ protect against a stray MCE, NMI, 1561 * SMI. They will resume execution at the instruction 1562 * following the HLT instruction and run into the problem 1563 * which this is trying to prevent. 1564 */ 1565 WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT); 1566 while(1) 1567 native_halt(); 1568 } 1569 } 1570 } 1571 1572 /* 1573 * Kick all "offline" CPUs out of mwait on kexec(). See comment in 1574 * mwait_play_dead(). 1575 */ 1576 void smp_kick_mwait_play_dead(void) 1577 { 1578 u32 newstate = CPUDEAD_MWAIT_KEXEC_HLT; 1579 struct mwait_cpu_dead *md; 1580 unsigned int cpu, i; 1581 1582 for_each_cpu_andnot(cpu, cpu_present_mask, cpu_online_mask) { 1583 md = per_cpu_ptr(&mwait_cpu_dead, cpu); 1584 1585 /* Does it sit in mwait_play_dead() ? */ 1586 if (READ_ONCE(md->status) != CPUDEAD_MWAIT_WAIT) 1587 continue; 1588 1589 /* Wait up to 5ms */ 1590 for (i = 0; READ_ONCE(md->status) != newstate && i < 1000; i++) { 1591 /* Bring it out of mwait */ 1592 WRITE_ONCE(md->control, newstate); 1593 udelay(5); 1594 } 1595 1596 if (READ_ONCE(md->status) != newstate) 1597 pr_err_once("CPU%u is stuck in mwait_play_dead()\n", cpu); 1598 } 1599 } 1600 1601 void __noreturn hlt_play_dead(void) 1602 { 1603 if (__this_cpu_read(cpu_info.x86) >= 4) 1604 wbinvd(); 1605 1606 while (1) 1607 native_halt(); 1608 } 1609 1610 /* 1611 * native_play_dead() is essentially a __noreturn function, but it can't 1612 * be marked as such as the compiler may complain about it. 1613 */ 1614 void native_play_dead(void) 1615 { 1616 if (cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS)) 1617 __update_spec_ctrl(0); 1618 1619 play_dead_common(); 1620 tboot_shutdown(TB_SHUTDOWN_WFS); 1621 1622 mwait_play_dead(); 1623 if (cpuidle_play_dead()) 1624 hlt_play_dead(); 1625 } 1626 1627 #else /* ... !CONFIG_HOTPLUG_CPU */ 1628 int native_cpu_disable(void) 1629 { 1630 return -ENOSYS; 1631 } 1632 1633 void native_play_dead(void) 1634 { 1635 BUG(); 1636 } 1637 1638 #endif 1639