1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 43 44 #include <linux/init.h> 45 #include <linux/smp.h> 46 #include <linux/export.h> 47 #include <linux/sched.h> 48 #include <linux/sched/topology.h> 49 #include <linux/sched/hotplug.h> 50 #include <linux/sched/task_stack.h> 51 #include <linux/percpu.h> 52 #include <linux/bootmem.h> 53 #include <linux/err.h> 54 #include <linux/nmi.h> 55 #include <linux/tboot.h> 56 #include <linux/stackprotector.h> 57 #include <linux/gfp.h> 58 #include <linux/cpuidle.h> 59 60 #include <asm/acpi.h> 61 #include <asm/desc.h> 62 #include <asm/nmi.h> 63 #include <asm/irq.h> 64 #include <asm/realmode.h> 65 #include <asm/cpu.h> 66 #include <asm/numa.h> 67 #include <asm/pgtable.h> 68 #include <asm/tlbflush.h> 69 #include <asm/mtrr.h> 70 #include <asm/mwait.h> 71 #include <asm/apic.h> 72 #include <asm/io_apic.h> 73 #include <asm/fpu/internal.h> 74 #include <asm/setup.h> 75 #include <asm/uv/uv.h> 76 #include <linux/mc146818rtc.h> 77 #include <asm/i8259.h> 78 #include <asm/realmode.h> 79 #include <asm/misc.h> 80 #include <asm/qspinlock.h> 81 82 /* Number of siblings per CPU package */ 83 int smp_num_siblings = 1; 84 EXPORT_SYMBOL(smp_num_siblings); 85 86 /* Last level cache ID of each logical CPU */ 87 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 88 89 /* representing HT siblings of each logical CPU */ 90 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 91 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 92 93 /* representing HT and core siblings of each logical CPU */ 94 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 95 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 96 97 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); 98 99 /* Per CPU bogomips and other parameters */ 100 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 101 EXPORT_PER_CPU_SYMBOL(cpu_info); 102 103 /* Logical package management. We might want to allocate that dynamically */ 104 static int *physical_to_logical_pkg __read_mostly; 105 static unsigned long *physical_package_map __read_mostly;; 106 static unsigned int max_physical_pkg_id __read_mostly; 107 unsigned int __max_logical_packages __read_mostly; 108 EXPORT_SYMBOL(__max_logical_packages); 109 static unsigned int logical_packages __read_mostly; 110 111 /* Maximum number of SMT threads on any online core */ 112 int __max_smt_threads __read_mostly; 113 114 /* Flag to indicate if a complete sched domain rebuild is required */ 115 bool x86_topology_update; 116 117 int arch_update_cpu_topology(void) 118 { 119 int retval = x86_topology_update; 120 121 x86_topology_update = false; 122 return retval; 123 } 124 125 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 126 { 127 unsigned long flags; 128 129 spin_lock_irqsave(&rtc_lock, flags); 130 CMOS_WRITE(0xa, 0xf); 131 spin_unlock_irqrestore(&rtc_lock, flags); 132 local_flush_tlb(); 133 pr_debug("1.\n"); 134 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = 135 start_eip >> 4; 136 pr_debug("2.\n"); 137 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 138 start_eip & 0xf; 139 pr_debug("3.\n"); 140 } 141 142 static inline void smpboot_restore_warm_reset_vector(void) 143 { 144 unsigned long flags; 145 146 /* 147 * Install writable page 0 entry to set BIOS data area. 148 */ 149 local_flush_tlb(); 150 151 /* 152 * Paranoid: Set warm reset code and vector here back 153 * to default values. 154 */ 155 spin_lock_irqsave(&rtc_lock, flags); 156 CMOS_WRITE(0, 0xf); 157 spin_unlock_irqrestore(&rtc_lock, flags); 158 159 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 160 } 161 162 /* 163 * Report back to the Boot Processor during boot time or to the caller processor 164 * during CPU online. 165 */ 166 static void smp_callin(void) 167 { 168 int cpuid, phys_id; 169 170 /* 171 * If waken up by an INIT in an 82489DX configuration 172 * cpu_callout_mask guarantees we don't get here before 173 * an INIT_deassert IPI reaches our local APIC, so it is 174 * now safe to touch our local APIC. 175 */ 176 cpuid = smp_processor_id(); 177 178 /* 179 * (This works even if the APIC is not enabled.) 180 */ 181 phys_id = read_apic_id(); 182 183 /* 184 * the boot CPU has finished the init stage and is spinning 185 * on callin_map until we finish. We are free to set up this 186 * CPU, first the APIC. (this is probably redundant on most 187 * boards) 188 */ 189 apic_ap_setup(); 190 191 /* 192 * Save our processor parameters. Note: this information 193 * is needed for clock calibration. 194 */ 195 smp_store_cpu_info(cpuid); 196 197 /* 198 * The topology information must be up to date before 199 * calibrate_delay() and notify_cpu_starting(). 200 */ 201 set_cpu_sibling_map(raw_smp_processor_id()); 202 203 /* 204 * Get our bogomips. 205 * Update loops_per_jiffy in cpu_data. Previous call to 206 * smp_store_cpu_info() stored a value that is close but not as 207 * accurate as the value just calculated. 208 */ 209 calibrate_delay(); 210 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 211 pr_debug("Stack at about %p\n", &cpuid); 212 213 wmb(); 214 215 notify_cpu_starting(cpuid); 216 217 /* 218 * Allow the master to continue. 219 */ 220 cpumask_set_cpu(cpuid, cpu_callin_mask); 221 } 222 223 static int cpu0_logical_apicid; 224 static int enable_start_cpu0; 225 /* 226 * Activate a secondary processor. 227 */ 228 static void notrace start_secondary(void *unused) 229 { 230 /* 231 * Don't put *anything* except direct CPU state initialization 232 * before cpu_init(), SMP booting is too fragile that we want to 233 * limit the things done here to the most necessary things. 234 */ 235 if (boot_cpu_has(X86_FEATURE_PCID)) 236 __write_cr4(__read_cr4() | X86_CR4_PCIDE); 237 238 #ifdef CONFIG_X86_32 239 /* switch away from the initial page table */ 240 load_cr3(swapper_pg_dir); 241 __flush_tlb_all(); 242 #endif 243 244 cpu_init(); 245 x86_cpuinit.early_percpu_clock_init(); 246 preempt_disable(); 247 smp_callin(); 248 249 enable_start_cpu0 = 0; 250 251 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 252 barrier(); 253 /* 254 * Check TSC synchronization with the BP: 255 */ 256 check_tsc_sync_target(); 257 258 /* 259 * Lock vector_lock and initialize the vectors on this cpu 260 * before setting the cpu online. We must set it online with 261 * vector_lock held to prevent a concurrent setup/teardown 262 * from seeing a half valid vector space. 263 */ 264 lock_vector_lock(); 265 setup_vector_irq(smp_processor_id()); 266 set_cpu_online(smp_processor_id(), true); 267 unlock_vector_lock(); 268 cpu_set_state_online(smp_processor_id()); 269 x86_platform.nmi_init(); 270 271 /* enable local interrupts */ 272 local_irq_enable(); 273 274 /* to prevent fake stack check failure in clock setup */ 275 boot_init_stack_canary(); 276 277 x86_cpuinit.setup_percpu_clockev(); 278 279 wmb(); 280 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 281 } 282 283 /** 284 * topology_update_package_map - Update the physical to logical package map 285 * @pkg: The physical package id as retrieved via CPUID 286 * @cpu: The cpu for which this is updated 287 */ 288 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 289 { 290 unsigned int new; 291 292 /* Called from early boot ? */ 293 if (!physical_package_map) 294 return 0; 295 296 if (pkg >= max_physical_pkg_id) 297 return -EINVAL; 298 299 /* Set the logical package id */ 300 if (test_and_set_bit(pkg, physical_package_map)) 301 goto found; 302 303 if (logical_packages >= __max_logical_packages) { 304 pr_warn("Package %u of CPU %u exceeds BIOS package data %u.\n", 305 logical_packages, cpu, __max_logical_packages); 306 return -ENOSPC; 307 } 308 309 new = logical_packages++; 310 if (new != pkg) { 311 pr_info("CPU %u Converting physical %u to logical package %u\n", 312 cpu, pkg, new); 313 } 314 physical_to_logical_pkg[pkg] = new; 315 316 found: 317 cpu_data(cpu).logical_proc_id = physical_to_logical_pkg[pkg]; 318 return 0; 319 } 320 321 /** 322 * topology_phys_to_logical_pkg - Map a physical package id to a logical 323 * 324 * Returns logical package id or -1 if not found 325 */ 326 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 327 { 328 if (phys_pkg >= max_physical_pkg_id) 329 return -1; 330 return physical_to_logical_pkg[phys_pkg]; 331 } 332 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 333 334 static void __init smp_init_package_map(struct cpuinfo_x86 *c, unsigned int cpu) 335 { 336 unsigned int ncpus; 337 size_t size; 338 339 /* 340 * Today neither Intel nor AMD support heterogenous systems. That 341 * might change in the future.... 342 * 343 * While ideally we'd want '* smp_num_siblings' in the below @ncpus 344 * computation, this won't actually work since some Intel BIOSes 345 * report inconsistent HT data when they disable HT. 346 * 347 * In particular, they reduce the APIC-IDs to only include the cores, 348 * but leave the CPUID topology to say there are (2) siblings. 349 * This means we don't know how many threads there will be until 350 * after the APIC enumeration. 351 * 352 * By not including this we'll sometimes over-estimate the number of 353 * logical packages by the amount of !present siblings, but this is 354 * still better than MAX_LOCAL_APIC. 355 * 356 * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited 357 * on the command line leading to a similar issue as the HT disable 358 * problem because the hyperthreads are usually enumerated after the 359 * primary cores. 360 */ 361 ncpus = boot_cpu_data.x86_max_cores; 362 if (!ncpus) { 363 pr_warn("x86_max_cores == zero !?!?"); 364 ncpus = 1; 365 } 366 367 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); 368 logical_packages = 0; 369 370 /* 371 * Possibly larger than what we need as the number of apic ids per 372 * package can be smaller than the actual used apic ids. 373 */ 374 max_physical_pkg_id = DIV_ROUND_UP(MAX_LOCAL_APIC, ncpus); 375 size = max_physical_pkg_id * sizeof(unsigned int); 376 physical_to_logical_pkg = kmalloc(size, GFP_KERNEL); 377 memset(physical_to_logical_pkg, 0xff, size); 378 size = BITS_TO_LONGS(max_physical_pkg_id) * sizeof(unsigned long); 379 physical_package_map = kzalloc(size, GFP_KERNEL); 380 381 pr_info("Max logical packages: %u\n", __max_logical_packages); 382 383 topology_update_package_map(c->phys_proc_id, cpu); 384 } 385 386 void __init smp_store_boot_cpu_info(void) 387 { 388 int id = 0; /* CPU 0 */ 389 struct cpuinfo_x86 *c = &cpu_data(id); 390 391 *c = boot_cpu_data; 392 c->cpu_index = id; 393 smp_init_package_map(c, id); 394 } 395 396 /* 397 * The bootstrap kernel entry code has set these up. Save them for 398 * a given CPU 399 */ 400 void smp_store_cpu_info(int id) 401 { 402 struct cpuinfo_x86 *c = &cpu_data(id); 403 404 *c = boot_cpu_data; 405 c->cpu_index = id; 406 /* 407 * During boot time, CPU0 has this setup already. Save the info when 408 * bringing up AP or offlined CPU0. 409 */ 410 identify_secondary_cpu(c); 411 } 412 413 static bool 414 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 415 { 416 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 417 418 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 419 } 420 421 static bool 422 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 423 { 424 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 425 426 return !WARN_ONCE(!topology_same_node(c, o), 427 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 428 "[node: %d != %d]. Ignoring dependency.\n", 429 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 430 } 431 432 #define link_mask(mfunc, c1, c2) \ 433 do { \ 434 cpumask_set_cpu((c1), mfunc(c2)); \ 435 cpumask_set_cpu((c2), mfunc(c1)); \ 436 } while (0) 437 438 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 439 { 440 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 441 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 442 443 if (c->phys_proc_id == o->phys_proc_id && 444 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { 445 if (c->cpu_core_id == o->cpu_core_id) 446 return topology_sane(c, o, "smt"); 447 448 if ((c->cu_id != 0xff) && 449 (o->cu_id != 0xff) && 450 (c->cu_id == o->cu_id)) 451 return topology_sane(c, o, "smt"); 452 } 453 454 } else if (c->phys_proc_id == o->phys_proc_id && 455 c->cpu_core_id == o->cpu_core_id) { 456 return topology_sane(c, o, "smt"); 457 } 458 459 return false; 460 } 461 462 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 463 { 464 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 465 466 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && 467 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) 468 return topology_sane(c, o, "llc"); 469 470 return false; 471 } 472 473 /* 474 * Unlike the other levels, we do not enforce keeping a 475 * multicore group inside a NUMA node. If this happens, we will 476 * discard the MC level of the topology later. 477 */ 478 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 479 { 480 if (c->phys_proc_id == o->phys_proc_id) 481 return true; 482 return false; 483 } 484 485 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC) 486 static inline int x86_sched_itmt_flags(void) 487 { 488 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 489 } 490 491 #ifdef CONFIG_SCHED_MC 492 static int x86_core_flags(void) 493 { 494 return cpu_core_flags() | x86_sched_itmt_flags(); 495 } 496 #endif 497 #ifdef CONFIG_SCHED_SMT 498 static int x86_smt_flags(void) 499 { 500 return cpu_smt_flags() | x86_sched_itmt_flags(); 501 } 502 #endif 503 #endif 504 505 static struct sched_domain_topology_level x86_numa_in_package_topology[] = { 506 #ifdef CONFIG_SCHED_SMT 507 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 508 #endif 509 #ifdef CONFIG_SCHED_MC 510 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 511 #endif 512 { NULL, }, 513 }; 514 515 static struct sched_domain_topology_level x86_topology[] = { 516 #ifdef CONFIG_SCHED_SMT 517 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 518 #endif 519 #ifdef CONFIG_SCHED_MC 520 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 521 #endif 522 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 523 { NULL, }, 524 }; 525 526 /* 527 * Set if a package/die has multiple NUMA nodes inside. 528 * AMD Magny-Cours and Intel Cluster-on-Die have this. 529 */ 530 static bool x86_has_numa_in_package; 531 532 void set_cpu_sibling_map(int cpu) 533 { 534 bool has_smt = smp_num_siblings > 1; 535 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 536 struct cpuinfo_x86 *c = &cpu_data(cpu); 537 struct cpuinfo_x86 *o; 538 int i, threads; 539 540 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 541 542 if (!has_mp) { 543 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 544 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 545 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 546 c->booted_cores = 1; 547 return; 548 } 549 550 for_each_cpu(i, cpu_sibling_setup_mask) { 551 o = &cpu_data(i); 552 553 if ((i == cpu) || (has_smt && match_smt(c, o))) 554 link_mask(topology_sibling_cpumask, cpu, i); 555 556 if ((i == cpu) || (has_mp && match_llc(c, o))) 557 link_mask(cpu_llc_shared_mask, cpu, i); 558 559 } 560 561 /* 562 * This needs a separate iteration over the cpus because we rely on all 563 * topology_sibling_cpumask links to be set-up. 564 */ 565 for_each_cpu(i, cpu_sibling_setup_mask) { 566 o = &cpu_data(i); 567 568 if ((i == cpu) || (has_mp && match_die(c, o))) { 569 link_mask(topology_core_cpumask, cpu, i); 570 571 /* 572 * Does this new cpu bringup a new core? 573 */ 574 if (cpumask_weight( 575 topology_sibling_cpumask(cpu)) == 1) { 576 /* 577 * for each core in package, increment 578 * the booted_cores for this new cpu 579 */ 580 if (cpumask_first( 581 topology_sibling_cpumask(i)) == i) 582 c->booted_cores++; 583 /* 584 * increment the core count for all 585 * the other cpus in this package 586 */ 587 if (i != cpu) 588 cpu_data(i).booted_cores++; 589 } else if (i != cpu && !c->booted_cores) 590 c->booted_cores = cpu_data(i).booted_cores; 591 } 592 if (match_die(c, o) && !topology_same_node(c, o)) 593 x86_has_numa_in_package = true; 594 } 595 596 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 597 if (threads > __max_smt_threads) 598 __max_smt_threads = threads; 599 } 600 601 /* maps the cpu to the sched domain representing multi-core */ 602 const struct cpumask *cpu_coregroup_mask(int cpu) 603 { 604 return cpu_llc_shared_mask(cpu); 605 } 606 607 static void impress_friends(void) 608 { 609 int cpu; 610 unsigned long bogosum = 0; 611 /* 612 * Allow the user to impress friends. 613 */ 614 pr_debug("Before bogomips\n"); 615 for_each_possible_cpu(cpu) 616 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 617 bogosum += cpu_data(cpu).loops_per_jiffy; 618 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 619 num_online_cpus(), 620 bogosum/(500000/HZ), 621 (bogosum/(5000/HZ))%100); 622 623 pr_debug("Before bogocount - setting activated=1\n"); 624 } 625 626 void __inquire_remote_apic(int apicid) 627 { 628 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 629 const char * const names[] = { "ID", "VERSION", "SPIV" }; 630 int timeout; 631 u32 status; 632 633 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 634 635 for (i = 0; i < ARRAY_SIZE(regs); i++) { 636 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 637 638 /* 639 * Wait for idle. 640 */ 641 status = safe_apic_wait_icr_idle(); 642 if (status) 643 pr_cont("a previous APIC delivery may have failed\n"); 644 645 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 646 647 timeout = 0; 648 do { 649 udelay(100); 650 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 651 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 652 653 switch (status) { 654 case APIC_ICR_RR_VALID: 655 status = apic_read(APIC_RRR); 656 pr_cont("%08x\n", status); 657 break; 658 default: 659 pr_cont("failed\n"); 660 } 661 } 662 } 663 664 /* 665 * The Multiprocessor Specification 1.4 (1997) example code suggests 666 * that there should be a 10ms delay between the BSP asserting INIT 667 * and de-asserting INIT, when starting a remote processor. 668 * But that slows boot and resume on modern processors, which include 669 * many cores and don't require that delay. 670 * 671 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 672 * Modern processor families are quirked to remove the delay entirely. 673 */ 674 #define UDELAY_10MS_DEFAULT 10000 675 676 static unsigned int init_udelay = UINT_MAX; 677 678 static int __init cpu_init_udelay(char *str) 679 { 680 get_option(&str, &init_udelay); 681 682 return 0; 683 } 684 early_param("cpu_init_udelay", cpu_init_udelay); 685 686 static void __init smp_quirk_init_udelay(void) 687 { 688 /* if cmdline changed it from default, leave it alone */ 689 if (init_udelay != UINT_MAX) 690 return; 691 692 /* if modern processor, use no delay */ 693 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 694 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 695 init_udelay = 0; 696 return; 697 } 698 /* else, use legacy delay */ 699 init_udelay = UDELAY_10MS_DEFAULT; 700 } 701 702 /* 703 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 704 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 705 * won't ... remember to clear down the APIC, etc later. 706 */ 707 int 708 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 709 { 710 unsigned long send_status, accept_status = 0; 711 int maxlvt; 712 713 /* Target chip */ 714 /* Boot on the stack */ 715 /* Kick the second */ 716 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); 717 718 pr_debug("Waiting for send to finish...\n"); 719 send_status = safe_apic_wait_icr_idle(); 720 721 /* 722 * Give the other CPU some time to accept the IPI. 723 */ 724 udelay(200); 725 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 726 maxlvt = lapic_get_maxlvt(); 727 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 728 apic_write(APIC_ESR, 0); 729 accept_status = (apic_read(APIC_ESR) & 0xEF); 730 } 731 pr_debug("NMI sent\n"); 732 733 if (send_status) 734 pr_err("APIC never delivered???\n"); 735 if (accept_status) 736 pr_err("APIC delivery error (%lx)\n", accept_status); 737 738 return (send_status | accept_status); 739 } 740 741 static int 742 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 743 { 744 unsigned long send_status = 0, accept_status = 0; 745 int maxlvt, num_starts, j; 746 747 maxlvt = lapic_get_maxlvt(); 748 749 /* 750 * Be paranoid about clearing APIC errors. 751 */ 752 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 753 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 754 apic_write(APIC_ESR, 0); 755 apic_read(APIC_ESR); 756 } 757 758 pr_debug("Asserting INIT\n"); 759 760 /* 761 * Turn INIT on target chip 762 */ 763 /* 764 * Send IPI 765 */ 766 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 767 phys_apicid); 768 769 pr_debug("Waiting for send to finish...\n"); 770 send_status = safe_apic_wait_icr_idle(); 771 772 udelay(init_udelay); 773 774 pr_debug("Deasserting INIT\n"); 775 776 /* Target chip */ 777 /* Send IPI */ 778 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 779 780 pr_debug("Waiting for send to finish...\n"); 781 send_status = safe_apic_wait_icr_idle(); 782 783 mb(); 784 785 /* 786 * Should we send STARTUP IPIs ? 787 * 788 * Determine this based on the APIC version. 789 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 790 */ 791 if (APIC_INTEGRATED(boot_cpu_apic_version)) 792 num_starts = 2; 793 else 794 num_starts = 0; 795 796 /* 797 * Run STARTUP IPI loop. 798 */ 799 pr_debug("#startup loops: %d\n", num_starts); 800 801 for (j = 1; j <= num_starts; j++) { 802 pr_debug("Sending STARTUP #%d\n", j); 803 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 804 apic_write(APIC_ESR, 0); 805 apic_read(APIC_ESR); 806 pr_debug("After apic_write\n"); 807 808 /* 809 * STARTUP IPI 810 */ 811 812 /* Target chip */ 813 /* Boot on the stack */ 814 /* Kick the second */ 815 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 816 phys_apicid); 817 818 /* 819 * Give the other CPU some time to accept the IPI. 820 */ 821 if (init_udelay == 0) 822 udelay(10); 823 else 824 udelay(300); 825 826 pr_debug("Startup point 1\n"); 827 828 pr_debug("Waiting for send to finish...\n"); 829 send_status = safe_apic_wait_icr_idle(); 830 831 /* 832 * Give the other CPU some time to accept the IPI. 833 */ 834 if (init_udelay == 0) 835 udelay(10); 836 else 837 udelay(200); 838 839 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 840 apic_write(APIC_ESR, 0); 841 accept_status = (apic_read(APIC_ESR) & 0xEF); 842 if (send_status || accept_status) 843 break; 844 } 845 pr_debug("After Startup\n"); 846 847 if (send_status) 848 pr_err("APIC never delivered???\n"); 849 if (accept_status) 850 pr_err("APIC delivery error (%lx)\n", accept_status); 851 852 return (send_status | accept_status); 853 } 854 855 /* reduce the number of lines printed when booting a large cpu count system */ 856 static void announce_cpu(int cpu, int apicid) 857 { 858 static int current_node = -1; 859 int node = early_cpu_to_node(cpu); 860 static int width, node_width; 861 862 if (!width) 863 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 864 865 if (!node_width) 866 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 867 868 if (cpu == 1) 869 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 870 871 if (system_state < SYSTEM_RUNNING) { 872 if (node != current_node) { 873 if (current_node > (-1)) 874 pr_cont("\n"); 875 current_node = node; 876 877 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 878 node_width - num_digits(node), " ", node); 879 } 880 881 /* Add padding for the BSP */ 882 if (cpu == 1) 883 pr_cont("%*s", width + 1, " "); 884 885 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 886 887 } else 888 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 889 node, cpu, apicid); 890 } 891 892 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 893 { 894 int cpu; 895 896 cpu = smp_processor_id(); 897 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 898 return NMI_HANDLED; 899 900 return NMI_DONE; 901 } 902 903 /* 904 * Wake up AP by INIT, INIT, STARTUP sequence. 905 * 906 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 907 * boot-strap code which is not a desired behavior for waking up BSP. To 908 * void the boot-strap code, wake up CPU0 by NMI instead. 909 * 910 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 911 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 912 * We'll change this code in the future to wake up hard offlined CPU0 if 913 * real platform and request are available. 914 */ 915 static int 916 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 917 int *cpu0_nmi_registered) 918 { 919 int id; 920 int boot_error; 921 922 preempt_disable(); 923 924 /* 925 * Wake up AP by INIT, INIT, STARTUP sequence. 926 */ 927 if (cpu) { 928 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 929 goto out; 930 } 931 932 /* 933 * Wake up BSP by nmi. 934 * 935 * Register a NMI handler to help wake up CPU0. 936 */ 937 boot_error = register_nmi_handler(NMI_LOCAL, 938 wakeup_cpu0_nmi, 0, "wake_cpu0"); 939 940 if (!boot_error) { 941 enable_start_cpu0 = 1; 942 *cpu0_nmi_registered = 1; 943 if (apic->dest_logical == APIC_DEST_LOGICAL) 944 id = cpu0_logical_apicid; 945 else 946 id = apicid; 947 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 948 } 949 950 out: 951 preempt_enable(); 952 953 return boot_error; 954 } 955 956 void common_cpu_up(unsigned int cpu, struct task_struct *idle) 957 { 958 /* Just in case we booted with a single CPU. */ 959 alternatives_enable_smp(); 960 961 per_cpu(current_task, cpu) = idle; 962 963 #ifdef CONFIG_X86_32 964 /* Stack for startup_32 can be just as for start_secondary onwards */ 965 irq_ctx_init(cpu); 966 per_cpu(cpu_current_top_of_stack, cpu) = 967 (unsigned long)task_stack_page(idle) + THREAD_SIZE; 968 #else 969 initial_gs = per_cpu_offset(cpu); 970 #endif 971 } 972 973 /* 974 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 975 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 976 * Returns zero if CPU booted OK, else error code from 977 * ->wakeup_secondary_cpu. 978 */ 979 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle, 980 int *cpu0_nmi_registered) 981 { 982 volatile u32 *trampoline_status = 983 (volatile u32 *) __va(real_mode_header->trampoline_status); 984 /* start_ip had better be page-aligned! */ 985 unsigned long start_ip = real_mode_header->trampoline_start; 986 987 unsigned long boot_error = 0; 988 unsigned long timeout; 989 990 idle->thread.sp = (unsigned long)task_pt_regs(idle); 991 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 992 initial_code = (unsigned long)start_secondary; 993 initial_stack = idle->thread.sp; 994 995 /* 996 * Enable the espfix hack for this CPU 997 */ 998 #ifdef CONFIG_X86_ESPFIX64 999 init_espfix_ap(cpu); 1000 #endif 1001 1002 /* So we see what's up */ 1003 announce_cpu(cpu, apicid); 1004 1005 /* 1006 * This grunge runs the startup process for 1007 * the targeted processor. 1008 */ 1009 1010 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 1011 1012 pr_debug("Setting warm reset code and vector.\n"); 1013 1014 smpboot_setup_warm_reset_vector(start_ip); 1015 /* 1016 * Be paranoid about clearing APIC errors. 1017 */ 1018 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 1019 apic_write(APIC_ESR, 0); 1020 apic_read(APIC_ESR); 1021 } 1022 } 1023 1024 /* 1025 * AP might wait on cpu_callout_mask in cpu_init() with 1026 * cpu_initialized_mask set if previous attempt to online 1027 * it timed-out. Clear cpu_initialized_mask so that after 1028 * INIT/SIPI it could start with a clean state. 1029 */ 1030 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1031 smp_mb(); 1032 1033 /* 1034 * Wake up a CPU in difference cases: 1035 * - Use the method in the APIC driver if it's defined 1036 * Otherwise, 1037 * - Use an INIT boot APIC message for APs or NMI for BSP. 1038 */ 1039 if (apic->wakeup_secondary_cpu) 1040 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 1041 else 1042 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 1043 cpu0_nmi_registered); 1044 1045 if (!boot_error) { 1046 /* 1047 * Wait 10s total for first sign of life from AP 1048 */ 1049 boot_error = -1; 1050 timeout = jiffies + 10*HZ; 1051 while (time_before(jiffies, timeout)) { 1052 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 1053 /* 1054 * Tell AP to proceed with initialization 1055 */ 1056 cpumask_set_cpu(cpu, cpu_callout_mask); 1057 boot_error = 0; 1058 break; 1059 } 1060 schedule(); 1061 } 1062 } 1063 1064 if (!boot_error) { 1065 /* 1066 * Wait till AP completes initial initialization 1067 */ 1068 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 1069 /* 1070 * Allow other tasks to run while we wait for the 1071 * AP to come online. This also gives a chance 1072 * for the MTRR work(triggered by the AP coming online) 1073 * to be completed in the stop machine context. 1074 */ 1075 schedule(); 1076 } 1077 } 1078 1079 /* mark "stuck" area as not stuck */ 1080 *trampoline_status = 0; 1081 1082 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 1083 /* 1084 * Cleanup possible dangling ends... 1085 */ 1086 smpboot_restore_warm_reset_vector(); 1087 } 1088 1089 return boot_error; 1090 } 1091 1092 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 1093 { 1094 int apicid = apic->cpu_present_to_apicid(cpu); 1095 int cpu0_nmi_registered = 0; 1096 unsigned long flags; 1097 int err, ret = 0; 1098 1099 lockdep_assert_irqs_enabled(); 1100 1101 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1102 1103 if (apicid == BAD_APICID || 1104 !physid_isset(apicid, phys_cpu_present_map) || 1105 !apic->apic_id_valid(apicid)) { 1106 pr_err("%s: bad cpu %d\n", __func__, cpu); 1107 return -EINVAL; 1108 } 1109 1110 /* 1111 * Already booted CPU? 1112 */ 1113 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 1114 pr_debug("do_boot_cpu %d Already started\n", cpu); 1115 return -ENOSYS; 1116 } 1117 1118 /* 1119 * Save current MTRR state in case it was changed since early boot 1120 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1121 */ 1122 mtrr_save_state(); 1123 1124 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 1125 err = cpu_check_up_prepare(cpu); 1126 if (err && err != -EBUSY) 1127 return err; 1128 1129 /* the FPU context is blank, nobody can own it */ 1130 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1131 1132 common_cpu_up(cpu, tidle); 1133 1134 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered); 1135 if (err) { 1136 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1137 ret = -EIO; 1138 goto unreg_nmi; 1139 } 1140 1141 /* 1142 * Check TSC synchronization with the AP (keep irqs disabled 1143 * while doing so): 1144 */ 1145 local_irq_save(flags); 1146 check_tsc_sync_source(cpu); 1147 local_irq_restore(flags); 1148 1149 while (!cpu_online(cpu)) { 1150 cpu_relax(); 1151 touch_nmi_watchdog(); 1152 } 1153 1154 unreg_nmi: 1155 /* 1156 * Clean up the nmi handler. Do this after the callin and callout sync 1157 * to avoid impact of possible long unregister time. 1158 */ 1159 if (cpu0_nmi_registered) 1160 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 1161 1162 return ret; 1163 } 1164 1165 /** 1166 * arch_disable_smp_support() - disables SMP support for x86 at runtime 1167 */ 1168 void arch_disable_smp_support(void) 1169 { 1170 disable_ioapic_support(); 1171 } 1172 1173 /* 1174 * Fall back to non SMP mode after errors. 1175 * 1176 * RED-PEN audit/test this more. I bet there is more state messed up here. 1177 */ 1178 static __init void disable_smp(void) 1179 { 1180 pr_info("SMP disabled\n"); 1181 1182 disable_ioapic_support(); 1183 1184 init_cpu_present(cpumask_of(0)); 1185 init_cpu_possible(cpumask_of(0)); 1186 1187 if (smp_found_config) 1188 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1189 else 1190 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1191 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1192 cpumask_set_cpu(0, topology_core_cpumask(0)); 1193 } 1194 1195 enum { 1196 SMP_OK, 1197 SMP_NO_CONFIG, 1198 SMP_NO_APIC, 1199 SMP_FORCE_UP, 1200 }; 1201 1202 /* 1203 * Various sanity checks. 1204 */ 1205 static int __init smp_sanity_check(unsigned max_cpus) 1206 { 1207 preempt_disable(); 1208 1209 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1210 if (def_to_bigsmp && nr_cpu_ids > 8) { 1211 unsigned int cpu; 1212 unsigned nr; 1213 1214 pr_warn("More than 8 CPUs detected - skipping them\n" 1215 "Use CONFIG_X86_BIGSMP\n"); 1216 1217 nr = 0; 1218 for_each_present_cpu(cpu) { 1219 if (nr >= 8) 1220 set_cpu_present(cpu, false); 1221 nr++; 1222 } 1223 1224 nr = 0; 1225 for_each_possible_cpu(cpu) { 1226 if (nr >= 8) 1227 set_cpu_possible(cpu, false); 1228 nr++; 1229 } 1230 1231 nr_cpu_ids = 8; 1232 } 1233 #endif 1234 1235 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1236 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1237 hard_smp_processor_id()); 1238 1239 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1240 } 1241 1242 /* 1243 * If we couldn't find an SMP configuration at boot time, 1244 * get out of here now! 1245 */ 1246 if (!smp_found_config && !acpi_lapic) { 1247 preempt_enable(); 1248 pr_notice("SMP motherboard not detected\n"); 1249 return SMP_NO_CONFIG; 1250 } 1251 1252 /* 1253 * Should not be necessary because the MP table should list the boot 1254 * CPU too, but we do it for the sake of robustness anyway. 1255 */ 1256 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1257 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1258 boot_cpu_physical_apicid); 1259 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1260 } 1261 preempt_enable(); 1262 1263 /* 1264 * If we couldn't find a local APIC, then get out of here now! 1265 */ 1266 if (APIC_INTEGRATED(boot_cpu_apic_version) && 1267 !boot_cpu_has(X86_FEATURE_APIC)) { 1268 if (!disable_apic) { 1269 pr_err("BIOS bug, local APIC #%d not detected!...\n", 1270 boot_cpu_physical_apicid); 1271 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); 1272 } 1273 return SMP_NO_APIC; 1274 } 1275 1276 /* 1277 * If SMP should be disabled, then really disable it! 1278 */ 1279 if (!max_cpus) { 1280 pr_info("SMP mode deactivated\n"); 1281 return SMP_FORCE_UP; 1282 } 1283 1284 return SMP_OK; 1285 } 1286 1287 static void __init smp_cpu_index_default(void) 1288 { 1289 int i; 1290 struct cpuinfo_x86 *c; 1291 1292 for_each_possible_cpu(i) { 1293 c = &cpu_data(i); 1294 /* mark all to hotplug */ 1295 c->cpu_index = nr_cpu_ids; 1296 } 1297 } 1298 1299 /* 1300 * Prepare for SMP bootup. The MP table or ACPI has been read 1301 * earlier. Just do some sanity checking here and enable APIC mode. 1302 */ 1303 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1304 { 1305 unsigned int i; 1306 1307 smp_cpu_index_default(); 1308 1309 /* 1310 * Setup boot CPU information 1311 */ 1312 smp_store_boot_cpu_info(); /* Final full version of the data */ 1313 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1314 mb(); 1315 1316 for_each_possible_cpu(i) { 1317 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1318 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1319 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1320 } 1321 1322 /* 1323 * Set 'default' x86 topology, this matches default_topology() in that 1324 * it has NUMA nodes as a topology level. See also 1325 * native_smp_cpus_done(). 1326 * 1327 * Must be done before set_cpus_sibling_map() is ran. 1328 */ 1329 set_sched_topology(x86_topology); 1330 1331 set_cpu_sibling_map(0); 1332 1333 switch (smp_sanity_check(max_cpus)) { 1334 case SMP_NO_CONFIG: 1335 disable_smp(); 1336 if (APIC_init_uniprocessor()) 1337 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); 1338 return; 1339 case SMP_NO_APIC: 1340 disable_smp(); 1341 return; 1342 case SMP_FORCE_UP: 1343 disable_smp(); 1344 apic_bsp_setup(false); 1345 return; 1346 case SMP_OK: 1347 break; 1348 } 1349 1350 if (read_apic_id() != boot_cpu_physical_apicid) { 1351 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1352 read_apic_id(), boot_cpu_physical_apicid); 1353 /* Or can we switch back to PIC here? */ 1354 } 1355 1356 default_setup_apic_routing(); 1357 cpu0_logical_apicid = apic_bsp_setup(false); 1358 1359 pr_info("CPU0: "); 1360 print_cpu_info(&cpu_data(0)); 1361 1362 native_pv_lock_init(); 1363 1364 uv_system_init(); 1365 1366 set_mtrr_aps_delayed_init(); 1367 1368 smp_quirk_init_udelay(); 1369 } 1370 1371 void arch_enable_nonboot_cpus_begin(void) 1372 { 1373 set_mtrr_aps_delayed_init(); 1374 } 1375 1376 void arch_enable_nonboot_cpus_end(void) 1377 { 1378 mtrr_aps_init(); 1379 } 1380 1381 /* 1382 * Early setup to make printk work. 1383 */ 1384 void __init native_smp_prepare_boot_cpu(void) 1385 { 1386 int me = smp_processor_id(); 1387 switch_to_new_gdt(me); 1388 /* already set me in cpu_online_mask in boot_cpu_init() */ 1389 cpumask_set_cpu(me, cpu_callout_mask); 1390 cpu_set_state_online(me); 1391 } 1392 1393 void __init native_smp_cpus_done(unsigned int max_cpus) 1394 { 1395 pr_debug("Boot done\n"); 1396 1397 if (x86_has_numa_in_package) 1398 set_sched_topology(x86_numa_in_package_topology); 1399 1400 nmi_selftest(); 1401 impress_friends(); 1402 setup_ioapic_dest(); 1403 mtrr_aps_init(); 1404 } 1405 1406 static int __initdata setup_possible_cpus = -1; 1407 static int __init _setup_possible_cpus(char *str) 1408 { 1409 get_option(&str, &setup_possible_cpus); 1410 return 0; 1411 } 1412 early_param("possible_cpus", _setup_possible_cpus); 1413 1414 1415 /* 1416 * cpu_possible_mask should be static, it cannot change as cpu's 1417 * are onlined, or offlined. The reason is per-cpu data-structures 1418 * are allocated by some modules at init time, and dont expect to 1419 * do this dynamically on cpu arrival/departure. 1420 * cpu_present_mask on the other hand can change dynamically. 1421 * In case when cpu_hotplug is not compiled, then we resort to current 1422 * behaviour, which is cpu_possible == cpu_present. 1423 * - Ashok Raj 1424 * 1425 * Three ways to find out the number of additional hotplug CPUs: 1426 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1427 * - The user can overwrite it with possible_cpus=NUM 1428 * - Otherwise don't reserve additional CPUs. 1429 * We do this because additional CPUs waste a lot of memory. 1430 * -AK 1431 */ 1432 __init void prefill_possible_map(void) 1433 { 1434 int i, possible; 1435 1436 /* No boot processor was found in mptable or ACPI MADT */ 1437 if (!num_processors) { 1438 if (boot_cpu_has(X86_FEATURE_APIC)) { 1439 int apicid = boot_cpu_physical_apicid; 1440 int cpu = hard_smp_processor_id(); 1441 1442 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); 1443 1444 /* Make sure boot cpu is enumerated */ 1445 if (apic->cpu_present_to_apicid(0) == BAD_APICID && 1446 apic->apic_id_valid(apicid)) 1447 generic_processor_info(apicid, boot_cpu_apic_version); 1448 } 1449 1450 if (!num_processors) 1451 num_processors = 1; 1452 } 1453 1454 i = setup_max_cpus ?: 1; 1455 if (setup_possible_cpus == -1) { 1456 possible = num_processors; 1457 #ifdef CONFIG_HOTPLUG_CPU 1458 if (setup_max_cpus) 1459 possible += disabled_cpus; 1460 #else 1461 if (possible > i) 1462 possible = i; 1463 #endif 1464 } else 1465 possible = setup_possible_cpus; 1466 1467 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1468 1469 /* nr_cpu_ids could be reduced via nr_cpus= */ 1470 if (possible > nr_cpu_ids) { 1471 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", 1472 possible, nr_cpu_ids); 1473 possible = nr_cpu_ids; 1474 } 1475 1476 #ifdef CONFIG_HOTPLUG_CPU 1477 if (!setup_max_cpus) 1478 #endif 1479 if (possible > i) { 1480 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1481 possible, setup_max_cpus); 1482 possible = i; 1483 } 1484 1485 nr_cpu_ids = possible; 1486 1487 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1488 possible, max_t(int, possible - num_processors, 0)); 1489 1490 reset_cpu_possible_mask(); 1491 1492 for (i = 0; i < possible; i++) 1493 set_cpu_possible(i, true); 1494 } 1495 1496 #ifdef CONFIG_HOTPLUG_CPU 1497 1498 /* Recompute SMT state for all CPUs on offline */ 1499 static void recompute_smt_state(void) 1500 { 1501 int max_threads, cpu; 1502 1503 max_threads = 0; 1504 for_each_online_cpu (cpu) { 1505 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1506 1507 if (threads > max_threads) 1508 max_threads = threads; 1509 } 1510 __max_smt_threads = max_threads; 1511 } 1512 1513 static void remove_siblinginfo(int cpu) 1514 { 1515 int sibling; 1516 struct cpuinfo_x86 *c = &cpu_data(cpu); 1517 1518 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1519 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1520 /*/ 1521 * last thread sibling in this cpu core going down 1522 */ 1523 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1524 cpu_data(sibling).booted_cores--; 1525 } 1526 1527 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) 1528 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1529 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1530 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1531 cpumask_clear(cpu_llc_shared_mask(cpu)); 1532 cpumask_clear(topology_sibling_cpumask(cpu)); 1533 cpumask_clear(topology_core_cpumask(cpu)); 1534 c->phys_proc_id = 0; 1535 c->cpu_core_id = 0; 1536 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1537 recompute_smt_state(); 1538 } 1539 1540 static void remove_cpu_from_maps(int cpu) 1541 { 1542 set_cpu_online(cpu, false); 1543 cpumask_clear_cpu(cpu, cpu_callout_mask); 1544 cpumask_clear_cpu(cpu, cpu_callin_mask); 1545 /* was set by cpu_init() */ 1546 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1547 numa_remove_cpu(cpu); 1548 } 1549 1550 void cpu_disable_common(void) 1551 { 1552 int cpu = smp_processor_id(); 1553 1554 remove_siblinginfo(cpu); 1555 1556 /* It's now safe to remove this processor from the online map */ 1557 lock_vector_lock(); 1558 remove_cpu_from_maps(cpu); 1559 unlock_vector_lock(); 1560 fixup_irqs(); 1561 } 1562 1563 int native_cpu_disable(void) 1564 { 1565 int ret; 1566 1567 ret = check_irq_vectors_for_cpu_disable(); 1568 if (ret) 1569 return ret; 1570 1571 clear_local_APIC(); 1572 cpu_disable_common(); 1573 1574 return 0; 1575 } 1576 1577 int common_cpu_die(unsigned int cpu) 1578 { 1579 int ret = 0; 1580 1581 /* We don't do anything here: idle task is faking death itself. */ 1582 1583 /* They ack this in play_dead() by setting CPU_DEAD */ 1584 if (cpu_wait_death(cpu, 5)) { 1585 if (system_state == SYSTEM_RUNNING) 1586 pr_info("CPU %u is now offline\n", cpu); 1587 } else { 1588 pr_err("CPU %u didn't die...\n", cpu); 1589 ret = -1; 1590 } 1591 1592 return ret; 1593 } 1594 1595 void native_cpu_die(unsigned int cpu) 1596 { 1597 common_cpu_die(cpu); 1598 } 1599 1600 void play_dead_common(void) 1601 { 1602 idle_task_exit(); 1603 1604 /* Ack it */ 1605 (void)cpu_report_death(); 1606 1607 /* 1608 * With physical CPU hotplug, we should halt the cpu 1609 */ 1610 local_irq_disable(); 1611 } 1612 1613 static bool wakeup_cpu0(void) 1614 { 1615 if (smp_processor_id() == 0 && enable_start_cpu0) 1616 return true; 1617 1618 return false; 1619 } 1620 1621 /* 1622 * We need to flush the caches before going to sleep, lest we have 1623 * dirty data in our caches when we come back up. 1624 */ 1625 static inline void mwait_play_dead(void) 1626 { 1627 unsigned int eax, ebx, ecx, edx; 1628 unsigned int highest_cstate = 0; 1629 unsigned int highest_subcstate = 0; 1630 void *mwait_ptr; 1631 int i; 1632 1633 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1634 return; 1635 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1636 return; 1637 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1638 return; 1639 1640 eax = CPUID_MWAIT_LEAF; 1641 ecx = 0; 1642 native_cpuid(&eax, &ebx, &ecx, &edx); 1643 1644 /* 1645 * eax will be 0 if EDX enumeration is not valid. 1646 * Initialized below to cstate, sub_cstate value when EDX is valid. 1647 */ 1648 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1649 eax = 0; 1650 } else { 1651 edx >>= MWAIT_SUBSTATE_SIZE; 1652 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1653 if (edx & MWAIT_SUBSTATE_MASK) { 1654 highest_cstate = i; 1655 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1656 } 1657 } 1658 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1659 (highest_subcstate - 1); 1660 } 1661 1662 /* 1663 * This should be a memory location in a cache line which is 1664 * unlikely to be touched by other processors. The actual 1665 * content is immaterial as it is not actually modified in any way. 1666 */ 1667 mwait_ptr = ¤t_thread_info()->flags; 1668 1669 wbinvd(); 1670 1671 while (1) { 1672 /* 1673 * The CLFLUSH is a workaround for erratum AAI65 for 1674 * the Xeon 7400 series. It's not clear it is actually 1675 * needed, but it should be harmless in either case. 1676 * The WBINVD is insufficient due to the spurious-wakeup 1677 * case where we return around the loop. 1678 */ 1679 mb(); 1680 clflush(mwait_ptr); 1681 mb(); 1682 __monitor(mwait_ptr, 0, 0); 1683 mb(); 1684 __mwait(eax, 0); 1685 /* 1686 * If NMI wants to wake up CPU0, start CPU0. 1687 */ 1688 if (wakeup_cpu0()) 1689 start_cpu0(); 1690 } 1691 } 1692 1693 void hlt_play_dead(void) 1694 { 1695 if (__this_cpu_read(cpu_info.x86) >= 4) 1696 wbinvd(); 1697 1698 while (1) { 1699 native_halt(); 1700 /* 1701 * If NMI wants to wake up CPU0, start CPU0. 1702 */ 1703 if (wakeup_cpu0()) 1704 start_cpu0(); 1705 } 1706 } 1707 1708 void native_play_dead(void) 1709 { 1710 play_dead_common(); 1711 tboot_shutdown(TB_SHUTDOWN_WFS); 1712 1713 mwait_play_dead(); /* Only returns on failure */ 1714 if (cpuidle_play_dead()) 1715 hlt_play_dead(); 1716 } 1717 1718 #else /* ... !CONFIG_HOTPLUG_CPU */ 1719 int native_cpu_disable(void) 1720 { 1721 return -ENOSYS; 1722 } 1723 1724 void native_cpu_die(unsigned int cpu) 1725 { 1726 /* We said "no" in __cpu_disable */ 1727 BUG(); 1728 } 1729 1730 void native_play_dead(void) 1731 { 1732 BUG(); 1733 } 1734 1735 #endif 1736