1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * x86 SMP booting functions 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 7 * Copyright 2001 Andi Kleen, SuSE Labs. 8 * 9 * Much of the core SMP work is based on previous work by Thomas Radke, to 10 * whom a great many thanks are extended. 11 * 12 * Thanks to Intel for making available several different Pentium, 13 * Pentium Pro and Pentium-II/Xeon MP machines. 14 * Original development of Linux SMP code supported by Caldera. 15 * 16 * Fixes 17 * Felix Koop : NR_CPUS used properly 18 * Jose Renau : Handle single CPU case. 19 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 20 * Greg Wright : Fix for kernel stacks panic. 21 * Erich Boleyn : MP v1.4 and additional changes. 22 * Matthias Sattler : Changes for 2.1 kernel map. 23 * Michel Lespinasse : Changes for 2.1 kernel map. 24 * Michael Chastain : Change trampoline.S to gnu as. 25 * Alan Cox : Dumb bug: 'B' step PPro's are fine 26 * Ingo Molnar : Added APIC timers, based on code 27 * from Jose Renau 28 * Ingo Molnar : various cleanups and rewrites 29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 31 * Andi Kleen : Changed for SMP boot into long mode. 32 * Martin J. Bligh : Added support for multi-quad systems 33 * Dave Jones : Report invalid combinations of Athlon CPUs. 34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 35 * Andi Kleen : Converted to new state machine. 36 * Ashok Raj : CPU hotplug support 37 * Glauber Costa : i386 and x86_64 integration 38 */ 39 40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/export.h> 45 #include <linux/sched.h> 46 #include <linux/sched/topology.h> 47 #include <linux/sched/hotplug.h> 48 #include <linux/sched/task_stack.h> 49 #include <linux/percpu.h> 50 #include <linux/memblock.h> 51 #include <linux/err.h> 52 #include <linux/nmi.h> 53 #include <linux/tboot.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 #include <linux/kexec.h> 57 #include <linux/numa.h> 58 #include <linux/pgtable.h> 59 #include <linux/overflow.h> 60 #include <linux/stackprotector.h> 61 #include <linux/cpuhotplug.h> 62 #include <linux/mc146818rtc.h> 63 #include <linux/acpi.h> 64 65 #include <asm/acpi.h> 66 #include <asm/cacheinfo.h> 67 #include <asm/cpuid/api.h> 68 #include <asm/desc.h> 69 #include <asm/nmi.h> 70 #include <asm/irq.h> 71 #include <asm/realmode.h> 72 #include <asm/cpu.h> 73 #include <asm/numa.h> 74 #include <asm/tlbflush.h> 75 #include <asm/mtrr.h> 76 #include <asm/mwait.h> 77 #include <asm/apic.h> 78 #include <asm/io_apic.h> 79 #include <asm/fpu/api.h> 80 #include <asm/setup.h> 81 #include <asm/uv/uv.h> 82 #include <asm/microcode.h> 83 #include <asm/i8259.h> 84 #include <asm/misc.h> 85 #include <asm/qspinlock.h> 86 #include <asm/intel-family.h> 87 #include <asm/cpu_device_id.h> 88 #include <asm/spec-ctrl.h> 89 #include <asm/hw_irq.h> 90 #include <asm/stackprotector.h> 91 #include <asm/sev.h> 92 #include <asm/spec-ctrl.h> 93 94 /* representing HT siblings of each logical CPU */ 95 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 96 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 97 98 /* representing HT and core siblings of each logical CPU */ 99 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 100 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 101 102 /* representing HT, core, and die siblings of each logical CPU */ 103 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); 104 EXPORT_PER_CPU_SYMBOL(cpu_die_map); 105 106 /* CPUs which are the primary SMT threads */ 107 struct cpumask __cpu_primary_thread_mask __read_mostly; 108 109 /* Representing CPUs for which sibling maps can be computed */ 110 static cpumask_var_t cpu_sibling_setup_mask; 111 112 struct mwait_cpu_dead { 113 unsigned int control; 114 unsigned int status; 115 }; 116 117 #define CPUDEAD_MWAIT_WAIT 0xDEADBEEF 118 #define CPUDEAD_MWAIT_KEXEC_HLT 0x4A17DEAD 119 120 /* 121 * Cache line aligned data for mwait_play_dead(). Separate on purpose so 122 * that it's unlikely to be touched by other CPUs. 123 */ 124 static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead); 125 126 /* Maximum number of SMT threads on any online core */ 127 int __read_mostly __max_smt_threads = 1; 128 129 /* Flag to indicate if a complete sched domain rebuild is required */ 130 bool x86_topology_update; 131 132 int arch_update_cpu_topology(void) 133 { 134 int retval = x86_topology_update; 135 136 x86_topology_update = false; 137 return retval; 138 } 139 140 static unsigned int smpboot_warm_reset_vector_count; 141 142 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 143 { 144 unsigned long flags; 145 146 spin_lock_irqsave(&rtc_lock, flags); 147 if (!smpboot_warm_reset_vector_count++) { 148 CMOS_WRITE(0xa, 0xf); 149 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = start_eip >> 4; 150 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = start_eip & 0xf; 151 } 152 spin_unlock_irqrestore(&rtc_lock, flags); 153 } 154 155 static inline void smpboot_restore_warm_reset_vector(void) 156 { 157 unsigned long flags; 158 159 /* 160 * Paranoid: Set warm reset code and vector here back 161 * to default values. 162 */ 163 spin_lock_irqsave(&rtc_lock, flags); 164 if (!--smpboot_warm_reset_vector_count) { 165 CMOS_WRITE(0, 0xf); 166 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 167 } 168 spin_unlock_irqrestore(&rtc_lock, flags); 169 170 } 171 172 /* Run the next set of setup steps for the upcoming CPU */ 173 static void ap_starting(void) 174 { 175 int cpuid = smp_processor_id(); 176 177 /* Mop up eventual mwait_play_dead() wreckage */ 178 this_cpu_write(mwait_cpu_dead.status, 0); 179 this_cpu_write(mwait_cpu_dead.control, 0); 180 181 /* 182 * If woken up by an INIT in an 82489DX configuration the alive 183 * synchronization guarantees that the CPU does not reach this 184 * point before an INIT_deassert IPI reaches the local APIC, so it 185 * is now safe to touch the local APIC. 186 * 187 * Set up this CPU, first the APIC, which is probably redundant on 188 * most boards. 189 */ 190 apic_ap_setup(); 191 192 /* Save the processor parameters. */ 193 identify_secondary_cpu(cpuid); 194 195 /* 196 * The topology information must be up to date before 197 * notify_cpu_starting(). 198 */ 199 set_cpu_sibling_map(cpuid); 200 201 ap_init_aperfmperf(); 202 203 pr_debug("Stack at about %p\n", &cpuid); 204 205 wmb(); 206 207 /* 208 * This runs the AP through all the cpuhp states to its target 209 * state CPUHP_ONLINE. 210 */ 211 notify_cpu_starting(cpuid); 212 } 213 214 static void ap_calibrate_delay(void) 215 { 216 /* 217 * Calibrate the delay loop and update loops_per_jiffy in cpu_data. 218 * identify_secondary_cpu() stored a value that is close but not as 219 * accurate as the value just calculated. 220 * 221 * As this is invoked after the TSC synchronization check, 222 * calibrate_delay_is_known() will skip the calibration routine 223 * when TSC is synchronized across sockets. 224 */ 225 calibrate_delay(); 226 cpu_data(smp_processor_id()).loops_per_jiffy = loops_per_jiffy; 227 } 228 229 /* 230 * Activate a secondary processor. 231 */ 232 static void notrace __noendbr start_secondary(void *unused) 233 { 234 /* 235 * Don't put *anything* except direct CPU state initialization 236 * before cpu_init(), SMP booting is too fragile that we want to 237 * limit the things done here to the most necessary things. 238 */ 239 cr4_init(); 240 241 /* 242 * 32-bit specific. 64-bit reaches this code with the correct page 243 * table established. Yet another historical divergence. 244 */ 245 if (IS_ENABLED(CONFIG_X86_32)) { 246 /* switch away from the initial page table */ 247 load_cr3(swapper_pg_dir); 248 __flush_tlb_all(); 249 } 250 251 cpu_init_exception_handling(false); 252 253 /* 254 * Load the microcode before reaching the AP alive synchronization 255 * point below so it is not part of the full per CPU serialized 256 * bringup part when "parallel" bringup is enabled. 257 * 258 * That's even safe when hyperthreading is enabled in the CPU as 259 * the core code starts the primary threads first and leaves the 260 * secondary threads waiting for SIPI. Loading microcode on 261 * physical cores concurrently is a safe operation. 262 * 263 * This covers both the Intel specific issue that concurrent 264 * microcode loading on SMT siblings must be prohibited and the 265 * vendor independent issue`that microcode loading which changes 266 * CPUID, MSRs etc. must be strictly serialized to maintain 267 * software state correctness. 268 */ 269 load_ucode_ap(); 270 271 /* 272 * Synchronization point with the hotplug core. Sets this CPUs 273 * synchronization state to ALIVE and spin-waits for the control CPU to 274 * release this CPU for further bringup. 275 */ 276 cpuhp_ap_sync_alive(); 277 278 cpu_init(); 279 fpu__init_cpu(); 280 rcutree_report_cpu_starting(raw_smp_processor_id()); 281 x86_cpuinit.early_percpu_clock_init(); 282 283 ap_starting(); 284 285 /* Check TSC synchronization with the control CPU. */ 286 check_tsc_sync_target(); 287 288 /* 289 * Calibrate the delay loop after the TSC synchronization check. 290 * This allows to skip the calibration when TSC is synchronized 291 * across sockets. 292 */ 293 ap_calibrate_delay(); 294 295 speculative_store_bypass_ht_init(); 296 297 /* 298 * Lock vector_lock, set CPU online and bring the vector 299 * allocator online. Online must be set with vector_lock held 300 * to prevent a concurrent irq setup/teardown from seeing a 301 * half valid vector space. 302 */ 303 lock_vector_lock(); 304 set_cpu_online(smp_processor_id(), true); 305 lapic_online(); 306 unlock_vector_lock(); 307 x86_platform.nmi_init(); 308 309 /* enable local interrupts */ 310 local_irq_enable(); 311 312 x86_cpuinit.setup_percpu_clockev(); 313 314 wmb(); 315 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 316 } 317 ANNOTATE_NOENDBR_SYM(start_secondary); 318 319 static bool 320 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 321 { 322 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 323 324 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 325 } 326 327 static bool 328 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 329 { 330 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 331 332 return !WARN_ONCE(!topology_same_node(c, o), 333 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 334 "[node: %d != %d]. Ignoring dependency.\n", 335 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 336 } 337 338 #define link_mask(mfunc, c1, c2) \ 339 do { \ 340 cpumask_set_cpu((c1), mfunc(c2)); \ 341 cpumask_set_cpu((c2), mfunc(c1)); \ 342 } while (0) 343 344 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 345 { 346 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 347 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 348 349 if (c->topo.pkg_id == o->topo.pkg_id && 350 c->topo.die_id == o->topo.die_id && 351 c->topo.amd_node_id == o->topo.amd_node_id && 352 per_cpu_llc_id(cpu1) == per_cpu_llc_id(cpu2)) { 353 if (c->topo.core_id == o->topo.core_id) 354 return topology_sane(c, o, "smt"); 355 356 if ((c->topo.cu_id != 0xff) && 357 (o->topo.cu_id != 0xff) && 358 (c->topo.cu_id == o->topo.cu_id)) 359 return topology_sane(c, o, "smt"); 360 } 361 362 } else if (c->topo.pkg_id == o->topo.pkg_id && 363 c->topo.die_id == o->topo.die_id && 364 c->topo.core_id == o->topo.core_id) { 365 return topology_sane(c, o, "smt"); 366 } 367 368 return false; 369 } 370 371 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 372 { 373 if (c->topo.pkg_id != o->topo.pkg_id || c->topo.die_id != o->topo.die_id) 374 return false; 375 376 if (cpu_feature_enabled(X86_FEATURE_TOPOEXT) && topology_amd_nodes_per_pkg() > 1) 377 return c->topo.amd_node_id == o->topo.amd_node_id; 378 379 return true; 380 } 381 382 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 383 { 384 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 385 386 /* If the arch didn't set up l2c_id, fall back to SMT */ 387 if (per_cpu_l2c_id(cpu1) == BAD_APICID) 388 return match_smt(c, o); 389 390 /* Do not match if L2 cache id does not match: */ 391 if (per_cpu_l2c_id(cpu1) != per_cpu_l2c_id(cpu2)) 392 return false; 393 394 return topology_sane(c, o, "l2c"); 395 } 396 397 /* 398 * Unlike the other levels, we do not enforce keeping a 399 * multicore group inside a NUMA node. If this happens, we will 400 * discard the MC level of the topology later. 401 */ 402 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 403 { 404 if (c->topo.pkg_id == o->topo.pkg_id) 405 return true; 406 return false; 407 } 408 409 /* 410 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs. 411 * 412 * Any Intel CPU that has multiple nodes per package and does not 413 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology. 414 * 415 * When in SNC mode, these CPUs enumerate an LLC that is shared 416 * by multiple NUMA nodes. The LLC is shared for off-package data 417 * access but private to the NUMA node (half of the package) for 418 * on-package access. CPUID (the source of the information about 419 * the LLC) can only enumerate the cache as shared or unshared, 420 * but not this particular configuration. 421 */ 422 423 static const struct x86_cpu_id intel_cod_cpu[] = { 424 X86_MATCH_VFM(INTEL_HASWELL_X, 0), /* COD */ 425 X86_MATCH_VFM(INTEL_BROADWELL_X, 0), /* COD */ 426 X86_MATCH_VFM(INTEL_ANY, 1), /* SNC */ 427 {} 428 }; 429 430 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 431 { 432 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu); 433 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 434 bool intel_snc = id && id->driver_data; 435 436 /* Do not match if we do not have a valid APICID for cpu: */ 437 if (per_cpu_llc_id(cpu1) == BAD_APICID) 438 return false; 439 440 /* Do not match if LLC id does not match: */ 441 if (per_cpu_llc_id(cpu1) != per_cpu_llc_id(cpu2)) 442 return false; 443 444 /* 445 * Allow the SNC topology without warning. Return of false 446 * means 'c' does not share the LLC of 'o'. This will be 447 * reflected to userspace. 448 */ 449 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc) 450 return false; 451 452 return topology_sane(c, o, "llc"); 453 } 454 455 456 static inline int x86_sched_itmt_flags(void) 457 { 458 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 459 } 460 461 #ifdef CONFIG_SCHED_MC 462 static int x86_core_flags(void) 463 { 464 return cpu_core_flags() | x86_sched_itmt_flags(); 465 } 466 #endif 467 #ifdef CONFIG_SCHED_CLUSTER 468 static int x86_cluster_flags(void) 469 { 470 return cpu_cluster_flags() | x86_sched_itmt_flags(); 471 } 472 #endif 473 474 /* 475 * Set if a package/die has multiple NUMA nodes inside. 476 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel 477 * Sub-NUMA Clustering have this. 478 */ 479 static bool x86_has_numa_in_package; 480 481 static struct sched_domain_topology_level x86_topology[] = { 482 SDTL_INIT(tl_smt_mask, cpu_smt_flags, SMT), 483 #ifdef CONFIG_SCHED_CLUSTER 484 SDTL_INIT(tl_cls_mask, x86_cluster_flags, CLS), 485 #endif 486 #ifdef CONFIG_SCHED_MC 487 SDTL_INIT(tl_mc_mask, x86_core_flags, MC), 488 #endif 489 SDTL_INIT(tl_pkg_mask, x86_sched_itmt_flags, PKG), 490 { NULL }, 491 }; 492 493 static void __init build_sched_topology(void) 494 { 495 struct sched_domain_topology_level *topology = x86_topology; 496 497 /* 498 * When there is NUMA topology inside the package invalidate the 499 * PKG domain since the NUMA domains will auto-magically create the 500 * right spanning domains based on the SLIT. 501 */ 502 if (x86_has_numa_in_package) { 503 unsigned int pkgdom = ARRAY_SIZE(x86_topology) - 2; 504 505 memset(&x86_topology[pkgdom], 0, sizeof(x86_topology[pkgdom])); 506 } 507 508 /* 509 * Drop the SMT domains if there is only one thread per-core 510 * since it'll get degenerated by the scheduler anyways. 511 */ 512 if (cpu_smt_num_threads <= 1) 513 ++topology; 514 515 set_sched_topology(topology); 516 } 517 518 #ifdef CONFIG_NUMA 519 static int sched_avg_remote_distance; 520 static int avg_remote_numa_distance(void) 521 { 522 int i, j; 523 int distance, nr_remote, total_distance; 524 525 if (sched_avg_remote_distance > 0) 526 return sched_avg_remote_distance; 527 528 nr_remote = 0; 529 total_distance = 0; 530 for_each_node_state(i, N_CPU) { 531 for_each_node_state(j, N_CPU) { 532 distance = node_distance(i, j); 533 534 if (distance >= REMOTE_DISTANCE) { 535 nr_remote++; 536 total_distance += distance; 537 } 538 } 539 } 540 if (nr_remote) 541 sched_avg_remote_distance = total_distance / nr_remote; 542 else 543 sched_avg_remote_distance = REMOTE_DISTANCE; 544 545 return sched_avg_remote_distance; 546 } 547 548 int arch_sched_node_distance(int from, int to) 549 { 550 int d = node_distance(from, to); 551 552 switch (boot_cpu_data.x86_vfm) { 553 case INTEL_GRANITERAPIDS_X: 554 case INTEL_ATOM_DARKMONT_X: 555 556 if (!x86_has_numa_in_package || topology_max_packages() == 1 || 557 d < REMOTE_DISTANCE) 558 return d; 559 560 /* 561 * With SNC enabled, there could be too many levels of remote 562 * NUMA node distances, creating NUMA domain levels 563 * including local nodes and partial remote nodes. 564 * 565 * Trim finer distance tuning for NUMA nodes in remote package 566 * for the purpose of building sched domains. Group NUMA nodes 567 * in the remote package in the same sched group. 568 * Simplify NUMA domains and avoid extra NUMA levels including 569 * different remote NUMA nodes and local nodes. 570 * 571 * GNR and CWF don't expect systems with more than 2 packages 572 * and more than 2 hops between packages. Single average remote 573 * distance won't be appropriate if there are more than 2 574 * packages as average distance to different remote packages 575 * could be different. 576 */ 577 WARN_ONCE(topology_max_packages() > 2, 578 "sched: Expect only up to 2 packages for GNR or CWF, " 579 "but saw %d packages when building sched domains.", 580 topology_max_packages()); 581 582 d = avg_remote_numa_distance(); 583 } 584 return d; 585 } 586 #endif /* CONFIG_NUMA */ 587 588 void set_cpu_sibling_map(int cpu) 589 { 590 bool has_smt = __max_threads_per_core > 1; 591 bool has_mp = has_smt || topology_num_cores_per_package() > 1; 592 struct cpuinfo_x86 *c = &cpu_data(cpu); 593 struct cpuinfo_x86 *o; 594 int i, threads; 595 596 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 597 598 if (!has_mp) { 599 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 600 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 601 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu)); 602 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 603 cpumask_set_cpu(cpu, topology_die_cpumask(cpu)); 604 c->booted_cores = 1; 605 return; 606 } 607 608 for_each_cpu(i, cpu_sibling_setup_mask) { 609 o = &cpu_data(i); 610 611 if (match_pkg(c, o) && !topology_same_node(c, o)) 612 x86_has_numa_in_package = true; 613 614 if ((i == cpu) || (has_smt && match_smt(c, o))) 615 link_mask(topology_sibling_cpumask, cpu, i); 616 617 if ((i == cpu) || (has_mp && match_llc(c, o))) 618 link_mask(cpu_llc_shared_mask, cpu, i); 619 620 if ((i == cpu) || (has_mp && match_l2c(c, o))) 621 link_mask(cpu_l2c_shared_mask, cpu, i); 622 623 if ((i == cpu) || (has_mp && match_die(c, o))) 624 link_mask(topology_die_cpumask, cpu, i); 625 } 626 627 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 628 if (threads > __max_smt_threads) 629 __max_smt_threads = threads; 630 631 for_each_cpu(i, topology_sibling_cpumask(cpu)) 632 cpu_data(i).smt_active = threads > 1; 633 634 /* 635 * This needs a separate iteration over the cpus because we rely on all 636 * topology_sibling_cpumask links to be set-up. 637 */ 638 for_each_cpu(i, cpu_sibling_setup_mask) { 639 o = &cpu_data(i); 640 641 if ((i == cpu) || (has_mp && match_pkg(c, o))) { 642 link_mask(topology_core_cpumask, cpu, i); 643 644 /* 645 * Does this new cpu bringup a new core? 646 */ 647 if (threads == 1) { 648 /* 649 * for each core in package, increment 650 * the booted_cores for this new cpu 651 */ 652 if (cpumask_first( 653 topology_sibling_cpumask(i)) == i) 654 c->booted_cores++; 655 /* 656 * increment the core count for all 657 * the other cpus in this package 658 */ 659 if (i != cpu) 660 cpu_data(i).booted_cores++; 661 } else if (i != cpu && !c->booted_cores) 662 c->booted_cores = cpu_data(i).booted_cores; 663 } 664 } 665 } 666 667 /* maps the cpu to the sched domain representing multi-core */ 668 const struct cpumask *cpu_coregroup_mask(int cpu) 669 { 670 return cpu_llc_shared_mask(cpu); 671 } 672 673 const struct cpumask *cpu_clustergroup_mask(int cpu) 674 { 675 return cpu_l2c_shared_mask(cpu); 676 } 677 EXPORT_SYMBOL_GPL(cpu_clustergroup_mask); 678 679 static void impress_friends(void) 680 { 681 int cpu; 682 unsigned long bogosum = 0; 683 /* 684 * Allow the user to impress friends. 685 */ 686 pr_debug("Before bogomips\n"); 687 for_each_online_cpu(cpu) 688 bogosum += cpu_data(cpu).loops_per_jiffy; 689 690 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 691 num_online_cpus(), 692 bogosum/(500000/HZ), 693 (bogosum/(5000/HZ))%100); 694 695 pr_debug("Before bogocount - setting activated=1\n"); 696 } 697 698 /* 699 * The Multiprocessor Specification 1.4 (1997) example code suggests 700 * that there should be a 10ms delay between the BSP asserting INIT 701 * and de-asserting INIT, when starting a remote processor. 702 * But that slows boot and resume on modern processors, which include 703 * many cores and don't require that delay. 704 * 705 * Cmdline "cpu_init_udelay=" is available to override this delay. 706 */ 707 #define UDELAY_10MS_LEGACY 10000 708 709 static unsigned int init_udelay = UINT_MAX; 710 711 static int __init cpu_init_udelay(char *str) 712 { 713 get_option(&str, &init_udelay); 714 715 return 0; 716 } 717 early_param("cpu_init_udelay", cpu_init_udelay); 718 719 static void __init smp_set_init_udelay(void) 720 { 721 /* if cmdline changed it from default, leave it alone */ 722 if (init_udelay != UINT_MAX) 723 return; 724 725 /* if modern processor, use no delay */ 726 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && boot_cpu_data.x86_vfm >= INTEL_PENTIUM_PRO) || 727 (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON && boot_cpu_data.x86 >= 0x18) || 728 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && boot_cpu_data.x86 >= 0xF)) { 729 init_udelay = 0; 730 return; 731 } 732 /* else, use legacy delay */ 733 init_udelay = UDELAY_10MS_LEGACY; 734 } 735 736 /* 737 * Wake up AP by INIT, INIT, STARTUP sequence. 738 */ 739 static void send_init_sequence(u32 phys_apicid) 740 { 741 int maxlvt = lapic_get_maxlvt(); 742 743 /* Be paranoid about clearing APIC errors. */ 744 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 745 /* Due to the Pentium erratum 3AP. */ 746 if (maxlvt > 3) 747 apic_write(APIC_ESR, 0); 748 apic_read(APIC_ESR); 749 } 750 751 /* Assert INIT on the target CPU */ 752 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, phys_apicid); 753 safe_apic_wait_icr_idle(); 754 755 udelay(init_udelay); 756 757 /* Deassert INIT on the target CPU */ 758 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 759 safe_apic_wait_icr_idle(); 760 } 761 762 /* 763 * Wake up AP by INIT, INIT, STARTUP sequence. 764 */ 765 static int wakeup_secondary_cpu_via_init(u32 phys_apicid, unsigned long start_eip, unsigned int cpu) 766 { 767 unsigned long send_status = 0, accept_status = 0; 768 int num_starts, j, maxlvt; 769 770 preempt_disable(); 771 maxlvt = lapic_get_maxlvt(); 772 send_init_sequence(phys_apicid); 773 774 mb(); 775 776 /* 777 * Should we send STARTUP IPIs ? 778 * 779 * Determine this based on the APIC version. 780 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 781 */ 782 if (APIC_INTEGRATED(boot_cpu_apic_version)) 783 num_starts = 2; 784 else 785 num_starts = 0; 786 787 /* 788 * Run STARTUP IPI loop. 789 */ 790 pr_debug("#startup loops: %d\n", num_starts); 791 792 for (j = 1; j <= num_starts; j++) { 793 pr_debug("Sending STARTUP #%d\n", j); 794 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 795 apic_write(APIC_ESR, 0); 796 apic_read(APIC_ESR); 797 pr_debug("After apic_write\n"); 798 799 /* 800 * STARTUP IPI 801 */ 802 803 /* Target chip */ 804 /* Boot on the stack */ 805 /* Kick the second */ 806 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 807 phys_apicid); 808 809 /* 810 * Give the other CPU some time to accept the IPI. 811 */ 812 if (init_udelay == 0) 813 udelay(10); 814 else 815 udelay(300); 816 817 pr_debug("Startup point 1\n"); 818 819 pr_debug("Waiting for send to finish...\n"); 820 send_status = safe_apic_wait_icr_idle(); 821 822 /* 823 * Give the other CPU some time to accept the IPI. 824 */ 825 if (init_udelay == 0) 826 udelay(10); 827 else 828 udelay(200); 829 830 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 831 apic_write(APIC_ESR, 0); 832 accept_status = (apic_read(APIC_ESR) & 0xEF); 833 if (send_status || accept_status) 834 break; 835 } 836 pr_debug("After Startup\n"); 837 838 if (send_status) 839 pr_err("APIC never delivered???\n"); 840 if (accept_status) 841 pr_err("APIC delivery error (%lx)\n", accept_status); 842 843 preempt_enable(); 844 return (send_status | accept_status); 845 } 846 847 /* reduce the number of lines printed when booting a large cpu count system */ 848 static void announce_cpu(int cpu, int apicid) 849 { 850 static int width, node_width, first = 1; 851 static int current_node = NUMA_NO_NODE; 852 int node = early_cpu_to_node(cpu); 853 854 if (!width) 855 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 856 857 if (!node_width) 858 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 859 860 if (system_state < SYSTEM_RUNNING) { 861 if (first) 862 pr_info("x86: Booting SMP configuration:\n"); 863 864 if (node != current_node) { 865 if (current_node > (-1)) 866 pr_cont("\n"); 867 current_node = node; 868 869 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 870 node_width - num_digits(node), " ", node); 871 } 872 873 /* Add padding for the BSP */ 874 if (first) 875 pr_cont("%*s", width + 1, " "); 876 first = 0; 877 878 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 879 } else 880 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 881 node, cpu, apicid); 882 } 883 884 int common_cpu_up(unsigned int cpu, struct task_struct *idle) 885 { 886 int ret; 887 888 /* Just in case we booted with a single CPU. */ 889 alternatives_enable_smp(); 890 891 per_cpu(current_task, cpu) = idle; 892 cpu_init_stack_canary(cpu, idle); 893 894 /* Initialize the interrupt stack(s) */ 895 ret = irq_init_percpu_irqstack(cpu); 896 if (ret) 897 return ret; 898 899 #ifdef CONFIG_X86_32 900 /* Stack for startup_32 can be just as for start_secondary onwards */ 901 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle); 902 #endif 903 return 0; 904 } 905 906 /* 907 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 908 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 909 * Returns zero if startup was successfully sent, else error code from 910 * ->wakeup_secondary_cpu. 911 */ 912 static int do_boot_cpu(u32 apicid, unsigned int cpu, struct task_struct *idle) 913 { 914 unsigned long start_ip = real_mode_header->trampoline_start; 915 int ret; 916 917 #ifdef CONFIG_X86_64 918 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */ 919 if (apic->wakeup_secondary_cpu_64) 920 start_ip = real_mode_header->trampoline_start64; 921 #endif 922 idle->thread.sp = (unsigned long)task_pt_regs(idle); 923 initial_code = (unsigned long)start_secondary; 924 925 if (IS_ENABLED(CONFIG_X86_32)) { 926 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 927 initial_stack = idle->thread.sp; 928 } else if (!(smpboot_control & STARTUP_PARALLEL_MASK)) { 929 smpboot_control = cpu; 930 } 931 932 /* Enable the espfix hack for this CPU */ 933 init_espfix_ap(cpu); 934 935 /* So we see what's up */ 936 announce_cpu(cpu, apicid); 937 938 /* 939 * This grunge runs the startup process for 940 * the targeted processor. 941 */ 942 if (x86_platform.legacy.warm_reset) { 943 944 pr_debug("Setting warm reset code and vector.\n"); 945 946 smpboot_setup_warm_reset_vector(start_ip); 947 /* 948 * Be paranoid about clearing APIC errors. 949 */ 950 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 951 apic_write(APIC_ESR, 0); 952 apic_read(APIC_ESR); 953 } 954 } 955 956 smp_mb(); 957 958 /* 959 * Wake up a CPU in difference cases: 960 * - Use a method from the APIC driver if one defined, with wakeup 961 * straight to 64-bit mode preferred over wakeup to RM. 962 * Otherwise, 963 * - Use an INIT boot APIC message 964 */ 965 if (apic->wakeup_secondary_cpu_64) 966 ret = apic->wakeup_secondary_cpu_64(apicid, start_ip, cpu); 967 else if (apic->wakeup_secondary_cpu) 968 ret = apic->wakeup_secondary_cpu(apicid, start_ip, cpu); 969 else 970 ret = wakeup_secondary_cpu_via_init(apicid, start_ip, cpu); 971 972 /* If the wakeup mechanism failed, cleanup the warm reset vector */ 973 if (ret) 974 arch_cpuhp_cleanup_kick_cpu(cpu); 975 return ret; 976 } 977 978 int native_kick_ap(unsigned int cpu, struct task_struct *tidle) 979 { 980 u32 apicid = apic->cpu_present_to_apicid(cpu); 981 int err; 982 983 lockdep_assert_irqs_enabled(); 984 985 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 986 987 if (apicid == BAD_APICID || !apic_id_valid(apicid)) { 988 pr_err("CPU %u has invalid APIC ID %x. Aborting bringup\n", cpu, apicid); 989 return -EINVAL; 990 } 991 992 if (!test_bit(apicid, phys_cpu_present_map)) { 993 pr_err("CPU %u APIC ID %x is not present. Aborting bringup\n", cpu, apicid); 994 return -EINVAL; 995 } 996 997 /* 998 * Save current MTRR state in case it was changed since early boot 999 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1000 */ 1001 mtrr_save_state(); 1002 1003 /* the FPU context is blank, nobody can own it */ 1004 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1005 1006 err = common_cpu_up(cpu, tidle); 1007 if (err) 1008 return err; 1009 1010 err = do_boot_cpu(apicid, cpu, tidle); 1011 if (err) 1012 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1013 1014 return err; 1015 } 1016 1017 int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *tidle) 1018 { 1019 return smp_ops.kick_ap_alive(cpu, tidle); 1020 } 1021 1022 void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu) 1023 { 1024 /* Cleanup possible dangling ends... */ 1025 if (smp_ops.kick_ap_alive == native_kick_ap && x86_platform.legacy.warm_reset) 1026 smpboot_restore_warm_reset_vector(); 1027 } 1028 1029 void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu) 1030 { 1031 if (smp_ops.cleanup_dead_cpu) 1032 smp_ops.cleanup_dead_cpu(cpu); 1033 1034 if (system_state == SYSTEM_RUNNING) 1035 pr_info("CPU %u is now offline\n", cpu); 1036 } 1037 1038 void arch_cpuhp_sync_state_poll(void) 1039 { 1040 if (smp_ops.poll_sync_state) 1041 smp_ops.poll_sync_state(); 1042 } 1043 1044 /** 1045 * arch_disable_smp_support() - Disables SMP support for x86 at boottime 1046 */ 1047 void __init arch_disable_smp_support(void) 1048 { 1049 disable_ioapic_support(); 1050 } 1051 1052 /* 1053 * Fall back to non SMP mode after errors. 1054 * 1055 * RED-PEN audit/test this more. I bet there is more state messed up here. 1056 */ 1057 static __init void disable_smp(void) 1058 { 1059 pr_info("SMP disabled\n"); 1060 1061 disable_ioapic_support(); 1062 topology_reset_possible_cpus_up(); 1063 1064 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1065 cpumask_set_cpu(0, topology_core_cpumask(0)); 1066 cpumask_set_cpu(0, topology_die_cpumask(0)); 1067 } 1068 1069 void __init smp_prepare_cpus_common(void) 1070 { 1071 unsigned int cpu, node; 1072 1073 /* Mark all except the boot CPU as hotpluggable */ 1074 for_each_possible_cpu(cpu) { 1075 if (cpu) 1076 per_cpu(cpu_info.cpu_index, cpu) = nr_cpu_ids; 1077 } 1078 1079 for_each_possible_cpu(cpu) { 1080 node = cpu_to_node(cpu); 1081 1082 zalloc_cpumask_var_node(&per_cpu(cpu_sibling_map, cpu), GFP_KERNEL, node); 1083 zalloc_cpumask_var_node(&per_cpu(cpu_core_map, cpu), GFP_KERNEL, node); 1084 zalloc_cpumask_var_node(&per_cpu(cpu_die_map, cpu), GFP_KERNEL, node); 1085 zalloc_cpumask_var_node(&per_cpu(cpu_llc_shared_map, cpu), GFP_KERNEL, node); 1086 zalloc_cpumask_var_node(&per_cpu(cpu_l2c_shared_map, cpu), GFP_KERNEL, node); 1087 } 1088 1089 set_cpu_sibling_map(0); 1090 } 1091 1092 void __init smp_prepare_boot_cpu(void) 1093 { 1094 smp_ops.smp_prepare_boot_cpu(); 1095 } 1096 1097 #ifdef CONFIG_X86_64 1098 /* Establish whether parallel bringup can be supported. */ 1099 bool __init arch_cpuhp_init_parallel_bringup(void) 1100 { 1101 if (!x86_cpuinit.parallel_bringup) { 1102 pr_info("Parallel CPU startup disabled by the platform\n"); 1103 return false; 1104 } 1105 1106 smpboot_control = STARTUP_READ_APICID; 1107 pr_debug("Parallel CPU startup enabled: 0x%08x\n", smpboot_control); 1108 return true; 1109 } 1110 #endif 1111 1112 /* 1113 * Prepare for SMP bootup. 1114 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1115 * for common interface support. 1116 */ 1117 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1118 { 1119 smp_prepare_cpus_common(); 1120 1121 switch (apic_intr_mode) { 1122 case APIC_PIC: 1123 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1124 disable_smp(); 1125 return; 1126 case APIC_SYMMETRIC_IO_NO_ROUTING: 1127 disable_smp(); 1128 /* Setup local timer */ 1129 x86_init.timers.setup_percpu_clockev(); 1130 return; 1131 case APIC_VIRTUAL_WIRE: 1132 case APIC_SYMMETRIC_IO: 1133 break; 1134 } 1135 1136 /* Setup local timer */ 1137 x86_init.timers.setup_percpu_clockev(); 1138 1139 pr_info("CPU0: "); 1140 print_cpu_info(&cpu_data(0)); 1141 1142 uv_system_init(); 1143 1144 smp_set_init_udelay(); 1145 1146 speculative_store_bypass_ht_init(); 1147 1148 snp_set_wakeup_secondary_cpu(); 1149 } 1150 1151 void arch_thaw_secondary_cpus_begin(void) 1152 { 1153 set_cache_aps_delayed_init(true); 1154 } 1155 1156 void arch_thaw_secondary_cpus_end(void) 1157 { 1158 cache_aps_init(); 1159 } 1160 1161 /* 1162 * Early setup to make printk work. 1163 */ 1164 void __init native_smp_prepare_boot_cpu(void) 1165 { 1166 int me = smp_processor_id(); 1167 1168 /* SMP handles this from setup_per_cpu_areas() */ 1169 if (!IS_ENABLED(CONFIG_SMP)) 1170 switch_gdt_and_percpu_base(me); 1171 1172 native_pv_lock_init(); 1173 } 1174 1175 void __init native_smp_cpus_done(unsigned int max_cpus) 1176 { 1177 pr_debug("Boot done\n"); 1178 1179 build_sched_topology(); 1180 nmi_selftest(); 1181 impress_friends(); 1182 cache_aps_init(); 1183 } 1184 1185 /* correctly size the local cpu masks */ 1186 void __init setup_cpu_local_masks(void) 1187 { 1188 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 1189 } 1190 1191 #ifdef CONFIG_HOTPLUG_CPU 1192 1193 /* Recompute SMT state for all CPUs on offline */ 1194 static void recompute_smt_state(void) 1195 { 1196 int max_threads, cpu; 1197 1198 max_threads = 0; 1199 for_each_online_cpu (cpu) { 1200 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1201 1202 if (threads > max_threads) 1203 max_threads = threads; 1204 } 1205 __max_smt_threads = max_threads; 1206 } 1207 1208 static void remove_siblinginfo(int cpu) 1209 { 1210 int sibling; 1211 struct cpuinfo_x86 *c = &cpu_data(cpu); 1212 1213 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1214 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1215 /*/ 1216 * last thread sibling in this cpu core going down 1217 */ 1218 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1219 cpu_data(sibling).booted_cores--; 1220 } 1221 1222 for_each_cpu(sibling, topology_die_cpumask(cpu)) 1223 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling)); 1224 1225 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) { 1226 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1227 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1) 1228 cpu_data(sibling).smt_active = false; 1229 } 1230 1231 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1232 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1233 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu)) 1234 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling)); 1235 cpumask_clear(cpu_llc_shared_mask(cpu)); 1236 cpumask_clear(cpu_l2c_shared_mask(cpu)); 1237 cpumask_clear(topology_sibling_cpumask(cpu)); 1238 cpumask_clear(topology_core_cpumask(cpu)); 1239 cpumask_clear(topology_die_cpumask(cpu)); 1240 c->topo.core_id = 0; 1241 c->booted_cores = 0; 1242 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1243 recompute_smt_state(); 1244 } 1245 1246 static void remove_cpu_from_maps(int cpu) 1247 { 1248 set_cpu_online(cpu, false); 1249 numa_remove_cpu(cpu); 1250 } 1251 1252 void cpu_disable_common(void) 1253 { 1254 int cpu = smp_processor_id(); 1255 1256 remove_siblinginfo(cpu); 1257 1258 /* 1259 * Stop allowing kernel-mode FPU. This is needed so that if the CPU is 1260 * brought online again, the initial state is not allowed: 1261 */ 1262 this_cpu_write(kernel_fpu_allowed, false); 1263 1264 /* It's now safe to remove this processor from the online map */ 1265 lock_vector_lock(); 1266 remove_cpu_from_maps(cpu); 1267 unlock_vector_lock(); 1268 fixup_irqs(); 1269 lapic_offline(); 1270 } 1271 1272 int native_cpu_disable(void) 1273 { 1274 int ret; 1275 1276 ret = lapic_can_unplug_cpu(); 1277 if (ret) 1278 return ret; 1279 1280 cpu_disable_common(); 1281 1282 /* 1283 * Disable the local APIC. Otherwise IPI broadcasts will reach 1284 * it. It still responds normally to INIT, NMI, SMI, and SIPI 1285 * messages. 1286 * 1287 * Disabling the APIC must happen after cpu_disable_common() 1288 * which invokes fixup_irqs(). 1289 * 1290 * Disabling the APIC preserves already set bits in IRR, but 1291 * an interrupt arriving after disabling the local APIC does not 1292 * set the corresponding IRR bit. 1293 * 1294 * fixup_irqs() scans IRR for set bits so it can raise a not 1295 * yet handled interrupt on the new destination CPU via an IPI 1296 * but obviously it can't do so for IRR bits which are not set. 1297 * IOW, interrupts arriving after disabling the local APIC will 1298 * be lost. 1299 */ 1300 apic_soft_disable(); 1301 1302 return 0; 1303 } 1304 1305 void play_dead_common(void) 1306 { 1307 idle_task_exit(); 1308 1309 cpuhp_ap_report_dead(); 1310 1311 local_irq_disable(); 1312 } 1313 1314 /* 1315 * We need to flush the caches before going to sleep, lest we have 1316 * dirty data in our caches when we come back up. 1317 */ 1318 void __noreturn mwait_play_dead(unsigned int eax_hint) 1319 { 1320 struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead); 1321 1322 /* Set up state for the kexec() hack below */ 1323 md->status = CPUDEAD_MWAIT_WAIT; 1324 md->control = CPUDEAD_MWAIT_WAIT; 1325 1326 wbinvd(); 1327 1328 while (1) { 1329 /* 1330 * The CLFLUSH is a workaround for erratum AAI65 for 1331 * the Xeon 7400 series. It's not clear it is actually 1332 * needed, but it should be harmless in either case. 1333 * The WBINVD is insufficient due to the spurious-wakeup 1334 * case where we return around the loop. 1335 */ 1336 mb(); 1337 clflush(md); 1338 mb(); 1339 __monitor(md, 0, 0); 1340 mb(); 1341 __mwait(eax_hint, 0); 1342 1343 if (READ_ONCE(md->control) == CPUDEAD_MWAIT_KEXEC_HLT) { 1344 /* 1345 * Kexec is about to happen. Don't go back into mwait() as 1346 * the kexec kernel might overwrite text and data including 1347 * page tables and stack. So mwait() would resume when the 1348 * monitor cache line is written to and then the CPU goes 1349 * south due to overwritten text, page tables and stack. 1350 * 1351 * Note: This does _NOT_ protect against a stray MCE, NMI, 1352 * SMI. They will resume execution at the instruction 1353 * following the HLT instruction and run into the problem 1354 * which this is trying to prevent. 1355 */ 1356 WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT); 1357 while(1) 1358 native_halt(); 1359 } 1360 } 1361 } 1362 1363 /* 1364 * Kick all "offline" CPUs out of mwait on kexec(). See comment in 1365 * mwait_play_dead(). 1366 */ 1367 void smp_kick_mwait_play_dead(void) 1368 { 1369 u32 newstate = CPUDEAD_MWAIT_KEXEC_HLT; 1370 struct mwait_cpu_dead *md; 1371 unsigned int cpu, i; 1372 1373 for_each_cpu_andnot(cpu, cpu_present_mask, cpu_online_mask) { 1374 md = per_cpu_ptr(&mwait_cpu_dead, cpu); 1375 1376 /* Does it sit in mwait_play_dead() ? */ 1377 if (READ_ONCE(md->status) != CPUDEAD_MWAIT_WAIT) 1378 continue; 1379 1380 /* Wait up to 5ms */ 1381 for (i = 0; READ_ONCE(md->status) != newstate && i < 1000; i++) { 1382 /* Bring it out of mwait */ 1383 WRITE_ONCE(md->control, newstate); 1384 udelay(5); 1385 } 1386 1387 if (READ_ONCE(md->status) != newstate) 1388 pr_err_once("CPU%u is stuck in mwait_play_dead()\n", cpu); 1389 } 1390 } 1391 1392 void __noreturn hlt_play_dead(void) 1393 { 1394 if (__this_cpu_read(cpu_info.x86) >= 4) 1395 wbinvd(); 1396 1397 while (1) 1398 native_halt(); 1399 } 1400 1401 /* 1402 * native_play_dead() is essentially a __noreturn function, but it can't 1403 * be marked as such as the compiler may complain about it. 1404 */ 1405 void native_play_dead(void) 1406 { 1407 if (cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS)) 1408 __update_spec_ctrl(0); 1409 1410 play_dead_common(); 1411 tboot_shutdown(TB_SHUTDOWN_WFS); 1412 1413 /* Below returns only on error. */ 1414 cpuidle_play_dead(); 1415 hlt_play_dead(); 1416 } 1417 1418 #else /* ... !CONFIG_HOTPLUG_CPU */ 1419 int native_cpu_disable(void) 1420 { 1421 return -ENOSYS; 1422 } 1423 1424 void native_play_dead(void) 1425 { 1426 BUG(); 1427 } 1428 1429 #endif 1430