1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * x86 SMP booting functions 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 7 * Copyright 2001 Andi Kleen, SuSE Labs. 8 * 9 * Much of the core SMP work is based on previous work by Thomas Radke, to 10 * whom a great many thanks are extended. 11 * 12 * Thanks to Intel for making available several different Pentium, 13 * Pentium Pro and Pentium-II/Xeon MP machines. 14 * Original development of Linux SMP code supported by Caldera. 15 * 16 * Fixes 17 * Felix Koop : NR_CPUS used properly 18 * Jose Renau : Handle single CPU case. 19 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 20 * Greg Wright : Fix for kernel stacks panic. 21 * Erich Boleyn : MP v1.4 and additional changes. 22 * Matthias Sattler : Changes for 2.1 kernel map. 23 * Michel Lespinasse : Changes for 2.1 kernel map. 24 * Michael Chastain : Change trampoline.S to gnu as. 25 * Alan Cox : Dumb bug: 'B' step PPro's are fine 26 * Ingo Molnar : Added APIC timers, based on code 27 * from Jose Renau 28 * Ingo Molnar : various cleanups and rewrites 29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 31 * Andi Kleen : Changed for SMP boot into long mode. 32 * Martin J. Bligh : Added support for multi-quad systems 33 * Dave Jones : Report invalid combinations of Athlon CPUs. 34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 35 * Andi Kleen : Converted to new state machine. 36 * Ashok Raj : CPU hotplug support 37 * Glauber Costa : i386 and x86_64 integration 38 */ 39 40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/export.h> 45 #include <linux/sched.h> 46 #include <linux/sched/topology.h> 47 #include <linux/sched/hotplug.h> 48 #include <linux/sched/task_stack.h> 49 #include <linux/percpu.h> 50 #include <linux/memblock.h> 51 #include <linux/err.h> 52 #include <linux/nmi.h> 53 #include <linux/tboot.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 #include <linux/kexec.h> 57 #include <linux/numa.h> 58 #include <linux/pgtable.h> 59 #include <linux/overflow.h> 60 #include <linux/stackprotector.h> 61 #include <linux/cpuhotplug.h> 62 #include <linux/mc146818rtc.h> 63 #include <linux/acpi.h> 64 65 #include <asm/acpi.h> 66 #include <asm/cacheinfo.h> 67 #include <asm/desc.h> 68 #include <asm/nmi.h> 69 #include <asm/irq.h> 70 #include <asm/realmode.h> 71 #include <asm/cpu.h> 72 #include <asm/numa.h> 73 #include <asm/tlbflush.h> 74 #include <asm/mtrr.h> 75 #include <asm/mwait.h> 76 #include <asm/apic.h> 77 #include <asm/io_apic.h> 78 #include <asm/fpu/api.h> 79 #include <asm/setup.h> 80 #include <asm/uv/uv.h> 81 #include <asm/microcode.h> 82 #include <asm/i8259.h> 83 #include <asm/misc.h> 84 #include <asm/qspinlock.h> 85 #include <asm/intel-family.h> 86 #include <asm/cpu_device_id.h> 87 #include <asm/spec-ctrl.h> 88 #include <asm/hw_irq.h> 89 #include <asm/stackprotector.h> 90 #include <asm/sev.h> 91 #include <asm/spec-ctrl.h> 92 93 /* representing HT siblings of each logical CPU */ 94 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 95 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 96 97 /* representing HT and core siblings of each logical CPU */ 98 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 99 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 100 101 /* representing HT, core, and die siblings of each logical CPU */ 102 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); 103 EXPORT_PER_CPU_SYMBOL(cpu_die_map); 104 105 /* CPUs which are the primary SMT threads */ 106 struct cpumask __cpu_primary_thread_mask __read_mostly; 107 108 /* Representing CPUs for which sibling maps can be computed */ 109 static cpumask_var_t cpu_sibling_setup_mask; 110 111 struct mwait_cpu_dead { 112 unsigned int control; 113 unsigned int status; 114 }; 115 116 #define CPUDEAD_MWAIT_WAIT 0xDEADBEEF 117 #define CPUDEAD_MWAIT_KEXEC_HLT 0x4A17DEAD 118 119 /* 120 * Cache line aligned data for mwait_play_dead(). Separate on purpose so 121 * that it's unlikely to be touched by other CPUs. 122 */ 123 static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead); 124 125 /* Maximum number of SMT threads on any online core */ 126 int __read_mostly __max_smt_threads = 1; 127 128 /* Flag to indicate if a complete sched domain rebuild is required */ 129 bool x86_topology_update; 130 131 int arch_update_cpu_topology(void) 132 { 133 int retval = x86_topology_update; 134 135 x86_topology_update = false; 136 return retval; 137 } 138 139 static unsigned int smpboot_warm_reset_vector_count; 140 141 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 142 { 143 unsigned long flags; 144 145 spin_lock_irqsave(&rtc_lock, flags); 146 if (!smpboot_warm_reset_vector_count++) { 147 CMOS_WRITE(0xa, 0xf); 148 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = start_eip >> 4; 149 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = start_eip & 0xf; 150 } 151 spin_unlock_irqrestore(&rtc_lock, flags); 152 } 153 154 static inline void smpboot_restore_warm_reset_vector(void) 155 { 156 unsigned long flags; 157 158 /* 159 * Paranoid: Set warm reset code and vector here back 160 * to default values. 161 */ 162 spin_lock_irqsave(&rtc_lock, flags); 163 if (!--smpboot_warm_reset_vector_count) { 164 CMOS_WRITE(0, 0xf); 165 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 166 } 167 spin_unlock_irqrestore(&rtc_lock, flags); 168 169 } 170 171 /* Run the next set of setup steps for the upcoming CPU */ 172 static void ap_starting(void) 173 { 174 int cpuid = smp_processor_id(); 175 176 /* Mop up eventual mwait_play_dead() wreckage */ 177 this_cpu_write(mwait_cpu_dead.status, 0); 178 this_cpu_write(mwait_cpu_dead.control, 0); 179 180 /* 181 * If woken up by an INIT in an 82489DX configuration the alive 182 * synchronization guarantees that the CPU does not reach this 183 * point before an INIT_deassert IPI reaches the local APIC, so it 184 * is now safe to touch the local APIC. 185 * 186 * Set up this CPU, first the APIC, which is probably redundant on 187 * most boards. 188 */ 189 apic_ap_setup(); 190 191 /* Save the processor parameters. */ 192 smp_store_cpu_info(cpuid); 193 194 /* 195 * The topology information must be up to date before 196 * notify_cpu_starting(). 197 */ 198 set_cpu_sibling_map(cpuid); 199 200 ap_init_aperfmperf(); 201 202 pr_debug("Stack at about %p\n", &cpuid); 203 204 wmb(); 205 206 /* 207 * This runs the AP through all the cpuhp states to its target 208 * state CPUHP_ONLINE. 209 */ 210 notify_cpu_starting(cpuid); 211 } 212 213 static void ap_calibrate_delay(void) 214 { 215 /* 216 * Calibrate the delay loop and update loops_per_jiffy in cpu_data. 217 * smp_store_cpu_info() stored a value that is close but not as 218 * accurate as the value just calculated. 219 * 220 * As this is invoked after the TSC synchronization check, 221 * calibrate_delay_is_known() will skip the calibration routine 222 * when TSC is synchronized across sockets. 223 */ 224 calibrate_delay(); 225 cpu_data(smp_processor_id()).loops_per_jiffy = loops_per_jiffy; 226 } 227 228 /* 229 * Activate a secondary processor. 230 */ 231 static void notrace start_secondary(void *unused) 232 { 233 /* 234 * Don't put *anything* except direct CPU state initialization 235 * before cpu_init(), SMP booting is too fragile that we want to 236 * limit the things done here to the most necessary things. 237 */ 238 cr4_init(); 239 240 /* 241 * 32-bit specific. 64-bit reaches this code with the correct page 242 * table established. Yet another historical divergence. 243 */ 244 if (IS_ENABLED(CONFIG_X86_32)) { 245 /* switch away from the initial page table */ 246 load_cr3(swapper_pg_dir); 247 __flush_tlb_all(); 248 } 249 250 cpu_init_exception_handling(false); 251 252 /* 253 * Load the microcode before reaching the AP alive synchronization 254 * point below so it is not part of the full per CPU serialized 255 * bringup part when "parallel" bringup is enabled. 256 * 257 * That's even safe when hyperthreading is enabled in the CPU as 258 * the core code starts the primary threads first and leaves the 259 * secondary threads waiting for SIPI. Loading microcode on 260 * physical cores concurrently is a safe operation. 261 * 262 * This covers both the Intel specific issue that concurrent 263 * microcode loading on SMT siblings must be prohibited and the 264 * vendor independent issue`that microcode loading which changes 265 * CPUID, MSRs etc. must be strictly serialized to maintain 266 * software state correctness. 267 */ 268 load_ucode_ap(); 269 270 /* 271 * Synchronization point with the hotplug core. Sets this CPUs 272 * synchronization state to ALIVE and spin-waits for the control CPU to 273 * release this CPU for further bringup. 274 */ 275 cpuhp_ap_sync_alive(); 276 277 cpu_init(); 278 fpu__init_cpu(); 279 rcutree_report_cpu_starting(raw_smp_processor_id()); 280 x86_cpuinit.early_percpu_clock_init(); 281 282 ap_starting(); 283 284 /* Check TSC synchronization with the control CPU. */ 285 check_tsc_sync_target(); 286 287 /* 288 * Calibrate the delay loop after the TSC synchronization check. 289 * This allows to skip the calibration when TSC is synchronized 290 * across sockets. 291 */ 292 ap_calibrate_delay(); 293 294 speculative_store_bypass_ht_init(); 295 296 /* 297 * Lock vector_lock, set CPU online and bring the vector 298 * allocator online. Online must be set with vector_lock held 299 * to prevent a concurrent irq setup/teardown from seeing a 300 * half valid vector space. 301 */ 302 lock_vector_lock(); 303 set_cpu_online(smp_processor_id(), true); 304 lapic_online(); 305 unlock_vector_lock(); 306 x86_platform.nmi_init(); 307 308 /* enable local interrupts */ 309 local_irq_enable(); 310 311 x86_cpuinit.setup_percpu_clockev(); 312 313 wmb(); 314 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 315 } 316 317 /* 318 * The bootstrap kernel entry code has set these up. Save them for 319 * a given CPU 320 */ 321 void smp_store_cpu_info(int id) 322 { 323 struct cpuinfo_x86 *c = &cpu_data(id); 324 325 /* Copy boot_cpu_data only on the first bringup */ 326 if (!c->initialized) 327 *c = boot_cpu_data; 328 c->cpu_index = id; 329 /* 330 * During boot time, CPU0 has this setup already. Save the info when 331 * bringing up an AP. 332 */ 333 identify_secondary_cpu(c); 334 c->initialized = true; 335 } 336 337 static bool 338 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 339 { 340 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 341 342 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 343 } 344 345 static bool 346 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 347 { 348 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 349 350 return !WARN_ONCE(!topology_same_node(c, o), 351 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 352 "[node: %d != %d]. Ignoring dependency.\n", 353 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 354 } 355 356 #define link_mask(mfunc, c1, c2) \ 357 do { \ 358 cpumask_set_cpu((c1), mfunc(c2)); \ 359 cpumask_set_cpu((c2), mfunc(c1)); \ 360 } while (0) 361 362 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 363 { 364 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 365 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 366 367 if (c->topo.pkg_id == o->topo.pkg_id && 368 c->topo.die_id == o->topo.die_id && 369 c->topo.amd_node_id == o->topo.amd_node_id && 370 per_cpu_llc_id(cpu1) == per_cpu_llc_id(cpu2)) { 371 if (c->topo.core_id == o->topo.core_id) 372 return topology_sane(c, o, "smt"); 373 374 if ((c->topo.cu_id != 0xff) && 375 (o->topo.cu_id != 0xff) && 376 (c->topo.cu_id == o->topo.cu_id)) 377 return topology_sane(c, o, "smt"); 378 } 379 380 } else if (c->topo.pkg_id == o->topo.pkg_id && 381 c->topo.die_id == o->topo.die_id && 382 c->topo.core_id == o->topo.core_id) { 383 return topology_sane(c, o, "smt"); 384 } 385 386 return false; 387 } 388 389 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 390 { 391 if (c->topo.pkg_id != o->topo.pkg_id || c->topo.die_id != o->topo.die_id) 392 return false; 393 394 if (cpu_feature_enabled(X86_FEATURE_TOPOEXT) && topology_amd_nodes_per_pkg() > 1) 395 return c->topo.amd_node_id == o->topo.amd_node_id; 396 397 return true; 398 } 399 400 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 401 { 402 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 403 404 /* If the arch didn't set up l2c_id, fall back to SMT */ 405 if (per_cpu_l2c_id(cpu1) == BAD_APICID) 406 return match_smt(c, o); 407 408 /* Do not match if L2 cache id does not match: */ 409 if (per_cpu_l2c_id(cpu1) != per_cpu_l2c_id(cpu2)) 410 return false; 411 412 return topology_sane(c, o, "l2c"); 413 } 414 415 /* 416 * Unlike the other levels, we do not enforce keeping a 417 * multicore group inside a NUMA node. If this happens, we will 418 * discard the MC level of the topology later. 419 */ 420 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 421 { 422 if (c->topo.pkg_id == o->topo.pkg_id) 423 return true; 424 return false; 425 } 426 427 /* 428 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs. 429 * 430 * Any Intel CPU that has multiple nodes per package and does not 431 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology. 432 * 433 * When in SNC mode, these CPUs enumerate an LLC that is shared 434 * by multiple NUMA nodes. The LLC is shared for off-package data 435 * access but private to the NUMA node (half of the package) for 436 * on-package access. CPUID (the source of the information about 437 * the LLC) can only enumerate the cache as shared or unshared, 438 * but not this particular configuration. 439 */ 440 441 static const struct x86_cpu_id intel_cod_cpu[] = { 442 X86_MATCH_VFM(INTEL_HASWELL_X, 0), /* COD */ 443 X86_MATCH_VFM(INTEL_BROADWELL_X, 0), /* COD */ 444 X86_MATCH_VFM(INTEL_ANY, 1), /* SNC */ 445 {} 446 }; 447 448 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 449 { 450 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu); 451 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 452 bool intel_snc = id && id->driver_data; 453 454 /* Do not match if we do not have a valid APICID for cpu: */ 455 if (per_cpu_llc_id(cpu1) == BAD_APICID) 456 return false; 457 458 /* Do not match if LLC id does not match: */ 459 if (per_cpu_llc_id(cpu1) != per_cpu_llc_id(cpu2)) 460 return false; 461 462 /* 463 * Allow the SNC topology without warning. Return of false 464 * means 'c' does not share the LLC of 'o'. This will be 465 * reflected to userspace. 466 */ 467 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc) 468 return false; 469 470 return topology_sane(c, o, "llc"); 471 } 472 473 474 static inline int x86_sched_itmt_flags(void) 475 { 476 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 477 } 478 479 #ifdef CONFIG_SCHED_MC 480 static int x86_core_flags(void) 481 { 482 return cpu_core_flags() | x86_sched_itmt_flags(); 483 } 484 #endif 485 #ifdef CONFIG_SCHED_SMT 486 static int x86_smt_flags(void) 487 { 488 return cpu_smt_flags(); 489 } 490 #endif 491 #ifdef CONFIG_SCHED_CLUSTER 492 static int x86_cluster_flags(void) 493 { 494 return cpu_cluster_flags() | x86_sched_itmt_flags(); 495 } 496 #endif 497 498 static int x86_die_flags(void) 499 { 500 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) 501 return x86_sched_itmt_flags(); 502 503 return 0; 504 } 505 506 /* 507 * Set if a package/die has multiple NUMA nodes inside. 508 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel 509 * Sub-NUMA Clustering have this. 510 */ 511 static bool x86_has_numa_in_package; 512 513 static struct sched_domain_topology_level x86_topology[6]; 514 515 static void __init build_sched_topology(void) 516 { 517 int i = 0; 518 519 #ifdef CONFIG_SCHED_SMT 520 x86_topology[i++] = (struct sched_domain_topology_level){ 521 cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) 522 }; 523 #endif 524 #ifdef CONFIG_SCHED_CLUSTER 525 x86_topology[i++] = (struct sched_domain_topology_level){ 526 cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) 527 }; 528 #endif 529 #ifdef CONFIG_SCHED_MC 530 x86_topology[i++] = (struct sched_domain_topology_level){ 531 cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) 532 }; 533 #endif 534 /* 535 * When there is NUMA topology inside the package skip the PKG domain 536 * since the NUMA domains will auto-magically create the right spanning 537 * domains based on the SLIT. 538 */ 539 if (!x86_has_numa_in_package) { 540 x86_topology[i++] = (struct sched_domain_topology_level){ 541 cpu_cpu_mask, x86_die_flags, SD_INIT_NAME(PKG) 542 }; 543 } 544 545 /* 546 * There must be one trailing NULL entry left. 547 */ 548 BUG_ON(i >= ARRAY_SIZE(x86_topology)-1); 549 550 set_sched_topology(x86_topology); 551 } 552 553 void set_cpu_sibling_map(int cpu) 554 { 555 bool has_smt = __max_threads_per_core > 1; 556 bool has_mp = has_smt || topology_num_cores_per_package() > 1; 557 struct cpuinfo_x86 *c = &cpu_data(cpu); 558 struct cpuinfo_x86 *o; 559 int i, threads; 560 561 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 562 563 if (!has_mp) { 564 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 565 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 566 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu)); 567 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 568 cpumask_set_cpu(cpu, topology_die_cpumask(cpu)); 569 c->booted_cores = 1; 570 return; 571 } 572 573 for_each_cpu(i, cpu_sibling_setup_mask) { 574 o = &cpu_data(i); 575 576 if (match_pkg(c, o) && !topology_same_node(c, o)) 577 x86_has_numa_in_package = true; 578 579 if ((i == cpu) || (has_smt && match_smt(c, o))) 580 link_mask(topology_sibling_cpumask, cpu, i); 581 582 if ((i == cpu) || (has_mp && match_llc(c, o))) 583 link_mask(cpu_llc_shared_mask, cpu, i); 584 585 if ((i == cpu) || (has_mp && match_l2c(c, o))) 586 link_mask(cpu_l2c_shared_mask, cpu, i); 587 588 if ((i == cpu) || (has_mp && match_die(c, o))) 589 link_mask(topology_die_cpumask, cpu, i); 590 } 591 592 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 593 if (threads > __max_smt_threads) 594 __max_smt_threads = threads; 595 596 for_each_cpu(i, topology_sibling_cpumask(cpu)) 597 cpu_data(i).smt_active = threads > 1; 598 599 /* 600 * This needs a separate iteration over the cpus because we rely on all 601 * topology_sibling_cpumask links to be set-up. 602 */ 603 for_each_cpu(i, cpu_sibling_setup_mask) { 604 o = &cpu_data(i); 605 606 if ((i == cpu) || (has_mp && match_pkg(c, o))) { 607 link_mask(topology_core_cpumask, cpu, i); 608 609 /* 610 * Does this new cpu bringup a new core? 611 */ 612 if (threads == 1) { 613 /* 614 * for each core in package, increment 615 * the booted_cores for this new cpu 616 */ 617 if (cpumask_first( 618 topology_sibling_cpumask(i)) == i) 619 c->booted_cores++; 620 /* 621 * increment the core count for all 622 * the other cpus in this package 623 */ 624 if (i != cpu) 625 cpu_data(i).booted_cores++; 626 } else if (i != cpu && !c->booted_cores) 627 c->booted_cores = cpu_data(i).booted_cores; 628 } 629 } 630 } 631 632 /* maps the cpu to the sched domain representing multi-core */ 633 const struct cpumask *cpu_coregroup_mask(int cpu) 634 { 635 return cpu_llc_shared_mask(cpu); 636 } 637 638 const struct cpumask *cpu_clustergroup_mask(int cpu) 639 { 640 return cpu_l2c_shared_mask(cpu); 641 } 642 EXPORT_SYMBOL_GPL(cpu_clustergroup_mask); 643 644 static void impress_friends(void) 645 { 646 int cpu; 647 unsigned long bogosum = 0; 648 /* 649 * Allow the user to impress friends. 650 */ 651 pr_debug("Before bogomips\n"); 652 for_each_online_cpu(cpu) 653 bogosum += cpu_data(cpu).loops_per_jiffy; 654 655 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 656 num_online_cpus(), 657 bogosum/(500000/HZ), 658 (bogosum/(5000/HZ))%100); 659 660 pr_debug("Before bogocount - setting activated=1\n"); 661 } 662 663 /* 664 * The Multiprocessor Specification 1.4 (1997) example code suggests 665 * that there should be a 10ms delay between the BSP asserting INIT 666 * and de-asserting INIT, when starting a remote processor. 667 * But that slows boot and resume on modern processors, which include 668 * many cores and don't require that delay. 669 * 670 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 671 * Modern processor families are quirked to remove the delay entirely. 672 */ 673 #define UDELAY_10MS_DEFAULT 10000 674 675 static unsigned int init_udelay = UINT_MAX; 676 677 static int __init cpu_init_udelay(char *str) 678 { 679 get_option(&str, &init_udelay); 680 681 return 0; 682 } 683 early_param("cpu_init_udelay", cpu_init_udelay); 684 685 static void __init smp_quirk_init_udelay(void) 686 { 687 /* if cmdline changed it from default, leave it alone */ 688 if (init_udelay != UINT_MAX) 689 return; 690 691 /* if modern processor, use no delay */ 692 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 693 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || 694 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 695 init_udelay = 0; 696 return; 697 } 698 /* else, use legacy delay */ 699 init_udelay = UDELAY_10MS_DEFAULT; 700 } 701 702 /* 703 * Wake up AP by INIT, INIT, STARTUP sequence. 704 */ 705 static void send_init_sequence(u32 phys_apicid) 706 { 707 int maxlvt = lapic_get_maxlvt(); 708 709 /* Be paranoid about clearing APIC errors. */ 710 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 711 /* Due to the Pentium erratum 3AP. */ 712 if (maxlvt > 3) 713 apic_write(APIC_ESR, 0); 714 apic_read(APIC_ESR); 715 } 716 717 /* Assert INIT on the target CPU */ 718 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, phys_apicid); 719 safe_apic_wait_icr_idle(); 720 721 udelay(init_udelay); 722 723 /* Deassert INIT on the target CPU */ 724 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 725 safe_apic_wait_icr_idle(); 726 } 727 728 /* 729 * Wake up AP by INIT, INIT, STARTUP sequence. 730 */ 731 static int wakeup_secondary_cpu_via_init(u32 phys_apicid, unsigned long start_eip) 732 { 733 unsigned long send_status = 0, accept_status = 0; 734 int num_starts, j, maxlvt; 735 736 preempt_disable(); 737 maxlvt = lapic_get_maxlvt(); 738 send_init_sequence(phys_apicid); 739 740 mb(); 741 742 /* 743 * Should we send STARTUP IPIs ? 744 * 745 * Determine this based on the APIC version. 746 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 747 */ 748 if (APIC_INTEGRATED(boot_cpu_apic_version)) 749 num_starts = 2; 750 else 751 num_starts = 0; 752 753 /* 754 * Run STARTUP IPI loop. 755 */ 756 pr_debug("#startup loops: %d\n", num_starts); 757 758 for (j = 1; j <= num_starts; j++) { 759 pr_debug("Sending STARTUP #%d\n", j); 760 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 761 apic_write(APIC_ESR, 0); 762 apic_read(APIC_ESR); 763 pr_debug("After apic_write\n"); 764 765 /* 766 * STARTUP IPI 767 */ 768 769 /* Target chip */ 770 /* Boot on the stack */ 771 /* Kick the second */ 772 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 773 phys_apicid); 774 775 /* 776 * Give the other CPU some time to accept the IPI. 777 */ 778 if (init_udelay == 0) 779 udelay(10); 780 else 781 udelay(300); 782 783 pr_debug("Startup point 1\n"); 784 785 pr_debug("Waiting for send to finish...\n"); 786 send_status = safe_apic_wait_icr_idle(); 787 788 /* 789 * Give the other CPU some time to accept the IPI. 790 */ 791 if (init_udelay == 0) 792 udelay(10); 793 else 794 udelay(200); 795 796 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 797 apic_write(APIC_ESR, 0); 798 accept_status = (apic_read(APIC_ESR) & 0xEF); 799 if (send_status || accept_status) 800 break; 801 } 802 pr_debug("After Startup\n"); 803 804 if (send_status) 805 pr_err("APIC never delivered???\n"); 806 if (accept_status) 807 pr_err("APIC delivery error (%lx)\n", accept_status); 808 809 preempt_enable(); 810 return (send_status | accept_status); 811 } 812 813 /* reduce the number of lines printed when booting a large cpu count system */ 814 static void announce_cpu(int cpu, int apicid) 815 { 816 static int width, node_width, first = 1; 817 static int current_node = NUMA_NO_NODE; 818 int node = early_cpu_to_node(cpu); 819 820 if (!width) 821 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 822 823 if (!node_width) 824 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 825 826 if (system_state < SYSTEM_RUNNING) { 827 if (first) 828 pr_info("x86: Booting SMP configuration:\n"); 829 830 if (node != current_node) { 831 if (current_node > (-1)) 832 pr_cont("\n"); 833 current_node = node; 834 835 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 836 node_width - num_digits(node), " ", node); 837 } 838 839 /* Add padding for the BSP */ 840 if (first) 841 pr_cont("%*s", width + 1, " "); 842 first = 0; 843 844 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 845 } else 846 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 847 node, cpu, apicid); 848 } 849 850 int common_cpu_up(unsigned int cpu, struct task_struct *idle) 851 { 852 int ret; 853 854 /* Just in case we booted with a single CPU. */ 855 alternatives_enable_smp(); 856 857 per_cpu(pcpu_hot.current_task, cpu) = idle; 858 cpu_init_stack_canary(cpu, idle); 859 860 /* Initialize the interrupt stack(s) */ 861 ret = irq_init_percpu_irqstack(cpu); 862 if (ret) 863 return ret; 864 865 #ifdef CONFIG_X86_32 866 /* Stack for startup_32 can be just as for start_secondary onwards */ 867 per_cpu(pcpu_hot.top_of_stack, cpu) = task_top_of_stack(idle); 868 #endif 869 return 0; 870 } 871 872 /* 873 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 874 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 875 * Returns zero if startup was successfully sent, else error code from 876 * ->wakeup_secondary_cpu. 877 */ 878 static int do_boot_cpu(u32 apicid, int cpu, struct task_struct *idle) 879 { 880 unsigned long start_ip = real_mode_header->trampoline_start; 881 int ret; 882 883 #ifdef CONFIG_X86_64 884 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */ 885 if (apic->wakeup_secondary_cpu_64) 886 start_ip = real_mode_header->trampoline_start64; 887 #endif 888 idle->thread.sp = (unsigned long)task_pt_regs(idle); 889 initial_code = (unsigned long)start_secondary; 890 891 if (IS_ENABLED(CONFIG_X86_32)) { 892 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 893 initial_stack = idle->thread.sp; 894 } else if (!(smpboot_control & STARTUP_PARALLEL_MASK)) { 895 smpboot_control = cpu; 896 } 897 898 /* Enable the espfix hack for this CPU */ 899 init_espfix_ap(cpu); 900 901 /* So we see what's up */ 902 announce_cpu(cpu, apicid); 903 904 /* 905 * This grunge runs the startup process for 906 * the targeted processor. 907 */ 908 if (x86_platform.legacy.warm_reset) { 909 910 pr_debug("Setting warm reset code and vector.\n"); 911 912 smpboot_setup_warm_reset_vector(start_ip); 913 /* 914 * Be paranoid about clearing APIC errors. 915 */ 916 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 917 apic_write(APIC_ESR, 0); 918 apic_read(APIC_ESR); 919 } 920 } 921 922 smp_mb(); 923 924 /* 925 * Wake up a CPU in difference cases: 926 * - Use a method from the APIC driver if one defined, with wakeup 927 * straight to 64-bit mode preferred over wakeup to RM. 928 * Otherwise, 929 * - Use an INIT boot APIC message 930 */ 931 if (apic->wakeup_secondary_cpu_64) 932 ret = apic->wakeup_secondary_cpu_64(apicid, start_ip); 933 else if (apic->wakeup_secondary_cpu) 934 ret = apic->wakeup_secondary_cpu(apicid, start_ip); 935 else 936 ret = wakeup_secondary_cpu_via_init(apicid, start_ip); 937 938 /* If the wakeup mechanism failed, cleanup the warm reset vector */ 939 if (ret) 940 arch_cpuhp_cleanup_kick_cpu(cpu); 941 return ret; 942 } 943 944 int native_kick_ap(unsigned int cpu, struct task_struct *tidle) 945 { 946 u32 apicid = apic->cpu_present_to_apicid(cpu); 947 int err; 948 949 lockdep_assert_irqs_enabled(); 950 951 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 952 953 if (apicid == BAD_APICID || !apic_id_valid(apicid)) { 954 pr_err("CPU %u has invalid APIC ID %x. Aborting bringup\n", cpu, apicid); 955 return -EINVAL; 956 } 957 958 if (!test_bit(apicid, phys_cpu_present_map)) { 959 pr_err("CPU %u APIC ID %x is not present. Aborting bringup\n", cpu, apicid); 960 return -EINVAL; 961 } 962 963 /* 964 * Save current MTRR state in case it was changed since early boot 965 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 966 */ 967 mtrr_save_state(); 968 969 /* the FPU context is blank, nobody can own it */ 970 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 971 972 err = common_cpu_up(cpu, tidle); 973 if (err) 974 return err; 975 976 err = do_boot_cpu(apicid, cpu, tidle); 977 if (err) 978 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 979 980 return err; 981 } 982 983 int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *tidle) 984 { 985 return smp_ops.kick_ap_alive(cpu, tidle); 986 } 987 988 void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu) 989 { 990 /* Cleanup possible dangling ends... */ 991 if (smp_ops.kick_ap_alive == native_kick_ap && x86_platform.legacy.warm_reset) 992 smpboot_restore_warm_reset_vector(); 993 } 994 995 void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu) 996 { 997 if (smp_ops.cleanup_dead_cpu) 998 smp_ops.cleanup_dead_cpu(cpu); 999 1000 if (system_state == SYSTEM_RUNNING) 1001 pr_info("CPU %u is now offline\n", cpu); 1002 } 1003 1004 void arch_cpuhp_sync_state_poll(void) 1005 { 1006 if (smp_ops.poll_sync_state) 1007 smp_ops.poll_sync_state(); 1008 } 1009 1010 /** 1011 * arch_disable_smp_support() - Disables SMP support for x86 at boottime 1012 */ 1013 void __init arch_disable_smp_support(void) 1014 { 1015 disable_ioapic_support(); 1016 } 1017 1018 /* 1019 * Fall back to non SMP mode after errors. 1020 * 1021 * RED-PEN audit/test this more. I bet there is more state messed up here. 1022 */ 1023 static __init void disable_smp(void) 1024 { 1025 pr_info("SMP disabled\n"); 1026 1027 disable_ioapic_support(); 1028 topology_reset_possible_cpus_up(); 1029 1030 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1031 cpumask_set_cpu(0, topology_core_cpumask(0)); 1032 cpumask_set_cpu(0, topology_die_cpumask(0)); 1033 } 1034 1035 void __init smp_prepare_cpus_common(void) 1036 { 1037 unsigned int cpu, node; 1038 1039 /* Mark all except the boot CPU as hotpluggable */ 1040 for_each_possible_cpu(cpu) { 1041 if (cpu) 1042 per_cpu(cpu_info.cpu_index, cpu) = nr_cpu_ids; 1043 } 1044 1045 for_each_possible_cpu(cpu) { 1046 node = cpu_to_node(cpu); 1047 1048 zalloc_cpumask_var_node(&per_cpu(cpu_sibling_map, cpu), GFP_KERNEL, node); 1049 zalloc_cpumask_var_node(&per_cpu(cpu_core_map, cpu), GFP_KERNEL, node); 1050 zalloc_cpumask_var_node(&per_cpu(cpu_die_map, cpu), GFP_KERNEL, node); 1051 zalloc_cpumask_var_node(&per_cpu(cpu_llc_shared_map, cpu), GFP_KERNEL, node); 1052 zalloc_cpumask_var_node(&per_cpu(cpu_l2c_shared_map, cpu), GFP_KERNEL, node); 1053 } 1054 1055 set_cpu_sibling_map(0); 1056 } 1057 1058 void __init smp_prepare_boot_cpu(void) 1059 { 1060 smp_ops.smp_prepare_boot_cpu(); 1061 } 1062 1063 #ifdef CONFIG_X86_64 1064 /* Establish whether parallel bringup can be supported. */ 1065 bool __init arch_cpuhp_init_parallel_bringup(void) 1066 { 1067 if (!x86_cpuinit.parallel_bringup) { 1068 pr_info("Parallel CPU startup disabled by the platform\n"); 1069 return false; 1070 } 1071 1072 smpboot_control = STARTUP_READ_APICID; 1073 pr_debug("Parallel CPU startup enabled: 0x%08x\n", smpboot_control); 1074 return true; 1075 } 1076 #endif 1077 1078 /* 1079 * Prepare for SMP bootup. 1080 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1081 * for common interface support. 1082 */ 1083 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1084 { 1085 smp_prepare_cpus_common(); 1086 1087 switch (apic_intr_mode) { 1088 case APIC_PIC: 1089 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1090 disable_smp(); 1091 return; 1092 case APIC_SYMMETRIC_IO_NO_ROUTING: 1093 disable_smp(); 1094 /* Setup local timer */ 1095 x86_init.timers.setup_percpu_clockev(); 1096 return; 1097 case APIC_VIRTUAL_WIRE: 1098 case APIC_SYMMETRIC_IO: 1099 break; 1100 } 1101 1102 /* Setup local timer */ 1103 x86_init.timers.setup_percpu_clockev(); 1104 1105 pr_info("CPU0: "); 1106 print_cpu_info(&cpu_data(0)); 1107 1108 uv_system_init(); 1109 1110 smp_quirk_init_udelay(); 1111 1112 speculative_store_bypass_ht_init(); 1113 1114 snp_set_wakeup_secondary_cpu(); 1115 } 1116 1117 void arch_thaw_secondary_cpus_begin(void) 1118 { 1119 set_cache_aps_delayed_init(true); 1120 } 1121 1122 void arch_thaw_secondary_cpus_end(void) 1123 { 1124 cache_aps_init(); 1125 } 1126 1127 /* 1128 * Early setup to make printk work. 1129 */ 1130 void __init native_smp_prepare_boot_cpu(void) 1131 { 1132 int me = smp_processor_id(); 1133 1134 /* SMP handles this from setup_per_cpu_areas() */ 1135 if (!IS_ENABLED(CONFIG_SMP)) 1136 switch_gdt_and_percpu_base(me); 1137 1138 native_pv_lock_init(); 1139 } 1140 1141 void __init native_smp_cpus_done(unsigned int max_cpus) 1142 { 1143 pr_debug("Boot done\n"); 1144 1145 build_sched_topology(); 1146 nmi_selftest(); 1147 impress_friends(); 1148 cache_aps_init(); 1149 } 1150 1151 /* correctly size the local cpu masks */ 1152 void __init setup_cpu_local_masks(void) 1153 { 1154 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 1155 } 1156 1157 #ifdef CONFIG_HOTPLUG_CPU 1158 1159 /* Recompute SMT state for all CPUs on offline */ 1160 static void recompute_smt_state(void) 1161 { 1162 int max_threads, cpu; 1163 1164 max_threads = 0; 1165 for_each_online_cpu (cpu) { 1166 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1167 1168 if (threads > max_threads) 1169 max_threads = threads; 1170 } 1171 __max_smt_threads = max_threads; 1172 } 1173 1174 static void remove_siblinginfo(int cpu) 1175 { 1176 int sibling; 1177 struct cpuinfo_x86 *c = &cpu_data(cpu); 1178 1179 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1180 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1181 /*/ 1182 * last thread sibling in this cpu core going down 1183 */ 1184 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1185 cpu_data(sibling).booted_cores--; 1186 } 1187 1188 for_each_cpu(sibling, topology_die_cpumask(cpu)) 1189 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling)); 1190 1191 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) { 1192 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1193 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1) 1194 cpu_data(sibling).smt_active = false; 1195 } 1196 1197 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1198 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1199 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu)) 1200 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling)); 1201 cpumask_clear(cpu_llc_shared_mask(cpu)); 1202 cpumask_clear(cpu_l2c_shared_mask(cpu)); 1203 cpumask_clear(topology_sibling_cpumask(cpu)); 1204 cpumask_clear(topology_core_cpumask(cpu)); 1205 cpumask_clear(topology_die_cpumask(cpu)); 1206 c->topo.core_id = 0; 1207 c->booted_cores = 0; 1208 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1209 recompute_smt_state(); 1210 } 1211 1212 static void remove_cpu_from_maps(int cpu) 1213 { 1214 set_cpu_online(cpu, false); 1215 numa_remove_cpu(cpu); 1216 } 1217 1218 void cpu_disable_common(void) 1219 { 1220 int cpu = smp_processor_id(); 1221 1222 remove_siblinginfo(cpu); 1223 1224 /* It's now safe to remove this processor from the online map */ 1225 lock_vector_lock(); 1226 remove_cpu_from_maps(cpu); 1227 unlock_vector_lock(); 1228 fixup_irqs(); 1229 lapic_offline(); 1230 } 1231 1232 int native_cpu_disable(void) 1233 { 1234 int ret; 1235 1236 ret = lapic_can_unplug_cpu(); 1237 if (ret) 1238 return ret; 1239 1240 cpu_disable_common(); 1241 1242 /* 1243 * Disable the local APIC. Otherwise IPI broadcasts will reach 1244 * it. It still responds normally to INIT, NMI, SMI, and SIPI 1245 * messages. 1246 * 1247 * Disabling the APIC must happen after cpu_disable_common() 1248 * which invokes fixup_irqs(). 1249 * 1250 * Disabling the APIC preserves already set bits in IRR, but 1251 * an interrupt arriving after disabling the local APIC does not 1252 * set the corresponding IRR bit. 1253 * 1254 * fixup_irqs() scans IRR for set bits so it can raise a not 1255 * yet handled interrupt on the new destination CPU via an IPI 1256 * but obviously it can't do so for IRR bits which are not set. 1257 * IOW, interrupts arriving after disabling the local APIC will 1258 * be lost. 1259 */ 1260 apic_soft_disable(); 1261 1262 return 0; 1263 } 1264 1265 void play_dead_common(void) 1266 { 1267 idle_task_exit(); 1268 1269 cpuhp_ap_report_dead(); 1270 1271 local_irq_disable(); 1272 } 1273 1274 /* 1275 * We need to flush the caches before going to sleep, lest we have 1276 * dirty data in our caches when we come back up. 1277 */ 1278 static inline void mwait_play_dead(void) 1279 { 1280 struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead); 1281 unsigned int eax, ebx, ecx, edx; 1282 unsigned int highest_cstate = 0; 1283 unsigned int highest_subcstate = 0; 1284 int i; 1285 1286 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1287 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 1288 return; 1289 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1290 return; 1291 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1292 return; 1293 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1294 return; 1295 1296 eax = CPUID_MWAIT_LEAF; 1297 ecx = 0; 1298 native_cpuid(&eax, &ebx, &ecx, &edx); 1299 1300 /* 1301 * eax will be 0 if EDX enumeration is not valid. 1302 * Initialized below to cstate, sub_cstate value when EDX is valid. 1303 */ 1304 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1305 eax = 0; 1306 } else { 1307 edx >>= MWAIT_SUBSTATE_SIZE; 1308 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1309 if (edx & MWAIT_SUBSTATE_MASK) { 1310 highest_cstate = i; 1311 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1312 } 1313 } 1314 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1315 (highest_subcstate - 1); 1316 } 1317 1318 /* Set up state for the kexec() hack below */ 1319 md->status = CPUDEAD_MWAIT_WAIT; 1320 md->control = CPUDEAD_MWAIT_WAIT; 1321 1322 wbinvd(); 1323 1324 while (1) { 1325 /* 1326 * The CLFLUSH is a workaround for erratum AAI65 for 1327 * the Xeon 7400 series. It's not clear it is actually 1328 * needed, but it should be harmless in either case. 1329 * The WBINVD is insufficient due to the spurious-wakeup 1330 * case where we return around the loop. 1331 */ 1332 mb(); 1333 clflush(md); 1334 mb(); 1335 __monitor(md, 0, 0); 1336 mb(); 1337 __mwait(eax, 0); 1338 1339 if (READ_ONCE(md->control) == CPUDEAD_MWAIT_KEXEC_HLT) { 1340 /* 1341 * Kexec is about to happen. Don't go back into mwait() as 1342 * the kexec kernel might overwrite text and data including 1343 * page tables and stack. So mwait() would resume when the 1344 * monitor cache line is written to and then the CPU goes 1345 * south due to overwritten text, page tables and stack. 1346 * 1347 * Note: This does _NOT_ protect against a stray MCE, NMI, 1348 * SMI. They will resume execution at the instruction 1349 * following the HLT instruction and run into the problem 1350 * which this is trying to prevent. 1351 */ 1352 WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT); 1353 while(1) 1354 native_halt(); 1355 } 1356 } 1357 } 1358 1359 /* 1360 * Kick all "offline" CPUs out of mwait on kexec(). See comment in 1361 * mwait_play_dead(). 1362 */ 1363 void smp_kick_mwait_play_dead(void) 1364 { 1365 u32 newstate = CPUDEAD_MWAIT_KEXEC_HLT; 1366 struct mwait_cpu_dead *md; 1367 unsigned int cpu, i; 1368 1369 for_each_cpu_andnot(cpu, cpu_present_mask, cpu_online_mask) { 1370 md = per_cpu_ptr(&mwait_cpu_dead, cpu); 1371 1372 /* Does it sit in mwait_play_dead() ? */ 1373 if (READ_ONCE(md->status) != CPUDEAD_MWAIT_WAIT) 1374 continue; 1375 1376 /* Wait up to 5ms */ 1377 for (i = 0; READ_ONCE(md->status) != newstate && i < 1000; i++) { 1378 /* Bring it out of mwait */ 1379 WRITE_ONCE(md->control, newstate); 1380 udelay(5); 1381 } 1382 1383 if (READ_ONCE(md->status) != newstate) 1384 pr_err_once("CPU%u is stuck in mwait_play_dead()\n", cpu); 1385 } 1386 } 1387 1388 void __noreturn hlt_play_dead(void) 1389 { 1390 if (__this_cpu_read(cpu_info.x86) >= 4) 1391 wbinvd(); 1392 1393 while (1) 1394 native_halt(); 1395 } 1396 1397 /* 1398 * native_play_dead() is essentially a __noreturn function, but it can't 1399 * be marked as such as the compiler may complain about it. 1400 */ 1401 void native_play_dead(void) 1402 { 1403 if (cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS)) 1404 __update_spec_ctrl(0); 1405 1406 play_dead_common(); 1407 tboot_shutdown(TB_SHUTDOWN_WFS); 1408 1409 mwait_play_dead(); 1410 if (cpuidle_play_dead()) 1411 hlt_play_dead(); 1412 } 1413 1414 #else /* ... !CONFIG_HOTPLUG_CPU */ 1415 int native_cpu_disable(void) 1416 { 1417 return -ENOSYS; 1418 } 1419 1420 void native_play_dead(void) 1421 { 1422 BUG(); 1423 } 1424 1425 #endif 1426