1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/module.h> 45 #include <linux/sched.h> 46 #include <linux/percpu.h> 47 #include <linux/bootmem.h> 48 #include <linux/err.h> 49 #include <linux/nmi.h> 50 #include <linux/tboot.h> 51 #include <linux/stackprotector.h> 52 #include <linux/gfp.h> 53 #include <linux/cpuidle.h> 54 55 #include <asm/acpi.h> 56 #include <asm/desc.h> 57 #include <asm/nmi.h> 58 #include <asm/irq.h> 59 #include <asm/idle.h> 60 #include <asm/realmode.h> 61 #include <asm/cpu.h> 62 #include <asm/numa.h> 63 #include <asm/pgtable.h> 64 #include <asm/tlbflush.h> 65 #include <asm/mtrr.h> 66 #include <asm/mwait.h> 67 #include <asm/apic.h> 68 #include <asm/io_apic.h> 69 #include <asm/setup.h> 70 #include <asm/uv/uv.h> 71 #include <linux/mc146818rtc.h> 72 73 #include <asm/smpboot_hooks.h> 74 #include <asm/i8259.h> 75 76 #include <asm/realmode.h> 77 78 /* State of each CPU */ 79 DEFINE_PER_CPU(int, cpu_state) = { 0 }; 80 81 #ifdef CONFIG_HOTPLUG_CPU 82 /* 83 * We need this for trampoline_base protection from concurrent accesses when 84 * off- and onlining cores wildly. 85 */ 86 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex); 87 88 void cpu_hotplug_driver_lock(void) 89 { 90 mutex_lock(&x86_cpu_hotplug_driver_mutex); 91 } 92 93 void cpu_hotplug_driver_unlock(void) 94 { 95 mutex_unlock(&x86_cpu_hotplug_driver_mutex); 96 } 97 98 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; } 99 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; } 100 #endif 101 102 /* Number of siblings per CPU package */ 103 int smp_num_siblings = 1; 104 EXPORT_SYMBOL(smp_num_siblings); 105 106 /* Last level cache ID of each logical CPU */ 107 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; 108 109 /* representing HT siblings of each logical CPU */ 110 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); 111 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 112 113 /* representing HT and core siblings of each logical CPU */ 114 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); 115 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 116 117 DEFINE_PER_CPU(cpumask_var_t, cpu_llc_shared_map); 118 119 /* Per CPU bogomips and other parameters */ 120 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 121 EXPORT_PER_CPU_SYMBOL(cpu_info); 122 123 atomic_t init_deasserted; 124 125 /* 126 * Report back to the Boot Processor. 127 * Running on AP. 128 */ 129 static void __cpuinit smp_callin(void) 130 { 131 int cpuid, phys_id; 132 unsigned long timeout; 133 134 /* 135 * If waken up by an INIT in an 82489DX configuration 136 * we may get here before an INIT-deassert IPI reaches 137 * our local APIC. We have to wait for the IPI or we'll 138 * lock up on an APIC access. 139 */ 140 if (apic->wait_for_init_deassert) 141 apic->wait_for_init_deassert(&init_deasserted); 142 143 /* 144 * (This works even if the APIC is not enabled.) 145 */ 146 phys_id = read_apic_id(); 147 cpuid = smp_processor_id(); 148 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { 149 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, 150 phys_id, cpuid); 151 } 152 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); 153 154 /* 155 * STARTUP IPIs are fragile beasts as they might sometimes 156 * trigger some glue motherboard logic. Complete APIC bus 157 * silence for 1 second, this overestimates the time the 158 * boot CPU is spending to send the up to 2 STARTUP IPIs 159 * by a factor of two. This should be enough. 160 */ 161 162 /* 163 * Waiting 2s total for startup (udelay is not yet working) 164 */ 165 timeout = jiffies + 2*HZ; 166 while (time_before(jiffies, timeout)) { 167 /* 168 * Has the boot CPU finished it's STARTUP sequence? 169 */ 170 if (cpumask_test_cpu(cpuid, cpu_callout_mask)) 171 break; 172 cpu_relax(); 173 } 174 175 if (!time_before(jiffies, timeout)) { 176 panic("%s: CPU%d started up but did not get a callout!\n", 177 __func__, cpuid); 178 } 179 180 /* 181 * the boot CPU has finished the init stage and is spinning 182 * on callin_map until we finish. We are free to set up this 183 * CPU, first the APIC. (this is probably redundant on most 184 * boards) 185 */ 186 187 pr_debug("CALLIN, before setup_local_APIC().\n"); 188 if (apic->smp_callin_clear_local_apic) 189 apic->smp_callin_clear_local_apic(); 190 setup_local_APIC(); 191 end_local_APIC_setup(); 192 193 /* 194 * Need to setup vector mappings before we enable interrupts. 195 */ 196 setup_vector_irq(smp_processor_id()); 197 198 /* 199 * Save our processor parameters. Note: this information 200 * is needed for clock calibration. 201 */ 202 smp_store_cpu_info(cpuid); 203 204 /* 205 * Get our bogomips. 206 * Update loops_per_jiffy in cpu_data. Previous call to 207 * smp_store_cpu_info() stored a value that is close but not as 208 * accurate as the value just calculated. 209 */ 210 calibrate_delay(); 211 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 212 pr_debug("Stack at about %p\n", &cpuid); 213 214 /* 215 * This must be done before setting cpu_online_mask 216 * or calling notify_cpu_starting. 217 */ 218 set_cpu_sibling_map(raw_smp_processor_id()); 219 wmb(); 220 221 notify_cpu_starting(cpuid); 222 223 /* 224 * Allow the master to continue. 225 */ 226 cpumask_set_cpu(cpuid, cpu_callin_mask); 227 } 228 229 /* 230 * Activate a secondary processor. 231 */ 232 notrace static void __cpuinit start_secondary(void *unused) 233 { 234 /* 235 * Don't put *anything* before cpu_init(), SMP booting is too 236 * fragile that we want to limit the things done here to the 237 * most necessary things. 238 */ 239 cpu_init(); 240 x86_cpuinit.early_percpu_clock_init(); 241 preempt_disable(); 242 smp_callin(); 243 244 #ifdef CONFIG_X86_32 245 /* switch away from the initial page table */ 246 load_cr3(swapper_pg_dir); 247 __flush_tlb_all(); 248 #endif 249 250 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 251 barrier(); 252 /* 253 * Check TSC synchronization with the BP: 254 */ 255 check_tsc_sync_target(); 256 257 /* 258 * We need to hold call_lock, so there is no inconsistency 259 * between the time smp_call_function() determines number of 260 * IPI recipients, and the time when the determination is made 261 * for which cpus receive the IPI. Holding this 262 * lock helps us to not include this cpu in a currently in progress 263 * smp_call_function(). 264 * 265 * We need to hold vector_lock so there the set of online cpus 266 * does not change while we are assigning vectors to cpus. Holding 267 * this lock ensures we don't half assign or remove an irq from a cpu. 268 */ 269 ipi_call_lock(); 270 lock_vector_lock(); 271 set_cpu_online(smp_processor_id(), true); 272 unlock_vector_lock(); 273 ipi_call_unlock(); 274 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; 275 x86_platform.nmi_init(); 276 277 /* enable local interrupts */ 278 local_irq_enable(); 279 280 /* to prevent fake stack check failure in clock setup */ 281 boot_init_stack_canary(); 282 283 x86_cpuinit.setup_percpu_clockev(); 284 285 wmb(); 286 cpu_idle(); 287 } 288 289 /* 290 * The bootstrap kernel entry code has set these up. Save them for 291 * a given CPU 292 */ 293 294 void __cpuinit smp_store_cpu_info(int id) 295 { 296 struct cpuinfo_x86 *c = &cpu_data(id); 297 298 *c = boot_cpu_data; 299 c->cpu_index = id; 300 if (id != 0) 301 identify_secondary_cpu(c); 302 } 303 304 static bool __cpuinit 305 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 306 { 307 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 308 309 return !WARN_ONCE(cpu_to_node(cpu1) != cpu_to_node(cpu2), 310 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 311 "[node: %d != %d]. Ignoring dependency.\n", 312 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 313 } 314 315 #define link_mask(_m, c1, c2) \ 316 do { \ 317 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \ 318 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \ 319 } while (0) 320 321 static bool __cpuinit match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 322 { 323 if (cpu_has(c, X86_FEATURE_TOPOEXT)) { 324 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 325 326 if (c->phys_proc_id == o->phys_proc_id && 327 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && 328 c->compute_unit_id == o->compute_unit_id) 329 return topology_sane(c, o, "smt"); 330 331 } else if (c->phys_proc_id == o->phys_proc_id && 332 c->cpu_core_id == o->cpu_core_id) { 333 return topology_sane(c, o, "smt"); 334 } 335 336 return false; 337 } 338 339 static bool __cpuinit match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 340 { 341 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 342 343 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && 344 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) 345 return topology_sane(c, o, "llc"); 346 347 return false; 348 } 349 350 static bool __cpuinit match_mc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 351 { 352 if (c->phys_proc_id == o->phys_proc_id) { 353 if (cpu_has(c, X86_FEATURE_AMD_DCM)) 354 return true; 355 356 return topology_sane(c, o, "mc"); 357 } 358 return false; 359 } 360 361 void __cpuinit set_cpu_sibling_map(int cpu) 362 { 363 bool has_mc = boot_cpu_data.x86_max_cores > 1; 364 bool has_smt = smp_num_siblings > 1; 365 struct cpuinfo_x86 *c = &cpu_data(cpu); 366 struct cpuinfo_x86 *o; 367 int i; 368 369 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 370 371 if (!has_smt && !has_mc) { 372 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); 373 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 374 cpumask_set_cpu(cpu, cpu_core_mask(cpu)); 375 c->booted_cores = 1; 376 return; 377 } 378 379 for_each_cpu(i, cpu_sibling_setup_mask) { 380 o = &cpu_data(i); 381 382 if ((i == cpu) || (has_smt && match_smt(c, o))) 383 link_mask(sibling, cpu, i); 384 385 if ((i == cpu) || (has_mc && match_llc(c, o))) 386 link_mask(llc_shared, cpu, i); 387 388 } 389 390 /* 391 * This needs a separate iteration over the cpus because we rely on all 392 * cpu_sibling_mask links to be set-up. 393 */ 394 for_each_cpu(i, cpu_sibling_setup_mask) { 395 o = &cpu_data(i); 396 397 if ((i == cpu) || (has_mc && match_mc(c, o))) { 398 link_mask(core, cpu, i); 399 400 /* 401 * Does this new cpu bringup a new core? 402 */ 403 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { 404 /* 405 * for each core in package, increment 406 * the booted_cores for this new cpu 407 */ 408 if (cpumask_first(cpu_sibling_mask(i)) == i) 409 c->booted_cores++; 410 /* 411 * increment the core count for all 412 * the other cpus in this package 413 */ 414 if (i != cpu) 415 cpu_data(i).booted_cores++; 416 } else if (i != cpu && !c->booted_cores) 417 c->booted_cores = cpu_data(i).booted_cores; 418 } 419 } 420 } 421 422 /* maps the cpu to the sched domain representing multi-core */ 423 const struct cpumask *cpu_coregroup_mask(int cpu) 424 { 425 return cpu_llc_shared_mask(cpu); 426 } 427 428 static void impress_friends(void) 429 { 430 int cpu; 431 unsigned long bogosum = 0; 432 /* 433 * Allow the user to impress friends. 434 */ 435 pr_debug("Before bogomips.\n"); 436 for_each_possible_cpu(cpu) 437 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 438 bogosum += cpu_data(cpu).loops_per_jiffy; 439 printk(KERN_INFO 440 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", 441 num_online_cpus(), 442 bogosum/(500000/HZ), 443 (bogosum/(5000/HZ))%100); 444 445 pr_debug("Before bogocount - setting activated=1.\n"); 446 } 447 448 void __inquire_remote_apic(int apicid) 449 { 450 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 451 const char * const names[] = { "ID", "VERSION", "SPIV" }; 452 int timeout; 453 u32 status; 454 455 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); 456 457 for (i = 0; i < ARRAY_SIZE(regs); i++) { 458 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); 459 460 /* 461 * Wait for idle. 462 */ 463 status = safe_apic_wait_icr_idle(); 464 if (status) 465 printk(KERN_CONT 466 "a previous APIC delivery may have failed\n"); 467 468 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 469 470 timeout = 0; 471 do { 472 udelay(100); 473 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 474 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 475 476 switch (status) { 477 case APIC_ICR_RR_VALID: 478 status = apic_read(APIC_RRR); 479 printk(KERN_CONT "%08x\n", status); 480 break; 481 default: 482 printk(KERN_CONT "failed\n"); 483 } 484 } 485 } 486 487 /* 488 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 489 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 490 * won't ... remember to clear down the APIC, etc later. 491 */ 492 int __cpuinit 493 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) 494 { 495 unsigned long send_status, accept_status = 0; 496 int maxlvt; 497 498 /* Target chip */ 499 /* Boot on the stack */ 500 /* Kick the second */ 501 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); 502 503 pr_debug("Waiting for send to finish...\n"); 504 send_status = safe_apic_wait_icr_idle(); 505 506 /* 507 * Give the other CPU some time to accept the IPI. 508 */ 509 udelay(200); 510 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 511 maxlvt = lapic_get_maxlvt(); 512 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 513 apic_write(APIC_ESR, 0); 514 accept_status = (apic_read(APIC_ESR) & 0xEF); 515 } 516 pr_debug("NMI sent.\n"); 517 518 if (send_status) 519 printk(KERN_ERR "APIC never delivered???\n"); 520 if (accept_status) 521 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 522 523 return (send_status | accept_status); 524 } 525 526 static int __cpuinit 527 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 528 { 529 unsigned long send_status, accept_status = 0; 530 int maxlvt, num_starts, j; 531 532 maxlvt = lapic_get_maxlvt(); 533 534 /* 535 * Be paranoid about clearing APIC errors. 536 */ 537 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 538 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 539 apic_write(APIC_ESR, 0); 540 apic_read(APIC_ESR); 541 } 542 543 pr_debug("Asserting INIT.\n"); 544 545 /* 546 * Turn INIT on target chip 547 */ 548 /* 549 * Send IPI 550 */ 551 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 552 phys_apicid); 553 554 pr_debug("Waiting for send to finish...\n"); 555 send_status = safe_apic_wait_icr_idle(); 556 557 mdelay(10); 558 559 pr_debug("Deasserting INIT.\n"); 560 561 /* Target chip */ 562 /* Send IPI */ 563 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 564 565 pr_debug("Waiting for send to finish...\n"); 566 send_status = safe_apic_wait_icr_idle(); 567 568 mb(); 569 atomic_set(&init_deasserted, 1); 570 571 /* 572 * Should we send STARTUP IPIs ? 573 * 574 * Determine this based on the APIC version. 575 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 576 */ 577 if (APIC_INTEGRATED(apic_version[phys_apicid])) 578 num_starts = 2; 579 else 580 num_starts = 0; 581 582 /* 583 * Paravirt / VMI wants a startup IPI hook here to set up the 584 * target processor state. 585 */ 586 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, 587 stack_start); 588 589 /* 590 * Run STARTUP IPI loop. 591 */ 592 pr_debug("#startup loops: %d.\n", num_starts); 593 594 for (j = 1; j <= num_starts; j++) { 595 pr_debug("Sending STARTUP #%d.\n", j); 596 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 597 apic_write(APIC_ESR, 0); 598 apic_read(APIC_ESR); 599 pr_debug("After apic_write.\n"); 600 601 /* 602 * STARTUP IPI 603 */ 604 605 /* Target chip */ 606 /* Boot on the stack */ 607 /* Kick the second */ 608 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 609 phys_apicid); 610 611 /* 612 * Give the other CPU some time to accept the IPI. 613 */ 614 udelay(300); 615 616 pr_debug("Startup point 1.\n"); 617 618 pr_debug("Waiting for send to finish...\n"); 619 send_status = safe_apic_wait_icr_idle(); 620 621 /* 622 * Give the other CPU some time to accept the IPI. 623 */ 624 udelay(200); 625 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 626 apic_write(APIC_ESR, 0); 627 accept_status = (apic_read(APIC_ESR) & 0xEF); 628 if (send_status || accept_status) 629 break; 630 } 631 pr_debug("After Startup.\n"); 632 633 if (send_status) 634 printk(KERN_ERR "APIC never delivered???\n"); 635 if (accept_status) 636 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 637 638 return (send_status | accept_status); 639 } 640 641 /* reduce the number of lines printed when booting a large cpu count system */ 642 static void __cpuinit announce_cpu(int cpu, int apicid) 643 { 644 static int current_node = -1; 645 int node = early_cpu_to_node(cpu); 646 647 if (system_state == SYSTEM_BOOTING) { 648 if (node != current_node) { 649 if (current_node > (-1)) 650 pr_cont(" Ok.\n"); 651 current_node = node; 652 pr_info("Booting Node %3d, Processors ", node); 653 } 654 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : ""); 655 return; 656 } else 657 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 658 node, cpu, apicid); 659 } 660 661 /* 662 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 663 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 664 * Returns zero if CPU booted OK, else error code from 665 * ->wakeup_secondary_cpu. 666 */ 667 static int __cpuinit do_boot_cpu(int apicid, int cpu, struct task_struct *idle) 668 { 669 volatile u32 *trampoline_status = 670 (volatile u32 *) __va(real_mode_header->trampoline_status); 671 /* start_ip had better be page-aligned! */ 672 unsigned long start_ip = real_mode_header->trampoline_start; 673 674 unsigned long boot_error = 0; 675 int timeout; 676 677 alternatives_smp_switch(1); 678 679 idle->thread.sp = (unsigned long) (((struct pt_regs *) 680 (THREAD_SIZE + task_stack_page(idle))) - 1); 681 per_cpu(current_task, cpu) = idle; 682 683 #ifdef CONFIG_X86_32 684 /* Stack for startup_32 can be just as for start_secondary onwards */ 685 irq_ctx_init(cpu); 686 #else 687 clear_tsk_thread_flag(idle, TIF_FORK); 688 initial_gs = per_cpu_offset(cpu); 689 per_cpu(kernel_stack, cpu) = 690 (unsigned long)task_stack_page(idle) - 691 KERNEL_STACK_OFFSET + THREAD_SIZE; 692 #endif 693 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 694 initial_code = (unsigned long)start_secondary; 695 stack_start = idle->thread.sp; 696 697 /* So we see what's up */ 698 announce_cpu(cpu, apicid); 699 700 /* 701 * This grunge runs the startup process for 702 * the targeted processor. 703 */ 704 705 atomic_set(&init_deasserted, 0); 706 707 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 708 709 pr_debug("Setting warm reset code and vector.\n"); 710 711 smpboot_setup_warm_reset_vector(start_ip); 712 /* 713 * Be paranoid about clearing APIC errors. 714 */ 715 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 716 apic_write(APIC_ESR, 0); 717 apic_read(APIC_ESR); 718 } 719 } 720 721 /* 722 * Kick the secondary CPU. Use the method in the APIC driver 723 * if it's defined - or use an INIT boot APIC message otherwise: 724 */ 725 if (apic->wakeup_secondary_cpu) 726 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 727 else 728 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 729 730 if (!boot_error) { 731 /* 732 * allow APs to start initializing. 733 */ 734 pr_debug("Before Callout %d.\n", cpu); 735 cpumask_set_cpu(cpu, cpu_callout_mask); 736 pr_debug("After Callout %d.\n", cpu); 737 738 /* 739 * Wait 5s total for a response 740 */ 741 for (timeout = 0; timeout < 50000; timeout++) { 742 if (cpumask_test_cpu(cpu, cpu_callin_mask)) 743 break; /* It has booted */ 744 udelay(100); 745 /* 746 * Allow other tasks to run while we wait for the 747 * AP to come online. This also gives a chance 748 * for the MTRR work(triggered by the AP coming online) 749 * to be completed in the stop machine context. 750 */ 751 schedule(); 752 } 753 754 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 755 print_cpu_msr(&cpu_data(cpu)); 756 pr_debug("CPU%d: has booted.\n", cpu); 757 } else { 758 boot_error = 1; 759 if (*trampoline_status == 0xA5A5A5A5) 760 /* trampoline started but...? */ 761 pr_err("CPU%d: Stuck ??\n", cpu); 762 else 763 /* trampoline code not run */ 764 pr_err("CPU%d: Not responding.\n", cpu); 765 if (apic->inquire_remote_apic) 766 apic->inquire_remote_apic(apicid); 767 } 768 } 769 770 if (boot_error) { 771 /* Try to put things back the way they were before ... */ 772 numa_remove_cpu(cpu); /* was set by numa_add_cpu */ 773 774 /* was set by do_boot_cpu() */ 775 cpumask_clear_cpu(cpu, cpu_callout_mask); 776 777 /* was set by cpu_init() */ 778 cpumask_clear_cpu(cpu, cpu_initialized_mask); 779 780 set_cpu_present(cpu, false); 781 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; 782 } 783 784 /* mark "stuck" area as not stuck */ 785 *trampoline_status = 0; 786 787 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 788 /* 789 * Cleanup possible dangling ends... 790 */ 791 smpboot_restore_warm_reset_vector(); 792 } 793 return boot_error; 794 } 795 796 int __cpuinit native_cpu_up(unsigned int cpu, struct task_struct *tidle) 797 { 798 int apicid = apic->cpu_present_to_apicid(cpu); 799 unsigned long flags; 800 int err; 801 802 WARN_ON(irqs_disabled()); 803 804 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 805 806 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || 807 !physid_isset(apicid, phys_cpu_present_map) || 808 !apic->apic_id_valid(apicid)) { 809 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); 810 return -EINVAL; 811 } 812 813 /* 814 * Already booted CPU? 815 */ 816 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 817 pr_debug("do_boot_cpu %d Already started\n", cpu); 818 return -ENOSYS; 819 } 820 821 /* 822 * Save current MTRR state in case it was changed since early boot 823 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 824 */ 825 mtrr_save_state(); 826 827 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; 828 829 err = do_boot_cpu(apicid, cpu, tidle); 830 if (err) { 831 pr_debug("do_boot_cpu failed %d\n", err); 832 return -EIO; 833 } 834 835 /* 836 * Check TSC synchronization with the AP (keep irqs disabled 837 * while doing so): 838 */ 839 local_irq_save(flags); 840 check_tsc_sync_source(cpu); 841 local_irq_restore(flags); 842 843 while (!cpu_online(cpu)) { 844 cpu_relax(); 845 touch_nmi_watchdog(); 846 } 847 848 return 0; 849 } 850 851 /** 852 * arch_disable_smp_support() - disables SMP support for x86 at runtime 853 */ 854 void arch_disable_smp_support(void) 855 { 856 disable_ioapic_support(); 857 } 858 859 /* 860 * Fall back to non SMP mode after errors. 861 * 862 * RED-PEN audit/test this more. I bet there is more state messed up here. 863 */ 864 static __init void disable_smp(void) 865 { 866 init_cpu_present(cpumask_of(0)); 867 init_cpu_possible(cpumask_of(0)); 868 smpboot_clear_io_apic_irqs(); 869 870 if (smp_found_config) 871 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 872 else 873 physid_set_mask_of_physid(0, &phys_cpu_present_map); 874 cpumask_set_cpu(0, cpu_sibling_mask(0)); 875 cpumask_set_cpu(0, cpu_core_mask(0)); 876 } 877 878 /* 879 * Various sanity checks. 880 */ 881 static int __init smp_sanity_check(unsigned max_cpus) 882 { 883 preempt_disable(); 884 885 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 886 if (def_to_bigsmp && nr_cpu_ids > 8) { 887 unsigned int cpu; 888 unsigned nr; 889 890 printk(KERN_WARNING 891 "More than 8 CPUs detected - skipping them.\n" 892 "Use CONFIG_X86_BIGSMP.\n"); 893 894 nr = 0; 895 for_each_present_cpu(cpu) { 896 if (nr >= 8) 897 set_cpu_present(cpu, false); 898 nr++; 899 } 900 901 nr = 0; 902 for_each_possible_cpu(cpu) { 903 if (nr >= 8) 904 set_cpu_possible(cpu, false); 905 nr++; 906 } 907 908 nr_cpu_ids = 8; 909 } 910 #endif 911 912 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 913 printk(KERN_WARNING 914 "weird, boot CPU (#%d) not listed by the BIOS.\n", 915 hard_smp_processor_id()); 916 917 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 918 } 919 920 /* 921 * If we couldn't find an SMP configuration at boot time, 922 * get out of here now! 923 */ 924 if (!smp_found_config && !acpi_lapic) { 925 preempt_enable(); 926 printk(KERN_NOTICE "SMP motherboard not detected.\n"); 927 disable_smp(); 928 if (APIC_init_uniprocessor()) 929 printk(KERN_NOTICE "Local APIC not detected." 930 " Using dummy APIC emulation.\n"); 931 return -1; 932 } 933 934 /* 935 * Should not be necessary because the MP table should list the boot 936 * CPU too, but we do it for the sake of robustness anyway. 937 */ 938 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 939 printk(KERN_NOTICE 940 "weird, boot CPU (#%d) not listed by the BIOS.\n", 941 boot_cpu_physical_apicid); 942 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 943 } 944 preempt_enable(); 945 946 /* 947 * If we couldn't find a local APIC, then get out of here now! 948 */ 949 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 950 !cpu_has_apic) { 951 if (!disable_apic) { 952 pr_err("BIOS bug, local APIC #%d not detected!...\n", 953 boot_cpu_physical_apicid); 954 pr_err("... forcing use of dummy APIC emulation." 955 "(tell your hw vendor)\n"); 956 } 957 smpboot_clear_io_apic(); 958 disable_ioapic_support(); 959 return -1; 960 } 961 962 verify_local_APIC(); 963 964 /* 965 * If SMP should be disabled, then really disable it! 966 */ 967 if (!max_cpus) { 968 printk(KERN_INFO "SMP mode deactivated.\n"); 969 smpboot_clear_io_apic(); 970 971 connect_bsp_APIC(); 972 setup_local_APIC(); 973 bsp_end_local_APIC_setup(); 974 return -1; 975 } 976 977 return 0; 978 } 979 980 static void __init smp_cpu_index_default(void) 981 { 982 int i; 983 struct cpuinfo_x86 *c; 984 985 for_each_possible_cpu(i) { 986 c = &cpu_data(i); 987 /* mark all to hotplug */ 988 c->cpu_index = nr_cpu_ids; 989 } 990 } 991 992 /* 993 * Prepare for SMP bootup. The MP table or ACPI has been read 994 * earlier. Just do some sanity checking here and enable APIC mode. 995 */ 996 void __init native_smp_prepare_cpus(unsigned int max_cpus) 997 { 998 unsigned int i; 999 1000 preempt_disable(); 1001 smp_cpu_index_default(); 1002 1003 /* 1004 * Setup boot CPU information 1005 */ 1006 smp_store_cpu_info(0); /* Final full version of the data */ 1007 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1008 mb(); 1009 1010 current_thread_info()->cpu = 0; /* needed? */ 1011 for_each_possible_cpu(i) { 1012 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1013 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1014 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1015 } 1016 set_cpu_sibling_map(0); 1017 1018 1019 if (smp_sanity_check(max_cpus) < 0) { 1020 printk(KERN_INFO "SMP disabled\n"); 1021 disable_smp(); 1022 goto out; 1023 } 1024 1025 default_setup_apic_routing(); 1026 1027 preempt_disable(); 1028 if (read_apic_id() != boot_cpu_physical_apicid) { 1029 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1030 read_apic_id(), boot_cpu_physical_apicid); 1031 /* Or can we switch back to PIC here? */ 1032 } 1033 preempt_enable(); 1034 1035 connect_bsp_APIC(); 1036 1037 /* 1038 * Switch from PIC to APIC mode. 1039 */ 1040 setup_local_APIC(); 1041 1042 /* 1043 * Enable IO APIC before setting up error vector 1044 */ 1045 if (!skip_ioapic_setup && nr_ioapics) 1046 enable_IO_APIC(); 1047 1048 bsp_end_local_APIC_setup(); 1049 1050 if (apic->setup_portio_remap) 1051 apic->setup_portio_remap(); 1052 1053 smpboot_setup_io_apic(); 1054 /* 1055 * Set up local APIC timer on boot CPU. 1056 */ 1057 1058 printk(KERN_INFO "CPU%d: ", 0); 1059 print_cpu_info(&cpu_data(0)); 1060 x86_init.timers.setup_percpu_clockev(); 1061 1062 if (is_uv_system()) 1063 uv_system_init(); 1064 1065 set_mtrr_aps_delayed_init(); 1066 out: 1067 preempt_enable(); 1068 } 1069 1070 void arch_disable_nonboot_cpus_begin(void) 1071 { 1072 /* 1073 * Avoid the smp alternatives switch during the disable_nonboot_cpus(). 1074 * In the suspend path, we will be back in the SMP mode shortly anyways. 1075 */ 1076 skip_smp_alternatives = true; 1077 } 1078 1079 void arch_disable_nonboot_cpus_end(void) 1080 { 1081 skip_smp_alternatives = false; 1082 } 1083 1084 void arch_enable_nonboot_cpus_begin(void) 1085 { 1086 set_mtrr_aps_delayed_init(); 1087 } 1088 1089 void arch_enable_nonboot_cpus_end(void) 1090 { 1091 mtrr_aps_init(); 1092 } 1093 1094 /* 1095 * Early setup to make printk work. 1096 */ 1097 void __init native_smp_prepare_boot_cpu(void) 1098 { 1099 int me = smp_processor_id(); 1100 switch_to_new_gdt(me); 1101 /* already set me in cpu_online_mask in boot_cpu_init() */ 1102 cpumask_set_cpu(me, cpu_callout_mask); 1103 per_cpu(cpu_state, me) = CPU_ONLINE; 1104 } 1105 1106 void __init native_smp_cpus_done(unsigned int max_cpus) 1107 { 1108 pr_debug("Boot done.\n"); 1109 1110 nmi_selftest(); 1111 impress_friends(); 1112 #ifdef CONFIG_X86_IO_APIC 1113 setup_ioapic_dest(); 1114 #endif 1115 mtrr_aps_init(); 1116 } 1117 1118 static int __initdata setup_possible_cpus = -1; 1119 static int __init _setup_possible_cpus(char *str) 1120 { 1121 get_option(&str, &setup_possible_cpus); 1122 return 0; 1123 } 1124 early_param("possible_cpus", _setup_possible_cpus); 1125 1126 1127 /* 1128 * cpu_possible_mask should be static, it cannot change as cpu's 1129 * are onlined, or offlined. The reason is per-cpu data-structures 1130 * are allocated by some modules at init time, and dont expect to 1131 * do this dynamically on cpu arrival/departure. 1132 * cpu_present_mask on the other hand can change dynamically. 1133 * In case when cpu_hotplug is not compiled, then we resort to current 1134 * behaviour, which is cpu_possible == cpu_present. 1135 * - Ashok Raj 1136 * 1137 * Three ways to find out the number of additional hotplug CPUs: 1138 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1139 * - The user can overwrite it with possible_cpus=NUM 1140 * - Otherwise don't reserve additional CPUs. 1141 * We do this because additional CPUs waste a lot of memory. 1142 * -AK 1143 */ 1144 __init void prefill_possible_map(void) 1145 { 1146 int i, possible; 1147 1148 /* no processor from mptable or madt */ 1149 if (!num_processors) 1150 num_processors = 1; 1151 1152 i = setup_max_cpus ?: 1; 1153 if (setup_possible_cpus == -1) { 1154 possible = num_processors; 1155 #ifdef CONFIG_HOTPLUG_CPU 1156 if (setup_max_cpus) 1157 possible += disabled_cpus; 1158 #else 1159 if (possible > i) 1160 possible = i; 1161 #endif 1162 } else 1163 possible = setup_possible_cpus; 1164 1165 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1166 1167 /* nr_cpu_ids could be reduced via nr_cpus= */ 1168 if (possible > nr_cpu_ids) { 1169 printk(KERN_WARNING 1170 "%d Processors exceeds NR_CPUS limit of %d\n", 1171 possible, nr_cpu_ids); 1172 possible = nr_cpu_ids; 1173 } 1174 1175 #ifdef CONFIG_HOTPLUG_CPU 1176 if (!setup_max_cpus) 1177 #endif 1178 if (possible > i) { 1179 printk(KERN_WARNING 1180 "%d Processors exceeds max_cpus limit of %u\n", 1181 possible, setup_max_cpus); 1182 possible = i; 1183 } 1184 1185 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", 1186 possible, max_t(int, possible - num_processors, 0)); 1187 1188 for (i = 0; i < possible; i++) 1189 set_cpu_possible(i, true); 1190 for (; i < NR_CPUS; i++) 1191 set_cpu_possible(i, false); 1192 1193 nr_cpu_ids = possible; 1194 } 1195 1196 #ifdef CONFIG_HOTPLUG_CPU 1197 1198 static void remove_siblinginfo(int cpu) 1199 { 1200 int sibling; 1201 struct cpuinfo_x86 *c = &cpu_data(cpu); 1202 1203 for_each_cpu(sibling, cpu_core_mask(cpu)) { 1204 cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); 1205 /*/ 1206 * last thread sibling in this cpu core going down 1207 */ 1208 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) 1209 cpu_data(sibling).booted_cores--; 1210 } 1211 1212 for_each_cpu(sibling, cpu_sibling_mask(cpu)) 1213 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); 1214 cpumask_clear(cpu_sibling_mask(cpu)); 1215 cpumask_clear(cpu_core_mask(cpu)); 1216 c->phys_proc_id = 0; 1217 c->cpu_core_id = 0; 1218 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1219 } 1220 1221 static void __ref remove_cpu_from_maps(int cpu) 1222 { 1223 set_cpu_online(cpu, false); 1224 cpumask_clear_cpu(cpu, cpu_callout_mask); 1225 cpumask_clear_cpu(cpu, cpu_callin_mask); 1226 /* was set by cpu_init() */ 1227 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1228 numa_remove_cpu(cpu); 1229 } 1230 1231 void cpu_disable_common(void) 1232 { 1233 int cpu = smp_processor_id(); 1234 1235 remove_siblinginfo(cpu); 1236 1237 /* It's now safe to remove this processor from the online map */ 1238 lock_vector_lock(); 1239 remove_cpu_from_maps(cpu); 1240 unlock_vector_lock(); 1241 fixup_irqs(); 1242 } 1243 1244 int native_cpu_disable(void) 1245 { 1246 int cpu = smp_processor_id(); 1247 1248 /* 1249 * Perhaps use cpufreq to drop frequency, but that could go 1250 * into generic code. 1251 * 1252 * We won't take down the boot processor on i386 due to some 1253 * interrupts only being able to be serviced by the BSP. 1254 * Especially so if we're not using an IOAPIC -zwane 1255 */ 1256 if (cpu == 0) 1257 return -EBUSY; 1258 1259 clear_local_APIC(); 1260 1261 cpu_disable_common(); 1262 return 0; 1263 } 1264 1265 void native_cpu_die(unsigned int cpu) 1266 { 1267 /* We don't do anything here: idle task is faking death itself. */ 1268 unsigned int i; 1269 1270 for (i = 0; i < 10; i++) { 1271 /* They ack this in play_dead by setting CPU_DEAD */ 1272 if (per_cpu(cpu_state, cpu) == CPU_DEAD) { 1273 if (system_state == SYSTEM_RUNNING) 1274 pr_info("CPU %u is now offline\n", cpu); 1275 1276 if (1 == num_online_cpus()) 1277 alternatives_smp_switch(0); 1278 return; 1279 } 1280 msleep(100); 1281 } 1282 pr_err("CPU %u didn't die...\n", cpu); 1283 } 1284 1285 void play_dead_common(void) 1286 { 1287 idle_task_exit(); 1288 reset_lazy_tlbstate(); 1289 amd_e400_remove_cpu(raw_smp_processor_id()); 1290 1291 mb(); 1292 /* Ack it */ 1293 __this_cpu_write(cpu_state, CPU_DEAD); 1294 1295 /* 1296 * With physical CPU hotplug, we should halt the cpu 1297 */ 1298 local_irq_disable(); 1299 } 1300 1301 /* 1302 * We need to flush the caches before going to sleep, lest we have 1303 * dirty data in our caches when we come back up. 1304 */ 1305 static inline void mwait_play_dead(void) 1306 { 1307 unsigned int eax, ebx, ecx, edx; 1308 unsigned int highest_cstate = 0; 1309 unsigned int highest_subcstate = 0; 1310 int i; 1311 void *mwait_ptr; 1312 struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info); 1313 1314 if (!(this_cpu_has(X86_FEATURE_MWAIT) && mwait_usable(c))) 1315 return; 1316 if (!this_cpu_has(X86_FEATURE_CLFLSH)) 1317 return; 1318 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1319 return; 1320 1321 eax = CPUID_MWAIT_LEAF; 1322 ecx = 0; 1323 native_cpuid(&eax, &ebx, &ecx, &edx); 1324 1325 /* 1326 * eax will be 0 if EDX enumeration is not valid. 1327 * Initialized below to cstate, sub_cstate value when EDX is valid. 1328 */ 1329 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1330 eax = 0; 1331 } else { 1332 edx >>= MWAIT_SUBSTATE_SIZE; 1333 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1334 if (edx & MWAIT_SUBSTATE_MASK) { 1335 highest_cstate = i; 1336 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1337 } 1338 } 1339 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1340 (highest_subcstate - 1); 1341 } 1342 1343 /* 1344 * This should be a memory location in a cache line which is 1345 * unlikely to be touched by other processors. The actual 1346 * content is immaterial as it is not actually modified in any way. 1347 */ 1348 mwait_ptr = ¤t_thread_info()->flags; 1349 1350 wbinvd(); 1351 1352 while (1) { 1353 /* 1354 * The CLFLUSH is a workaround for erratum AAI65 for 1355 * the Xeon 7400 series. It's not clear it is actually 1356 * needed, but it should be harmless in either case. 1357 * The WBINVD is insufficient due to the spurious-wakeup 1358 * case where we return around the loop. 1359 */ 1360 clflush(mwait_ptr); 1361 __monitor(mwait_ptr, 0, 0); 1362 mb(); 1363 __mwait(eax, 0); 1364 } 1365 } 1366 1367 static inline void hlt_play_dead(void) 1368 { 1369 if (__this_cpu_read(cpu_info.x86) >= 4) 1370 wbinvd(); 1371 1372 while (1) { 1373 native_halt(); 1374 } 1375 } 1376 1377 void native_play_dead(void) 1378 { 1379 play_dead_common(); 1380 tboot_shutdown(TB_SHUTDOWN_WFS); 1381 1382 mwait_play_dead(); /* Only returns on failure */ 1383 if (cpuidle_play_dead()) 1384 hlt_play_dead(); 1385 } 1386 1387 #else /* ... !CONFIG_HOTPLUG_CPU */ 1388 int native_cpu_disable(void) 1389 { 1390 return -ENOSYS; 1391 } 1392 1393 void native_cpu_die(unsigned int cpu) 1394 { 1395 /* We said "no" in __cpu_disable */ 1396 BUG(); 1397 } 1398 1399 void native_play_dead(void) 1400 { 1401 BUG(); 1402 } 1403 1404 #endif 1405