1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 43 44 #include <linux/init.h> 45 #include <linux/smp.h> 46 #include <linux/export.h> 47 #include <linux/sched.h> 48 #include <linux/sched/topology.h> 49 #include <linux/sched/hotplug.h> 50 #include <linux/sched/task_stack.h> 51 #include <linux/percpu.h> 52 #include <linux/bootmem.h> 53 #include <linux/err.h> 54 #include <linux/nmi.h> 55 #include <linux/tboot.h> 56 #include <linux/stackprotector.h> 57 #include <linux/gfp.h> 58 #include <linux/cpuidle.h> 59 60 #include <asm/acpi.h> 61 #include <asm/desc.h> 62 #include <asm/nmi.h> 63 #include <asm/irq.h> 64 #include <asm/realmode.h> 65 #include <asm/cpu.h> 66 #include <asm/numa.h> 67 #include <asm/pgtable.h> 68 #include <asm/tlbflush.h> 69 #include <asm/mtrr.h> 70 #include <asm/mwait.h> 71 #include <asm/apic.h> 72 #include <asm/io_apic.h> 73 #include <asm/fpu/internal.h> 74 #include <asm/setup.h> 75 #include <asm/uv/uv.h> 76 #include <linux/mc146818rtc.h> 77 #include <asm/i8259.h> 78 #include <asm/realmode.h> 79 #include <asm/misc.h> 80 #include <asm/qspinlock.h> 81 82 /* Number of siblings per CPU package */ 83 int smp_num_siblings = 1; 84 EXPORT_SYMBOL(smp_num_siblings); 85 86 /* Last level cache ID of each logical CPU */ 87 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 88 89 /* representing HT siblings of each logical CPU */ 90 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 91 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 92 93 /* representing HT and core siblings of each logical CPU */ 94 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 95 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 96 97 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); 98 99 /* Per CPU bogomips and other parameters */ 100 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 101 EXPORT_PER_CPU_SYMBOL(cpu_info); 102 103 /* Logical package management. We might want to allocate that dynamically */ 104 unsigned int __max_logical_packages __read_mostly; 105 EXPORT_SYMBOL(__max_logical_packages); 106 static unsigned int logical_packages __read_mostly; 107 108 /* Maximum number of SMT threads on any online core */ 109 int __read_mostly __max_smt_threads = 1; 110 111 /* Flag to indicate if a complete sched domain rebuild is required */ 112 bool x86_topology_update; 113 114 int arch_update_cpu_topology(void) 115 { 116 int retval = x86_topology_update; 117 118 x86_topology_update = false; 119 return retval; 120 } 121 122 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 123 { 124 unsigned long flags; 125 126 spin_lock_irqsave(&rtc_lock, flags); 127 CMOS_WRITE(0xa, 0xf); 128 spin_unlock_irqrestore(&rtc_lock, flags); 129 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = 130 start_eip >> 4; 131 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 132 start_eip & 0xf; 133 } 134 135 static inline void smpboot_restore_warm_reset_vector(void) 136 { 137 unsigned long flags; 138 139 /* 140 * Paranoid: Set warm reset code and vector here back 141 * to default values. 142 */ 143 spin_lock_irqsave(&rtc_lock, flags); 144 CMOS_WRITE(0, 0xf); 145 spin_unlock_irqrestore(&rtc_lock, flags); 146 147 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 148 } 149 150 /* 151 * Report back to the Boot Processor during boot time or to the caller processor 152 * during CPU online. 153 */ 154 static void smp_callin(void) 155 { 156 int cpuid, phys_id; 157 158 /* 159 * If waken up by an INIT in an 82489DX configuration 160 * cpu_callout_mask guarantees we don't get here before 161 * an INIT_deassert IPI reaches our local APIC, so it is 162 * now safe to touch our local APIC. 163 */ 164 cpuid = smp_processor_id(); 165 166 /* 167 * (This works even if the APIC is not enabled.) 168 */ 169 phys_id = read_apic_id(); 170 171 /* 172 * the boot CPU has finished the init stage and is spinning 173 * on callin_map until we finish. We are free to set up this 174 * CPU, first the APIC. (this is probably redundant on most 175 * boards) 176 */ 177 apic_ap_setup(); 178 179 /* 180 * Save our processor parameters. Note: this information 181 * is needed for clock calibration. 182 */ 183 smp_store_cpu_info(cpuid); 184 185 /* 186 * The topology information must be up to date before 187 * calibrate_delay() and notify_cpu_starting(). 188 */ 189 set_cpu_sibling_map(raw_smp_processor_id()); 190 191 /* 192 * Get our bogomips. 193 * Update loops_per_jiffy in cpu_data. Previous call to 194 * smp_store_cpu_info() stored a value that is close but not as 195 * accurate as the value just calculated. 196 */ 197 calibrate_delay(); 198 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 199 pr_debug("Stack at about %p\n", &cpuid); 200 201 wmb(); 202 203 notify_cpu_starting(cpuid); 204 205 /* 206 * Allow the master to continue. 207 */ 208 cpumask_set_cpu(cpuid, cpu_callin_mask); 209 } 210 211 static int cpu0_logical_apicid; 212 static int enable_start_cpu0; 213 /* 214 * Activate a secondary processor. 215 */ 216 static void notrace start_secondary(void *unused) 217 { 218 /* 219 * Don't put *anything* except direct CPU state initialization 220 * before cpu_init(), SMP booting is too fragile that we want to 221 * limit the things done here to the most necessary things. 222 */ 223 if (boot_cpu_has(X86_FEATURE_PCID)) 224 __write_cr4(__read_cr4() | X86_CR4_PCIDE); 225 226 #ifdef CONFIG_X86_32 227 /* switch away from the initial page table */ 228 load_cr3(swapper_pg_dir); 229 __flush_tlb_all(); 230 #endif 231 load_current_idt(); 232 cpu_init(); 233 x86_cpuinit.early_percpu_clock_init(); 234 preempt_disable(); 235 smp_callin(); 236 237 enable_start_cpu0 = 0; 238 239 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 240 barrier(); 241 /* 242 * Check TSC synchronization with the boot CPU: 243 */ 244 check_tsc_sync_target(); 245 246 /* 247 * Lock vector_lock, set CPU online and bring the vector 248 * allocator online. Online must be set with vector_lock held 249 * to prevent a concurrent irq setup/teardown from seeing a 250 * half valid vector space. 251 */ 252 lock_vector_lock(); 253 set_cpu_online(smp_processor_id(), true); 254 lapic_online(); 255 unlock_vector_lock(); 256 cpu_set_state_online(smp_processor_id()); 257 x86_platform.nmi_init(); 258 259 /* enable local interrupts */ 260 local_irq_enable(); 261 262 /* to prevent fake stack check failure in clock setup */ 263 boot_init_stack_canary(); 264 265 x86_cpuinit.setup_percpu_clockev(); 266 267 wmb(); 268 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 269 } 270 271 /** 272 * topology_phys_to_logical_pkg - Map a physical package id to a logical 273 * 274 * Returns logical package id or -1 if not found 275 */ 276 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 277 { 278 int cpu; 279 280 for_each_possible_cpu(cpu) { 281 struct cpuinfo_x86 *c = &cpu_data(cpu); 282 283 if (c->initialized && c->phys_proc_id == phys_pkg) 284 return c->logical_proc_id; 285 } 286 return -1; 287 } 288 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 289 290 /** 291 * topology_update_package_map - Update the physical to logical package map 292 * @pkg: The physical package id as retrieved via CPUID 293 * @cpu: The cpu for which this is updated 294 */ 295 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 296 { 297 int new; 298 299 /* Already available somewhere? */ 300 new = topology_phys_to_logical_pkg(pkg); 301 if (new >= 0) 302 goto found; 303 304 new = logical_packages++; 305 if (new != pkg) { 306 pr_info("CPU %u Converting physical %u to logical package %u\n", 307 cpu, pkg, new); 308 } 309 found: 310 cpu_data(cpu).logical_proc_id = new; 311 return 0; 312 } 313 314 void __init smp_store_boot_cpu_info(void) 315 { 316 int id = 0; /* CPU 0 */ 317 struct cpuinfo_x86 *c = &cpu_data(id); 318 319 *c = boot_cpu_data; 320 c->cpu_index = id; 321 topology_update_package_map(c->phys_proc_id, id); 322 c->initialized = true; 323 } 324 325 /* 326 * The bootstrap kernel entry code has set these up. Save them for 327 * a given CPU 328 */ 329 void smp_store_cpu_info(int id) 330 { 331 struct cpuinfo_x86 *c = &cpu_data(id); 332 333 /* Copy boot_cpu_data only on the first bringup */ 334 if (!c->initialized) 335 *c = boot_cpu_data; 336 c->cpu_index = id; 337 /* 338 * During boot time, CPU0 has this setup already. Save the info when 339 * bringing up AP or offlined CPU0. 340 */ 341 identify_secondary_cpu(c); 342 c->initialized = true; 343 } 344 345 static bool 346 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 347 { 348 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 349 350 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 351 } 352 353 static bool 354 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 355 { 356 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 357 358 return !WARN_ONCE(!topology_same_node(c, o), 359 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 360 "[node: %d != %d]. Ignoring dependency.\n", 361 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 362 } 363 364 #define link_mask(mfunc, c1, c2) \ 365 do { \ 366 cpumask_set_cpu((c1), mfunc(c2)); \ 367 cpumask_set_cpu((c2), mfunc(c1)); \ 368 } while (0) 369 370 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 371 { 372 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 373 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 374 375 if (c->phys_proc_id == o->phys_proc_id && 376 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { 377 if (c->cpu_core_id == o->cpu_core_id) 378 return topology_sane(c, o, "smt"); 379 380 if ((c->cu_id != 0xff) && 381 (o->cu_id != 0xff) && 382 (c->cu_id == o->cu_id)) 383 return topology_sane(c, o, "smt"); 384 } 385 386 } else if (c->phys_proc_id == o->phys_proc_id && 387 c->cpu_core_id == o->cpu_core_id) { 388 return topology_sane(c, o, "smt"); 389 } 390 391 return false; 392 } 393 394 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 395 { 396 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 397 398 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && 399 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) 400 return topology_sane(c, o, "llc"); 401 402 return false; 403 } 404 405 /* 406 * Unlike the other levels, we do not enforce keeping a 407 * multicore group inside a NUMA node. If this happens, we will 408 * discard the MC level of the topology later. 409 */ 410 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 411 { 412 if (c->phys_proc_id == o->phys_proc_id) 413 return true; 414 return false; 415 } 416 417 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC) 418 static inline int x86_sched_itmt_flags(void) 419 { 420 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 421 } 422 423 #ifdef CONFIG_SCHED_MC 424 static int x86_core_flags(void) 425 { 426 return cpu_core_flags() | x86_sched_itmt_flags(); 427 } 428 #endif 429 #ifdef CONFIG_SCHED_SMT 430 static int x86_smt_flags(void) 431 { 432 return cpu_smt_flags() | x86_sched_itmt_flags(); 433 } 434 #endif 435 #endif 436 437 static struct sched_domain_topology_level x86_numa_in_package_topology[] = { 438 #ifdef CONFIG_SCHED_SMT 439 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 440 #endif 441 #ifdef CONFIG_SCHED_MC 442 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 443 #endif 444 { NULL, }, 445 }; 446 447 static struct sched_domain_topology_level x86_topology[] = { 448 #ifdef CONFIG_SCHED_SMT 449 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 450 #endif 451 #ifdef CONFIG_SCHED_MC 452 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 453 #endif 454 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 455 { NULL, }, 456 }; 457 458 /* 459 * Set if a package/die has multiple NUMA nodes inside. 460 * AMD Magny-Cours and Intel Cluster-on-Die have this. 461 */ 462 static bool x86_has_numa_in_package; 463 464 void set_cpu_sibling_map(int cpu) 465 { 466 bool has_smt = smp_num_siblings > 1; 467 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 468 struct cpuinfo_x86 *c = &cpu_data(cpu); 469 struct cpuinfo_x86 *o; 470 int i, threads; 471 472 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 473 474 if (!has_mp) { 475 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 476 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 477 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 478 c->booted_cores = 1; 479 return; 480 } 481 482 for_each_cpu(i, cpu_sibling_setup_mask) { 483 o = &cpu_data(i); 484 485 if ((i == cpu) || (has_smt && match_smt(c, o))) 486 link_mask(topology_sibling_cpumask, cpu, i); 487 488 if ((i == cpu) || (has_mp && match_llc(c, o))) 489 link_mask(cpu_llc_shared_mask, cpu, i); 490 491 } 492 493 /* 494 * This needs a separate iteration over the cpus because we rely on all 495 * topology_sibling_cpumask links to be set-up. 496 */ 497 for_each_cpu(i, cpu_sibling_setup_mask) { 498 o = &cpu_data(i); 499 500 if ((i == cpu) || (has_mp && match_die(c, o))) { 501 link_mask(topology_core_cpumask, cpu, i); 502 503 /* 504 * Does this new cpu bringup a new core? 505 */ 506 if (cpumask_weight( 507 topology_sibling_cpumask(cpu)) == 1) { 508 /* 509 * for each core in package, increment 510 * the booted_cores for this new cpu 511 */ 512 if (cpumask_first( 513 topology_sibling_cpumask(i)) == i) 514 c->booted_cores++; 515 /* 516 * increment the core count for all 517 * the other cpus in this package 518 */ 519 if (i != cpu) 520 cpu_data(i).booted_cores++; 521 } else if (i != cpu && !c->booted_cores) 522 c->booted_cores = cpu_data(i).booted_cores; 523 } 524 if (match_die(c, o) && !topology_same_node(c, o)) 525 x86_has_numa_in_package = true; 526 } 527 528 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 529 if (threads > __max_smt_threads) 530 __max_smt_threads = threads; 531 } 532 533 /* maps the cpu to the sched domain representing multi-core */ 534 const struct cpumask *cpu_coregroup_mask(int cpu) 535 { 536 return cpu_llc_shared_mask(cpu); 537 } 538 539 static void impress_friends(void) 540 { 541 int cpu; 542 unsigned long bogosum = 0; 543 /* 544 * Allow the user to impress friends. 545 */ 546 pr_debug("Before bogomips\n"); 547 for_each_possible_cpu(cpu) 548 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 549 bogosum += cpu_data(cpu).loops_per_jiffy; 550 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 551 num_online_cpus(), 552 bogosum/(500000/HZ), 553 (bogosum/(5000/HZ))%100); 554 555 pr_debug("Before bogocount - setting activated=1\n"); 556 } 557 558 void __inquire_remote_apic(int apicid) 559 { 560 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 561 const char * const names[] = { "ID", "VERSION", "SPIV" }; 562 int timeout; 563 u32 status; 564 565 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 566 567 for (i = 0; i < ARRAY_SIZE(regs); i++) { 568 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 569 570 /* 571 * Wait for idle. 572 */ 573 status = safe_apic_wait_icr_idle(); 574 if (status) 575 pr_cont("a previous APIC delivery may have failed\n"); 576 577 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 578 579 timeout = 0; 580 do { 581 udelay(100); 582 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 583 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 584 585 switch (status) { 586 case APIC_ICR_RR_VALID: 587 status = apic_read(APIC_RRR); 588 pr_cont("%08x\n", status); 589 break; 590 default: 591 pr_cont("failed\n"); 592 } 593 } 594 } 595 596 /* 597 * The Multiprocessor Specification 1.4 (1997) example code suggests 598 * that there should be a 10ms delay between the BSP asserting INIT 599 * and de-asserting INIT, when starting a remote processor. 600 * But that slows boot and resume on modern processors, which include 601 * many cores and don't require that delay. 602 * 603 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 604 * Modern processor families are quirked to remove the delay entirely. 605 */ 606 #define UDELAY_10MS_DEFAULT 10000 607 608 static unsigned int init_udelay = UINT_MAX; 609 610 static int __init cpu_init_udelay(char *str) 611 { 612 get_option(&str, &init_udelay); 613 614 return 0; 615 } 616 early_param("cpu_init_udelay", cpu_init_udelay); 617 618 static void __init smp_quirk_init_udelay(void) 619 { 620 /* if cmdline changed it from default, leave it alone */ 621 if (init_udelay != UINT_MAX) 622 return; 623 624 /* if modern processor, use no delay */ 625 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 626 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 627 init_udelay = 0; 628 return; 629 } 630 /* else, use legacy delay */ 631 init_udelay = UDELAY_10MS_DEFAULT; 632 } 633 634 /* 635 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 636 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 637 * won't ... remember to clear down the APIC, etc later. 638 */ 639 int 640 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 641 { 642 unsigned long send_status, accept_status = 0; 643 int maxlvt; 644 645 /* Target chip */ 646 /* Boot on the stack */ 647 /* Kick the second */ 648 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); 649 650 pr_debug("Waiting for send to finish...\n"); 651 send_status = safe_apic_wait_icr_idle(); 652 653 /* 654 * Give the other CPU some time to accept the IPI. 655 */ 656 udelay(200); 657 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 658 maxlvt = lapic_get_maxlvt(); 659 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 660 apic_write(APIC_ESR, 0); 661 accept_status = (apic_read(APIC_ESR) & 0xEF); 662 } 663 pr_debug("NMI sent\n"); 664 665 if (send_status) 666 pr_err("APIC never delivered???\n"); 667 if (accept_status) 668 pr_err("APIC delivery error (%lx)\n", accept_status); 669 670 return (send_status | accept_status); 671 } 672 673 static int 674 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 675 { 676 unsigned long send_status = 0, accept_status = 0; 677 int maxlvt, num_starts, j; 678 679 maxlvt = lapic_get_maxlvt(); 680 681 /* 682 * Be paranoid about clearing APIC errors. 683 */ 684 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 685 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 686 apic_write(APIC_ESR, 0); 687 apic_read(APIC_ESR); 688 } 689 690 pr_debug("Asserting INIT\n"); 691 692 /* 693 * Turn INIT on target chip 694 */ 695 /* 696 * Send IPI 697 */ 698 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 699 phys_apicid); 700 701 pr_debug("Waiting for send to finish...\n"); 702 send_status = safe_apic_wait_icr_idle(); 703 704 udelay(init_udelay); 705 706 pr_debug("Deasserting INIT\n"); 707 708 /* Target chip */ 709 /* Send IPI */ 710 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 711 712 pr_debug("Waiting for send to finish...\n"); 713 send_status = safe_apic_wait_icr_idle(); 714 715 mb(); 716 717 /* 718 * Should we send STARTUP IPIs ? 719 * 720 * Determine this based on the APIC version. 721 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 722 */ 723 if (APIC_INTEGRATED(boot_cpu_apic_version)) 724 num_starts = 2; 725 else 726 num_starts = 0; 727 728 /* 729 * Run STARTUP IPI loop. 730 */ 731 pr_debug("#startup loops: %d\n", num_starts); 732 733 for (j = 1; j <= num_starts; j++) { 734 pr_debug("Sending STARTUP #%d\n", j); 735 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 736 apic_write(APIC_ESR, 0); 737 apic_read(APIC_ESR); 738 pr_debug("After apic_write\n"); 739 740 /* 741 * STARTUP IPI 742 */ 743 744 /* Target chip */ 745 /* Boot on the stack */ 746 /* Kick the second */ 747 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 748 phys_apicid); 749 750 /* 751 * Give the other CPU some time to accept the IPI. 752 */ 753 if (init_udelay == 0) 754 udelay(10); 755 else 756 udelay(300); 757 758 pr_debug("Startup point 1\n"); 759 760 pr_debug("Waiting for send to finish...\n"); 761 send_status = safe_apic_wait_icr_idle(); 762 763 /* 764 * Give the other CPU some time to accept the IPI. 765 */ 766 if (init_udelay == 0) 767 udelay(10); 768 else 769 udelay(200); 770 771 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 772 apic_write(APIC_ESR, 0); 773 accept_status = (apic_read(APIC_ESR) & 0xEF); 774 if (send_status || accept_status) 775 break; 776 } 777 pr_debug("After Startup\n"); 778 779 if (send_status) 780 pr_err("APIC never delivered???\n"); 781 if (accept_status) 782 pr_err("APIC delivery error (%lx)\n", accept_status); 783 784 return (send_status | accept_status); 785 } 786 787 /* reduce the number of lines printed when booting a large cpu count system */ 788 static void announce_cpu(int cpu, int apicid) 789 { 790 static int current_node = -1; 791 int node = early_cpu_to_node(cpu); 792 static int width, node_width; 793 794 if (!width) 795 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 796 797 if (!node_width) 798 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 799 800 if (cpu == 1) 801 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 802 803 if (system_state < SYSTEM_RUNNING) { 804 if (node != current_node) { 805 if (current_node > (-1)) 806 pr_cont("\n"); 807 current_node = node; 808 809 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 810 node_width - num_digits(node), " ", node); 811 } 812 813 /* Add padding for the BSP */ 814 if (cpu == 1) 815 pr_cont("%*s", width + 1, " "); 816 817 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 818 819 } else 820 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 821 node, cpu, apicid); 822 } 823 824 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 825 { 826 int cpu; 827 828 cpu = smp_processor_id(); 829 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 830 return NMI_HANDLED; 831 832 return NMI_DONE; 833 } 834 835 /* 836 * Wake up AP by INIT, INIT, STARTUP sequence. 837 * 838 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 839 * boot-strap code which is not a desired behavior for waking up BSP. To 840 * void the boot-strap code, wake up CPU0 by NMI instead. 841 * 842 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 843 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 844 * We'll change this code in the future to wake up hard offlined CPU0 if 845 * real platform and request are available. 846 */ 847 static int 848 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 849 int *cpu0_nmi_registered) 850 { 851 int id; 852 int boot_error; 853 854 preempt_disable(); 855 856 /* 857 * Wake up AP by INIT, INIT, STARTUP sequence. 858 */ 859 if (cpu) { 860 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 861 goto out; 862 } 863 864 /* 865 * Wake up BSP by nmi. 866 * 867 * Register a NMI handler to help wake up CPU0. 868 */ 869 boot_error = register_nmi_handler(NMI_LOCAL, 870 wakeup_cpu0_nmi, 0, "wake_cpu0"); 871 872 if (!boot_error) { 873 enable_start_cpu0 = 1; 874 *cpu0_nmi_registered = 1; 875 if (apic->dest_logical == APIC_DEST_LOGICAL) 876 id = cpu0_logical_apicid; 877 else 878 id = apicid; 879 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 880 } 881 882 out: 883 preempt_enable(); 884 885 return boot_error; 886 } 887 888 void common_cpu_up(unsigned int cpu, struct task_struct *idle) 889 { 890 /* Just in case we booted with a single CPU. */ 891 alternatives_enable_smp(); 892 893 per_cpu(current_task, cpu) = idle; 894 895 #ifdef CONFIG_X86_32 896 /* Stack for startup_32 can be just as for start_secondary onwards */ 897 irq_ctx_init(cpu); 898 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle); 899 #else 900 initial_gs = per_cpu_offset(cpu); 901 #endif 902 } 903 904 /* 905 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 906 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 907 * Returns zero if CPU booted OK, else error code from 908 * ->wakeup_secondary_cpu. 909 */ 910 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle, 911 int *cpu0_nmi_registered) 912 { 913 volatile u32 *trampoline_status = 914 (volatile u32 *) __va(real_mode_header->trampoline_status); 915 /* start_ip had better be page-aligned! */ 916 unsigned long start_ip = real_mode_header->trampoline_start; 917 918 unsigned long boot_error = 0; 919 unsigned long timeout; 920 921 idle->thread.sp = (unsigned long)task_pt_regs(idle); 922 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 923 initial_code = (unsigned long)start_secondary; 924 initial_stack = idle->thread.sp; 925 926 /* Enable the espfix hack for this CPU */ 927 init_espfix_ap(cpu); 928 929 /* So we see what's up */ 930 announce_cpu(cpu, apicid); 931 932 /* 933 * This grunge runs the startup process for 934 * the targeted processor. 935 */ 936 937 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 938 939 pr_debug("Setting warm reset code and vector.\n"); 940 941 smpboot_setup_warm_reset_vector(start_ip); 942 /* 943 * Be paranoid about clearing APIC errors. 944 */ 945 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 946 apic_write(APIC_ESR, 0); 947 apic_read(APIC_ESR); 948 } 949 } 950 951 /* 952 * AP might wait on cpu_callout_mask in cpu_init() with 953 * cpu_initialized_mask set if previous attempt to online 954 * it timed-out. Clear cpu_initialized_mask so that after 955 * INIT/SIPI it could start with a clean state. 956 */ 957 cpumask_clear_cpu(cpu, cpu_initialized_mask); 958 smp_mb(); 959 960 /* 961 * Wake up a CPU in difference cases: 962 * - Use the method in the APIC driver if it's defined 963 * Otherwise, 964 * - Use an INIT boot APIC message for APs or NMI for BSP. 965 */ 966 if (apic->wakeup_secondary_cpu) 967 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 968 else 969 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 970 cpu0_nmi_registered); 971 972 if (!boot_error) { 973 /* 974 * Wait 10s total for first sign of life from AP 975 */ 976 boot_error = -1; 977 timeout = jiffies + 10*HZ; 978 while (time_before(jiffies, timeout)) { 979 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 980 /* 981 * Tell AP to proceed with initialization 982 */ 983 cpumask_set_cpu(cpu, cpu_callout_mask); 984 boot_error = 0; 985 break; 986 } 987 schedule(); 988 } 989 } 990 991 if (!boot_error) { 992 /* 993 * Wait till AP completes initial initialization 994 */ 995 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 996 /* 997 * Allow other tasks to run while we wait for the 998 * AP to come online. This also gives a chance 999 * for the MTRR work(triggered by the AP coming online) 1000 * to be completed in the stop machine context. 1001 */ 1002 schedule(); 1003 } 1004 } 1005 1006 /* mark "stuck" area as not stuck */ 1007 *trampoline_status = 0; 1008 1009 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 1010 /* 1011 * Cleanup possible dangling ends... 1012 */ 1013 smpboot_restore_warm_reset_vector(); 1014 } 1015 1016 return boot_error; 1017 } 1018 1019 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 1020 { 1021 int apicid = apic->cpu_present_to_apicid(cpu); 1022 int cpu0_nmi_registered = 0; 1023 unsigned long flags; 1024 int err, ret = 0; 1025 1026 lockdep_assert_irqs_enabled(); 1027 1028 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1029 1030 if (apicid == BAD_APICID || 1031 !physid_isset(apicid, phys_cpu_present_map) || 1032 !apic->apic_id_valid(apicid)) { 1033 pr_err("%s: bad cpu %d\n", __func__, cpu); 1034 return -EINVAL; 1035 } 1036 1037 /* 1038 * Already booted CPU? 1039 */ 1040 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 1041 pr_debug("do_boot_cpu %d Already started\n", cpu); 1042 return -ENOSYS; 1043 } 1044 1045 /* 1046 * Save current MTRR state in case it was changed since early boot 1047 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1048 */ 1049 mtrr_save_state(); 1050 1051 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 1052 err = cpu_check_up_prepare(cpu); 1053 if (err && err != -EBUSY) 1054 return err; 1055 1056 /* the FPU context is blank, nobody can own it */ 1057 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1058 1059 common_cpu_up(cpu, tidle); 1060 1061 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered); 1062 if (err) { 1063 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1064 ret = -EIO; 1065 goto unreg_nmi; 1066 } 1067 1068 /* 1069 * Check TSC synchronization with the AP (keep irqs disabled 1070 * while doing so): 1071 */ 1072 local_irq_save(flags); 1073 check_tsc_sync_source(cpu); 1074 local_irq_restore(flags); 1075 1076 while (!cpu_online(cpu)) { 1077 cpu_relax(); 1078 touch_nmi_watchdog(); 1079 } 1080 1081 unreg_nmi: 1082 /* 1083 * Clean up the nmi handler. Do this after the callin and callout sync 1084 * to avoid impact of possible long unregister time. 1085 */ 1086 if (cpu0_nmi_registered) 1087 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 1088 1089 return ret; 1090 } 1091 1092 /** 1093 * arch_disable_smp_support() - disables SMP support for x86 at runtime 1094 */ 1095 void arch_disable_smp_support(void) 1096 { 1097 disable_ioapic_support(); 1098 } 1099 1100 /* 1101 * Fall back to non SMP mode after errors. 1102 * 1103 * RED-PEN audit/test this more. I bet there is more state messed up here. 1104 */ 1105 static __init void disable_smp(void) 1106 { 1107 pr_info("SMP disabled\n"); 1108 1109 disable_ioapic_support(); 1110 1111 init_cpu_present(cpumask_of(0)); 1112 init_cpu_possible(cpumask_of(0)); 1113 1114 if (smp_found_config) 1115 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1116 else 1117 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1118 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1119 cpumask_set_cpu(0, topology_core_cpumask(0)); 1120 } 1121 1122 /* 1123 * Various sanity checks. 1124 */ 1125 static void __init smp_sanity_check(void) 1126 { 1127 preempt_disable(); 1128 1129 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1130 if (def_to_bigsmp && nr_cpu_ids > 8) { 1131 unsigned int cpu; 1132 unsigned nr; 1133 1134 pr_warn("More than 8 CPUs detected - skipping them\n" 1135 "Use CONFIG_X86_BIGSMP\n"); 1136 1137 nr = 0; 1138 for_each_present_cpu(cpu) { 1139 if (nr >= 8) 1140 set_cpu_present(cpu, false); 1141 nr++; 1142 } 1143 1144 nr = 0; 1145 for_each_possible_cpu(cpu) { 1146 if (nr >= 8) 1147 set_cpu_possible(cpu, false); 1148 nr++; 1149 } 1150 1151 nr_cpu_ids = 8; 1152 } 1153 #endif 1154 1155 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1156 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1157 hard_smp_processor_id()); 1158 1159 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1160 } 1161 1162 /* 1163 * Should not be necessary because the MP table should list the boot 1164 * CPU too, but we do it for the sake of robustness anyway. 1165 */ 1166 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1167 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1168 boot_cpu_physical_apicid); 1169 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1170 } 1171 preempt_enable(); 1172 } 1173 1174 static void __init smp_cpu_index_default(void) 1175 { 1176 int i; 1177 struct cpuinfo_x86 *c; 1178 1179 for_each_possible_cpu(i) { 1180 c = &cpu_data(i); 1181 /* mark all to hotplug */ 1182 c->cpu_index = nr_cpu_ids; 1183 } 1184 } 1185 1186 static void __init smp_get_logical_apicid(void) 1187 { 1188 if (x2apic_mode) 1189 cpu0_logical_apicid = apic_read(APIC_LDR); 1190 else 1191 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1192 } 1193 1194 /* 1195 * Prepare for SMP bootup. 1196 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1197 * for common interface support. 1198 */ 1199 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1200 { 1201 unsigned int i; 1202 1203 smp_cpu_index_default(); 1204 1205 /* 1206 * Setup boot CPU information 1207 */ 1208 smp_store_boot_cpu_info(); /* Final full version of the data */ 1209 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1210 mb(); 1211 1212 for_each_possible_cpu(i) { 1213 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1214 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1215 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1216 } 1217 1218 /* 1219 * Set 'default' x86 topology, this matches default_topology() in that 1220 * it has NUMA nodes as a topology level. See also 1221 * native_smp_cpus_done(). 1222 * 1223 * Must be done before set_cpus_sibling_map() is ran. 1224 */ 1225 set_sched_topology(x86_topology); 1226 1227 set_cpu_sibling_map(0); 1228 1229 smp_sanity_check(); 1230 1231 switch (apic_intr_mode) { 1232 case APIC_PIC: 1233 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1234 disable_smp(); 1235 return; 1236 case APIC_SYMMETRIC_IO_NO_ROUTING: 1237 disable_smp(); 1238 /* Setup local timer */ 1239 x86_init.timers.setup_percpu_clockev(); 1240 return; 1241 case APIC_VIRTUAL_WIRE: 1242 case APIC_SYMMETRIC_IO: 1243 break; 1244 } 1245 1246 /* Setup local timer */ 1247 x86_init.timers.setup_percpu_clockev(); 1248 1249 smp_get_logical_apicid(); 1250 1251 pr_info("CPU0: "); 1252 print_cpu_info(&cpu_data(0)); 1253 1254 native_pv_lock_init(); 1255 1256 uv_system_init(); 1257 1258 set_mtrr_aps_delayed_init(); 1259 1260 smp_quirk_init_udelay(); 1261 } 1262 1263 void arch_enable_nonboot_cpus_begin(void) 1264 { 1265 set_mtrr_aps_delayed_init(); 1266 } 1267 1268 void arch_enable_nonboot_cpus_end(void) 1269 { 1270 mtrr_aps_init(); 1271 } 1272 1273 /* 1274 * Early setup to make printk work. 1275 */ 1276 void __init native_smp_prepare_boot_cpu(void) 1277 { 1278 int me = smp_processor_id(); 1279 switch_to_new_gdt(me); 1280 /* already set me in cpu_online_mask in boot_cpu_init() */ 1281 cpumask_set_cpu(me, cpu_callout_mask); 1282 cpu_set_state_online(me); 1283 } 1284 1285 void __init native_smp_cpus_done(unsigned int max_cpus) 1286 { 1287 int ncpus; 1288 1289 pr_debug("Boot done\n"); 1290 /* 1291 * Today neither Intel nor AMD support heterogenous systems so 1292 * extrapolate the boot cpu's data to all packages. 1293 */ 1294 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); 1295 __max_logical_packages = DIV_ROUND_UP(nr_cpu_ids, ncpus); 1296 pr_info("Max logical packages: %u\n", __max_logical_packages); 1297 1298 if (x86_has_numa_in_package) 1299 set_sched_topology(x86_numa_in_package_topology); 1300 1301 nmi_selftest(); 1302 impress_friends(); 1303 mtrr_aps_init(); 1304 } 1305 1306 static int __initdata setup_possible_cpus = -1; 1307 static int __init _setup_possible_cpus(char *str) 1308 { 1309 get_option(&str, &setup_possible_cpus); 1310 return 0; 1311 } 1312 early_param("possible_cpus", _setup_possible_cpus); 1313 1314 1315 /* 1316 * cpu_possible_mask should be static, it cannot change as cpu's 1317 * are onlined, or offlined. The reason is per-cpu data-structures 1318 * are allocated by some modules at init time, and dont expect to 1319 * do this dynamically on cpu arrival/departure. 1320 * cpu_present_mask on the other hand can change dynamically. 1321 * In case when cpu_hotplug is not compiled, then we resort to current 1322 * behaviour, which is cpu_possible == cpu_present. 1323 * - Ashok Raj 1324 * 1325 * Three ways to find out the number of additional hotplug CPUs: 1326 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1327 * - The user can overwrite it with possible_cpus=NUM 1328 * - Otherwise don't reserve additional CPUs. 1329 * We do this because additional CPUs waste a lot of memory. 1330 * -AK 1331 */ 1332 __init void prefill_possible_map(void) 1333 { 1334 int i, possible; 1335 1336 /* No boot processor was found in mptable or ACPI MADT */ 1337 if (!num_processors) { 1338 if (boot_cpu_has(X86_FEATURE_APIC)) { 1339 int apicid = boot_cpu_physical_apicid; 1340 int cpu = hard_smp_processor_id(); 1341 1342 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); 1343 1344 /* Make sure boot cpu is enumerated */ 1345 if (apic->cpu_present_to_apicid(0) == BAD_APICID && 1346 apic->apic_id_valid(apicid)) 1347 generic_processor_info(apicid, boot_cpu_apic_version); 1348 } 1349 1350 if (!num_processors) 1351 num_processors = 1; 1352 } 1353 1354 i = setup_max_cpus ?: 1; 1355 if (setup_possible_cpus == -1) { 1356 possible = num_processors; 1357 #ifdef CONFIG_HOTPLUG_CPU 1358 if (setup_max_cpus) 1359 possible += disabled_cpus; 1360 #else 1361 if (possible > i) 1362 possible = i; 1363 #endif 1364 } else 1365 possible = setup_possible_cpus; 1366 1367 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1368 1369 /* nr_cpu_ids could be reduced via nr_cpus= */ 1370 if (possible > nr_cpu_ids) { 1371 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", 1372 possible, nr_cpu_ids); 1373 possible = nr_cpu_ids; 1374 } 1375 1376 #ifdef CONFIG_HOTPLUG_CPU 1377 if (!setup_max_cpus) 1378 #endif 1379 if (possible > i) { 1380 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1381 possible, setup_max_cpus); 1382 possible = i; 1383 } 1384 1385 nr_cpu_ids = possible; 1386 1387 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1388 possible, max_t(int, possible - num_processors, 0)); 1389 1390 reset_cpu_possible_mask(); 1391 1392 for (i = 0; i < possible; i++) 1393 set_cpu_possible(i, true); 1394 } 1395 1396 #ifdef CONFIG_HOTPLUG_CPU 1397 1398 /* Recompute SMT state for all CPUs on offline */ 1399 static void recompute_smt_state(void) 1400 { 1401 int max_threads, cpu; 1402 1403 max_threads = 0; 1404 for_each_online_cpu (cpu) { 1405 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1406 1407 if (threads > max_threads) 1408 max_threads = threads; 1409 } 1410 __max_smt_threads = max_threads; 1411 } 1412 1413 static void remove_siblinginfo(int cpu) 1414 { 1415 int sibling; 1416 struct cpuinfo_x86 *c = &cpu_data(cpu); 1417 1418 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1419 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1420 /*/ 1421 * last thread sibling in this cpu core going down 1422 */ 1423 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1424 cpu_data(sibling).booted_cores--; 1425 } 1426 1427 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) 1428 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1429 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1430 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1431 cpumask_clear(cpu_llc_shared_mask(cpu)); 1432 cpumask_clear(topology_sibling_cpumask(cpu)); 1433 cpumask_clear(topology_core_cpumask(cpu)); 1434 c->phys_proc_id = 0; 1435 c->cpu_core_id = 0; 1436 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1437 recompute_smt_state(); 1438 } 1439 1440 static void remove_cpu_from_maps(int cpu) 1441 { 1442 set_cpu_online(cpu, false); 1443 cpumask_clear_cpu(cpu, cpu_callout_mask); 1444 cpumask_clear_cpu(cpu, cpu_callin_mask); 1445 /* was set by cpu_init() */ 1446 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1447 numa_remove_cpu(cpu); 1448 } 1449 1450 void cpu_disable_common(void) 1451 { 1452 int cpu = smp_processor_id(); 1453 1454 remove_siblinginfo(cpu); 1455 1456 /* It's now safe to remove this processor from the online map */ 1457 lock_vector_lock(); 1458 remove_cpu_from_maps(cpu); 1459 unlock_vector_lock(); 1460 fixup_irqs(); 1461 lapic_offline(); 1462 } 1463 1464 int native_cpu_disable(void) 1465 { 1466 int ret; 1467 1468 ret = lapic_can_unplug_cpu(); 1469 if (ret) 1470 return ret; 1471 1472 clear_local_APIC(); 1473 cpu_disable_common(); 1474 1475 return 0; 1476 } 1477 1478 int common_cpu_die(unsigned int cpu) 1479 { 1480 int ret = 0; 1481 1482 /* We don't do anything here: idle task is faking death itself. */ 1483 1484 /* They ack this in play_dead() by setting CPU_DEAD */ 1485 if (cpu_wait_death(cpu, 5)) { 1486 if (system_state == SYSTEM_RUNNING) 1487 pr_info("CPU %u is now offline\n", cpu); 1488 } else { 1489 pr_err("CPU %u didn't die...\n", cpu); 1490 ret = -1; 1491 } 1492 1493 return ret; 1494 } 1495 1496 void native_cpu_die(unsigned int cpu) 1497 { 1498 common_cpu_die(cpu); 1499 } 1500 1501 void play_dead_common(void) 1502 { 1503 idle_task_exit(); 1504 1505 /* Ack it */ 1506 (void)cpu_report_death(); 1507 1508 /* 1509 * With physical CPU hotplug, we should halt the cpu 1510 */ 1511 local_irq_disable(); 1512 } 1513 1514 static bool wakeup_cpu0(void) 1515 { 1516 if (smp_processor_id() == 0 && enable_start_cpu0) 1517 return true; 1518 1519 return false; 1520 } 1521 1522 /* 1523 * We need to flush the caches before going to sleep, lest we have 1524 * dirty data in our caches when we come back up. 1525 */ 1526 static inline void mwait_play_dead(void) 1527 { 1528 unsigned int eax, ebx, ecx, edx; 1529 unsigned int highest_cstate = 0; 1530 unsigned int highest_subcstate = 0; 1531 void *mwait_ptr; 1532 int i; 1533 1534 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1535 return; 1536 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1537 return; 1538 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1539 return; 1540 1541 eax = CPUID_MWAIT_LEAF; 1542 ecx = 0; 1543 native_cpuid(&eax, &ebx, &ecx, &edx); 1544 1545 /* 1546 * eax will be 0 if EDX enumeration is not valid. 1547 * Initialized below to cstate, sub_cstate value when EDX is valid. 1548 */ 1549 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1550 eax = 0; 1551 } else { 1552 edx >>= MWAIT_SUBSTATE_SIZE; 1553 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1554 if (edx & MWAIT_SUBSTATE_MASK) { 1555 highest_cstate = i; 1556 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1557 } 1558 } 1559 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1560 (highest_subcstate - 1); 1561 } 1562 1563 /* 1564 * This should be a memory location in a cache line which is 1565 * unlikely to be touched by other processors. The actual 1566 * content is immaterial as it is not actually modified in any way. 1567 */ 1568 mwait_ptr = ¤t_thread_info()->flags; 1569 1570 wbinvd(); 1571 1572 while (1) { 1573 /* 1574 * The CLFLUSH is a workaround for erratum AAI65 for 1575 * the Xeon 7400 series. It's not clear it is actually 1576 * needed, but it should be harmless in either case. 1577 * The WBINVD is insufficient due to the spurious-wakeup 1578 * case where we return around the loop. 1579 */ 1580 mb(); 1581 clflush(mwait_ptr); 1582 mb(); 1583 __monitor(mwait_ptr, 0, 0); 1584 mb(); 1585 __mwait(eax, 0); 1586 /* 1587 * If NMI wants to wake up CPU0, start CPU0. 1588 */ 1589 if (wakeup_cpu0()) 1590 start_cpu0(); 1591 } 1592 } 1593 1594 void hlt_play_dead(void) 1595 { 1596 if (__this_cpu_read(cpu_info.x86) >= 4) 1597 wbinvd(); 1598 1599 while (1) { 1600 native_halt(); 1601 /* 1602 * If NMI wants to wake up CPU0, start CPU0. 1603 */ 1604 if (wakeup_cpu0()) 1605 start_cpu0(); 1606 } 1607 } 1608 1609 void native_play_dead(void) 1610 { 1611 play_dead_common(); 1612 tboot_shutdown(TB_SHUTDOWN_WFS); 1613 1614 mwait_play_dead(); /* Only returns on failure */ 1615 if (cpuidle_play_dead()) 1616 hlt_play_dead(); 1617 } 1618 1619 #else /* ... !CONFIG_HOTPLUG_CPU */ 1620 int native_cpu_disable(void) 1621 { 1622 return -ENOSYS; 1623 } 1624 1625 void native_cpu_die(unsigned int cpu) 1626 { 1627 /* We said "no" in __cpu_disable */ 1628 BUG(); 1629 } 1630 1631 void native_play_dead(void) 1632 { 1633 BUG(); 1634 } 1635 1636 #endif 1637