1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 43 44 #include <linux/init.h> 45 #include <linux/smp.h> 46 #include <linux/export.h> 47 #include <linux/sched.h> 48 #include <linux/percpu.h> 49 #include <linux/bootmem.h> 50 #include <linux/err.h> 51 #include <linux/nmi.h> 52 #include <linux/tboot.h> 53 #include <linux/stackprotector.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 57 #include <asm/acpi.h> 58 #include <asm/desc.h> 59 #include <asm/nmi.h> 60 #include <asm/irq.h> 61 #include <asm/idle.h> 62 #include <asm/realmode.h> 63 #include <asm/cpu.h> 64 #include <asm/numa.h> 65 #include <asm/pgtable.h> 66 #include <asm/tlbflush.h> 67 #include <asm/mtrr.h> 68 #include <asm/mwait.h> 69 #include <asm/apic.h> 70 #include <asm/io_apic.h> 71 #include <asm/fpu/internal.h> 72 #include <asm/setup.h> 73 #include <asm/uv/uv.h> 74 #include <linux/mc146818rtc.h> 75 #include <asm/i8259.h> 76 #include <asm/realmode.h> 77 #include <asm/misc.h> 78 79 /* Number of siblings per CPU package */ 80 int smp_num_siblings = 1; 81 EXPORT_SYMBOL(smp_num_siblings); 82 83 /* Last level cache ID of each logical CPU */ 84 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 85 86 /* representing HT siblings of each logical CPU */ 87 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 88 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 89 90 /* representing HT and core siblings of each logical CPU */ 91 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 92 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 93 94 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); 95 96 /* Per CPU bogomips and other parameters */ 97 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 98 EXPORT_PER_CPU_SYMBOL(cpu_info); 99 100 /* Logical package management. We might want to allocate that dynamically */ 101 static int *physical_to_logical_pkg __read_mostly; 102 static unsigned long *physical_package_map __read_mostly;; 103 static unsigned long *logical_package_map __read_mostly; 104 static unsigned int max_physical_pkg_id __read_mostly; 105 unsigned int __max_logical_packages __read_mostly; 106 EXPORT_SYMBOL(__max_logical_packages); 107 108 /* Maximum number of SMT threads on any online core */ 109 int __max_smt_threads __read_mostly; 110 111 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 112 { 113 unsigned long flags; 114 115 spin_lock_irqsave(&rtc_lock, flags); 116 CMOS_WRITE(0xa, 0xf); 117 spin_unlock_irqrestore(&rtc_lock, flags); 118 local_flush_tlb(); 119 pr_debug("1.\n"); 120 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = 121 start_eip >> 4; 122 pr_debug("2.\n"); 123 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 124 start_eip & 0xf; 125 pr_debug("3.\n"); 126 } 127 128 static inline void smpboot_restore_warm_reset_vector(void) 129 { 130 unsigned long flags; 131 132 /* 133 * Install writable page 0 entry to set BIOS data area. 134 */ 135 local_flush_tlb(); 136 137 /* 138 * Paranoid: Set warm reset code and vector here back 139 * to default values. 140 */ 141 spin_lock_irqsave(&rtc_lock, flags); 142 CMOS_WRITE(0, 0xf); 143 spin_unlock_irqrestore(&rtc_lock, flags); 144 145 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 146 } 147 148 /* 149 * Report back to the Boot Processor during boot time or to the caller processor 150 * during CPU online. 151 */ 152 static void smp_callin(void) 153 { 154 int cpuid, phys_id; 155 156 /* 157 * If waken up by an INIT in an 82489DX configuration 158 * cpu_callout_mask guarantees we don't get here before 159 * an INIT_deassert IPI reaches our local APIC, so it is 160 * now safe to touch our local APIC. 161 */ 162 cpuid = smp_processor_id(); 163 164 /* 165 * (This works even if the APIC is not enabled.) 166 */ 167 phys_id = read_apic_id(); 168 169 /* 170 * the boot CPU has finished the init stage and is spinning 171 * on callin_map until we finish. We are free to set up this 172 * CPU, first the APIC. (this is probably redundant on most 173 * boards) 174 */ 175 apic_ap_setup(); 176 177 /* 178 * Save our processor parameters. Note: this information 179 * is needed for clock calibration. 180 */ 181 smp_store_cpu_info(cpuid); 182 183 /* 184 * Get our bogomips. 185 * Update loops_per_jiffy in cpu_data. Previous call to 186 * smp_store_cpu_info() stored a value that is close but not as 187 * accurate as the value just calculated. 188 */ 189 calibrate_delay(); 190 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 191 pr_debug("Stack at about %p\n", &cpuid); 192 193 /* 194 * This must be done before setting cpu_online_mask 195 * or calling notify_cpu_starting. 196 */ 197 set_cpu_sibling_map(raw_smp_processor_id()); 198 wmb(); 199 200 notify_cpu_starting(cpuid); 201 202 /* 203 * Allow the master to continue. 204 */ 205 cpumask_set_cpu(cpuid, cpu_callin_mask); 206 } 207 208 static int cpu0_logical_apicid; 209 static int enable_start_cpu0; 210 /* 211 * Activate a secondary processor. 212 */ 213 static void notrace start_secondary(void *unused) 214 { 215 /* 216 * Don't put *anything* before cpu_init(), SMP booting is too 217 * fragile that we want to limit the things done here to the 218 * most necessary things. 219 */ 220 cpu_init(); 221 x86_cpuinit.early_percpu_clock_init(); 222 preempt_disable(); 223 smp_callin(); 224 225 enable_start_cpu0 = 0; 226 227 #ifdef CONFIG_X86_32 228 /* switch away from the initial page table */ 229 load_cr3(swapper_pg_dir); 230 __flush_tlb_all(); 231 #endif 232 233 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 234 barrier(); 235 /* 236 * Check TSC synchronization with the BP: 237 */ 238 check_tsc_sync_target(); 239 240 /* 241 * Lock vector_lock and initialize the vectors on this cpu 242 * before setting the cpu online. We must set it online with 243 * vector_lock held to prevent a concurrent setup/teardown 244 * from seeing a half valid vector space. 245 */ 246 lock_vector_lock(); 247 setup_vector_irq(smp_processor_id()); 248 set_cpu_online(smp_processor_id(), true); 249 unlock_vector_lock(); 250 cpu_set_state_online(smp_processor_id()); 251 x86_platform.nmi_init(); 252 253 /* enable local interrupts */ 254 local_irq_enable(); 255 256 /* to prevent fake stack check failure in clock setup */ 257 boot_init_stack_canary(); 258 259 x86_cpuinit.setup_percpu_clockev(); 260 261 wmb(); 262 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 263 } 264 265 int topology_update_package_map(unsigned int apicid, unsigned int cpu) 266 { 267 unsigned int new, pkg = apicid >> boot_cpu_data.x86_coreid_bits; 268 269 /* Called from early boot ? */ 270 if (!physical_package_map) 271 return 0; 272 273 if (pkg >= max_physical_pkg_id) 274 return -EINVAL; 275 276 /* Set the logical package id */ 277 if (test_and_set_bit(pkg, physical_package_map)) 278 goto found; 279 280 new = find_first_zero_bit(logical_package_map, __max_logical_packages); 281 if (new >= __max_logical_packages) { 282 physical_to_logical_pkg[pkg] = -1; 283 pr_warn("APIC(%x) Package %u exceeds logical package map\n", 284 apicid, pkg); 285 return -ENOSPC; 286 } 287 set_bit(new, logical_package_map); 288 pr_info("APIC(%x) Converting physical %u to logical package %u\n", 289 apicid, pkg, new); 290 physical_to_logical_pkg[pkg] = new; 291 292 found: 293 cpu_data(cpu).logical_proc_id = physical_to_logical_pkg[pkg]; 294 return 0; 295 } 296 297 /** 298 * topology_phys_to_logical_pkg - Map a physical package id to a logical 299 * 300 * Returns logical package id or -1 if not found 301 */ 302 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 303 { 304 if (phys_pkg >= max_physical_pkg_id) 305 return -1; 306 return physical_to_logical_pkg[phys_pkg]; 307 } 308 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 309 310 static void __init smp_init_package_map(void) 311 { 312 unsigned int ncpus, cpu; 313 size_t size; 314 315 /* 316 * Today neither Intel nor AMD support heterogenous systems. That 317 * might change in the future.... 318 * 319 * While ideally we'd want '* smp_num_siblings' in the below @ncpus 320 * computation, this won't actually work since some Intel BIOSes 321 * report inconsistent HT data when they disable HT. 322 * 323 * In particular, they reduce the APIC-IDs to only include the cores, 324 * but leave the CPUID topology to say there are (2) siblings. 325 * This means we don't know how many threads there will be until 326 * after the APIC enumeration. 327 * 328 * By not including this we'll sometimes over-estimate the number of 329 * logical packages by the amount of !present siblings, but this is 330 * still better than MAX_LOCAL_APIC. 331 * 332 * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited 333 * on the command line leading to a similar issue as the HT disable 334 * problem because the hyperthreads are usually enumerated after the 335 * primary cores. 336 */ 337 ncpus = boot_cpu_data.x86_max_cores; 338 if (!ncpus) { 339 pr_warn("x86_max_cores == zero !?!?"); 340 ncpus = 1; 341 } 342 343 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); 344 345 /* 346 * Possibly larger than what we need as the number of apic ids per 347 * package can be smaller than the actual used apic ids. 348 */ 349 max_physical_pkg_id = DIV_ROUND_UP(MAX_LOCAL_APIC, ncpus); 350 size = max_physical_pkg_id * sizeof(unsigned int); 351 physical_to_logical_pkg = kmalloc(size, GFP_KERNEL); 352 memset(physical_to_logical_pkg, 0xff, size); 353 size = BITS_TO_LONGS(max_physical_pkg_id) * sizeof(unsigned long); 354 physical_package_map = kzalloc(size, GFP_KERNEL); 355 size = BITS_TO_LONGS(__max_logical_packages) * sizeof(unsigned long); 356 logical_package_map = kzalloc(size, GFP_KERNEL); 357 358 pr_info("Max logical packages: %u\n", __max_logical_packages); 359 360 for_each_present_cpu(cpu) { 361 unsigned int apicid = apic->cpu_present_to_apicid(cpu); 362 363 if (apicid == BAD_APICID || !apic->apic_id_valid(apicid)) 364 continue; 365 if (!topology_update_package_map(apicid, cpu)) 366 continue; 367 pr_warn("CPU %u APICId %x disabled\n", cpu, apicid); 368 per_cpu(x86_bios_cpu_apicid, cpu) = BAD_APICID; 369 set_cpu_possible(cpu, false); 370 set_cpu_present(cpu, false); 371 } 372 } 373 374 void __init smp_store_boot_cpu_info(void) 375 { 376 int id = 0; /* CPU 0 */ 377 struct cpuinfo_x86 *c = &cpu_data(id); 378 379 *c = boot_cpu_data; 380 c->cpu_index = id; 381 smp_init_package_map(); 382 } 383 384 /* 385 * The bootstrap kernel entry code has set these up. Save them for 386 * a given CPU 387 */ 388 void smp_store_cpu_info(int id) 389 { 390 struct cpuinfo_x86 *c = &cpu_data(id); 391 392 *c = boot_cpu_data; 393 c->cpu_index = id; 394 /* 395 * During boot time, CPU0 has this setup already. Save the info when 396 * bringing up AP or offlined CPU0. 397 */ 398 identify_secondary_cpu(c); 399 } 400 401 static bool 402 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 403 { 404 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 405 406 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 407 } 408 409 static bool 410 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 411 { 412 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 413 414 return !WARN_ONCE(!topology_same_node(c, o), 415 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 416 "[node: %d != %d]. Ignoring dependency.\n", 417 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 418 } 419 420 #define link_mask(mfunc, c1, c2) \ 421 do { \ 422 cpumask_set_cpu((c1), mfunc(c2)); \ 423 cpumask_set_cpu((c2), mfunc(c1)); \ 424 } while (0) 425 426 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 427 { 428 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 429 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 430 431 if (c->phys_proc_id == o->phys_proc_id && 432 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && 433 c->cpu_core_id == o->cpu_core_id) 434 return topology_sane(c, o, "smt"); 435 436 } else if (c->phys_proc_id == o->phys_proc_id && 437 c->cpu_core_id == o->cpu_core_id) { 438 return topology_sane(c, o, "smt"); 439 } 440 441 return false; 442 } 443 444 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 445 { 446 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 447 448 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && 449 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) 450 return topology_sane(c, o, "llc"); 451 452 return false; 453 } 454 455 /* 456 * Unlike the other levels, we do not enforce keeping a 457 * multicore group inside a NUMA node. If this happens, we will 458 * discard the MC level of the topology later. 459 */ 460 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 461 { 462 if (c->phys_proc_id == o->phys_proc_id) 463 return true; 464 return false; 465 } 466 467 static struct sched_domain_topology_level numa_inside_package_topology[] = { 468 #ifdef CONFIG_SCHED_SMT 469 { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) }, 470 #endif 471 #ifdef CONFIG_SCHED_MC 472 { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) }, 473 #endif 474 { NULL, }, 475 }; 476 /* 477 * set_sched_topology() sets the topology internal to a CPU. The 478 * NUMA topologies are layered on top of it to build the full 479 * system topology. 480 * 481 * If NUMA nodes are observed to occur within a CPU package, this 482 * function should be called. It forces the sched domain code to 483 * only use the SMT level for the CPU portion of the topology. 484 * This essentially falls back to relying on NUMA information 485 * from the SRAT table to describe the entire system topology 486 * (except for hyperthreads). 487 */ 488 static void primarily_use_numa_for_topology(void) 489 { 490 set_sched_topology(numa_inside_package_topology); 491 } 492 493 void set_cpu_sibling_map(int cpu) 494 { 495 bool has_smt = smp_num_siblings > 1; 496 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 497 struct cpuinfo_x86 *c = &cpu_data(cpu); 498 struct cpuinfo_x86 *o; 499 int i, threads; 500 501 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 502 503 if (!has_mp) { 504 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 505 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 506 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 507 c->booted_cores = 1; 508 return; 509 } 510 511 for_each_cpu(i, cpu_sibling_setup_mask) { 512 o = &cpu_data(i); 513 514 if ((i == cpu) || (has_smt && match_smt(c, o))) 515 link_mask(topology_sibling_cpumask, cpu, i); 516 517 if ((i == cpu) || (has_mp && match_llc(c, o))) 518 link_mask(cpu_llc_shared_mask, cpu, i); 519 520 } 521 522 /* 523 * This needs a separate iteration over the cpus because we rely on all 524 * topology_sibling_cpumask links to be set-up. 525 */ 526 for_each_cpu(i, cpu_sibling_setup_mask) { 527 o = &cpu_data(i); 528 529 if ((i == cpu) || (has_mp && match_die(c, o))) { 530 link_mask(topology_core_cpumask, cpu, i); 531 532 /* 533 * Does this new cpu bringup a new core? 534 */ 535 if (cpumask_weight( 536 topology_sibling_cpumask(cpu)) == 1) { 537 /* 538 * for each core in package, increment 539 * the booted_cores for this new cpu 540 */ 541 if (cpumask_first( 542 topology_sibling_cpumask(i)) == i) 543 c->booted_cores++; 544 /* 545 * increment the core count for all 546 * the other cpus in this package 547 */ 548 if (i != cpu) 549 cpu_data(i).booted_cores++; 550 } else if (i != cpu && !c->booted_cores) 551 c->booted_cores = cpu_data(i).booted_cores; 552 } 553 if (match_die(c, o) && !topology_same_node(c, o)) 554 primarily_use_numa_for_topology(); 555 } 556 557 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 558 if (threads > __max_smt_threads) 559 __max_smt_threads = threads; 560 } 561 562 /* maps the cpu to the sched domain representing multi-core */ 563 const struct cpumask *cpu_coregroup_mask(int cpu) 564 { 565 return cpu_llc_shared_mask(cpu); 566 } 567 568 static void impress_friends(void) 569 { 570 int cpu; 571 unsigned long bogosum = 0; 572 /* 573 * Allow the user to impress friends. 574 */ 575 pr_debug("Before bogomips\n"); 576 for_each_possible_cpu(cpu) 577 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 578 bogosum += cpu_data(cpu).loops_per_jiffy; 579 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 580 num_online_cpus(), 581 bogosum/(500000/HZ), 582 (bogosum/(5000/HZ))%100); 583 584 pr_debug("Before bogocount - setting activated=1\n"); 585 } 586 587 void __inquire_remote_apic(int apicid) 588 { 589 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 590 const char * const names[] = { "ID", "VERSION", "SPIV" }; 591 int timeout; 592 u32 status; 593 594 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 595 596 for (i = 0; i < ARRAY_SIZE(regs); i++) { 597 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 598 599 /* 600 * Wait for idle. 601 */ 602 status = safe_apic_wait_icr_idle(); 603 if (status) 604 pr_cont("a previous APIC delivery may have failed\n"); 605 606 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 607 608 timeout = 0; 609 do { 610 udelay(100); 611 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 612 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 613 614 switch (status) { 615 case APIC_ICR_RR_VALID: 616 status = apic_read(APIC_RRR); 617 pr_cont("%08x\n", status); 618 break; 619 default: 620 pr_cont("failed\n"); 621 } 622 } 623 } 624 625 /* 626 * The Multiprocessor Specification 1.4 (1997) example code suggests 627 * that there should be a 10ms delay between the BSP asserting INIT 628 * and de-asserting INIT, when starting a remote processor. 629 * But that slows boot and resume on modern processors, which include 630 * many cores and don't require that delay. 631 * 632 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 633 * Modern processor families are quirked to remove the delay entirely. 634 */ 635 #define UDELAY_10MS_DEFAULT 10000 636 637 static unsigned int init_udelay = UINT_MAX; 638 639 static int __init cpu_init_udelay(char *str) 640 { 641 get_option(&str, &init_udelay); 642 643 return 0; 644 } 645 early_param("cpu_init_udelay", cpu_init_udelay); 646 647 static void __init smp_quirk_init_udelay(void) 648 { 649 /* if cmdline changed it from default, leave it alone */ 650 if (init_udelay != UINT_MAX) 651 return; 652 653 /* if modern processor, use no delay */ 654 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 655 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 656 init_udelay = 0; 657 return; 658 } 659 /* else, use legacy delay */ 660 init_udelay = UDELAY_10MS_DEFAULT; 661 } 662 663 /* 664 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 665 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 666 * won't ... remember to clear down the APIC, etc later. 667 */ 668 int 669 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 670 { 671 unsigned long send_status, accept_status = 0; 672 int maxlvt; 673 674 /* Target chip */ 675 /* Boot on the stack */ 676 /* Kick the second */ 677 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); 678 679 pr_debug("Waiting for send to finish...\n"); 680 send_status = safe_apic_wait_icr_idle(); 681 682 /* 683 * Give the other CPU some time to accept the IPI. 684 */ 685 udelay(200); 686 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 687 maxlvt = lapic_get_maxlvt(); 688 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 689 apic_write(APIC_ESR, 0); 690 accept_status = (apic_read(APIC_ESR) & 0xEF); 691 } 692 pr_debug("NMI sent\n"); 693 694 if (send_status) 695 pr_err("APIC never delivered???\n"); 696 if (accept_status) 697 pr_err("APIC delivery error (%lx)\n", accept_status); 698 699 return (send_status | accept_status); 700 } 701 702 static int 703 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 704 { 705 unsigned long send_status = 0, accept_status = 0; 706 int maxlvt, num_starts, j; 707 708 maxlvt = lapic_get_maxlvt(); 709 710 /* 711 * Be paranoid about clearing APIC errors. 712 */ 713 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 714 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 715 apic_write(APIC_ESR, 0); 716 apic_read(APIC_ESR); 717 } 718 719 pr_debug("Asserting INIT\n"); 720 721 /* 722 * Turn INIT on target chip 723 */ 724 /* 725 * Send IPI 726 */ 727 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 728 phys_apicid); 729 730 pr_debug("Waiting for send to finish...\n"); 731 send_status = safe_apic_wait_icr_idle(); 732 733 udelay(init_udelay); 734 735 pr_debug("Deasserting INIT\n"); 736 737 /* Target chip */ 738 /* Send IPI */ 739 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 740 741 pr_debug("Waiting for send to finish...\n"); 742 send_status = safe_apic_wait_icr_idle(); 743 744 mb(); 745 746 /* 747 * Should we send STARTUP IPIs ? 748 * 749 * Determine this based on the APIC version. 750 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 751 */ 752 if (APIC_INTEGRATED(apic_version[phys_apicid])) 753 num_starts = 2; 754 else 755 num_starts = 0; 756 757 /* 758 * Run STARTUP IPI loop. 759 */ 760 pr_debug("#startup loops: %d\n", num_starts); 761 762 for (j = 1; j <= num_starts; j++) { 763 pr_debug("Sending STARTUP #%d\n", j); 764 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 765 apic_write(APIC_ESR, 0); 766 apic_read(APIC_ESR); 767 pr_debug("After apic_write\n"); 768 769 /* 770 * STARTUP IPI 771 */ 772 773 /* Target chip */ 774 /* Boot on the stack */ 775 /* Kick the second */ 776 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 777 phys_apicid); 778 779 /* 780 * Give the other CPU some time to accept the IPI. 781 */ 782 if (init_udelay == 0) 783 udelay(10); 784 else 785 udelay(300); 786 787 pr_debug("Startup point 1\n"); 788 789 pr_debug("Waiting for send to finish...\n"); 790 send_status = safe_apic_wait_icr_idle(); 791 792 /* 793 * Give the other CPU some time to accept the IPI. 794 */ 795 if (init_udelay == 0) 796 udelay(10); 797 else 798 udelay(200); 799 800 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 801 apic_write(APIC_ESR, 0); 802 accept_status = (apic_read(APIC_ESR) & 0xEF); 803 if (send_status || accept_status) 804 break; 805 } 806 pr_debug("After Startup\n"); 807 808 if (send_status) 809 pr_err("APIC never delivered???\n"); 810 if (accept_status) 811 pr_err("APIC delivery error (%lx)\n", accept_status); 812 813 return (send_status | accept_status); 814 } 815 816 void smp_announce(void) 817 { 818 int num_nodes = num_online_nodes(); 819 820 printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n", 821 num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus()); 822 } 823 824 /* reduce the number of lines printed when booting a large cpu count system */ 825 static void announce_cpu(int cpu, int apicid) 826 { 827 static int current_node = -1; 828 int node = early_cpu_to_node(cpu); 829 static int width, node_width; 830 831 if (!width) 832 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 833 834 if (!node_width) 835 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 836 837 if (cpu == 1) 838 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 839 840 if (system_state == SYSTEM_BOOTING) { 841 if (node != current_node) { 842 if (current_node > (-1)) 843 pr_cont("\n"); 844 current_node = node; 845 846 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 847 node_width - num_digits(node), " ", node); 848 } 849 850 /* Add padding for the BSP */ 851 if (cpu == 1) 852 pr_cont("%*s", width + 1, " "); 853 854 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 855 856 } else 857 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 858 node, cpu, apicid); 859 } 860 861 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 862 { 863 int cpu; 864 865 cpu = smp_processor_id(); 866 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 867 return NMI_HANDLED; 868 869 return NMI_DONE; 870 } 871 872 /* 873 * Wake up AP by INIT, INIT, STARTUP sequence. 874 * 875 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 876 * boot-strap code which is not a desired behavior for waking up BSP. To 877 * void the boot-strap code, wake up CPU0 by NMI instead. 878 * 879 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 880 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 881 * We'll change this code in the future to wake up hard offlined CPU0 if 882 * real platform and request are available. 883 */ 884 static int 885 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 886 int *cpu0_nmi_registered) 887 { 888 int id; 889 int boot_error; 890 891 preempt_disable(); 892 893 /* 894 * Wake up AP by INIT, INIT, STARTUP sequence. 895 */ 896 if (cpu) { 897 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 898 goto out; 899 } 900 901 /* 902 * Wake up BSP by nmi. 903 * 904 * Register a NMI handler to help wake up CPU0. 905 */ 906 boot_error = register_nmi_handler(NMI_LOCAL, 907 wakeup_cpu0_nmi, 0, "wake_cpu0"); 908 909 if (!boot_error) { 910 enable_start_cpu0 = 1; 911 *cpu0_nmi_registered = 1; 912 if (apic->dest_logical == APIC_DEST_LOGICAL) 913 id = cpu0_logical_apicid; 914 else 915 id = apicid; 916 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 917 } 918 919 out: 920 preempt_enable(); 921 922 return boot_error; 923 } 924 925 void common_cpu_up(unsigned int cpu, struct task_struct *idle) 926 { 927 /* Just in case we booted with a single CPU. */ 928 alternatives_enable_smp(); 929 930 per_cpu(current_task, cpu) = idle; 931 932 #ifdef CONFIG_X86_32 933 /* Stack for startup_32 can be just as for start_secondary onwards */ 934 irq_ctx_init(cpu); 935 per_cpu(cpu_current_top_of_stack, cpu) = 936 (unsigned long)task_stack_page(idle) + THREAD_SIZE; 937 #else 938 clear_tsk_thread_flag(idle, TIF_FORK); 939 initial_gs = per_cpu_offset(cpu); 940 #endif 941 } 942 943 /* 944 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 945 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 946 * Returns zero if CPU booted OK, else error code from 947 * ->wakeup_secondary_cpu. 948 */ 949 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) 950 { 951 volatile u32 *trampoline_status = 952 (volatile u32 *) __va(real_mode_header->trampoline_status); 953 /* start_ip had better be page-aligned! */ 954 unsigned long start_ip = real_mode_header->trampoline_start; 955 956 unsigned long boot_error = 0; 957 int cpu0_nmi_registered = 0; 958 unsigned long timeout; 959 960 idle->thread.sp = (unsigned long) (((struct pt_regs *) 961 (THREAD_SIZE + task_stack_page(idle))) - 1); 962 963 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 964 initial_code = (unsigned long)start_secondary; 965 stack_start = idle->thread.sp; 966 967 /* 968 * Enable the espfix hack for this CPU 969 */ 970 #ifdef CONFIG_X86_ESPFIX64 971 init_espfix_ap(cpu); 972 #endif 973 974 /* So we see what's up */ 975 announce_cpu(cpu, apicid); 976 977 /* 978 * This grunge runs the startup process for 979 * the targeted processor. 980 */ 981 982 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 983 984 pr_debug("Setting warm reset code and vector.\n"); 985 986 smpboot_setup_warm_reset_vector(start_ip); 987 /* 988 * Be paranoid about clearing APIC errors. 989 */ 990 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 991 apic_write(APIC_ESR, 0); 992 apic_read(APIC_ESR); 993 } 994 } 995 996 /* 997 * AP might wait on cpu_callout_mask in cpu_init() with 998 * cpu_initialized_mask set if previous attempt to online 999 * it timed-out. Clear cpu_initialized_mask so that after 1000 * INIT/SIPI it could start with a clean state. 1001 */ 1002 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1003 smp_mb(); 1004 1005 /* 1006 * Wake up a CPU in difference cases: 1007 * - Use the method in the APIC driver if it's defined 1008 * Otherwise, 1009 * - Use an INIT boot APIC message for APs or NMI for BSP. 1010 */ 1011 if (apic->wakeup_secondary_cpu) 1012 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 1013 else 1014 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 1015 &cpu0_nmi_registered); 1016 1017 if (!boot_error) { 1018 /* 1019 * Wait 10s total for first sign of life from AP 1020 */ 1021 boot_error = -1; 1022 timeout = jiffies + 10*HZ; 1023 while (time_before(jiffies, timeout)) { 1024 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 1025 /* 1026 * Tell AP to proceed with initialization 1027 */ 1028 cpumask_set_cpu(cpu, cpu_callout_mask); 1029 boot_error = 0; 1030 break; 1031 } 1032 schedule(); 1033 } 1034 } 1035 1036 if (!boot_error) { 1037 /* 1038 * Wait till AP completes initial initialization 1039 */ 1040 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 1041 /* 1042 * Allow other tasks to run while we wait for the 1043 * AP to come online. This also gives a chance 1044 * for the MTRR work(triggered by the AP coming online) 1045 * to be completed in the stop machine context. 1046 */ 1047 schedule(); 1048 } 1049 } 1050 1051 /* mark "stuck" area as not stuck */ 1052 *trampoline_status = 0; 1053 1054 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 1055 /* 1056 * Cleanup possible dangling ends... 1057 */ 1058 smpboot_restore_warm_reset_vector(); 1059 } 1060 /* 1061 * Clean up the nmi handler. Do this after the callin and callout sync 1062 * to avoid impact of possible long unregister time. 1063 */ 1064 if (cpu0_nmi_registered) 1065 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 1066 1067 return boot_error; 1068 } 1069 1070 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 1071 { 1072 int apicid = apic->cpu_present_to_apicid(cpu); 1073 unsigned long flags; 1074 int err; 1075 1076 WARN_ON(irqs_disabled()); 1077 1078 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1079 1080 if (apicid == BAD_APICID || 1081 !physid_isset(apicid, phys_cpu_present_map) || 1082 !apic->apic_id_valid(apicid)) { 1083 pr_err("%s: bad cpu %d\n", __func__, cpu); 1084 return -EINVAL; 1085 } 1086 1087 /* 1088 * Already booted CPU? 1089 */ 1090 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 1091 pr_debug("do_boot_cpu %d Already started\n", cpu); 1092 return -ENOSYS; 1093 } 1094 1095 /* 1096 * Save current MTRR state in case it was changed since early boot 1097 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1098 */ 1099 mtrr_save_state(); 1100 1101 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 1102 err = cpu_check_up_prepare(cpu); 1103 if (err && err != -EBUSY) 1104 return err; 1105 1106 /* the FPU context is blank, nobody can own it */ 1107 __cpu_disable_lazy_restore(cpu); 1108 1109 common_cpu_up(cpu, tidle); 1110 1111 /* 1112 * We have to walk the irq descriptors to setup the vector 1113 * space for the cpu which comes online. Prevent irq 1114 * alloc/free across the bringup. 1115 */ 1116 irq_lock_sparse(); 1117 1118 err = do_boot_cpu(apicid, cpu, tidle); 1119 1120 if (err) { 1121 irq_unlock_sparse(); 1122 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1123 return -EIO; 1124 } 1125 1126 /* 1127 * Check TSC synchronization with the AP (keep irqs disabled 1128 * while doing so): 1129 */ 1130 local_irq_save(flags); 1131 check_tsc_sync_source(cpu); 1132 local_irq_restore(flags); 1133 1134 while (!cpu_online(cpu)) { 1135 cpu_relax(); 1136 touch_nmi_watchdog(); 1137 } 1138 1139 irq_unlock_sparse(); 1140 1141 return 0; 1142 } 1143 1144 /** 1145 * arch_disable_smp_support() - disables SMP support for x86 at runtime 1146 */ 1147 void arch_disable_smp_support(void) 1148 { 1149 disable_ioapic_support(); 1150 } 1151 1152 /* 1153 * Fall back to non SMP mode after errors. 1154 * 1155 * RED-PEN audit/test this more. I bet there is more state messed up here. 1156 */ 1157 static __init void disable_smp(void) 1158 { 1159 pr_info("SMP disabled\n"); 1160 1161 disable_ioapic_support(); 1162 1163 init_cpu_present(cpumask_of(0)); 1164 init_cpu_possible(cpumask_of(0)); 1165 1166 if (smp_found_config) 1167 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1168 else 1169 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1170 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1171 cpumask_set_cpu(0, topology_core_cpumask(0)); 1172 } 1173 1174 enum { 1175 SMP_OK, 1176 SMP_NO_CONFIG, 1177 SMP_NO_APIC, 1178 SMP_FORCE_UP, 1179 }; 1180 1181 /* 1182 * Various sanity checks. 1183 */ 1184 static int __init smp_sanity_check(unsigned max_cpus) 1185 { 1186 preempt_disable(); 1187 1188 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1189 if (def_to_bigsmp && nr_cpu_ids > 8) { 1190 unsigned int cpu; 1191 unsigned nr; 1192 1193 pr_warn("More than 8 CPUs detected - skipping them\n" 1194 "Use CONFIG_X86_BIGSMP\n"); 1195 1196 nr = 0; 1197 for_each_present_cpu(cpu) { 1198 if (nr >= 8) 1199 set_cpu_present(cpu, false); 1200 nr++; 1201 } 1202 1203 nr = 0; 1204 for_each_possible_cpu(cpu) { 1205 if (nr >= 8) 1206 set_cpu_possible(cpu, false); 1207 nr++; 1208 } 1209 1210 nr_cpu_ids = 8; 1211 } 1212 #endif 1213 1214 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1215 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1216 hard_smp_processor_id()); 1217 1218 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1219 } 1220 1221 /* 1222 * If we couldn't find an SMP configuration at boot time, 1223 * get out of here now! 1224 */ 1225 if (!smp_found_config && !acpi_lapic) { 1226 preempt_enable(); 1227 pr_notice("SMP motherboard not detected\n"); 1228 return SMP_NO_CONFIG; 1229 } 1230 1231 /* 1232 * Should not be necessary because the MP table should list the boot 1233 * CPU too, but we do it for the sake of robustness anyway. 1234 */ 1235 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1236 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1237 boot_cpu_physical_apicid); 1238 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1239 } 1240 preempt_enable(); 1241 1242 /* 1243 * If we couldn't find a local APIC, then get out of here now! 1244 */ 1245 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 1246 !boot_cpu_has(X86_FEATURE_APIC)) { 1247 if (!disable_apic) { 1248 pr_err("BIOS bug, local APIC #%d not detected!...\n", 1249 boot_cpu_physical_apicid); 1250 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); 1251 } 1252 return SMP_NO_APIC; 1253 } 1254 1255 /* 1256 * If SMP should be disabled, then really disable it! 1257 */ 1258 if (!max_cpus) { 1259 pr_info("SMP mode deactivated\n"); 1260 return SMP_FORCE_UP; 1261 } 1262 1263 return SMP_OK; 1264 } 1265 1266 static void __init smp_cpu_index_default(void) 1267 { 1268 int i; 1269 struct cpuinfo_x86 *c; 1270 1271 for_each_possible_cpu(i) { 1272 c = &cpu_data(i); 1273 /* mark all to hotplug */ 1274 c->cpu_index = nr_cpu_ids; 1275 } 1276 } 1277 1278 /* 1279 * Prepare for SMP bootup. The MP table or ACPI has been read 1280 * earlier. Just do some sanity checking here and enable APIC mode. 1281 */ 1282 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1283 { 1284 unsigned int i; 1285 1286 smp_cpu_index_default(); 1287 1288 /* 1289 * Setup boot CPU information 1290 */ 1291 smp_store_boot_cpu_info(); /* Final full version of the data */ 1292 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1293 mb(); 1294 1295 for_each_possible_cpu(i) { 1296 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1297 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1298 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1299 } 1300 set_cpu_sibling_map(0); 1301 1302 switch (smp_sanity_check(max_cpus)) { 1303 case SMP_NO_CONFIG: 1304 disable_smp(); 1305 if (APIC_init_uniprocessor()) 1306 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); 1307 return; 1308 case SMP_NO_APIC: 1309 disable_smp(); 1310 return; 1311 case SMP_FORCE_UP: 1312 disable_smp(); 1313 apic_bsp_setup(false); 1314 return; 1315 case SMP_OK: 1316 break; 1317 } 1318 1319 default_setup_apic_routing(); 1320 1321 if (read_apic_id() != boot_cpu_physical_apicid) { 1322 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1323 read_apic_id(), boot_cpu_physical_apicid); 1324 /* Or can we switch back to PIC here? */ 1325 } 1326 1327 cpu0_logical_apicid = apic_bsp_setup(false); 1328 1329 pr_info("CPU%d: ", 0); 1330 print_cpu_info(&cpu_data(0)); 1331 1332 if (is_uv_system()) 1333 uv_system_init(); 1334 1335 set_mtrr_aps_delayed_init(); 1336 1337 smp_quirk_init_udelay(); 1338 } 1339 1340 void arch_enable_nonboot_cpus_begin(void) 1341 { 1342 set_mtrr_aps_delayed_init(); 1343 } 1344 1345 void arch_enable_nonboot_cpus_end(void) 1346 { 1347 mtrr_aps_init(); 1348 } 1349 1350 /* 1351 * Early setup to make printk work. 1352 */ 1353 void __init native_smp_prepare_boot_cpu(void) 1354 { 1355 int me = smp_processor_id(); 1356 switch_to_new_gdt(me); 1357 /* already set me in cpu_online_mask in boot_cpu_init() */ 1358 cpumask_set_cpu(me, cpu_callout_mask); 1359 cpu_set_state_online(me); 1360 } 1361 1362 void __init native_smp_cpus_done(unsigned int max_cpus) 1363 { 1364 pr_debug("Boot done\n"); 1365 1366 nmi_selftest(); 1367 impress_friends(); 1368 setup_ioapic_dest(); 1369 mtrr_aps_init(); 1370 } 1371 1372 static int __initdata setup_possible_cpus = -1; 1373 static int __init _setup_possible_cpus(char *str) 1374 { 1375 get_option(&str, &setup_possible_cpus); 1376 return 0; 1377 } 1378 early_param("possible_cpus", _setup_possible_cpus); 1379 1380 1381 /* 1382 * cpu_possible_mask should be static, it cannot change as cpu's 1383 * are onlined, or offlined. The reason is per-cpu data-structures 1384 * are allocated by some modules at init time, and dont expect to 1385 * do this dynamically on cpu arrival/departure. 1386 * cpu_present_mask on the other hand can change dynamically. 1387 * In case when cpu_hotplug is not compiled, then we resort to current 1388 * behaviour, which is cpu_possible == cpu_present. 1389 * - Ashok Raj 1390 * 1391 * Three ways to find out the number of additional hotplug CPUs: 1392 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1393 * - The user can overwrite it with possible_cpus=NUM 1394 * - Otherwise don't reserve additional CPUs. 1395 * We do this because additional CPUs waste a lot of memory. 1396 * -AK 1397 */ 1398 __init void prefill_possible_map(void) 1399 { 1400 int i, possible; 1401 1402 /* no processor from mptable or madt */ 1403 if (!num_processors) 1404 num_processors = 1; 1405 1406 i = setup_max_cpus ?: 1; 1407 if (setup_possible_cpus == -1) { 1408 possible = num_processors; 1409 #ifdef CONFIG_HOTPLUG_CPU 1410 if (setup_max_cpus) 1411 possible += disabled_cpus; 1412 #else 1413 if (possible > i) 1414 possible = i; 1415 #endif 1416 } else 1417 possible = setup_possible_cpus; 1418 1419 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1420 1421 /* nr_cpu_ids could be reduced via nr_cpus= */ 1422 if (possible > nr_cpu_ids) { 1423 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", 1424 possible, nr_cpu_ids); 1425 possible = nr_cpu_ids; 1426 } 1427 1428 #ifdef CONFIG_HOTPLUG_CPU 1429 if (!setup_max_cpus) 1430 #endif 1431 if (possible > i) { 1432 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1433 possible, setup_max_cpus); 1434 possible = i; 1435 } 1436 1437 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1438 possible, max_t(int, possible - num_processors, 0)); 1439 1440 for (i = 0; i < possible; i++) 1441 set_cpu_possible(i, true); 1442 for (; i < NR_CPUS; i++) 1443 set_cpu_possible(i, false); 1444 1445 nr_cpu_ids = possible; 1446 } 1447 1448 #ifdef CONFIG_HOTPLUG_CPU 1449 1450 /* Recompute SMT state for all CPUs on offline */ 1451 static void recompute_smt_state(void) 1452 { 1453 int max_threads, cpu; 1454 1455 max_threads = 0; 1456 for_each_online_cpu (cpu) { 1457 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1458 1459 if (threads > max_threads) 1460 max_threads = threads; 1461 } 1462 __max_smt_threads = max_threads; 1463 } 1464 1465 static void remove_siblinginfo(int cpu) 1466 { 1467 int sibling; 1468 struct cpuinfo_x86 *c = &cpu_data(cpu); 1469 1470 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1471 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1472 /*/ 1473 * last thread sibling in this cpu core going down 1474 */ 1475 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1476 cpu_data(sibling).booted_cores--; 1477 } 1478 1479 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) 1480 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1481 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1482 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1483 cpumask_clear(cpu_llc_shared_mask(cpu)); 1484 cpumask_clear(topology_sibling_cpumask(cpu)); 1485 cpumask_clear(topology_core_cpumask(cpu)); 1486 c->phys_proc_id = 0; 1487 c->cpu_core_id = 0; 1488 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1489 recompute_smt_state(); 1490 } 1491 1492 static void remove_cpu_from_maps(int cpu) 1493 { 1494 set_cpu_online(cpu, false); 1495 cpumask_clear_cpu(cpu, cpu_callout_mask); 1496 cpumask_clear_cpu(cpu, cpu_callin_mask); 1497 /* was set by cpu_init() */ 1498 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1499 numa_remove_cpu(cpu); 1500 } 1501 1502 void cpu_disable_common(void) 1503 { 1504 int cpu = smp_processor_id(); 1505 1506 remove_siblinginfo(cpu); 1507 1508 /* It's now safe to remove this processor from the online map */ 1509 lock_vector_lock(); 1510 remove_cpu_from_maps(cpu); 1511 unlock_vector_lock(); 1512 fixup_irqs(); 1513 } 1514 1515 int native_cpu_disable(void) 1516 { 1517 int ret; 1518 1519 ret = check_irq_vectors_for_cpu_disable(); 1520 if (ret) 1521 return ret; 1522 1523 clear_local_APIC(); 1524 cpu_disable_common(); 1525 1526 return 0; 1527 } 1528 1529 int common_cpu_die(unsigned int cpu) 1530 { 1531 int ret = 0; 1532 1533 /* We don't do anything here: idle task is faking death itself. */ 1534 1535 /* They ack this in play_dead() by setting CPU_DEAD */ 1536 if (cpu_wait_death(cpu, 5)) { 1537 if (system_state == SYSTEM_RUNNING) 1538 pr_info("CPU %u is now offline\n", cpu); 1539 } else { 1540 pr_err("CPU %u didn't die...\n", cpu); 1541 ret = -1; 1542 } 1543 1544 return ret; 1545 } 1546 1547 void native_cpu_die(unsigned int cpu) 1548 { 1549 common_cpu_die(cpu); 1550 } 1551 1552 void play_dead_common(void) 1553 { 1554 idle_task_exit(); 1555 reset_lazy_tlbstate(); 1556 amd_e400_remove_cpu(raw_smp_processor_id()); 1557 1558 /* Ack it */ 1559 (void)cpu_report_death(); 1560 1561 /* 1562 * With physical CPU hotplug, we should halt the cpu 1563 */ 1564 local_irq_disable(); 1565 } 1566 1567 static bool wakeup_cpu0(void) 1568 { 1569 if (smp_processor_id() == 0 && enable_start_cpu0) 1570 return true; 1571 1572 return false; 1573 } 1574 1575 /* 1576 * We need to flush the caches before going to sleep, lest we have 1577 * dirty data in our caches when we come back up. 1578 */ 1579 static inline void mwait_play_dead(void) 1580 { 1581 unsigned int eax, ebx, ecx, edx; 1582 unsigned int highest_cstate = 0; 1583 unsigned int highest_subcstate = 0; 1584 void *mwait_ptr; 1585 int i; 1586 1587 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1588 return; 1589 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1590 return; 1591 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1592 return; 1593 1594 eax = CPUID_MWAIT_LEAF; 1595 ecx = 0; 1596 native_cpuid(&eax, &ebx, &ecx, &edx); 1597 1598 /* 1599 * eax will be 0 if EDX enumeration is not valid. 1600 * Initialized below to cstate, sub_cstate value when EDX is valid. 1601 */ 1602 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1603 eax = 0; 1604 } else { 1605 edx >>= MWAIT_SUBSTATE_SIZE; 1606 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1607 if (edx & MWAIT_SUBSTATE_MASK) { 1608 highest_cstate = i; 1609 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1610 } 1611 } 1612 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1613 (highest_subcstate - 1); 1614 } 1615 1616 /* 1617 * This should be a memory location in a cache line which is 1618 * unlikely to be touched by other processors. The actual 1619 * content is immaterial as it is not actually modified in any way. 1620 */ 1621 mwait_ptr = ¤t_thread_info()->flags; 1622 1623 wbinvd(); 1624 1625 while (1) { 1626 /* 1627 * The CLFLUSH is a workaround for erratum AAI65 for 1628 * the Xeon 7400 series. It's not clear it is actually 1629 * needed, but it should be harmless in either case. 1630 * The WBINVD is insufficient due to the spurious-wakeup 1631 * case where we return around the loop. 1632 */ 1633 mb(); 1634 clflush(mwait_ptr); 1635 mb(); 1636 __monitor(mwait_ptr, 0, 0); 1637 mb(); 1638 __mwait(eax, 0); 1639 /* 1640 * If NMI wants to wake up CPU0, start CPU0. 1641 */ 1642 if (wakeup_cpu0()) 1643 start_cpu0(); 1644 } 1645 } 1646 1647 void hlt_play_dead(void) 1648 { 1649 if (__this_cpu_read(cpu_info.x86) >= 4) 1650 wbinvd(); 1651 1652 while (1) { 1653 native_halt(); 1654 /* 1655 * If NMI wants to wake up CPU0, start CPU0. 1656 */ 1657 if (wakeup_cpu0()) 1658 start_cpu0(); 1659 } 1660 } 1661 1662 void native_play_dead(void) 1663 { 1664 play_dead_common(); 1665 tboot_shutdown(TB_SHUTDOWN_WFS); 1666 1667 mwait_play_dead(); /* Only returns on failure */ 1668 if (cpuidle_play_dead()) 1669 hlt_play_dead(); 1670 } 1671 1672 #else /* ... !CONFIG_HOTPLUG_CPU */ 1673 int native_cpu_disable(void) 1674 { 1675 return -ENOSYS; 1676 } 1677 1678 void native_cpu_die(unsigned int cpu) 1679 { 1680 /* We said "no" in __cpu_disable */ 1681 BUG(); 1682 } 1683 1684 void native_play_dead(void) 1685 { 1686 BUG(); 1687 } 1688 1689 #endif 1690