1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/module.h> 45 #include <linux/sched.h> 46 #include <linux/percpu.h> 47 #include <linux/bootmem.h> 48 #include <linux/err.h> 49 #include <linux/nmi.h> 50 #include <linux/tboot.h> 51 #include <linux/stackprotector.h> 52 #include <linux/gfp.h> 53 54 #include <asm/acpi.h> 55 #include <asm/desc.h> 56 #include <asm/nmi.h> 57 #include <asm/irq.h> 58 #include <asm/idle.h> 59 #include <asm/trampoline.h> 60 #include <asm/cpu.h> 61 #include <asm/numa.h> 62 #include <asm/pgtable.h> 63 #include <asm/tlbflush.h> 64 #include <asm/mtrr.h> 65 #include <asm/mwait.h> 66 #include <asm/apic.h> 67 #include <asm/setup.h> 68 #include <asm/uv/uv.h> 69 #include <linux/mc146818rtc.h> 70 71 #include <asm/smpboot_hooks.h> 72 #include <asm/i8259.h> 73 74 #ifdef CONFIG_X86_32 75 u8 apicid_2_node[MAX_APICID]; 76 #endif 77 78 /* State of each CPU */ 79 DEFINE_PER_CPU(int, cpu_state) = { 0 }; 80 81 /* Store all idle threads, this can be reused instead of creating 82 * a new thread. Also avoids complicated thread destroy functionality 83 * for idle threads. 84 */ 85 #ifdef CONFIG_HOTPLUG_CPU 86 /* 87 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is 88 * removed after init for !CONFIG_HOTPLUG_CPU. 89 */ 90 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); 91 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) 92 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) 93 94 /* 95 * We need this for trampoline_base protection from concurrent accesses when 96 * off- and onlining cores wildly. 97 */ 98 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex); 99 100 void cpu_hotplug_driver_lock() 101 { 102 mutex_lock(&x86_cpu_hotplug_driver_mutex); 103 } 104 105 void cpu_hotplug_driver_unlock() 106 { 107 mutex_unlock(&x86_cpu_hotplug_driver_mutex); 108 } 109 110 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; } 111 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; } 112 #else 113 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; 114 #define get_idle_for_cpu(x) (idle_thread_array[(x)]) 115 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) 116 #endif 117 118 /* Number of siblings per CPU package */ 119 int smp_num_siblings = 1; 120 EXPORT_SYMBOL(smp_num_siblings); 121 122 /* Last level cache ID of each logical CPU */ 123 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; 124 125 /* representing HT siblings of each logical CPU */ 126 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); 127 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 128 129 /* representing HT and core siblings of each logical CPU */ 130 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); 131 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 132 133 /* Per CPU bogomips and other parameters */ 134 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 135 EXPORT_PER_CPU_SYMBOL(cpu_info); 136 137 atomic_t init_deasserted; 138 139 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) 140 /* which node each logical CPU is on */ 141 int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; 142 EXPORT_SYMBOL(cpu_to_node_map); 143 144 /* set up a mapping between cpu and node. */ 145 static void map_cpu_to_node(int cpu, int node) 146 { 147 printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); 148 cpumask_set_cpu(cpu, node_to_cpumask_map[node]); 149 cpu_to_node_map[cpu] = node; 150 } 151 152 /* undo a mapping between cpu and node. */ 153 static void unmap_cpu_to_node(int cpu) 154 { 155 int node; 156 157 printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); 158 for (node = 0; node < MAX_NUMNODES; node++) 159 cpumask_clear_cpu(cpu, node_to_cpumask_map[node]); 160 cpu_to_node_map[cpu] = 0; 161 } 162 #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ 163 #define map_cpu_to_node(cpu, node) ({}) 164 #define unmap_cpu_to_node(cpu) ({}) 165 #endif 166 167 #ifdef CONFIG_X86_32 168 static int boot_cpu_logical_apicid; 169 170 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = 171 { [0 ... NR_CPUS-1] = BAD_APICID }; 172 173 static void map_cpu_to_logical_apicid(void) 174 { 175 int cpu = smp_processor_id(); 176 int apicid = logical_smp_processor_id(); 177 int node = apic->apicid_to_node(apicid); 178 179 if (!node_online(node)) 180 node = first_online_node; 181 182 cpu_2_logical_apicid[cpu] = apicid; 183 map_cpu_to_node(cpu, node); 184 } 185 186 void numa_remove_cpu(int cpu) 187 { 188 cpu_2_logical_apicid[cpu] = BAD_APICID; 189 unmap_cpu_to_node(cpu); 190 } 191 #else 192 #define map_cpu_to_logical_apicid() do {} while (0) 193 #endif 194 195 /* 196 * Report back to the Boot Processor. 197 * Running on AP. 198 */ 199 static void __cpuinit smp_callin(void) 200 { 201 int cpuid, phys_id; 202 unsigned long timeout; 203 204 /* 205 * If waken up by an INIT in an 82489DX configuration 206 * we may get here before an INIT-deassert IPI reaches 207 * our local APIC. We have to wait for the IPI or we'll 208 * lock up on an APIC access. 209 */ 210 if (apic->wait_for_init_deassert) 211 apic->wait_for_init_deassert(&init_deasserted); 212 213 /* 214 * (This works even if the APIC is not enabled.) 215 */ 216 phys_id = read_apic_id(); 217 cpuid = smp_processor_id(); 218 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { 219 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, 220 phys_id, cpuid); 221 } 222 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); 223 224 /* 225 * STARTUP IPIs are fragile beasts as they might sometimes 226 * trigger some glue motherboard logic. Complete APIC bus 227 * silence for 1 second, this overestimates the time the 228 * boot CPU is spending to send the up to 2 STARTUP IPIs 229 * by a factor of two. This should be enough. 230 */ 231 232 /* 233 * Waiting 2s total for startup (udelay is not yet working) 234 */ 235 timeout = jiffies + 2*HZ; 236 while (time_before(jiffies, timeout)) { 237 /* 238 * Has the boot CPU finished it's STARTUP sequence? 239 */ 240 if (cpumask_test_cpu(cpuid, cpu_callout_mask)) 241 break; 242 cpu_relax(); 243 } 244 245 if (!time_before(jiffies, timeout)) { 246 panic("%s: CPU%d started up but did not get a callout!\n", 247 __func__, cpuid); 248 } 249 250 /* 251 * the boot CPU has finished the init stage and is spinning 252 * on callin_map until we finish. We are free to set up this 253 * CPU, first the APIC. (this is probably redundant on most 254 * boards) 255 */ 256 257 pr_debug("CALLIN, before setup_local_APIC().\n"); 258 if (apic->smp_callin_clear_local_apic) 259 apic->smp_callin_clear_local_apic(); 260 setup_local_APIC(); 261 end_local_APIC_setup(); 262 map_cpu_to_logical_apicid(); 263 264 /* 265 * Need to setup vector mappings before we enable interrupts. 266 */ 267 setup_vector_irq(smp_processor_id()); 268 /* 269 * Get our bogomips. 270 * 271 * Need to enable IRQs because it can take longer and then 272 * the NMI watchdog might kill us. 273 */ 274 local_irq_enable(); 275 calibrate_delay(); 276 local_irq_disable(); 277 pr_debug("Stack at about %p\n", &cpuid); 278 279 /* 280 * Save our processor parameters 281 */ 282 smp_store_cpu_info(cpuid); 283 284 notify_cpu_starting(cpuid); 285 286 /* 287 * Allow the master to continue. 288 */ 289 cpumask_set_cpu(cpuid, cpu_callin_mask); 290 } 291 292 /* 293 * Activate a secondary processor. 294 */ 295 notrace static void __cpuinit start_secondary(void *unused) 296 { 297 /* 298 * Don't put *anything* before cpu_init(), SMP booting is too 299 * fragile that we want to limit the things done here to the 300 * most necessary things. 301 */ 302 303 #ifdef CONFIG_X86_32 304 /* 305 * Switch away from the trampoline page-table 306 * 307 * Do this before cpu_init() because it needs to access per-cpu 308 * data which may not be mapped in the trampoline page-table. 309 */ 310 load_cr3(swapper_pg_dir); 311 __flush_tlb_all(); 312 #endif 313 314 cpu_init(); 315 preempt_disable(); 316 smp_callin(); 317 318 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 319 barrier(); 320 /* 321 * Check TSC synchronization with the BP: 322 */ 323 check_tsc_sync_target(); 324 325 if (nmi_watchdog == NMI_IO_APIC) { 326 legacy_pic->mask(0); 327 enable_NMI_through_LVT0(); 328 legacy_pic->unmask(0); 329 } 330 331 /* This must be done before setting cpu_online_mask */ 332 set_cpu_sibling_map(raw_smp_processor_id()); 333 wmb(); 334 335 /* 336 * We need to hold call_lock, so there is no inconsistency 337 * between the time smp_call_function() determines number of 338 * IPI recipients, and the time when the determination is made 339 * for which cpus receive the IPI. Holding this 340 * lock helps us to not include this cpu in a currently in progress 341 * smp_call_function(). 342 * 343 * We need to hold vector_lock so there the set of online cpus 344 * does not change while we are assigning vectors to cpus. Holding 345 * this lock ensures we don't half assign or remove an irq from a cpu. 346 */ 347 ipi_call_lock(); 348 lock_vector_lock(); 349 set_cpu_online(smp_processor_id(), true); 350 unlock_vector_lock(); 351 ipi_call_unlock(); 352 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; 353 x86_platform.nmi_init(); 354 355 /* enable local interrupts */ 356 local_irq_enable(); 357 358 /* to prevent fake stack check failure in clock setup */ 359 boot_init_stack_canary(); 360 361 x86_cpuinit.setup_percpu_clockev(); 362 363 wmb(); 364 cpu_idle(); 365 } 366 367 #ifdef CONFIG_CPUMASK_OFFSTACK 368 /* In this case, llc_shared_map is a pointer to a cpumask. */ 369 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, 370 const struct cpuinfo_x86 *src) 371 { 372 struct cpumask *llc = dst->llc_shared_map; 373 *dst = *src; 374 dst->llc_shared_map = llc; 375 } 376 #else 377 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, 378 const struct cpuinfo_x86 *src) 379 { 380 *dst = *src; 381 } 382 #endif /* CONFIG_CPUMASK_OFFSTACK */ 383 384 /* 385 * The bootstrap kernel entry code has set these up. Save them for 386 * a given CPU 387 */ 388 389 void __cpuinit smp_store_cpu_info(int id) 390 { 391 struct cpuinfo_x86 *c = &cpu_data(id); 392 393 copy_cpuinfo_x86(c, &boot_cpu_data); 394 c->cpu_index = id; 395 if (id != 0) 396 identify_secondary_cpu(c); 397 } 398 399 static void __cpuinit link_thread_siblings(int cpu1, int cpu2) 400 { 401 struct cpuinfo_x86 *c1 = &cpu_data(cpu1); 402 struct cpuinfo_x86 *c2 = &cpu_data(cpu2); 403 404 cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2)); 405 cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1)); 406 cpumask_set_cpu(cpu1, cpu_core_mask(cpu2)); 407 cpumask_set_cpu(cpu2, cpu_core_mask(cpu1)); 408 cpumask_set_cpu(cpu1, c2->llc_shared_map); 409 cpumask_set_cpu(cpu2, c1->llc_shared_map); 410 } 411 412 413 void __cpuinit set_cpu_sibling_map(int cpu) 414 { 415 int i; 416 struct cpuinfo_x86 *c = &cpu_data(cpu); 417 418 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 419 420 if (smp_num_siblings > 1) { 421 for_each_cpu(i, cpu_sibling_setup_mask) { 422 struct cpuinfo_x86 *o = &cpu_data(i); 423 424 if (cpu_has(c, X86_FEATURE_TOPOEXT)) { 425 if (c->phys_proc_id == o->phys_proc_id && 426 c->compute_unit_id == o->compute_unit_id) 427 link_thread_siblings(cpu, i); 428 } else if (c->phys_proc_id == o->phys_proc_id && 429 c->cpu_core_id == o->cpu_core_id) { 430 link_thread_siblings(cpu, i); 431 } 432 } 433 } else { 434 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); 435 } 436 437 cpumask_set_cpu(cpu, c->llc_shared_map); 438 439 if (current_cpu_data.x86_max_cores == 1) { 440 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); 441 c->booted_cores = 1; 442 return; 443 } 444 445 for_each_cpu(i, cpu_sibling_setup_mask) { 446 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && 447 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { 448 cpumask_set_cpu(i, c->llc_shared_map); 449 cpumask_set_cpu(cpu, cpu_data(i).llc_shared_map); 450 } 451 if (c->phys_proc_id == cpu_data(i).phys_proc_id) { 452 cpumask_set_cpu(i, cpu_core_mask(cpu)); 453 cpumask_set_cpu(cpu, cpu_core_mask(i)); 454 /* 455 * Does this new cpu bringup a new core? 456 */ 457 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { 458 /* 459 * for each core in package, increment 460 * the booted_cores for this new cpu 461 */ 462 if (cpumask_first(cpu_sibling_mask(i)) == i) 463 c->booted_cores++; 464 /* 465 * increment the core count for all 466 * the other cpus in this package 467 */ 468 if (i != cpu) 469 cpu_data(i).booted_cores++; 470 } else if (i != cpu && !c->booted_cores) 471 c->booted_cores = cpu_data(i).booted_cores; 472 } 473 } 474 } 475 476 /* maps the cpu to the sched domain representing multi-core */ 477 const struct cpumask *cpu_coregroup_mask(int cpu) 478 { 479 struct cpuinfo_x86 *c = &cpu_data(cpu); 480 /* 481 * For perf, we return last level cache shared map. 482 * And for power savings, we return cpu_core_map 483 */ 484 if ((sched_mc_power_savings || sched_smt_power_savings) && 485 !(cpu_has(c, X86_FEATURE_AMD_DCM))) 486 return cpu_core_mask(cpu); 487 else 488 return c->llc_shared_map; 489 } 490 491 static void impress_friends(void) 492 { 493 int cpu; 494 unsigned long bogosum = 0; 495 /* 496 * Allow the user to impress friends. 497 */ 498 pr_debug("Before bogomips.\n"); 499 for_each_possible_cpu(cpu) 500 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 501 bogosum += cpu_data(cpu).loops_per_jiffy; 502 printk(KERN_INFO 503 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", 504 num_online_cpus(), 505 bogosum/(500000/HZ), 506 (bogosum/(5000/HZ))%100); 507 508 pr_debug("Before bogocount - setting activated=1.\n"); 509 } 510 511 void __inquire_remote_apic(int apicid) 512 { 513 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 514 char *names[] = { "ID", "VERSION", "SPIV" }; 515 int timeout; 516 u32 status; 517 518 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); 519 520 for (i = 0; i < ARRAY_SIZE(regs); i++) { 521 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); 522 523 /* 524 * Wait for idle. 525 */ 526 status = safe_apic_wait_icr_idle(); 527 if (status) 528 printk(KERN_CONT 529 "a previous APIC delivery may have failed\n"); 530 531 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 532 533 timeout = 0; 534 do { 535 udelay(100); 536 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 537 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 538 539 switch (status) { 540 case APIC_ICR_RR_VALID: 541 status = apic_read(APIC_RRR); 542 printk(KERN_CONT "%08x\n", status); 543 break; 544 default: 545 printk(KERN_CONT "failed\n"); 546 } 547 } 548 } 549 550 /* 551 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 552 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 553 * won't ... remember to clear down the APIC, etc later. 554 */ 555 int __cpuinit 556 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) 557 { 558 unsigned long send_status, accept_status = 0; 559 int maxlvt; 560 561 /* Target chip */ 562 /* Boot on the stack */ 563 /* Kick the second */ 564 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); 565 566 pr_debug("Waiting for send to finish...\n"); 567 send_status = safe_apic_wait_icr_idle(); 568 569 /* 570 * Give the other CPU some time to accept the IPI. 571 */ 572 udelay(200); 573 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 574 maxlvt = lapic_get_maxlvt(); 575 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 576 apic_write(APIC_ESR, 0); 577 accept_status = (apic_read(APIC_ESR) & 0xEF); 578 } 579 pr_debug("NMI sent.\n"); 580 581 if (send_status) 582 printk(KERN_ERR "APIC never delivered???\n"); 583 if (accept_status) 584 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 585 586 return (send_status | accept_status); 587 } 588 589 static int __cpuinit 590 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 591 { 592 unsigned long send_status, accept_status = 0; 593 int maxlvt, num_starts, j; 594 595 maxlvt = lapic_get_maxlvt(); 596 597 /* 598 * Be paranoid about clearing APIC errors. 599 */ 600 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 601 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 602 apic_write(APIC_ESR, 0); 603 apic_read(APIC_ESR); 604 } 605 606 pr_debug("Asserting INIT.\n"); 607 608 /* 609 * Turn INIT on target chip 610 */ 611 /* 612 * Send IPI 613 */ 614 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 615 phys_apicid); 616 617 pr_debug("Waiting for send to finish...\n"); 618 send_status = safe_apic_wait_icr_idle(); 619 620 mdelay(10); 621 622 pr_debug("Deasserting INIT.\n"); 623 624 /* Target chip */ 625 /* Send IPI */ 626 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 627 628 pr_debug("Waiting for send to finish...\n"); 629 send_status = safe_apic_wait_icr_idle(); 630 631 mb(); 632 atomic_set(&init_deasserted, 1); 633 634 /* 635 * Should we send STARTUP IPIs ? 636 * 637 * Determine this based on the APIC version. 638 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 639 */ 640 if (APIC_INTEGRATED(apic_version[phys_apicid])) 641 num_starts = 2; 642 else 643 num_starts = 0; 644 645 /* 646 * Paravirt / VMI wants a startup IPI hook here to set up the 647 * target processor state. 648 */ 649 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, 650 (unsigned long)stack_start.sp); 651 652 /* 653 * Run STARTUP IPI loop. 654 */ 655 pr_debug("#startup loops: %d.\n", num_starts); 656 657 for (j = 1; j <= num_starts; j++) { 658 pr_debug("Sending STARTUP #%d.\n", j); 659 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 660 apic_write(APIC_ESR, 0); 661 apic_read(APIC_ESR); 662 pr_debug("After apic_write.\n"); 663 664 /* 665 * STARTUP IPI 666 */ 667 668 /* Target chip */ 669 /* Boot on the stack */ 670 /* Kick the second */ 671 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 672 phys_apicid); 673 674 /* 675 * Give the other CPU some time to accept the IPI. 676 */ 677 udelay(300); 678 679 pr_debug("Startup point 1.\n"); 680 681 pr_debug("Waiting for send to finish...\n"); 682 send_status = safe_apic_wait_icr_idle(); 683 684 /* 685 * Give the other CPU some time to accept the IPI. 686 */ 687 udelay(200); 688 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 689 apic_write(APIC_ESR, 0); 690 accept_status = (apic_read(APIC_ESR) & 0xEF); 691 if (send_status || accept_status) 692 break; 693 } 694 pr_debug("After Startup.\n"); 695 696 if (send_status) 697 printk(KERN_ERR "APIC never delivered???\n"); 698 if (accept_status) 699 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 700 701 return (send_status | accept_status); 702 } 703 704 struct create_idle { 705 struct work_struct work; 706 struct task_struct *idle; 707 struct completion done; 708 int cpu; 709 }; 710 711 static void __cpuinit do_fork_idle(struct work_struct *work) 712 { 713 struct create_idle *c_idle = 714 container_of(work, struct create_idle, work); 715 716 c_idle->idle = fork_idle(c_idle->cpu); 717 complete(&c_idle->done); 718 } 719 720 /* reduce the number of lines printed when booting a large cpu count system */ 721 static void __cpuinit announce_cpu(int cpu, int apicid) 722 { 723 static int current_node = -1; 724 int node = early_cpu_to_node(cpu); 725 726 if (system_state == SYSTEM_BOOTING) { 727 if (node != current_node) { 728 if (current_node > (-1)) 729 pr_cont(" Ok.\n"); 730 current_node = node; 731 pr_info("Booting Node %3d, Processors ", node); 732 } 733 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : ""); 734 return; 735 } else 736 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 737 node, cpu, apicid); 738 } 739 740 /* 741 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 742 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 743 * Returns zero if CPU booted OK, else error code from 744 * ->wakeup_secondary_cpu. 745 */ 746 static int __cpuinit do_boot_cpu(int apicid, int cpu) 747 { 748 unsigned long boot_error = 0; 749 unsigned long start_ip; 750 int timeout; 751 struct create_idle c_idle = { 752 .cpu = cpu, 753 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), 754 }; 755 756 INIT_WORK_ON_STACK(&c_idle.work, do_fork_idle); 757 758 alternatives_smp_switch(1); 759 760 c_idle.idle = get_idle_for_cpu(cpu); 761 762 /* 763 * We can't use kernel_thread since we must avoid to 764 * reschedule the child. 765 */ 766 if (c_idle.idle) { 767 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) 768 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); 769 init_idle(c_idle.idle, cpu); 770 goto do_rest; 771 } 772 773 schedule_work(&c_idle.work); 774 wait_for_completion(&c_idle.done); 775 776 if (IS_ERR(c_idle.idle)) { 777 printk("failed fork for CPU %d\n", cpu); 778 destroy_work_on_stack(&c_idle.work); 779 return PTR_ERR(c_idle.idle); 780 } 781 782 set_idle_for_cpu(cpu, c_idle.idle); 783 do_rest: 784 per_cpu(current_task, cpu) = c_idle.idle; 785 #ifdef CONFIG_X86_32 786 /* Stack for startup_32 can be just as for start_secondary onwards */ 787 irq_ctx_init(cpu); 788 initial_page_table = __pa(&trampoline_pg_dir); 789 #else 790 clear_tsk_thread_flag(c_idle.idle, TIF_FORK); 791 initial_gs = per_cpu_offset(cpu); 792 per_cpu(kernel_stack, cpu) = 793 (unsigned long)task_stack_page(c_idle.idle) - 794 KERNEL_STACK_OFFSET + THREAD_SIZE; 795 #endif 796 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 797 initial_code = (unsigned long)start_secondary; 798 stack_start.sp = (void *) c_idle.idle->thread.sp; 799 800 /* start_ip had better be page-aligned! */ 801 start_ip = setup_trampoline(); 802 803 /* So we see what's up */ 804 announce_cpu(cpu, apicid); 805 806 /* 807 * This grunge runs the startup process for 808 * the targeted processor. 809 */ 810 811 atomic_set(&init_deasserted, 0); 812 813 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 814 815 pr_debug("Setting warm reset code and vector.\n"); 816 817 smpboot_setup_warm_reset_vector(start_ip); 818 /* 819 * Be paranoid about clearing APIC errors. 820 */ 821 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 822 apic_write(APIC_ESR, 0); 823 apic_read(APIC_ESR); 824 } 825 } 826 827 /* 828 * Kick the secondary CPU. Use the method in the APIC driver 829 * if it's defined - or use an INIT boot APIC message otherwise: 830 */ 831 if (apic->wakeup_secondary_cpu) 832 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 833 else 834 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 835 836 if (!boot_error) { 837 /* 838 * allow APs to start initializing. 839 */ 840 pr_debug("Before Callout %d.\n", cpu); 841 cpumask_set_cpu(cpu, cpu_callout_mask); 842 pr_debug("After Callout %d.\n", cpu); 843 844 /* 845 * Wait 5s total for a response 846 */ 847 for (timeout = 0; timeout < 50000; timeout++) { 848 if (cpumask_test_cpu(cpu, cpu_callin_mask)) 849 break; /* It has booted */ 850 udelay(100); 851 /* 852 * Allow other tasks to run while we wait for the 853 * AP to come online. This also gives a chance 854 * for the MTRR work(triggered by the AP coming online) 855 * to be completed in the stop machine context. 856 */ 857 schedule(); 858 } 859 860 if (cpumask_test_cpu(cpu, cpu_callin_mask)) 861 pr_debug("CPU%d: has booted.\n", cpu); 862 else { 863 boot_error = 1; 864 if (*((volatile unsigned char *)trampoline_base) 865 == 0xA5) 866 /* trampoline started but...? */ 867 pr_err("CPU%d: Stuck ??\n", cpu); 868 else 869 /* trampoline code not run */ 870 pr_err("CPU%d: Not responding.\n", cpu); 871 if (apic->inquire_remote_apic) 872 apic->inquire_remote_apic(apicid); 873 } 874 } 875 876 if (boot_error) { 877 /* Try to put things back the way they were before ... */ 878 numa_remove_cpu(cpu); /* was set by numa_add_cpu */ 879 880 /* was set by do_boot_cpu() */ 881 cpumask_clear_cpu(cpu, cpu_callout_mask); 882 883 /* was set by cpu_init() */ 884 cpumask_clear_cpu(cpu, cpu_initialized_mask); 885 886 set_cpu_present(cpu, false); 887 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; 888 } 889 890 /* mark "stuck" area as not stuck */ 891 *((volatile unsigned long *)trampoline_base) = 0; 892 893 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 894 /* 895 * Cleanup possible dangling ends... 896 */ 897 smpboot_restore_warm_reset_vector(); 898 } 899 900 destroy_work_on_stack(&c_idle.work); 901 return boot_error; 902 } 903 904 int __cpuinit native_cpu_up(unsigned int cpu) 905 { 906 int apicid = apic->cpu_present_to_apicid(cpu); 907 unsigned long flags; 908 int err; 909 910 WARN_ON(irqs_disabled()); 911 912 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 913 914 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || 915 !physid_isset(apicid, phys_cpu_present_map)) { 916 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); 917 return -EINVAL; 918 } 919 920 /* 921 * Already booted CPU? 922 */ 923 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 924 pr_debug("do_boot_cpu %d Already started\n", cpu); 925 return -ENOSYS; 926 } 927 928 /* 929 * Save current MTRR state in case it was changed since early boot 930 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 931 */ 932 mtrr_save_state(); 933 934 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; 935 936 err = do_boot_cpu(apicid, cpu); 937 938 if (err) { 939 pr_debug("do_boot_cpu failed %d\n", err); 940 return -EIO; 941 } 942 943 /* 944 * Check TSC synchronization with the AP (keep irqs disabled 945 * while doing so): 946 */ 947 local_irq_save(flags); 948 check_tsc_sync_source(cpu); 949 local_irq_restore(flags); 950 951 while (!cpu_online(cpu)) { 952 cpu_relax(); 953 touch_nmi_watchdog(); 954 } 955 956 return 0; 957 } 958 959 /* 960 * Fall back to non SMP mode after errors. 961 * 962 * RED-PEN audit/test this more. I bet there is more state messed up here. 963 */ 964 static __init void disable_smp(void) 965 { 966 init_cpu_present(cpumask_of(0)); 967 init_cpu_possible(cpumask_of(0)); 968 smpboot_clear_io_apic_irqs(); 969 970 if (smp_found_config) 971 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 972 else 973 physid_set_mask_of_physid(0, &phys_cpu_present_map); 974 map_cpu_to_logical_apicid(); 975 cpumask_set_cpu(0, cpu_sibling_mask(0)); 976 cpumask_set_cpu(0, cpu_core_mask(0)); 977 } 978 979 /* 980 * Various sanity checks. 981 */ 982 static int __init smp_sanity_check(unsigned max_cpus) 983 { 984 preempt_disable(); 985 986 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 987 if (def_to_bigsmp && nr_cpu_ids > 8) { 988 unsigned int cpu; 989 unsigned nr; 990 991 printk(KERN_WARNING 992 "More than 8 CPUs detected - skipping them.\n" 993 "Use CONFIG_X86_BIGSMP.\n"); 994 995 nr = 0; 996 for_each_present_cpu(cpu) { 997 if (nr >= 8) 998 set_cpu_present(cpu, false); 999 nr++; 1000 } 1001 1002 nr = 0; 1003 for_each_possible_cpu(cpu) { 1004 if (nr >= 8) 1005 set_cpu_possible(cpu, false); 1006 nr++; 1007 } 1008 1009 nr_cpu_ids = 8; 1010 } 1011 #endif 1012 1013 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1014 printk(KERN_WARNING 1015 "weird, boot CPU (#%d) not listed by the BIOS.\n", 1016 hard_smp_processor_id()); 1017 1018 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1019 } 1020 1021 /* 1022 * If we couldn't find an SMP configuration at boot time, 1023 * get out of here now! 1024 */ 1025 if (!smp_found_config && !acpi_lapic) { 1026 preempt_enable(); 1027 printk(KERN_NOTICE "SMP motherboard not detected.\n"); 1028 disable_smp(); 1029 if (APIC_init_uniprocessor()) 1030 printk(KERN_NOTICE "Local APIC not detected." 1031 " Using dummy APIC emulation.\n"); 1032 return -1; 1033 } 1034 1035 /* 1036 * Should not be necessary because the MP table should list the boot 1037 * CPU too, but we do it for the sake of robustness anyway. 1038 */ 1039 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1040 printk(KERN_NOTICE 1041 "weird, boot CPU (#%d) not listed by the BIOS.\n", 1042 boot_cpu_physical_apicid); 1043 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1044 } 1045 preempt_enable(); 1046 1047 /* 1048 * If we couldn't find a local APIC, then get out of here now! 1049 */ 1050 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 1051 !cpu_has_apic) { 1052 if (!disable_apic) { 1053 pr_err("BIOS bug, local APIC #%d not detected!...\n", 1054 boot_cpu_physical_apicid); 1055 pr_err("... forcing use of dummy APIC emulation." 1056 "(tell your hw vendor)\n"); 1057 } 1058 smpboot_clear_io_apic(); 1059 arch_disable_smp_support(); 1060 return -1; 1061 } 1062 1063 verify_local_APIC(); 1064 1065 /* 1066 * If SMP should be disabled, then really disable it! 1067 */ 1068 if (!max_cpus) { 1069 printk(KERN_INFO "SMP mode deactivated.\n"); 1070 smpboot_clear_io_apic(); 1071 1072 localise_nmi_watchdog(); 1073 1074 connect_bsp_APIC(); 1075 setup_local_APIC(); 1076 end_local_APIC_setup(); 1077 return -1; 1078 } 1079 1080 return 0; 1081 } 1082 1083 static void __init smp_cpu_index_default(void) 1084 { 1085 int i; 1086 struct cpuinfo_x86 *c; 1087 1088 for_each_possible_cpu(i) { 1089 c = &cpu_data(i); 1090 /* mark all to hotplug */ 1091 c->cpu_index = nr_cpu_ids; 1092 } 1093 } 1094 1095 /* 1096 * Prepare for SMP bootup. The MP table or ACPI has been read 1097 * earlier. Just do some sanity checking here and enable APIC mode. 1098 */ 1099 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1100 { 1101 unsigned int i; 1102 1103 preempt_disable(); 1104 smp_cpu_index_default(); 1105 current_cpu_data = boot_cpu_data; 1106 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1107 mb(); 1108 /* 1109 * Setup boot CPU information 1110 */ 1111 smp_store_cpu_info(0); /* Final full version of the data */ 1112 #ifdef CONFIG_X86_32 1113 boot_cpu_logical_apicid = logical_smp_processor_id(); 1114 #endif 1115 current_thread_info()->cpu = 0; /* needed? */ 1116 for_each_possible_cpu(i) { 1117 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1118 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1119 zalloc_cpumask_var(&cpu_data(i).llc_shared_map, GFP_KERNEL); 1120 } 1121 set_cpu_sibling_map(0); 1122 1123 1124 if (smp_sanity_check(max_cpus) < 0) { 1125 printk(KERN_INFO "SMP disabled\n"); 1126 disable_smp(); 1127 goto out; 1128 } 1129 1130 default_setup_apic_routing(); 1131 1132 preempt_disable(); 1133 if (read_apic_id() != boot_cpu_physical_apicid) { 1134 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1135 read_apic_id(), boot_cpu_physical_apicid); 1136 /* Or can we switch back to PIC here? */ 1137 } 1138 preempt_enable(); 1139 1140 connect_bsp_APIC(); 1141 1142 /* 1143 * Switch from PIC to APIC mode. 1144 */ 1145 setup_local_APIC(); 1146 1147 /* 1148 * Enable IO APIC before setting up error vector 1149 */ 1150 if (!skip_ioapic_setup && nr_ioapics) 1151 enable_IO_APIC(); 1152 1153 end_local_APIC_setup(); 1154 1155 map_cpu_to_logical_apicid(); 1156 1157 if (apic->setup_portio_remap) 1158 apic->setup_portio_remap(); 1159 1160 smpboot_setup_io_apic(); 1161 /* 1162 * Set up local APIC timer on boot CPU. 1163 */ 1164 1165 printk(KERN_INFO "CPU%d: ", 0); 1166 print_cpu_info(&cpu_data(0)); 1167 x86_init.timers.setup_percpu_clockev(); 1168 1169 if (is_uv_system()) 1170 uv_system_init(); 1171 1172 set_mtrr_aps_delayed_init(); 1173 out: 1174 preempt_enable(); 1175 } 1176 1177 void arch_enable_nonboot_cpus_begin(void) 1178 { 1179 set_mtrr_aps_delayed_init(); 1180 } 1181 1182 void arch_enable_nonboot_cpus_end(void) 1183 { 1184 mtrr_aps_init(); 1185 } 1186 1187 /* 1188 * Early setup to make printk work. 1189 */ 1190 void __init native_smp_prepare_boot_cpu(void) 1191 { 1192 int me = smp_processor_id(); 1193 switch_to_new_gdt(me); 1194 /* already set me in cpu_online_mask in boot_cpu_init() */ 1195 cpumask_set_cpu(me, cpu_callout_mask); 1196 per_cpu(cpu_state, me) = CPU_ONLINE; 1197 } 1198 1199 void __init native_smp_cpus_done(unsigned int max_cpus) 1200 { 1201 pr_debug("Boot done.\n"); 1202 1203 impress_friends(); 1204 #ifdef CONFIG_X86_IO_APIC 1205 setup_ioapic_dest(); 1206 #endif 1207 check_nmi_watchdog(); 1208 mtrr_aps_init(); 1209 } 1210 1211 static int __initdata setup_possible_cpus = -1; 1212 static int __init _setup_possible_cpus(char *str) 1213 { 1214 get_option(&str, &setup_possible_cpus); 1215 return 0; 1216 } 1217 early_param("possible_cpus", _setup_possible_cpus); 1218 1219 1220 /* 1221 * cpu_possible_mask should be static, it cannot change as cpu's 1222 * are onlined, or offlined. The reason is per-cpu data-structures 1223 * are allocated by some modules at init time, and dont expect to 1224 * do this dynamically on cpu arrival/departure. 1225 * cpu_present_mask on the other hand can change dynamically. 1226 * In case when cpu_hotplug is not compiled, then we resort to current 1227 * behaviour, which is cpu_possible == cpu_present. 1228 * - Ashok Raj 1229 * 1230 * Three ways to find out the number of additional hotplug CPUs: 1231 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1232 * - The user can overwrite it with possible_cpus=NUM 1233 * - Otherwise don't reserve additional CPUs. 1234 * We do this because additional CPUs waste a lot of memory. 1235 * -AK 1236 */ 1237 __init void prefill_possible_map(void) 1238 { 1239 int i, possible; 1240 1241 /* no processor from mptable or madt */ 1242 if (!num_processors) 1243 num_processors = 1; 1244 1245 i = setup_max_cpus ?: 1; 1246 if (setup_possible_cpus == -1) { 1247 possible = num_processors; 1248 #ifdef CONFIG_HOTPLUG_CPU 1249 if (setup_max_cpus) 1250 possible += disabled_cpus; 1251 #else 1252 if (possible > i) 1253 possible = i; 1254 #endif 1255 } else 1256 possible = setup_possible_cpus; 1257 1258 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1259 1260 /* nr_cpu_ids could be reduced via nr_cpus= */ 1261 if (possible > nr_cpu_ids) { 1262 printk(KERN_WARNING 1263 "%d Processors exceeds NR_CPUS limit of %d\n", 1264 possible, nr_cpu_ids); 1265 possible = nr_cpu_ids; 1266 } 1267 1268 #ifdef CONFIG_HOTPLUG_CPU 1269 if (!setup_max_cpus) 1270 #endif 1271 if (possible > i) { 1272 printk(KERN_WARNING 1273 "%d Processors exceeds max_cpus limit of %u\n", 1274 possible, setup_max_cpus); 1275 possible = i; 1276 } 1277 1278 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", 1279 possible, max_t(int, possible - num_processors, 0)); 1280 1281 for (i = 0; i < possible; i++) 1282 set_cpu_possible(i, true); 1283 for (; i < NR_CPUS; i++) 1284 set_cpu_possible(i, false); 1285 1286 nr_cpu_ids = possible; 1287 } 1288 1289 #ifdef CONFIG_HOTPLUG_CPU 1290 1291 static void remove_siblinginfo(int cpu) 1292 { 1293 int sibling; 1294 struct cpuinfo_x86 *c = &cpu_data(cpu); 1295 1296 for_each_cpu(sibling, cpu_core_mask(cpu)) { 1297 cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); 1298 /*/ 1299 * last thread sibling in this cpu core going down 1300 */ 1301 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) 1302 cpu_data(sibling).booted_cores--; 1303 } 1304 1305 for_each_cpu(sibling, cpu_sibling_mask(cpu)) 1306 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); 1307 cpumask_clear(cpu_sibling_mask(cpu)); 1308 cpumask_clear(cpu_core_mask(cpu)); 1309 c->phys_proc_id = 0; 1310 c->cpu_core_id = 0; 1311 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1312 } 1313 1314 static void __ref remove_cpu_from_maps(int cpu) 1315 { 1316 set_cpu_online(cpu, false); 1317 cpumask_clear_cpu(cpu, cpu_callout_mask); 1318 cpumask_clear_cpu(cpu, cpu_callin_mask); 1319 /* was set by cpu_init() */ 1320 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1321 numa_remove_cpu(cpu); 1322 } 1323 1324 void cpu_disable_common(void) 1325 { 1326 int cpu = smp_processor_id(); 1327 1328 remove_siblinginfo(cpu); 1329 1330 /* It's now safe to remove this processor from the online map */ 1331 lock_vector_lock(); 1332 remove_cpu_from_maps(cpu); 1333 unlock_vector_lock(); 1334 fixup_irqs(); 1335 } 1336 1337 int native_cpu_disable(void) 1338 { 1339 int cpu = smp_processor_id(); 1340 1341 /* 1342 * Perhaps use cpufreq to drop frequency, but that could go 1343 * into generic code. 1344 * 1345 * We won't take down the boot processor on i386 due to some 1346 * interrupts only being able to be serviced by the BSP. 1347 * Especially so if we're not using an IOAPIC -zwane 1348 */ 1349 if (cpu == 0) 1350 return -EBUSY; 1351 1352 if (nmi_watchdog == NMI_LOCAL_APIC) 1353 stop_apic_nmi_watchdog(NULL); 1354 clear_local_APIC(); 1355 1356 cpu_disable_common(); 1357 return 0; 1358 } 1359 1360 void native_cpu_die(unsigned int cpu) 1361 { 1362 /* We don't do anything here: idle task is faking death itself. */ 1363 unsigned int i; 1364 1365 for (i = 0; i < 10; i++) { 1366 /* They ack this in play_dead by setting CPU_DEAD */ 1367 if (per_cpu(cpu_state, cpu) == CPU_DEAD) { 1368 if (system_state == SYSTEM_RUNNING) 1369 pr_info("CPU %u is now offline\n", cpu); 1370 1371 if (1 == num_online_cpus()) 1372 alternatives_smp_switch(0); 1373 return; 1374 } 1375 msleep(100); 1376 } 1377 pr_err("CPU %u didn't die...\n", cpu); 1378 } 1379 1380 void play_dead_common(void) 1381 { 1382 idle_task_exit(); 1383 reset_lazy_tlbstate(); 1384 irq_ctx_exit(raw_smp_processor_id()); 1385 c1e_remove_cpu(raw_smp_processor_id()); 1386 1387 mb(); 1388 /* Ack it */ 1389 __get_cpu_var(cpu_state) = CPU_DEAD; 1390 1391 /* 1392 * With physical CPU hotplug, we should halt the cpu 1393 */ 1394 local_irq_disable(); 1395 } 1396 1397 /* 1398 * We need to flush the caches before going to sleep, lest we have 1399 * dirty data in our caches when we come back up. 1400 */ 1401 static inline void mwait_play_dead(void) 1402 { 1403 unsigned int eax, ebx, ecx, edx; 1404 unsigned int highest_cstate = 0; 1405 unsigned int highest_subcstate = 0; 1406 int i; 1407 void *mwait_ptr; 1408 1409 if (!cpu_has(¤t_cpu_data, X86_FEATURE_MWAIT)) 1410 return; 1411 if (!cpu_has(¤t_cpu_data, X86_FEATURE_CLFLSH)) 1412 return; 1413 if (current_cpu_data.cpuid_level < CPUID_MWAIT_LEAF) 1414 return; 1415 1416 eax = CPUID_MWAIT_LEAF; 1417 ecx = 0; 1418 native_cpuid(&eax, &ebx, &ecx, &edx); 1419 1420 /* 1421 * eax will be 0 if EDX enumeration is not valid. 1422 * Initialized below to cstate, sub_cstate value when EDX is valid. 1423 */ 1424 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1425 eax = 0; 1426 } else { 1427 edx >>= MWAIT_SUBSTATE_SIZE; 1428 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1429 if (edx & MWAIT_SUBSTATE_MASK) { 1430 highest_cstate = i; 1431 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1432 } 1433 } 1434 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1435 (highest_subcstate - 1); 1436 } 1437 1438 /* 1439 * This should be a memory location in a cache line which is 1440 * unlikely to be touched by other processors. The actual 1441 * content is immaterial as it is not actually modified in any way. 1442 */ 1443 mwait_ptr = ¤t_thread_info()->flags; 1444 1445 wbinvd(); 1446 1447 while (1) { 1448 /* 1449 * The CLFLUSH is a workaround for erratum AAI65 for 1450 * the Xeon 7400 series. It's not clear it is actually 1451 * needed, but it should be harmless in either case. 1452 * The WBINVD is insufficient due to the spurious-wakeup 1453 * case where we return around the loop. 1454 */ 1455 clflush(mwait_ptr); 1456 __monitor(mwait_ptr, 0, 0); 1457 mb(); 1458 __mwait(eax, 0); 1459 } 1460 } 1461 1462 static inline void hlt_play_dead(void) 1463 { 1464 if (current_cpu_data.x86 >= 4) 1465 wbinvd(); 1466 1467 while (1) { 1468 native_halt(); 1469 } 1470 } 1471 1472 void native_play_dead(void) 1473 { 1474 play_dead_common(); 1475 tboot_shutdown(TB_SHUTDOWN_WFS); 1476 1477 mwait_play_dead(); /* Only returns on failure */ 1478 hlt_play_dead(); 1479 } 1480 1481 #else /* ... !CONFIG_HOTPLUG_CPU */ 1482 int native_cpu_disable(void) 1483 { 1484 return -ENOSYS; 1485 } 1486 1487 void native_cpu_die(unsigned int cpu) 1488 { 1489 /* We said "no" in __cpu_disable */ 1490 BUG(); 1491 } 1492 1493 void native_play_dead(void) 1494 { 1495 BUG(); 1496 } 1497 1498 #endif 1499