1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * x86 SMP booting functions 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 7 * Copyright 2001 Andi Kleen, SuSE Labs. 8 * 9 * Much of the core SMP work is based on previous work by Thomas Radke, to 10 * whom a great many thanks are extended. 11 * 12 * Thanks to Intel for making available several different Pentium, 13 * Pentium Pro and Pentium-II/Xeon MP machines. 14 * Original development of Linux SMP code supported by Caldera. 15 * 16 * Fixes 17 * Felix Koop : NR_CPUS used properly 18 * Jose Renau : Handle single CPU case. 19 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 20 * Greg Wright : Fix for kernel stacks panic. 21 * Erich Boleyn : MP v1.4 and additional changes. 22 * Matthias Sattler : Changes for 2.1 kernel map. 23 * Michel Lespinasse : Changes for 2.1 kernel map. 24 * Michael Chastain : Change trampoline.S to gnu as. 25 * Alan Cox : Dumb bug: 'B' step PPro's are fine 26 * Ingo Molnar : Added APIC timers, based on code 27 * from Jose Renau 28 * Ingo Molnar : various cleanups and rewrites 29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 31 * Andi Kleen : Changed for SMP boot into long mode. 32 * Martin J. Bligh : Added support for multi-quad systems 33 * Dave Jones : Report invalid combinations of Athlon CPUs. 34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 35 * Andi Kleen : Converted to new state machine. 36 * Ashok Raj : CPU hotplug support 37 * Glauber Costa : i386 and x86_64 integration 38 */ 39 40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/export.h> 45 #include <linux/sched.h> 46 #include <linux/sched/topology.h> 47 #include <linux/sched/hotplug.h> 48 #include <linux/sched/task_stack.h> 49 #include <linux/percpu.h> 50 #include <linux/memblock.h> 51 #include <linux/err.h> 52 #include <linux/nmi.h> 53 #include <linux/tboot.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 #include <linux/kexec.h> 57 #include <linux/numa.h> 58 #include <linux/pgtable.h> 59 #include <linux/overflow.h> 60 #include <linux/stackprotector.h> 61 #include <linux/cpuhotplug.h> 62 #include <linux/mc146818rtc.h> 63 64 #include <asm/acpi.h> 65 #include <asm/cacheinfo.h> 66 #include <asm/desc.h> 67 #include <asm/nmi.h> 68 #include <asm/irq.h> 69 #include <asm/realmode.h> 70 #include <asm/cpu.h> 71 #include <asm/numa.h> 72 #include <asm/tlbflush.h> 73 #include <asm/mtrr.h> 74 #include <asm/mwait.h> 75 #include <asm/apic.h> 76 #include <asm/io_apic.h> 77 #include <asm/fpu/api.h> 78 #include <asm/setup.h> 79 #include <asm/uv/uv.h> 80 #include <asm/microcode.h> 81 #include <asm/i8259.h> 82 #include <asm/misc.h> 83 #include <asm/qspinlock.h> 84 #include <asm/intel-family.h> 85 #include <asm/cpu_device_id.h> 86 #include <asm/spec-ctrl.h> 87 #include <asm/hw_irq.h> 88 #include <asm/stackprotector.h> 89 #include <asm/sev.h> 90 #include <asm/spec-ctrl.h> 91 92 /* representing HT siblings of each logical CPU */ 93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 94 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 95 96 /* representing HT and core siblings of each logical CPU */ 97 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 98 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 99 100 /* representing HT, core, and die siblings of each logical CPU */ 101 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); 102 EXPORT_PER_CPU_SYMBOL(cpu_die_map); 103 104 /* Per CPU bogomips and other parameters */ 105 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 106 EXPORT_PER_CPU_SYMBOL(cpu_info); 107 108 /* CPUs which are the primary SMT threads */ 109 struct cpumask __cpu_primary_thread_mask __read_mostly; 110 111 /* Representing CPUs for which sibling maps can be computed */ 112 static cpumask_var_t cpu_sibling_setup_mask; 113 114 struct mwait_cpu_dead { 115 unsigned int control; 116 unsigned int status; 117 }; 118 119 #define CPUDEAD_MWAIT_WAIT 0xDEADBEEF 120 #define CPUDEAD_MWAIT_KEXEC_HLT 0x4A17DEAD 121 122 /* 123 * Cache line aligned data for mwait_play_dead(). Separate on purpose so 124 * that it's unlikely to be touched by other CPUs. 125 */ 126 static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead); 127 128 /* Logical package management. */ 129 struct logical_maps { 130 u32 phys_pkg_id; 131 u32 phys_die_id; 132 u32 logical_pkg_id; 133 u32 logical_die_id; 134 }; 135 136 /* Temporary workaround until the full topology mechanics is in place */ 137 static DEFINE_PER_CPU_READ_MOSTLY(struct logical_maps, logical_maps) = { 138 .phys_pkg_id = U32_MAX, 139 .phys_die_id = U32_MAX, 140 }; 141 142 unsigned int __max_logical_packages __read_mostly; 143 EXPORT_SYMBOL(__max_logical_packages); 144 static unsigned int logical_packages __read_mostly; 145 static unsigned int logical_die __read_mostly; 146 147 /* Maximum number of SMT threads on any online core */ 148 int __read_mostly __max_smt_threads = 1; 149 150 /* Flag to indicate if a complete sched domain rebuild is required */ 151 bool x86_topology_update; 152 153 int arch_update_cpu_topology(void) 154 { 155 int retval = x86_topology_update; 156 157 x86_topology_update = false; 158 return retval; 159 } 160 161 static unsigned int smpboot_warm_reset_vector_count; 162 163 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 164 { 165 unsigned long flags; 166 167 spin_lock_irqsave(&rtc_lock, flags); 168 if (!smpboot_warm_reset_vector_count++) { 169 CMOS_WRITE(0xa, 0xf); 170 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = start_eip >> 4; 171 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = start_eip & 0xf; 172 } 173 spin_unlock_irqrestore(&rtc_lock, flags); 174 } 175 176 static inline void smpboot_restore_warm_reset_vector(void) 177 { 178 unsigned long flags; 179 180 /* 181 * Paranoid: Set warm reset code and vector here back 182 * to default values. 183 */ 184 spin_lock_irqsave(&rtc_lock, flags); 185 if (!--smpboot_warm_reset_vector_count) { 186 CMOS_WRITE(0, 0xf); 187 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 188 } 189 spin_unlock_irqrestore(&rtc_lock, flags); 190 191 } 192 193 /* Run the next set of setup steps for the upcoming CPU */ 194 static void ap_starting(void) 195 { 196 int cpuid = smp_processor_id(); 197 198 /* Mop up eventual mwait_play_dead() wreckage */ 199 this_cpu_write(mwait_cpu_dead.status, 0); 200 this_cpu_write(mwait_cpu_dead.control, 0); 201 202 /* 203 * If woken up by an INIT in an 82489DX configuration the alive 204 * synchronization guarantees that the CPU does not reach this 205 * point before an INIT_deassert IPI reaches the local APIC, so it 206 * is now safe to touch the local APIC. 207 * 208 * Set up this CPU, first the APIC, which is probably redundant on 209 * most boards. 210 */ 211 apic_ap_setup(); 212 213 /* Save the processor parameters. */ 214 smp_store_cpu_info(cpuid); 215 216 /* 217 * The topology information must be up to date before 218 * notify_cpu_starting(). 219 */ 220 set_cpu_sibling_map(cpuid); 221 222 ap_init_aperfmperf(); 223 224 pr_debug("Stack at about %p\n", &cpuid); 225 226 wmb(); 227 228 /* 229 * This runs the AP through all the cpuhp states to its target 230 * state CPUHP_ONLINE. 231 */ 232 notify_cpu_starting(cpuid); 233 } 234 235 static void ap_calibrate_delay(void) 236 { 237 /* 238 * Calibrate the delay loop and update loops_per_jiffy in cpu_data. 239 * smp_store_cpu_info() stored a value that is close but not as 240 * accurate as the value just calculated. 241 * 242 * As this is invoked after the TSC synchronization check, 243 * calibrate_delay_is_known() will skip the calibration routine 244 * when TSC is synchronized across sockets. 245 */ 246 calibrate_delay(); 247 cpu_data(smp_processor_id()).loops_per_jiffy = loops_per_jiffy; 248 } 249 250 /* 251 * Activate a secondary processor. 252 */ 253 static void notrace start_secondary(void *unused) 254 { 255 /* 256 * Don't put *anything* except direct CPU state initialization 257 * before cpu_init(), SMP booting is too fragile that we want to 258 * limit the things done here to the most necessary things. 259 */ 260 cr4_init(); 261 262 /* 263 * 32-bit specific. 64-bit reaches this code with the correct page 264 * table established. Yet another historical divergence. 265 */ 266 if (IS_ENABLED(CONFIG_X86_32)) { 267 /* switch away from the initial page table */ 268 load_cr3(swapper_pg_dir); 269 __flush_tlb_all(); 270 } 271 272 cpu_init_exception_handling(); 273 274 /* 275 * 32-bit systems load the microcode from the ASM startup code for 276 * historical reasons. 277 * 278 * On 64-bit systems load it before reaching the AP alive 279 * synchronization point below so it is not part of the full per 280 * CPU serialized bringup part when "parallel" bringup is enabled. 281 * 282 * That's even safe when hyperthreading is enabled in the CPU as 283 * the core code starts the primary threads first and leaves the 284 * secondary threads waiting for SIPI. Loading microcode on 285 * physical cores concurrently is a safe operation. 286 * 287 * This covers both the Intel specific issue that concurrent 288 * microcode loading on SMT siblings must be prohibited and the 289 * vendor independent issue`that microcode loading which changes 290 * CPUID, MSRs etc. must be strictly serialized to maintain 291 * software state correctness. 292 */ 293 if (IS_ENABLED(CONFIG_X86_64)) 294 load_ucode_ap(); 295 296 /* 297 * Synchronization point with the hotplug core. Sets this CPUs 298 * synchronization state to ALIVE and spin-waits for the control CPU to 299 * release this CPU for further bringup. 300 */ 301 cpuhp_ap_sync_alive(); 302 303 cpu_init(); 304 fpu__init_cpu(); 305 rcutree_report_cpu_starting(raw_smp_processor_id()); 306 x86_cpuinit.early_percpu_clock_init(); 307 308 ap_starting(); 309 310 /* Check TSC synchronization with the control CPU. */ 311 check_tsc_sync_target(); 312 313 /* 314 * Calibrate the delay loop after the TSC synchronization check. 315 * This allows to skip the calibration when TSC is synchronized 316 * across sockets. 317 */ 318 ap_calibrate_delay(); 319 320 speculative_store_bypass_ht_init(); 321 322 /* 323 * Lock vector_lock, set CPU online and bring the vector 324 * allocator online. Online must be set with vector_lock held 325 * to prevent a concurrent irq setup/teardown from seeing a 326 * half valid vector space. 327 */ 328 lock_vector_lock(); 329 set_cpu_online(smp_processor_id(), true); 330 lapic_online(); 331 unlock_vector_lock(); 332 x86_platform.nmi_init(); 333 334 /* enable local interrupts */ 335 local_irq_enable(); 336 337 x86_cpuinit.setup_percpu_clockev(); 338 339 wmb(); 340 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 341 } 342 343 /** 344 * topology_phys_to_logical_pkg - Map a physical package id to a logical 345 * @phys_pkg: The physical package id to map 346 * 347 * Returns logical package id or -1 if not found 348 */ 349 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 350 { 351 int cpu; 352 353 for_each_possible_cpu(cpu) { 354 if (per_cpu(logical_maps.phys_pkg_id, cpu) == phys_pkg) 355 return per_cpu(logical_maps.logical_pkg_id, cpu); 356 } 357 return -1; 358 } 359 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 360 361 /** 362 * topology_phys_to_logical_die - Map a physical die id to logical 363 * @die_id: The physical die id to map 364 * @cur_cpu: The CPU for which the mapping is done 365 * 366 * Returns logical die id or -1 if not found 367 */ 368 static int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu) 369 { 370 int cpu, proc_id = cpu_data(cur_cpu).topo.pkg_id; 371 372 for_each_possible_cpu(cpu) { 373 if (per_cpu(logical_maps.phys_pkg_id, cpu) == proc_id && 374 per_cpu(logical_maps.phys_die_id, cpu) == die_id) 375 return per_cpu(logical_maps.logical_die_id, cpu); 376 } 377 return -1; 378 } 379 380 /** 381 * topology_update_package_map - Update the physical to logical package map 382 * @pkg: The physical package id as retrieved via CPUID 383 * @cpu: The cpu for which this is updated 384 */ 385 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 386 { 387 int new; 388 389 /* Already available somewhere? */ 390 new = topology_phys_to_logical_pkg(pkg); 391 if (new >= 0) 392 goto found; 393 394 new = logical_packages++; 395 if (new != pkg) { 396 pr_info("CPU %u Converting physical %u to logical package %u\n", 397 cpu, pkg, new); 398 } 399 found: 400 per_cpu(logical_maps.phys_pkg_id, cpu) = pkg; 401 per_cpu(logical_maps.logical_pkg_id, cpu) = new; 402 cpu_data(cpu).topo.logical_pkg_id = new; 403 return 0; 404 } 405 /** 406 * topology_update_die_map - Update the physical to logical die map 407 * @die: The die id as retrieved via CPUID 408 * @cpu: The cpu for which this is updated 409 */ 410 int topology_update_die_map(unsigned int die, unsigned int cpu) 411 { 412 int new; 413 414 /* Already available somewhere? */ 415 new = topology_phys_to_logical_die(die, cpu); 416 if (new >= 0) 417 goto found; 418 419 new = logical_die++; 420 if (new != die) { 421 pr_info("CPU %u Converting physical %u to logical die %u\n", 422 cpu, die, new); 423 } 424 found: 425 per_cpu(logical_maps.phys_die_id, cpu) = die; 426 per_cpu(logical_maps.logical_die_id, cpu) = new; 427 cpu_data(cpu).topo.logical_die_id = new; 428 return 0; 429 } 430 431 static void __init smp_store_boot_cpu_info(void) 432 { 433 int id = 0; /* CPU 0 */ 434 struct cpuinfo_x86 *c = &cpu_data(id); 435 436 *c = boot_cpu_data; 437 c->cpu_index = id; 438 topology_update_package_map(c->topo.pkg_id, id); 439 topology_update_die_map(c->topo.die_id, id); 440 c->initialized = true; 441 } 442 443 /* 444 * The bootstrap kernel entry code has set these up. Save them for 445 * a given CPU 446 */ 447 void smp_store_cpu_info(int id) 448 { 449 struct cpuinfo_x86 *c = &cpu_data(id); 450 451 /* Copy boot_cpu_data only on the first bringup */ 452 if (!c->initialized) 453 *c = boot_cpu_data; 454 c->cpu_index = id; 455 /* 456 * During boot time, CPU0 has this setup already. Save the info when 457 * bringing up an AP. 458 */ 459 identify_secondary_cpu(c); 460 c->initialized = true; 461 } 462 463 static bool 464 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 465 { 466 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 467 468 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 469 } 470 471 static bool 472 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 473 { 474 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 475 476 return !WARN_ONCE(!topology_same_node(c, o), 477 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 478 "[node: %d != %d]. Ignoring dependency.\n", 479 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 480 } 481 482 #define link_mask(mfunc, c1, c2) \ 483 do { \ 484 cpumask_set_cpu((c1), mfunc(c2)); \ 485 cpumask_set_cpu((c2), mfunc(c1)); \ 486 } while (0) 487 488 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 489 { 490 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 491 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 492 493 if (c->topo.pkg_id == o->topo.pkg_id && 494 c->topo.die_id == o->topo.die_id && 495 per_cpu_llc_id(cpu1) == per_cpu_llc_id(cpu2)) { 496 if (c->topo.core_id == o->topo.core_id) 497 return topology_sane(c, o, "smt"); 498 499 if ((c->topo.cu_id != 0xff) && 500 (o->topo.cu_id != 0xff) && 501 (c->topo.cu_id == o->topo.cu_id)) 502 return topology_sane(c, o, "smt"); 503 } 504 505 } else if (c->topo.pkg_id == o->topo.pkg_id && 506 c->topo.die_id == o->topo.die_id && 507 c->topo.core_id == o->topo.core_id) { 508 return topology_sane(c, o, "smt"); 509 } 510 511 return false; 512 } 513 514 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 515 { 516 if (c->topo.pkg_id == o->topo.pkg_id && 517 c->topo.die_id == o->topo.die_id) 518 return true; 519 return false; 520 } 521 522 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 523 { 524 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 525 526 /* If the arch didn't set up l2c_id, fall back to SMT */ 527 if (per_cpu_l2c_id(cpu1) == BAD_APICID) 528 return match_smt(c, o); 529 530 /* Do not match if L2 cache id does not match: */ 531 if (per_cpu_l2c_id(cpu1) != per_cpu_l2c_id(cpu2)) 532 return false; 533 534 return topology_sane(c, o, "l2c"); 535 } 536 537 /* 538 * Unlike the other levels, we do not enforce keeping a 539 * multicore group inside a NUMA node. If this happens, we will 540 * discard the MC level of the topology later. 541 */ 542 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 543 { 544 if (c->topo.pkg_id == o->topo.pkg_id) 545 return true; 546 return false; 547 } 548 549 /* 550 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs. 551 * 552 * Any Intel CPU that has multiple nodes per package and does not 553 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology. 554 * 555 * When in SNC mode, these CPUs enumerate an LLC that is shared 556 * by multiple NUMA nodes. The LLC is shared for off-package data 557 * access but private to the NUMA node (half of the package) for 558 * on-package access. CPUID (the source of the information about 559 * the LLC) can only enumerate the cache as shared or unshared, 560 * but not this particular configuration. 561 */ 562 563 static const struct x86_cpu_id intel_cod_cpu[] = { 564 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */ 565 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */ 566 X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */ 567 {} 568 }; 569 570 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 571 { 572 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu); 573 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 574 bool intel_snc = id && id->driver_data; 575 576 /* Do not match if we do not have a valid APICID for cpu: */ 577 if (per_cpu_llc_id(cpu1) == BAD_APICID) 578 return false; 579 580 /* Do not match if LLC id does not match: */ 581 if (per_cpu_llc_id(cpu1) != per_cpu_llc_id(cpu2)) 582 return false; 583 584 /* 585 * Allow the SNC topology without warning. Return of false 586 * means 'c' does not share the LLC of 'o'. This will be 587 * reflected to userspace. 588 */ 589 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc) 590 return false; 591 592 return topology_sane(c, o, "llc"); 593 } 594 595 596 static inline int x86_sched_itmt_flags(void) 597 { 598 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 599 } 600 601 #ifdef CONFIG_SCHED_MC 602 static int x86_core_flags(void) 603 { 604 return cpu_core_flags() | x86_sched_itmt_flags(); 605 } 606 #endif 607 #ifdef CONFIG_SCHED_SMT 608 static int x86_smt_flags(void) 609 { 610 return cpu_smt_flags(); 611 } 612 #endif 613 #ifdef CONFIG_SCHED_CLUSTER 614 static int x86_cluster_flags(void) 615 { 616 return cpu_cluster_flags() | x86_sched_itmt_flags(); 617 } 618 #endif 619 620 static int x86_die_flags(void) 621 { 622 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) 623 return x86_sched_itmt_flags(); 624 625 return 0; 626 } 627 628 /* 629 * Set if a package/die has multiple NUMA nodes inside. 630 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel 631 * Sub-NUMA Clustering have this. 632 */ 633 static bool x86_has_numa_in_package; 634 635 static struct sched_domain_topology_level x86_topology[6]; 636 637 static void __init build_sched_topology(void) 638 { 639 int i = 0; 640 641 #ifdef CONFIG_SCHED_SMT 642 x86_topology[i++] = (struct sched_domain_topology_level){ 643 cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) 644 }; 645 #endif 646 #ifdef CONFIG_SCHED_CLUSTER 647 x86_topology[i++] = (struct sched_domain_topology_level){ 648 cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) 649 }; 650 #endif 651 #ifdef CONFIG_SCHED_MC 652 x86_topology[i++] = (struct sched_domain_topology_level){ 653 cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) 654 }; 655 #endif 656 /* 657 * When there is NUMA topology inside the package skip the PKG domain 658 * since the NUMA domains will auto-magically create the right spanning 659 * domains based on the SLIT. 660 */ 661 if (!x86_has_numa_in_package) { 662 x86_topology[i++] = (struct sched_domain_topology_level){ 663 cpu_cpu_mask, x86_die_flags, SD_INIT_NAME(PKG) 664 }; 665 } 666 667 /* 668 * There must be one trailing NULL entry left. 669 */ 670 BUG_ON(i >= ARRAY_SIZE(x86_topology)-1); 671 672 set_sched_topology(x86_topology); 673 } 674 675 void set_cpu_sibling_map(int cpu) 676 { 677 bool has_smt = smp_num_siblings > 1; 678 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 679 struct cpuinfo_x86 *c = &cpu_data(cpu); 680 struct cpuinfo_x86 *o; 681 int i, threads; 682 683 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 684 685 if (!has_mp) { 686 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 687 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 688 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu)); 689 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 690 cpumask_set_cpu(cpu, topology_die_cpumask(cpu)); 691 c->booted_cores = 1; 692 return; 693 } 694 695 for_each_cpu(i, cpu_sibling_setup_mask) { 696 o = &cpu_data(i); 697 698 if (match_pkg(c, o) && !topology_same_node(c, o)) 699 x86_has_numa_in_package = true; 700 701 if ((i == cpu) || (has_smt && match_smt(c, o))) 702 link_mask(topology_sibling_cpumask, cpu, i); 703 704 if ((i == cpu) || (has_mp && match_llc(c, o))) 705 link_mask(cpu_llc_shared_mask, cpu, i); 706 707 if ((i == cpu) || (has_mp && match_l2c(c, o))) 708 link_mask(cpu_l2c_shared_mask, cpu, i); 709 710 if ((i == cpu) || (has_mp && match_die(c, o))) 711 link_mask(topology_die_cpumask, cpu, i); 712 } 713 714 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 715 if (threads > __max_smt_threads) 716 __max_smt_threads = threads; 717 718 for_each_cpu(i, topology_sibling_cpumask(cpu)) 719 cpu_data(i).smt_active = threads > 1; 720 721 /* 722 * This needs a separate iteration over the cpus because we rely on all 723 * topology_sibling_cpumask links to be set-up. 724 */ 725 for_each_cpu(i, cpu_sibling_setup_mask) { 726 o = &cpu_data(i); 727 728 if ((i == cpu) || (has_mp && match_pkg(c, o))) { 729 link_mask(topology_core_cpumask, cpu, i); 730 731 /* 732 * Does this new cpu bringup a new core? 733 */ 734 if (threads == 1) { 735 /* 736 * for each core in package, increment 737 * the booted_cores for this new cpu 738 */ 739 if (cpumask_first( 740 topology_sibling_cpumask(i)) == i) 741 c->booted_cores++; 742 /* 743 * increment the core count for all 744 * the other cpus in this package 745 */ 746 if (i != cpu) 747 cpu_data(i).booted_cores++; 748 } else if (i != cpu && !c->booted_cores) 749 c->booted_cores = cpu_data(i).booted_cores; 750 } 751 } 752 } 753 754 /* maps the cpu to the sched domain representing multi-core */ 755 const struct cpumask *cpu_coregroup_mask(int cpu) 756 { 757 return cpu_llc_shared_mask(cpu); 758 } 759 760 const struct cpumask *cpu_clustergroup_mask(int cpu) 761 { 762 return cpu_l2c_shared_mask(cpu); 763 } 764 765 static void impress_friends(void) 766 { 767 int cpu; 768 unsigned long bogosum = 0; 769 /* 770 * Allow the user to impress friends. 771 */ 772 pr_debug("Before bogomips\n"); 773 for_each_online_cpu(cpu) 774 bogosum += cpu_data(cpu).loops_per_jiffy; 775 776 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 777 num_online_cpus(), 778 bogosum/(500000/HZ), 779 (bogosum/(5000/HZ))%100); 780 781 pr_debug("Before bogocount - setting activated=1\n"); 782 } 783 784 /* 785 * The Multiprocessor Specification 1.4 (1997) example code suggests 786 * that there should be a 10ms delay between the BSP asserting INIT 787 * and de-asserting INIT, when starting a remote processor. 788 * But that slows boot and resume on modern processors, which include 789 * many cores and don't require that delay. 790 * 791 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 792 * Modern processor families are quirked to remove the delay entirely. 793 */ 794 #define UDELAY_10MS_DEFAULT 10000 795 796 static unsigned int init_udelay = UINT_MAX; 797 798 static int __init cpu_init_udelay(char *str) 799 { 800 get_option(&str, &init_udelay); 801 802 return 0; 803 } 804 early_param("cpu_init_udelay", cpu_init_udelay); 805 806 static void __init smp_quirk_init_udelay(void) 807 { 808 /* if cmdline changed it from default, leave it alone */ 809 if (init_udelay != UINT_MAX) 810 return; 811 812 /* if modern processor, use no delay */ 813 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 814 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || 815 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 816 init_udelay = 0; 817 return; 818 } 819 /* else, use legacy delay */ 820 init_udelay = UDELAY_10MS_DEFAULT; 821 } 822 823 /* 824 * Wake up AP by INIT, INIT, STARTUP sequence. 825 */ 826 static void send_init_sequence(u32 phys_apicid) 827 { 828 int maxlvt = lapic_get_maxlvt(); 829 830 /* Be paranoid about clearing APIC errors. */ 831 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 832 /* Due to the Pentium erratum 3AP. */ 833 if (maxlvt > 3) 834 apic_write(APIC_ESR, 0); 835 apic_read(APIC_ESR); 836 } 837 838 /* Assert INIT on the target CPU */ 839 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, phys_apicid); 840 safe_apic_wait_icr_idle(); 841 842 udelay(init_udelay); 843 844 /* Deassert INIT on the target CPU */ 845 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 846 safe_apic_wait_icr_idle(); 847 } 848 849 /* 850 * Wake up AP by INIT, INIT, STARTUP sequence. 851 */ 852 static int wakeup_secondary_cpu_via_init(u32 phys_apicid, unsigned long start_eip) 853 { 854 unsigned long send_status = 0, accept_status = 0; 855 int num_starts, j, maxlvt; 856 857 preempt_disable(); 858 maxlvt = lapic_get_maxlvt(); 859 send_init_sequence(phys_apicid); 860 861 mb(); 862 863 /* 864 * Should we send STARTUP IPIs ? 865 * 866 * Determine this based on the APIC version. 867 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 868 */ 869 if (APIC_INTEGRATED(boot_cpu_apic_version)) 870 num_starts = 2; 871 else 872 num_starts = 0; 873 874 /* 875 * Run STARTUP IPI loop. 876 */ 877 pr_debug("#startup loops: %d\n", num_starts); 878 879 for (j = 1; j <= num_starts; j++) { 880 pr_debug("Sending STARTUP #%d\n", j); 881 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 882 apic_write(APIC_ESR, 0); 883 apic_read(APIC_ESR); 884 pr_debug("After apic_write\n"); 885 886 /* 887 * STARTUP IPI 888 */ 889 890 /* Target chip */ 891 /* Boot on the stack */ 892 /* Kick the second */ 893 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 894 phys_apicid); 895 896 /* 897 * Give the other CPU some time to accept the IPI. 898 */ 899 if (init_udelay == 0) 900 udelay(10); 901 else 902 udelay(300); 903 904 pr_debug("Startup point 1\n"); 905 906 pr_debug("Waiting for send to finish...\n"); 907 send_status = safe_apic_wait_icr_idle(); 908 909 /* 910 * Give the other CPU some time to accept the IPI. 911 */ 912 if (init_udelay == 0) 913 udelay(10); 914 else 915 udelay(200); 916 917 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 918 apic_write(APIC_ESR, 0); 919 accept_status = (apic_read(APIC_ESR) & 0xEF); 920 if (send_status || accept_status) 921 break; 922 } 923 pr_debug("After Startup\n"); 924 925 if (send_status) 926 pr_err("APIC never delivered???\n"); 927 if (accept_status) 928 pr_err("APIC delivery error (%lx)\n", accept_status); 929 930 preempt_enable(); 931 return (send_status | accept_status); 932 } 933 934 /* reduce the number of lines printed when booting a large cpu count system */ 935 static void announce_cpu(int cpu, int apicid) 936 { 937 static int width, node_width, first = 1; 938 static int current_node = NUMA_NO_NODE; 939 int node = early_cpu_to_node(cpu); 940 941 if (!width) 942 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 943 944 if (!node_width) 945 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 946 947 if (system_state < SYSTEM_RUNNING) { 948 if (first) 949 pr_info("x86: Booting SMP configuration:\n"); 950 951 if (node != current_node) { 952 if (current_node > (-1)) 953 pr_cont("\n"); 954 current_node = node; 955 956 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 957 node_width - num_digits(node), " ", node); 958 } 959 960 /* Add padding for the BSP */ 961 if (first) 962 pr_cont("%*s", width + 1, " "); 963 first = 0; 964 965 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 966 } else 967 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 968 node, cpu, apicid); 969 } 970 971 int common_cpu_up(unsigned int cpu, struct task_struct *idle) 972 { 973 int ret; 974 975 /* Just in case we booted with a single CPU. */ 976 alternatives_enable_smp(); 977 978 per_cpu(pcpu_hot.current_task, cpu) = idle; 979 cpu_init_stack_canary(cpu, idle); 980 981 /* Initialize the interrupt stack(s) */ 982 ret = irq_init_percpu_irqstack(cpu); 983 if (ret) 984 return ret; 985 986 #ifdef CONFIG_X86_32 987 /* Stack for startup_32 can be just as for start_secondary onwards */ 988 per_cpu(pcpu_hot.top_of_stack, cpu) = task_top_of_stack(idle); 989 #endif 990 return 0; 991 } 992 993 /* 994 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 995 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 996 * Returns zero if startup was successfully sent, else error code from 997 * ->wakeup_secondary_cpu. 998 */ 999 static int do_boot_cpu(u32 apicid, int cpu, struct task_struct *idle) 1000 { 1001 unsigned long start_ip = real_mode_header->trampoline_start; 1002 int ret; 1003 1004 #ifdef CONFIG_X86_64 1005 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */ 1006 if (apic->wakeup_secondary_cpu_64) 1007 start_ip = real_mode_header->trampoline_start64; 1008 #endif 1009 idle->thread.sp = (unsigned long)task_pt_regs(idle); 1010 initial_code = (unsigned long)start_secondary; 1011 1012 if (IS_ENABLED(CONFIG_X86_32)) { 1013 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 1014 initial_stack = idle->thread.sp; 1015 } else if (!(smpboot_control & STARTUP_PARALLEL_MASK)) { 1016 smpboot_control = cpu; 1017 } 1018 1019 /* Enable the espfix hack for this CPU */ 1020 init_espfix_ap(cpu); 1021 1022 /* So we see what's up */ 1023 announce_cpu(cpu, apicid); 1024 1025 /* 1026 * This grunge runs the startup process for 1027 * the targeted processor. 1028 */ 1029 if (x86_platform.legacy.warm_reset) { 1030 1031 pr_debug("Setting warm reset code and vector.\n"); 1032 1033 smpboot_setup_warm_reset_vector(start_ip); 1034 /* 1035 * Be paranoid about clearing APIC errors. 1036 */ 1037 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 1038 apic_write(APIC_ESR, 0); 1039 apic_read(APIC_ESR); 1040 } 1041 } 1042 1043 smp_mb(); 1044 1045 /* 1046 * Wake up a CPU in difference cases: 1047 * - Use a method from the APIC driver if one defined, with wakeup 1048 * straight to 64-bit mode preferred over wakeup to RM. 1049 * Otherwise, 1050 * - Use an INIT boot APIC message 1051 */ 1052 if (apic->wakeup_secondary_cpu_64) 1053 ret = apic->wakeup_secondary_cpu_64(apicid, start_ip); 1054 else if (apic->wakeup_secondary_cpu) 1055 ret = apic->wakeup_secondary_cpu(apicid, start_ip); 1056 else 1057 ret = wakeup_secondary_cpu_via_init(apicid, start_ip); 1058 1059 /* If the wakeup mechanism failed, cleanup the warm reset vector */ 1060 if (ret) 1061 arch_cpuhp_cleanup_kick_cpu(cpu); 1062 return ret; 1063 } 1064 1065 int native_kick_ap(unsigned int cpu, struct task_struct *tidle) 1066 { 1067 u32 apicid = apic->cpu_present_to_apicid(cpu); 1068 int err; 1069 1070 lockdep_assert_irqs_enabled(); 1071 1072 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1073 1074 if (apicid == BAD_APICID || !physid_isset(apicid, phys_cpu_present_map) || 1075 !apic_id_valid(apicid)) { 1076 pr_err("%s: bad cpu %d\n", __func__, cpu); 1077 return -EINVAL; 1078 } 1079 1080 /* 1081 * Save current MTRR state in case it was changed since early boot 1082 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1083 */ 1084 mtrr_save_state(); 1085 1086 /* the FPU context is blank, nobody can own it */ 1087 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1088 1089 err = common_cpu_up(cpu, tidle); 1090 if (err) 1091 return err; 1092 1093 err = do_boot_cpu(apicid, cpu, tidle); 1094 if (err) 1095 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1096 1097 return err; 1098 } 1099 1100 int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *tidle) 1101 { 1102 return smp_ops.kick_ap_alive(cpu, tidle); 1103 } 1104 1105 void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu) 1106 { 1107 /* Cleanup possible dangling ends... */ 1108 if (smp_ops.kick_ap_alive == native_kick_ap && x86_platform.legacy.warm_reset) 1109 smpboot_restore_warm_reset_vector(); 1110 } 1111 1112 void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu) 1113 { 1114 if (smp_ops.cleanup_dead_cpu) 1115 smp_ops.cleanup_dead_cpu(cpu); 1116 1117 if (system_state == SYSTEM_RUNNING) 1118 pr_info("CPU %u is now offline\n", cpu); 1119 } 1120 1121 void arch_cpuhp_sync_state_poll(void) 1122 { 1123 if (smp_ops.poll_sync_state) 1124 smp_ops.poll_sync_state(); 1125 } 1126 1127 /** 1128 * arch_disable_smp_support() - Disables SMP support for x86 at boottime 1129 */ 1130 void __init arch_disable_smp_support(void) 1131 { 1132 disable_ioapic_support(); 1133 } 1134 1135 /* 1136 * Fall back to non SMP mode after errors. 1137 * 1138 * RED-PEN audit/test this more. I bet there is more state messed up here. 1139 */ 1140 static __init void disable_smp(void) 1141 { 1142 pr_info("SMP disabled\n"); 1143 1144 disable_ioapic_support(); 1145 1146 init_cpu_present(cpumask_of(0)); 1147 init_cpu_possible(cpumask_of(0)); 1148 1149 if (smp_found_config) 1150 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1151 else 1152 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1153 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1154 cpumask_set_cpu(0, topology_core_cpumask(0)); 1155 cpumask_set_cpu(0, topology_die_cpumask(0)); 1156 } 1157 1158 static void __init smp_cpu_index_default(void) 1159 { 1160 int i; 1161 struct cpuinfo_x86 *c; 1162 1163 for_each_possible_cpu(i) { 1164 c = &cpu_data(i); 1165 /* mark all to hotplug */ 1166 c->cpu_index = nr_cpu_ids; 1167 } 1168 } 1169 1170 void __init smp_prepare_cpus_common(void) 1171 { 1172 unsigned int i; 1173 1174 smp_cpu_index_default(); 1175 1176 /* 1177 * Setup boot CPU information 1178 */ 1179 smp_store_boot_cpu_info(); /* Final full version of the data */ 1180 mb(); 1181 1182 for_each_possible_cpu(i) { 1183 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1184 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1185 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL); 1186 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1187 zalloc_cpumask_var(&per_cpu(cpu_l2c_shared_map, i), GFP_KERNEL); 1188 } 1189 1190 set_cpu_sibling_map(0); 1191 } 1192 1193 #ifdef CONFIG_X86_64 1194 /* Establish whether parallel bringup can be supported. */ 1195 bool __init arch_cpuhp_init_parallel_bringup(void) 1196 { 1197 if (!x86_cpuinit.parallel_bringup) { 1198 pr_info("Parallel CPU startup disabled by the platform\n"); 1199 return false; 1200 } 1201 1202 smpboot_control = STARTUP_READ_APICID; 1203 pr_debug("Parallel CPU startup enabled: 0x%08x\n", smpboot_control); 1204 return true; 1205 } 1206 #endif 1207 1208 /* 1209 * Prepare for SMP bootup. 1210 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1211 * for common interface support. 1212 */ 1213 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1214 { 1215 smp_prepare_cpus_common(); 1216 1217 switch (apic_intr_mode) { 1218 case APIC_PIC: 1219 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1220 disable_smp(); 1221 return; 1222 case APIC_SYMMETRIC_IO_NO_ROUTING: 1223 disable_smp(); 1224 /* Setup local timer */ 1225 x86_init.timers.setup_percpu_clockev(); 1226 return; 1227 case APIC_VIRTUAL_WIRE: 1228 case APIC_SYMMETRIC_IO: 1229 break; 1230 } 1231 1232 /* Setup local timer */ 1233 x86_init.timers.setup_percpu_clockev(); 1234 1235 pr_info("CPU0: "); 1236 print_cpu_info(&cpu_data(0)); 1237 1238 uv_system_init(); 1239 1240 smp_quirk_init_udelay(); 1241 1242 speculative_store_bypass_ht_init(); 1243 1244 snp_set_wakeup_secondary_cpu(); 1245 } 1246 1247 void arch_thaw_secondary_cpus_begin(void) 1248 { 1249 set_cache_aps_delayed_init(true); 1250 } 1251 1252 void arch_thaw_secondary_cpus_end(void) 1253 { 1254 cache_aps_init(); 1255 } 1256 1257 /* 1258 * Early setup to make printk work. 1259 */ 1260 void __init native_smp_prepare_boot_cpu(void) 1261 { 1262 int me = smp_processor_id(); 1263 1264 /* SMP handles this from setup_per_cpu_areas() */ 1265 if (!IS_ENABLED(CONFIG_SMP)) 1266 switch_gdt_and_percpu_base(me); 1267 1268 native_pv_lock_init(); 1269 } 1270 1271 void __init calculate_max_logical_packages(void) 1272 { 1273 int ncpus; 1274 1275 /* 1276 * Today neither Intel nor AMD support heterogeneous systems so 1277 * extrapolate the boot cpu's data to all packages. 1278 */ 1279 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); 1280 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); 1281 pr_info("Max logical packages: %u\n", __max_logical_packages); 1282 } 1283 1284 void __init native_smp_cpus_done(unsigned int max_cpus) 1285 { 1286 pr_debug("Boot done\n"); 1287 1288 calculate_max_logical_packages(); 1289 build_sched_topology(); 1290 nmi_selftest(); 1291 impress_friends(); 1292 cache_aps_init(); 1293 } 1294 1295 static int __initdata setup_possible_cpus = -1; 1296 static int __init _setup_possible_cpus(char *str) 1297 { 1298 get_option(&str, &setup_possible_cpus); 1299 return 0; 1300 } 1301 early_param("possible_cpus", _setup_possible_cpus); 1302 1303 1304 /* 1305 * cpu_possible_mask should be static, it cannot change as cpu's 1306 * are onlined, or offlined. The reason is per-cpu data-structures 1307 * are allocated by some modules at init time, and don't expect to 1308 * do this dynamically on cpu arrival/departure. 1309 * cpu_present_mask on the other hand can change dynamically. 1310 * In case when cpu_hotplug is not compiled, then we resort to current 1311 * behaviour, which is cpu_possible == cpu_present. 1312 * - Ashok Raj 1313 * 1314 * Three ways to find out the number of additional hotplug CPUs: 1315 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1316 * - The user can overwrite it with possible_cpus=NUM 1317 * - Otherwise don't reserve additional CPUs. 1318 * We do this because additional CPUs waste a lot of memory. 1319 * -AK 1320 */ 1321 __init void prefill_possible_map(void) 1322 { 1323 int i, possible; 1324 1325 i = setup_max_cpus ?: 1; 1326 if (setup_possible_cpus == -1) { 1327 possible = num_processors; 1328 #ifdef CONFIG_HOTPLUG_CPU 1329 if (setup_max_cpus) 1330 possible += disabled_cpus; 1331 #else 1332 if (possible > i) 1333 possible = i; 1334 #endif 1335 } else 1336 possible = setup_possible_cpus; 1337 1338 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1339 1340 /* nr_cpu_ids could be reduced via nr_cpus= */ 1341 if (possible > nr_cpu_ids) { 1342 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", 1343 possible, nr_cpu_ids); 1344 possible = nr_cpu_ids; 1345 } 1346 1347 #ifdef CONFIG_HOTPLUG_CPU 1348 if (!setup_max_cpus) 1349 #endif 1350 if (possible > i) { 1351 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1352 possible, setup_max_cpus); 1353 possible = i; 1354 } 1355 1356 set_nr_cpu_ids(possible); 1357 1358 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1359 possible, max_t(int, possible - num_processors, 0)); 1360 1361 reset_cpu_possible_mask(); 1362 1363 for (i = 0; i < possible; i++) 1364 set_cpu_possible(i, true); 1365 } 1366 1367 /* correctly size the local cpu masks */ 1368 void __init setup_cpu_local_masks(void) 1369 { 1370 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 1371 } 1372 1373 #ifdef CONFIG_HOTPLUG_CPU 1374 1375 /* Recompute SMT state for all CPUs on offline */ 1376 static void recompute_smt_state(void) 1377 { 1378 int max_threads, cpu; 1379 1380 max_threads = 0; 1381 for_each_online_cpu (cpu) { 1382 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1383 1384 if (threads > max_threads) 1385 max_threads = threads; 1386 } 1387 __max_smt_threads = max_threads; 1388 } 1389 1390 static void remove_siblinginfo(int cpu) 1391 { 1392 int sibling; 1393 struct cpuinfo_x86 *c = &cpu_data(cpu); 1394 1395 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1396 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1397 /*/ 1398 * last thread sibling in this cpu core going down 1399 */ 1400 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1401 cpu_data(sibling).booted_cores--; 1402 } 1403 1404 for_each_cpu(sibling, topology_die_cpumask(cpu)) 1405 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling)); 1406 1407 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) { 1408 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1409 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1) 1410 cpu_data(sibling).smt_active = false; 1411 } 1412 1413 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1414 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1415 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu)) 1416 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling)); 1417 cpumask_clear(cpu_llc_shared_mask(cpu)); 1418 cpumask_clear(cpu_l2c_shared_mask(cpu)); 1419 cpumask_clear(topology_sibling_cpumask(cpu)); 1420 cpumask_clear(topology_core_cpumask(cpu)); 1421 cpumask_clear(topology_die_cpumask(cpu)); 1422 c->topo.core_id = 0; 1423 c->booted_cores = 0; 1424 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1425 recompute_smt_state(); 1426 } 1427 1428 static void remove_cpu_from_maps(int cpu) 1429 { 1430 set_cpu_online(cpu, false); 1431 numa_remove_cpu(cpu); 1432 } 1433 1434 void cpu_disable_common(void) 1435 { 1436 int cpu = smp_processor_id(); 1437 1438 remove_siblinginfo(cpu); 1439 1440 /* It's now safe to remove this processor from the online map */ 1441 lock_vector_lock(); 1442 remove_cpu_from_maps(cpu); 1443 unlock_vector_lock(); 1444 fixup_irqs(); 1445 lapic_offline(); 1446 } 1447 1448 int native_cpu_disable(void) 1449 { 1450 int ret; 1451 1452 ret = lapic_can_unplug_cpu(); 1453 if (ret) 1454 return ret; 1455 1456 cpu_disable_common(); 1457 1458 /* 1459 * Disable the local APIC. Otherwise IPI broadcasts will reach 1460 * it. It still responds normally to INIT, NMI, SMI, and SIPI 1461 * messages. 1462 * 1463 * Disabling the APIC must happen after cpu_disable_common() 1464 * which invokes fixup_irqs(). 1465 * 1466 * Disabling the APIC preserves already set bits in IRR, but 1467 * an interrupt arriving after disabling the local APIC does not 1468 * set the corresponding IRR bit. 1469 * 1470 * fixup_irqs() scans IRR for set bits so it can raise a not 1471 * yet handled interrupt on the new destination CPU via an IPI 1472 * but obviously it can't do so for IRR bits which are not set. 1473 * IOW, interrupts arriving after disabling the local APIC will 1474 * be lost. 1475 */ 1476 apic_soft_disable(); 1477 1478 return 0; 1479 } 1480 1481 void play_dead_common(void) 1482 { 1483 idle_task_exit(); 1484 1485 cpuhp_ap_report_dead(); 1486 1487 local_irq_disable(); 1488 } 1489 1490 /* 1491 * We need to flush the caches before going to sleep, lest we have 1492 * dirty data in our caches when we come back up. 1493 */ 1494 static inline void mwait_play_dead(void) 1495 { 1496 struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead); 1497 unsigned int eax, ebx, ecx, edx; 1498 unsigned int highest_cstate = 0; 1499 unsigned int highest_subcstate = 0; 1500 int i; 1501 1502 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1503 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 1504 return; 1505 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1506 return; 1507 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1508 return; 1509 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1510 return; 1511 1512 eax = CPUID_MWAIT_LEAF; 1513 ecx = 0; 1514 native_cpuid(&eax, &ebx, &ecx, &edx); 1515 1516 /* 1517 * eax will be 0 if EDX enumeration is not valid. 1518 * Initialized below to cstate, sub_cstate value when EDX is valid. 1519 */ 1520 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1521 eax = 0; 1522 } else { 1523 edx >>= MWAIT_SUBSTATE_SIZE; 1524 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1525 if (edx & MWAIT_SUBSTATE_MASK) { 1526 highest_cstate = i; 1527 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1528 } 1529 } 1530 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1531 (highest_subcstate - 1); 1532 } 1533 1534 /* Set up state for the kexec() hack below */ 1535 md->status = CPUDEAD_MWAIT_WAIT; 1536 md->control = CPUDEAD_MWAIT_WAIT; 1537 1538 wbinvd(); 1539 1540 while (1) { 1541 /* 1542 * The CLFLUSH is a workaround for erratum AAI65 for 1543 * the Xeon 7400 series. It's not clear it is actually 1544 * needed, but it should be harmless in either case. 1545 * The WBINVD is insufficient due to the spurious-wakeup 1546 * case where we return around the loop. 1547 */ 1548 mb(); 1549 clflush(md); 1550 mb(); 1551 __monitor(md, 0, 0); 1552 mb(); 1553 __mwait(eax, 0); 1554 1555 if (READ_ONCE(md->control) == CPUDEAD_MWAIT_KEXEC_HLT) { 1556 /* 1557 * Kexec is about to happen. Don't go back into mwait() as 1558 * the kexec kernel might overwrite text and data including 1559 * page tables and stack. So mwait() would resume when the 1560 * monitor cache line is written to and then the CPU goes 1561 * south due to overwritten text, page tables and stack. 1562 * 1563 * Note: This does _NOT_ protect against a stray MCE, NMI, 1564 * SMI. They will resume execution at the instruction 1565 * following the HLT instruction and run into the problem 1566 * which this is trying to prevent. 1567 */ 1568 WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT); 1569 while(1) 1570 native_halt(); 1571 } 1572 } 1573 } 1574 1575 /* 1576 * Kick all "offline" CPUs out of mwait on kexec(). See comment in 1577 * mwait_play_dead(). 1578 */ 1579 void smp_kick_mwait_play_dead(void) 1580 { 1581 u32 newstate = CPUDEAD_MWAIT_KEXEC_HLT; 1582 struct mwait_cpu_dead *md; 1583 unsigned int cpu, i; 1584 1585 for_each_cpu_andnot(cpu, cpu_present_mask, cpu_online_mask) { 1586 md = per_cpu_ptr(&mwait_cpu_dead, cpu); 1587 1588 /* Does it sit in mwait_play_dead() ? */ 1589 if (READ_ONCE(md->status) != CPUDEAD_MWAIT_WAIT) 1590 continue; 1591 1592 /* Wait up to 5ms */ 1593 for (i = 0; READ_ONCE(md->status) != newstate && i < 1000; i++) { 1594 /* Bring it out of mwait */ 1595 WRITE_ONCE(md->control, newstate); 1596 udelay(5); 1597 } 1598 1599 if (READ_ONCE(md->status) != newstate) 1600 pr_err_once("CPU%u is stuck in mwait_play_dead()\n", cpu); 1601 } 1602 } 1603 1604 void __noreturn hlt_play_dead(void) 1605 { 1606 if (__this_cpu_read(cpu_info.x86) >= 4) 1607 wbinvd(); 1608 1609 while (1) 1610 native_halt(); 1611 } 1612 1613 /* 1614 * native_play_dead() is essentially a __noreturn function, but it can't 1615 * be marked as such as the compiler may complain about it. 1616 */ 1617 void native_play_dead(void) 1618 { 1619 if (cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS)) 1620 __update_spec_ctrl(0); 1621 1622 play_dead_common(); 1623 tboot_shutdown(TB_SHUTDOWN_WFS); 1624 1625 mwait_play_dead(); 1626 if (cpuidle_play_dead()) 1627 hlt_play_dead(); 1628 } 1629 1630 #else /* ... !CONFIG_HOTPLUG_CPU */ 1631 int native_cpu_disable(void) 1632 { 1633 return -ENOSYS; 1634 } 1635 1636 void native_play_dead(void) 1637 { 1638 BUG(); 1639 } 1640 1641 #endif 1642